Method for manufacturing a semiconductor structure and structure thereof

Abstract

This disclosure relates to the semiconductor field, providing a method for fabricating a semiconductor structure and its structure. The method includes: providing a substrate; forming a stacked structure spaced apart along a first direction and a first isolation layer between adjacent stacked structures on the substrate surface; the stacked structure includes a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming an oxide semiconductor layer in the first trench, the oxide semiconductor layer being in contact with a retained initial active layer; etching a portion of the oxide semiconductor layer and the retained initial active layer to form an active structure arrayed along a first direction and a second direction; the first direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface. This method can improve the carrier mobility of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a method for fabricating a semiconductor structure and the structure thereof. Background Technology

[0002] As semiconductor structures continue to evolve and their critical dimensions shrink, limitations in lithography machines restrict further reduction. Therefore, achieving higher storage density chips on a single wafer remains a key research focus for many researchers and semiconductor professionals. In two-dimensional or planar semiconductor devices, memory cells are arranged horizontally. Thus, the integration density of two-dimensional or planar semiconductor devices is determined by the area occupied by each memory cell. This integration density is significantly influenced by the technology used to form intricate patterns, limiting the potential for further increases in integration density. Consequently, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.

[0003] However, in three-dimensional semiconductor devices, there is still a continuous pursuit of higher storage density, faster speed and lower power consumption. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor structure, which can at least improve the mobility of semiconductor charge carriers.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, including providing a substrate; forming a stacked structure spaced apart along a first direction and a first isolation layer located between adjacent stacked structures on the surface of the substrate, the stacked structure including a first interlayer dielectric layer, an initial active layer and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming an oxide semiconductor layer in the first trench, the oxide semiconductor layer being in contact with a retained initial active layer; etching a portion of the oxide semiconductor layer and the retained initial active layer to form an active structure arrayed along the first direction and a second direction; the first direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface.

[0006] In some embodiments, after forming the active structure, the method further includes: forming a word line that surrounds a portion of the surface of the oxide semiconductor layer and extends along one of a first direction and a second direction; and forming a bit line that surrounds a portion of the surface of the oxide semiconductor layer, the bit line being spaced from the word line and extending along the other of the first direction and the second direction.

[0007] In some embodiments, the word line extends along the second direction, and the method of forming the word line includes: forming a first word line surrounding the oxide semiconductor layer; and forming a second word line covering the sidewall of the first word line.

[0008] In some embodiments, the method of forming the first word line includes: etching the first interlayer dielectric layer and the second interlayer dielectric layer of the stacked structure to form a first trench, the first trench exposing the surface of the oxide semiconductor layer; forming a gate dielectric layer on the surface of the first trench; forming the first word line on the surface of the gate dielectric layer, the gate dielectric layer and the first word line filling the first trench.

[0009] In some embodiments, the method of forming the second character line includes: etching the stacked structure along the second direction to form a second groove, the second groove exposing the sidewall of the first character line; forming a second initial character line, the second initial character line filling the second groove; etching the second initial character line to form the second character line, wherein the length of the second character lines arranged along the first direction decreases sequentially in the second direction.

[0010] In some embodiments, the method of forming the bit line includes: forming a third isolation layer; the third isolation layer covering a portion of the surface of the oxide semiconductor layer, and the third isolation layer being in contact with a sidewall of the word line arranged in a third direction; forming the bit line, the bit line being in contact with the sidewall of the third isolation layer arranged in the third direction, and the bit line covering the oxide semiconductor layer.

[0011] In some embodiments, the material of the oxide semiconductor layer includes indium gallium zinc oxide or zinc tin oxide.

[0012] In some embodiments, etching a portion of the oxide semiconductor layer includes: etching the stacked structure to form the active structures spaced apart along the second direction; and forming a second isolation layer located between the active structures spaced apart along the second direction.

[0013] In some embodiments, the method further includes: etching the first interlayer dielectric layer, the first isolation layer, and the second interlayer dielectric layer to form a third groove, the third groove exposing a portion of the surface of the initial active layer; forming a lower electrode plate, the lower electrode plate covering a portion of the surface of the initial active layer; forming a capacitor dielectric layer, the capacitor dielectric layer covering the surface of the lower electrode plate and the surface of the initial active layer; and forming an upper electrode plate, the upper electrode plate covering the surface of the capacitor dielectric layer, wherein the lower electrode plate, the capacitor dielectric layer, and the upper electrode plate constitute a capacitor.

[0014] In some embodiments, the step of forming the lower electrode plate includes: forming a fourth isolation layer, the fourth isolation layer covering the sidewall surface of the third groove arranged in a third direction; forming an initial lower electrode plate, the initial lower electrode plate covering the surface of the fourth isolation layer and the surface of the retained initial active layer; removing the fourth isolation layer and the initial lower electrode plate covering the surface of the fourth isolation layer, leaving the remaining initial lower electrode plate as the lower electrode plate.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate; active structures located on the surface of the substrate and spaced apart along a first direction and a second direction; the active structures include an oxide semiconductor layer and an initial active layer arranged along a third direction, the oxide semiconductor layer and the initial active layer being in contact; the first direction being perpendicular to the surface of the substrate, and the second direction being parallel to the surface of the substrate; a first isolation layer located between adjacent active structures in the first direction, and the projections of the first isolation layer and the active structures on the surface of the substrate overlapping.

[0016] In some embodiments, the system further includes: a word line that surrounds a portion of the surface of the oxide semiconductor layer and extends along one of a first direction and a second direction; a bit line that surrounds a portion of the surface of the oxide semiconductor layer, is spaced from the word line, and extends along the other of the first direction and the second direction; and a capacitor that is in contact with the initial active layer and extends along the first direction and is spaced along the second direction and the third direction.

[0017] In some embodiments, the capacitor includes: a lower electrode plate covering a portion of the surface of the initial active layer; a capacitor dielectric layer covering the surface of the lower electrode plate, and the capacitor dielectric layer also covering a portion of the surface of the initial active layer away from the lower electrode plate; and an upper electrode plate covering the surface of the capacitor dielectric layer.

[0018] In some embodiments, the word line extends along the second direction, and the word line includes: a first word line that surrounds a portion of the surface of the oxide semiconductor layer; and a second word line that covers the sidewall of the first word line.

[0019] In some embodiments, the projection of the second character line on the substrate surface coincides with the projection of the first character line on the substrate surface.

[0020] In some embodiments, the thickness of the active structure in the first direction is 15–25 nm.

[0021] In some embodiments, the doping concentration of the initial active layer is 1E19 to 1E22 cm⁻¹. -3 .

[0022] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by forming a stacked structure spaced along a first direction and a first isolation layer between adjacent stacked structures on the substrate surface, etching the initial active layer of the stacked structure to form a first trench, forming an oxide semiconductor layer in the first trench, and etching part of the oxide semiconductor layer and the remaining initial active layer to form an active structure arranged in an array along the first direction and the second direction, the carrier mobility of the active structure can be improved by forming an oxide semiconductor layer. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figures 1 to 21 A schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure provided in this embodiment of the disclosure;

[0025] Figure 22 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Detailed Implementation

[0026] As the background technology shows, with the continuous miniaturization of integration, traditional semiconductor structures with silicon as the active structure will encounter doping and stress problems during the stacking process, which will increase the difficulty of forming three-dimensional semiconductor devices.

[0027] This disclosure provides a method for fabricating a semiconductor structure. After forming a stacked structure on the surface of a substrate, the initial active layer of the stacked structure is etched to form a first trench, and an oxide semiconductor layer is formed in the first trench. Then, by etching a portion of the oxide semiconductor layer and the remaining initial active layer, an active structure arranged in an array along a first direction and a second direction is formed. By etching a portion of the initial active layer, the doping and stress problems encountered during the stacking process can be ignored. Subsequently, an oxide semiconductor layer can be formed as part of the active structure, and the carrier mobility of the semiconductor structure can be improved by forming the active structure.

[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0029] refer to Figures 1 to 21 , Figures 1 to 21 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0030] For details, please refer to Figure 1 and Figure 2 ,in Figure 1 This is a top view of the semiconductor structure. Figure 2 For along Figure 1 A cross-sectional view along the AA direction.

[0031] Specifically, a substrate 100 is provided, and stacked structures 110 arranged at intervals along a first direction X and a first isolation layer 120 located between adjacent stacked structures 110 are formed on the surface of the substrate 100. The stacked structure 110 includes a first interlayer dielectric layer 130, an initial active layer 140 and a second interlayer dielectric layer 150.

[0032] In some embodiments, the substrate 100 is a semiconductor material, including but not limited to any one of a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate. The substrate 100 may also be an ion-doped substrate, wherein the doping ions are N-type ions or P-type ions. Specifically, N-type ions may be phosphorus ions, arsenic ions, or antimony ions, and P-type ions may be boron ions, indium ions, or boron fluoride ions.

[0033] In some instances, the material of the first interlayer dielectric layer 130 can be the same as that of the second interlayer dielectric layer 150, such as silicon oxide or other insulating materials. The formation of the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 can provide a basis for the subsequent formation of bit lines, and the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 can also isolate the initial active layer 140 spaced apart in the first direction X.

[0034] The material of the initial active layer 140 can be silicon or polycrystalline silicon semiconductor material. Forming the initial active layer 140 can provide a process basis for the subsequent formation of an array of active structures.

[0035] In some embodiments, the initial active layer 140 is further ion-doped. The doping can be either N-type or P-type ions, depending on the requirements, and the doping concentration can be 1E19–1E22 cm⁻¹. -3 .

[0036] refer to Figure 3 The initial active layer 140 is etched to form a first trench 160, which provides a process basis for the subsequent formation of an oxide semiconductor layer.

[0037] In some embodiments, the method of etching the initial active layer 140 may be to use wet etching to etch the initial active layer 140 through the sidewalls of the stacked structure 110.

[0038] refer to Figures 4 to 6 ,in Figure 4 for Figure 1 A cross-sectional view along the AA direction. Figure 5 and Figure 6 This is a top view of the semiconductor structure.

[0039] An oxide semiconductor layer 170 is formed in the first trench 160, and the oxide semiconductor layer 170 is in contact with the retained initial active layer 140. Parts of the oxide semiconductor layer 170 and the retained initial active layer 140 are etched to form an active structure 180 arranged in an array along a first direction X and a second direction Y. The first direction X is perpendicular to the surface of the substrate 100, and the second direction Y is parallel to the surface of the substrate 100.

[0040] In some embodiments, an oxide semiconductor layer 170 may be formed by atomic layer deposition to fill the first trench 160 formed by etching the initial active layer 140.

[0041] In some embodiments, the material of the oxide semiconductor layer 170 may include indium gallium zinc oxide or zinc tin oxide. Using indium gallium zinc oxide or zinc tin oxide as the material of the oxide semiconductor layer can improve the ion mobility of the oxide semiconductor layer 170, thereby improving the performance of the subsequent oxide semiconductor layer 170 as a channel region. The material of the oxide semiconductor layer 170 may also be one or more of other similar materials such as indium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, etc.

[0042] In some embodiments, etching a portion of the oxide semiconductor layer 170 includes: etching a stacked structure 110 to form active structures 180 spaced apart along a second direction Y; and forming a second isolation layer 190 located between the active structures 180 spaced apart along the second direction Y. By etching the oxide semiconductor layer 170 and the stacked structure to form the oxide semiconductor layer 170 spaced apart along a first direction and the initial active layer 140, the remaining oxide semiconductor layer 170 and the remaining initial active layer 140 constitute the active structure 180. By forming the second isolation layer 190, the active structures 180 spaced apart along the second direction Y can be isolated, thereby preventing mutual interference between the active structures 180 spaced apart along the second direction Y.

[0043] refer to Figures 7 to 12 In some embodiments, after forming the active structure 180, the method further includes forming a word line 200. The word line 200 surrounds a portion of the surface of the oxide semiconductor layer 170 and extends along one of a first direction X and a second direction Y. By forming the word line 200, the conduction of the active structure 180 can be controlled; that is, the word line 200 can act as a gate to control the carrier flow of the active structure 180. Forming the word line 200 surrounding the oxide semiconductor layer 170 can improve the controllability of the word line 200.

[0044] In some embodiments, taking the word line 200 extending along the second direction Y as an example, the word line 200 covers the top surface of a plurality of active structures 180 arranged along the second direction Y. In other words, the word line 200 can control the conduction of a plurality of active structures 180, thereby increasing the stacking density of the semiconductor structure and improving the space utilization of the semiconductor structure.

[0045] In some embodiments, the word line 200 extends along a second direction Y. The method of forming the word line 200 includes: forming a first word line 201 surrounding the oxide semiconductor layer 170; and forming a second word line 203 covering the sidewalls of the first word line 201. The first word line 201 surrounding the surface of the oxide semiconductor layer 170 increases the contact area between the word line 200 and the active structure 180. The formation of the second word line 203 also provides a conductive basis for the subsequent formation of conductive pillars corresponding to and connected to the word line 200.

[0046] In some embodiments, the first character line 201 and the second character line 203 may be made of the same material, such as conductive materials such as titanium, titanium nitride, tungsten, aluminum or cobalt; in other embodiments, the materials of the first character line 201 and the second character line 203 may be different, and adjustments may be made according to the actual situation.

[0047] In some embodiments, the method of forming the first word line 201 may include: etching the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 of the stacked structure 110 to form a first recess 220; forming a gate dielectric layer 210 on the surface of the first recess 220; and forming the first word line 201 on the surface of the gate dielectric layer 210, wherein the gate dielectric layer 210 and the first word line 201 fill the first recess 220. It can be understood that the step of etching the first interlayer dielectric layer 130 and the second interlayer dielectric layer 150 of the stacked structure 110 further includes etching a portion of the second isolation layer 190 to form the first recess 220 exposing the surface of the oxide semiconductor layer 170 in the active structure 180. By forming the first word line 201, the facing area between the word line 200 and the active structure 180 can be increased, thereby improving the ability of the word line 200 to control the conduction of the active structure 180.

[0048] Understandably, when word line 200 provides a voltage to control active structure 180 to conduct, the charge carriers in active structure 180 flow toward word line 200. However, due to the presence of gate dielectric layer 210, the charge carriers cannot flow into word line 200, so current is formed by the accumulation on the surface of gate dielectric layer 210 near active structure 180.

[0049] In some embodiments, the material of the gate dielectric layer 210 may be an insulating material such as silicon oxide, silicon nitride, or hafnium oxide, and the material of the gate dielectric layer 210 may be selected according to the required dielectric constant of the gate dielectric layer 210.

[0050] In some embodiments, the thickness of the gate dielectric layer 210 can be 8 to 20 nm. It is understood that, under the same conditions, the thinner the gate dielectric layer 210, the better the performance of the semiconductor structure, but the lower the reliability of the semiconductor structure and the more prone it is to current tunneling. Correspondingly, the thicker the gate dielectric layer 210, the higher the reliability of the semiconductor structure, but the performance of the semiconductor structure will decrease. By setting the thickness of the gate dielectric layer 210 to 8 to 20 nm, the performance of the semiconductor structure can be improved while ensuring a certain level of reliability.

[0051] By forming the gate dielectric layer 210 and the first isolation layer 120, the oxide semiconductor layer 170 of the active structure 180 can also be isolated from oxygen and water vapor in the air, thereby improving the reliability of the semiconductor structure.

[0052] In some embodiments, the method of forming the second word line 203 includes: etching the stacked structure 110 along the second direction Y to form a second groove 221, the second groove 221 exposing the sidewalls of the first word line 201; forming a second initial word line 204, the second initial word line 204 filling the second groove 221; etching the second initial word line 204 to form the second word line 203, the length of the second word lines 203 arranged along the first direction X decreasing sequentially in the second direction Y. By forming second word lines 203 with sequentially decreasing lengths in the second direction Y, they can cooperate with subsequently formed conductive pillars that are connected to the word lines 200, so that one word line 200 is correspondingly connected to one conductive pillar, and different word lines 200 are led out through the conductive pillars, so as to control the word lines 200 corresponding to the conductive pillars through different conductive pillars, thereby controlling the supply of electrical signals to any word line 200.

[0053] refer to Figures 13 to 15 In some embodiments, the method further includes forming a bit line 230 that surrounds a portion of the surface of the oxide semiconductor layer 170, the bit line 230 being spaced from the word line 200, and the bit line 230 extending along the other of a first direction X and a second direction Y. It is understood that the extension direction of the word line 200 intersects the extension direction of the bit line 230; the word line 200 extends along the first direction X, and the bit line 230 extends along the second direction Y; or the word line 200 extends along the second direction Y, and the bit line 230 extends along the first direction X.

[0054] In some embodiments, taking the bit line 230 extending along the first direction as an example, a bit line 230 can contact and connect with a plurality of active structures 180 arranged along the first direction, that is, a bit line 230 can transmit signals to a plurality of active structures 180 arranged along the first direction X, thereby increasing the stacking density of the semiconductor structure and improving the space utilization of the semiconductor structure.

[0055] However, it is understandable that the extension direction of bit line 230 intersects the extension direction of word line 200, and there is only one intersection point between bit line 230 and word line 200. In other words, an active structure 180 can be selected through word line 200 and bit line 230.

[0056] In some embodiments, the method of forming bit line 230 may include: forming a third isolation layer 240, the third isolation layer 240 covering a portion of the surface of oxide semiconductor layer 170, and the third isolation layer 240 being in contact with the sidewalls of word line 200 arranged in a third direction Z; forming bit line 230, the bit line 230 being in contact with the sidewalls of third isolation layer 240 arranged in a third direction, and the bit line 230 covering oxide semiconductor layer 170. By forming the third isolation layer 240, bit line 230 can be isolated from word line 200, thereby avoiding electrical connection between bit line 230 and word line 200, thereby improving the reliability of semiconductor structure, and providing a basis for reading and writing data in semiconductor structure by forming bit line 230.

[0057] In some embodiments, the method of forming the third isolation layer 240 may include: etching a portion of the first word line to expose a portion of the surface of the oxide semiconductor layer 170, and etching a portion of the gate dielectric layer 210 while etching the first word line 201; forming a third initial isolation layer 241, the third initial isolation layer 241 being located between the first isolation layer 120 and the oxide semiconductor layer 170; etching the third initial isolation layer 241, the remaining third initial isolation layer 241 serving as the third isolation layer 240.

[0058] In some embodiments, etching the third initial isolation layer 241 also includes etching the first isolation layer 120. During the formation of the bit line 230, the formed bit line 230 may also cover the sidewall of the first isolation layer 120.

[0059] In some embodiments, the material of the third initial isolation layer 241 can be the same as that of the first isolation layer 120, which can both be silicon nitride. This allows the same etching reagent to be used to etch the third initial isolation layer 241 and the first isolation layer, thereby reducing the types of etching reagents and process steps.

[0060] refer to Figures 16 to 21 In some embodiments, the method further includes: etching the first interlayer dielectric layer 130, the first isolation layer 120, and the second interlayer dielectric layer 150 to form a third groove 250, the third groove 250 exposing a portion of the surface of the retained initial active layer 140; forming a lower electrode plate 261, the lower electrode plate 261 covering a portion of the surface of the retained initial active layer 140; forming a capacitor dielectric layer 262, the capacitor dielectric layer 262 covering the surface of the lower electrode plate 261 and the surface of a portion of the retained initial active layer 140; forming an upper electrode plate 263, the upper electrode plate 263 covering the surface of the capacitor dielectric layer 262, the lower electrode plate 261, the capacitor dielectric layer 262, and the upper electrode plate 263 constituting a capacitor 260.

[0061] The material of the lower electrode plate 261 may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper or tungsten; the material of the capacitor dielectric layer 262 may include any one or any combination of ZrO, AlO, ZrNbO, ZrHfO, ZrAlO; the material of the upper electrode plate 263 may include compounds formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride or other conductive materials, or the material of the upper electrode plate 263 may also be a conductive semiconductor material, such as polycrystalline silicon, germanium silicon, etc.

[0062] It is understandable that the relative area between the lower electrode plate 261 and the upper electrode plate 263 of the capacitor 260, the distance between the lower electrode plate 261 and the upper electrode plate 263, and the material of the capacitor dielectric layer 262 may all affect the capacitance of the capacitor 260. Therefore, the relative area between the lower electrode plate 261 and the upper electrode plate 263, the distance between the lower electrode plate 261 and the upper electrode plate 263, and the material of the capacitor dielectric layer 262 of the capacitor 260 can be set according to actual needs.

[0063] In some embodiments, capacitors 260 arranged along the first direction share an upper electrode plate 263. By forming capacitors 260 sharing an upper electrode plate 263, the space utilization of the semiconductor structure can be improved, and the formation of the semiconductor structure can also be facilitated.

[0064] In some embodiments, reference Figures 17 to 19 The steps for forming the lower electrode plate 261 include: forming a fourth isolation layer 270, which covers the sidewall surface of the third groove 250 arranged in the third direction Z; forming an initial lower electrode plate 264, which covers the surface of the fourth isolation layer 270 and the surface of the retained initial active layer 140; removing the fourth isolation layer 270 and the initial lower electrode plate 264 covering the surface of the fourth isolation layer 270, leaving the remaining initial lower electrode plate 264 as the lower electrode plate 261. The formation of the fourth isolation layer provides a process basis for the subsequent formation of spaced lower electrode plates 261, thereby allowing for the definition of each different capacitor 260 for each subsequent spaced lower electrode plate 261.

[0065] In some embodiments, before forming the fourth isolation layer 270, a sixth isolation layer 300 is formed, which is located between the fourth isolation layer 270 and the remaining stack structure 110. Forming the sixth isolation layer 300 can improve the insulation between the capacitor 260 and the word line 200.

[0066] In some embodiments, the step of removing the fourth isolation layer 270 and the initial lower electrode plate 264 covering the surface of the fourth isolation layer 270 may include: forming a fifth isolation layer 280, which covers the surface of the initial lower electrode plate 264 located on the surface of the initial active layer 140. By forming the fifth isolation layer 280, the initial lower electrode plate 264 that does not need to be etched can be covered, and then the initial lower electrode plate 264 and the fourth isolation layer 270 that do not need to be etched can be etched. This can improve the pattern accuracy of the formed lower electrode plate 261 and also avoid protecting the lower electrode plate 261 during the etching of the initial lower electrode plate 264 and the fourth isolation layer 270.

[0067] In some embodiments, the material of the fourth isolation layer 270 may be silicon oxide, the material of the fifth isolation layer 280 may be silicon oxynitride, and the material of the sixth isolation layer 300 may be silicon nitride. The materials of the fourth isolation layer 270 and the fifth isolation layer 280 are relatively soft, which facilitates subsequent etching processes. The material of the sixth isolation layer 300 is relatively hard, which facilitates the subsequent formation of the capacitor dielectric layer 262 and the upper electrode plate 263 attached to the surface of the sixth isolation layer 300.

[0068] In some embodiments, after forming the lower electrode plate 261, the fifth isolation layer 280 may be removed, thereby providing a process basis for the subsequent formation of the capacitor dielectric layer 262 and the upper electrode plate 263.

[0069] In some embodiments, it also includes: reference Figure 21 Conductive posts 290 are formed, and conductive posts 290 are in contact with second word lines 203. One conductive post 290 is in contact with one second word line 203. Thus, by providing signals to different conductive posts 290, an electrical signal can be provided to the word line 200 connected to that conductive post 290. In other words, different word lines 200 can be controlled by controlling different conductive posts 290.

[0070] This embodiment of the present disclosure forms a stacked structure 110 arranged at intervals along a first direction X on a substrate 100 and a first isolation layer 120 located between adjacent stacked structures 110. An initial active layer 140 is etched to form a first trench 160. An oxide semiconductor layer 170 is formed in the first trench 160. The oxide semiconductor layer 170 and the remaining initial active layer 140 are contacted to form an active structure 180, thereby improving the carrier mobility of the active structure 180 and increasing the transmission rate of the semiconductor structure.

[0071] Another embodiment of this disclosure also provides a semiconductor structure, which can be formed by some or all of the steps of the above-described semiconductor structure fabrication method. The same or corresponding parts can be referred to the above embodiments, and will not be repeated here. The semiconductor structure provided by the embodiments of this disclosure will be described below with reference to the accompanying drawings.

[0072] refer to Figure 12 , Figure 20 , Figure 21 and Figure 22 The semiconductor structure may include: a substrate 100; active structures 180 located on the surface of the substrate 100 and spaced apart along a first direction X and a second direction Y; the active structures 180 include an oxide semiconductor layer 170 and an initial active layer 140 arranged along a third direction Z, the oxide semiconductor layer 170 and the initial active layer 140 being in contact; the first direction X is perpendicular to the surface of the substrate 100, and the second direction Y is parallel to the surface of the substrate 100; a first isolation layer 120 located between adjacent active structures 180 in the first direction X, and the projections of the first isolation layer 120 and the active structures 180 on the surface of the substrate 100 overlap.

[0073] By setting the active structure 180 to include an oxide semiconductor layer 170 and an initial active layer 140, the mobility of carriers within the active structure 180 can be improved. By setting the oxide semiconductor layer 170 as the channel region of the active structure 180, the activity of carriers within the oxide semiconductor layer 170 is high, thereby improving the carrier mobility. By setting the first isolation layer 120 between adjacent active structures 180 in the first direction X, the active structures 180 can be spaced apart in the first direction X, thereby avoiding mutual interference between the active structures 180.

[0074] In some embodiments, the semiconductor structure further includes: a word line 200, which surrounds a portion of the surface of the oxide semiconductor layer 170 and extends along one of a first direction X and a second direction Y; a bit line 230, which surrounds a portion of the surface of the oxide semiconductor layer 170, is spaced from the word line 200, and extends along the other of the first direction X and the second direction Y; and a capacitor 260, which is in contact with the initial active layer 140 and extends along the first direction X and is spaced along the second direction Y and the third direction Z. By setting the word line 200 to surround a portion of the surface of the oxide semiconductor layer 170 of the active structure 180, the conduction of the active structure 180 can be controlled. By setting the bit line 230 to be in contact with the oxide semiconductor layer 170, the reading and writing of the semiconductor structure can be achieved through the bit line 230. By setting the capacitor 260 to be in contact with the initial active layer 140, the storage of the semiconductor structure can be achieved.

[0075] In some embodiments, the word line 200 extends along a second direction Y, and includes: a first word line 201 surrounding a portion of the surface of the oxide semiconductor layer 170; and a second word line 203 covering the sidewall of the first word line 201. The first word line 201 can increase the facing area between the word line 200 and the active structure 180, thereby improving the ability of the word line 200 to control the conduction of the active structure 180. The second word line 203 can be used for one-to-one connection with the conductive post 290.

[0076] In some embodiments, the length of the second word line 203 arranged along the first direction X decreases sequentially in the second direction Y. By setting the length of the second word line 203 to decrease sequentially, it can lead out the conductive post 290 and also avoid mutual interference between adjacent conductive posts 290.

[0077] In some embodiments, the projection of the second character line 203 onto the surface of the substrate 100 partially coincides with the projection of the first character line 201 onto the surface of the substrate 100. That is, the second character line 203 does not only contact the sidewall surface of the first character line 201, but a portion of the second character line 203 is located within the space formed by the first character line 201. By setting the second character line 203 to be partially located within the space formed by the first character line 201, the tightness of the connection between the second character line 203 and the first character line 201 can be improved.

[0078] In some embodiments, capacitor 260 may include: a lower electrode plate 261 covering a portion of the surface of the initial active layer 140; a capacitor dielectric layer 262 covering the surface of the lower electrode plate 261 and also covering a portion of the surface of the initial active layer 140 away from the lower electrode plate 261; and an upper electrode plate 263 covering the surface of the capacitor dielectric layer 262. The relative area between the lower electrode plate 261 and the upper electrode plate 263, the distance between the lower electrode plate 261 and the upper electrode plate 263, and the material of the capacitor dielectric layer 262 may all affect the capacitance of capacitor 260. Therefore, the relative area between the lower electrode plate 261 and the upper electrode plate 263, the distance between the lower electrode plate 261 and the upper electrode plate 263, and the material of the capacitor dielectric layer 262 can be set according to actual needs.

[0079] In some embodiments, capacitors 260 arranged along the first direction share an upper electrode plate 263. By forming capacitors 260 sharing an upper electrode plate 263, the space utilization of the semiconductor structure can be improved, and the formation of the semiconductor structure can also be facilitated.

[0080] In some embodiments, the thickness of the active structure 180 in the first direction X is 15–25 nm, for example, 18 nm, 20 nm, or 22 nm. By setting the thickness of the active structure 180 to 15–25 nm, the electrical performance of the semiconductor structure can be improved.

[0081] In some embodiments, the doping concentration of the initial active layer 140 is 1E19 to 1E22 cm⁻¹. -3 For example, 1E20cm -3 Or 1E21cm -3 It is understandable that the remaining initial active layer 140 can serve as the source or drain of the semiconductor structure, and the concentration of the initial active layer 140 corresponds to the number of charge carriers in the source or drain of the semiconductor structure. This can be achieved by setting the doping concentration of the initial active layer 140 to 1E19–1E22 cm⁻¹. -3 It can increase the number of charge carriers in the source or drain, thereby improving the performance of the semiconductor structure.

[0082] In some embodiments, the semiconductor structure further includes a second isolation layer 190, which is located between active structures 180 spaced apart along the second direction Y. The active structures 180 spaced apart along the second direction Y can be isolated by the second isolation layer 190, thereby preventing mutual interference between the active structures 180 spaced apart along the second direction Y.

[0083] In some embodiments, the top surface of the conductive post 290 can be flush, that is, the length of the conductive post 290 can be unequal. Along the first direction X, the length of the word line 200 decreases sequentially, and the length of the conductive post 290 increases sequentially. That is, the conductive post 290 connected to the word line 200 located on the bottom surface has the longest length. By setting the conductive post 290 with its top surface flush, it can provide electrical signals to the word line 200 through its top surface, thereby controlling the reading and writing of the semiconductor structure.

[0084] This disclosure provides a semiconductor structure including: a substrate 100, an active structure 180 located on the surface of the substrate, the active structure 180 including an oxide semiconductor layer 170 and an initial active layer 140, the oxide semiconductor layer 170 and the initial active layer 140 being in contact connection, and a first isolation layer 120 located between adjacent active structures 180 in a first direction X. By providing the active structure 180 including the oxide semiconductor layer 170 and the initial active layer 140, the carrier mobility of the active structure 180 can be improved through the oxide semiconductor layer 170, thereby improving the performance of the semiconductor structure.

[0085] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A stacked structure arranged at intervals along a first direction and a first isolation layer located between adjacent stacked structures are formed on the surface of the substrate. The stacked structure includes a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer. The initial active layer is etched to form a first trench; An oxide semiconductor layer is formed in the first trench, and the oxide semiconductor layer is in contact with the retained initial active layer; Etching portions of the oxide semiconductor layer and the retained initial active layer to form an active structure arranged in an array along the first and second directions; The first direction is perpendicular to the substrate surface, and the second direction is parallel to the substrate surface.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After forming the active structure, the method further includes: A word line is formed, the word line being located on at least a portion of the surface of the oxide semiconductor layer of the active structure, and the word line extending along one of the first direction and the second direction; A bit line is formed, the bit line being connected to the oxide semiconductor layer in contact, the bit line being spaced from the word line, and the bit line extending along the other of the first direction and the second direction.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The character line extends along the second direction, and the method for forming the character line includes: A first word line and a second word line are formed, wherein the first word line covers the top surface of the plurality of oxide semiconductor layers; and the second word line covers the bottom surface of the plurality of oxide semiconductor layers. A third character line is formed, which covers the sidewalls of the first character line and the second character line.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The method for forming the first word line and the second word line includes: etching the first interlayer dielectric layer and the second interlayer dielectric layer of the stacked structure to form a first groove; A gate dielectric layer is formed on the surface of the first groove; The first word line and the second word line are formed on the surface of the gate dielectric layer, and the gate dielectric layer, the first word line and the second word line fill the first groove.

5. The method for fabricating a semiconductor structure according to claim 3, characterized in that, The method for forming the third character line includes: The stacked structure is etched along the second direction to form a second groove, the second groove exposing the sidewalls of the first letter line and the second letter line; A third initial character line is formed, which fills the second groove; The third initial character line is etched to form the third character line, and the length of the third character line arranged along the first direction decreases sequentially in the second direction.

6. The method for fabricating a semiconductor structure according to claim 2, characterized in that, The method of forming the bit line includes: A third isolation layer is formed; the third isolation layer covers a portion of the surface of the oxide semiconductor layer, and the third isolation layer is in contact with the sidewall of the word line arranged in a third direction; The bit line is formed, and the bit line is in contact with the third-direction sidewall of the third isolation layer, and the bit line covers the oxide semiconductor layer.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The materials of the oxide semiconductor layer include indium gallium zinc oxide or zinc tin oxide.

8. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The etching portion of the oxide semiconductor layer includes: etching the stacked structure to form the active structures spaced apart along the second direction; A second isolation layer is formed between the active structures spaced apart along the second direction.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Also includes: The first interlayer dielectric layer, the first isolation layer, and the second interlayer dielectric layer are etched to form a third groove, the third groove exposing a portion of the surface of the initial active layer; A lower electrode plate is formed, which covers a portion of the surface of the initial active layer that is retained. A capacitor dielectric layer is formed, which covers the surface of the lower electrode plate and the surface of the initial active layer that is partially retained; An upper electrode plate is formed, which covers the surface of the capacitor dielectric layer. The lower electrode plate, the capacitor dielectric layer, and the upper electrode plate constitute a capacitor.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The step of forming the lower electrode plate includes: forming a fourth isolation layer, the fourth isolation layer covering the sidewall surface of the third groove arranged in a third direction; An initial lower electrode plate is formed, which covers the surface of the fourth isolation layer and the surface of the retained initial active layer; Remove the fourth isolation layer and the initial lower electrode plate covering the surface of the fourth isolation layer, leaving the remaining initial lower electrode plate as the lower electrode plate.

11. A semiconductor structure, characterized in that, The semiconductor structure is fabricated according to any one of claims 1-10, comprising: Base; An active structure is located on the surface of the substrate and is arranged at intervals along a first direction and a second direction; the active structure includes an oxide semiconductor layer and an initial active layer arranged along a third direction, the oxide semiconductor layer and the initial active layer being in contact and connected; the first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate; A first isolation layer is located between adjacent active structures in the first direction, and the projections of the first isolation layer and the active structures on the substrate surface overlap.

12. The semiconductor structure according to claim 11, characterized in that, Also includes: A word line, the word line being located on at least a portion of the surface of the oxide semiconductor layer of the active structure, and the word line extending along one of the first direction and the second direction; Bit lines are contacted and connected to the oxide semiconductor layer, the bit lines are spaced apart from the word lines, and the bit lines extend along the other of the first direction and the second direction; A capacitor is in contact with the initial active layer, and the capacitor extends along the first direction and is spaced apart along the second direction and the third direction.

13. The semiconductor structure according to claim 12, characterized in that, The capacitor includes: A lower electrode plate that covers a portion of the surface of the initial active layer; A capacitor dielectric layer covers the surface of the lower electrode plate, and the capacitor dielectric layer also covers a portion of the surface of the initial active layer away from the lower electrode plate; An upper electrode plate that covers the surface of the capacitor dielectric layer.

14. The semiconductor structure according to claim 12, characterized in that, The character line extends along the second direction, and the character line includes: A first word line, the first word line covering the top surface of the plurality of oxide semiconductor layers; The second word line covers the bottom surface of the plurality of oxide semiconductor layers; The third character line covers the sidewalls of the first character line and the second character line.

15. The semiconductor structure according to claim 14, characterized in that, The projection of the third character line on the substrate surface coincides with the projection of the first character line on the substrate surface.

16. The method for fabricating a semiconductor structure according to claim 11, characterized in that, In the first direction, the thickness of the active structure is 15~25nm.

17. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The initial active layer has a doping concentration of 1E19~1E22 cm⁻³.

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