Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device includes: a silicon carbide substrate having a first main surface; an interlayer insulating film covering the first main surface; and gate pads and source pads disposed on the interlayer insulating film. When viewed from a direction perpendicular to the first main surface, the silicon carbide substrate has: a first region including a plurality of unit cells; a second region overlapping the gate pads; and a third region connected to the second region. Each of the plurality of unit cells has: a drift region having a first conductivity type; a body region having a second conductivity type different from the first conductivity type; a source region disposed on the first main surface, separated from the drift region by the body region, and having the first conductivity type; a contact region disposed on the first main surface, electrically connected to the body region, and having the second conductivity type; a gate electrode electrically connected to the gate pads; and a gate insulating film. The third region is disposed between the drift region, the body region, the source region, and the gate electrode. The second region has a first semiconductor region with a second conductivity type. The third region has a second semiconductor region with a second conductivity type. The first semiconductor region and the second semiconductor region are connected to each other in the first main surface. A first contact hole reaching the source region and the contact region and a second contact hole reaching the second semiconductor region are formed on the interlayer insulating film. The source pad is electrically connected to the source region and the contact region through the first contact hole and to the second semiconductor region through the second contact hole. When viewed from a cross-section parallel to the first main surface, the second dimension of the second contact hole in the short side direction is larger than the first dimension of the first contact hole in the short side direction.

Description

Technical Field

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2021-150122, filed on September 15, 2021, and incorporates all the contents described in the said Japanese application. Background Technology

[0003] A silicon carbide semiconductor device for suppressing insulation breakdown of the insulating film under the gate pad has been disclosed (e.g., Patent Document 1).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: International Publication No. 2018 / 055719 Summary of the Invention

[0007] The silicon carbide semiconductor device disclosed herein comprises: a silicon carbide substrate having a first main surface; an interlayer insulating film covering the first main surface; and gate pads and source pads disposed on the interlayer insulating film. When viewed from a direction perpendicular to the first main surface, the silicon carbide substrate has: a first region comprising a plurality of unit cells; a second region overlapping the gate pads; and a third region connected to the second region. Each of the plurality of unit cells comprises: a drift region having a first conductivity type; a body region having a second conductivity type different from the first conductivity type; a source region disposed on the first main surface, separated from the drift region by the body region, and having the first conductivity type; a contact region disposed on the first main surface, electrically connected to the body region, and having the second conductivity type; a gate electrode electrically connected to the gate pads; and a gate insulating film. A third region is disposed between the drift region, the body region, the source region, and the gate electrode. The second region has a first semiconductor region with a second conductivity type. The third region has a second semiconductor region with a second conductivity type. The first semiconductor region and the second semiconductor region are connected to each other in the first main surface. A first contact hole reaching the source region and the contact region and a second contact hole reaching the second semiconductor region are formed in the interlayer insulating film. The source pad is electrically connected to the source region and the contact region through the first contact hole and to the second semiconductor region through the second contact hole. When viewed from a cross-section parallel to the first main surface, the second dimension of the second contact hole in the short side direction is larger than the first dimension of the first contact hole in the short side direction. Attached Figure Description

[0008] Figure 1 This is a top view showing the silicon carbide semiconductor device according to the first embodiment.

[0009] Figure 2 This is a diagram showing the regions within the silicon carbide substrate of the silicon carbide semiconductor device according to the first embodiment.

[0010] Figure 3 It is shown through the passivation film, gate pads and source pads. Figure 1 and Figure 2 Top view of region 221 in the image.

[0011] Figure 4 It is shown Figure 1 and Figure 2 A top view of the structure of the first main surface of the silicon carbide substrate in region 221.

[0012] Figure 5 It is shown through the passivation film, gate pads and source pads. Figure 1 and Figure 2 Top view of area 222 in the image.

[0013] Figure 6 It is shown through the passivation film, gate pads and source pads. Figure 1 and Figure 2 Top view of area 222 in the image.

[0014] Figure 7 This is a cross-sectional view showing the silicon carbide semiconductor device according to the first embodiment.

[0015] Figure 8 It is a cross-sectional view showing the structure of a unit cell.

[0016] Figure 9 This is a cross-sectional view showing the silicon carbide semiconductor device according to the second embodiment.

[0017] Figure 10 This is a top view showing the silicon carbide semiconductor device according to the third embodiment.

[0018] Figure 11 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the third embodiment.

[0019] Figure 12 This is a cross-sectional view (1) showing the silicon carbide semiconductor device according to the third embodiment.

[0020] Figure 13 This is a cross-sectional view (2) showing the silicon carbide semiconductor device according to the third embodiment.

[0021] Figure 14 This is a top view showing the silicon carbide semiconductor device according to the fourth embodiment.

[0022] Figure 15 This is a diagram showing the regions within the silicon carbide substrate of the silicon carbide semiconductor device according to the fourth embodiment.

[0023] Figure 16 This is a cross-sectional view showing the silicon carbide semiconductor device according to the fourth embodiment.

[0024] Figure 17 This is a top view showing the silicon carbide semiconductor device according to the fifth embodiment.

[0025] Figure 18 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the fifth embodiment.

[0026] Figure 19 This is a top view showing the silicon carbide semiconductor device according to the sixth embodiment.

[0027] Figure 20 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the sixth embodiment.

[0028] Figure 21 This is a top view showing the silicon carbide semiconductor device according to the seventh embodiment.

[0029] Figure 22 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the seventh embodiment.

[0030] Figure 23 This is a top view showing the silicon carbide semiconductor device according to the eighth embodiment.

[0031] Figure 24 It is shown Figure 23 A top view of the structure of the first main surface of the silicon carbide substrate in region 223.

[0032] Figure 25 This is a cross-sectional view (1) showing the silicon carbide semiconductor device according to the eighth embodiment.

[0033] Figure 26 This is a cross-sectional view (2) showing the silicon carbide semiconductor device according to the eighth embodiment.

[0034] Figure 27 This is a cross-sectional view (3) showing the silicon carbide semiconductor device according to the eighth embodiment.

[0035] Figure 28This is a top view showing a modified example of the first region. Detailed Implementation

[0036] [The technical problem this disclosure aims to solve]

[0037] In the silicon carbide semiconductor device described in Patent Document 1, an electric field is easily concentrated in the interlayer insulating film during a surge. Such electric field concentration may lead to damage.

[0038] The purpose of this disclosure is to provide a silicon carbide semiconductor device capable of mitigating electric field concentration in interlayer insulating films.

[0039] [The Effects of This Disclosure]

[0040] According to this disclosure, the electric field concentration of the interlayer insulating film can be mitigated.

[0041] The following describes the implementation method.

[0042] [Description of embodiments of this disclosure]

[0043] First, embodiments of this disclosure will be described. In the crystallographic descriptions in this specification and accompanying drawings, individual crystal phases are represented by [], groups of crystal phases by <>, individual planes by (), and groups of planes by {}. Furthermore, while negative crystallographic indices are typically represented by placing a "-" (hyphen) above the number, in this specification, a negative sign is placed before the number.

[0044] [1] A silicon carbide semiconductor device according to one aspect of this disclosure includes: a silicon carbide substrate having a first main surface; an interlayer insulating film covering the first main surface; and gate pads and source pads disposed on the interlayer insulating film. When viewed from a direction perpendicular to the first main surface, the silicon carbide substrate has: a first region including a plurality of unit cells; a second region overlapping the gate pads; and a third region connected to the second region. The plurality of unit cells each have: a drift region having a first conductivity type; a body region having a second conductivity type different from the first conductivity type; a source region disposed on the first main surface, separated from the drift region by the body region, and having the first conductivity type; a contact region disposed on the first main surface, electrically connected to the body region, and having the second conductivity type; a gate electrode electrically connected to the gate pads; and a gate... An interlayer insulating film is disposed between the drift region, the body region, the source region, and the gate electrode. The second region has a first semiconductor region with a second conductivity type. The third region has a second semiconductor region with a second conductivity type. The first semiconductor region and the second semiconductor region are connected to each other in the first main surface. A first contact hole reaching the source region and the contact region, and a second contact hole reaching the second semiconductor region are formed in the interlayer insulating film. The source pad is electrically connected to the source region and the contact region through the first contact hole and to the second semiconductor region through the second contact hole. When viewed from a cross-section parallel to the first main surface, the second dimension of the second contact hole in the short side direction is larger than the first dimension of the first contact hole in the short side direction.

[0045] A third region connected to the second region is provided, and the first semiconductor region and the second semiconductor region are connected in the first main surface. Furthermore, when viewed from a cross-section parallel to the first main surface, the second dimension of the second contact hole in the short side direction is larger than the first dimension of the first contact hole in the short side direction. Therefore, the contact resistance between the source pad and the second semiconductor region can be reduced, and even in the event of a surge, the electric field concentration towards the interlayer insulating film in the second region can be mitigated.

[0046] [2] In [1], the contact area and the second semiconductor region may also be connected to each other in the first main surface. In this case, it is easy to control the contact area and the second semiconductor region to the same potential.

[0047] [3] In [1] or [2], it may also have: an active region including the plurality of unit cells; and a terminal region disposed around the active region, the terminal region having a third semiconductor region having a second conductivity type, the second semiconductor region including a fourth semiconductor region disposed between the gate pad and the terminal region when viewed from a direction perpendicular to the first main surface, connected to the first semiconductor region and the third semiconductor region in the first main surface, the concentration of impurities of the second conductivity type in the third semiconductor region being lower than the concentration of impurities of the second conductivity type in the fourth semiconductor region, and the second contact hole including a third contact hole reaching the fourth semiconductor region. In this case, the electric field concentration towards the interlayer insulating film near the terminal region can be mitigated.

[0048] [4] In [3], a field insulating film may also be provided, which is disposed between the first semiconductor region, the fourth semiconductor region, the third semiconductor region, and the interlayer insulating film. A fourth contact hole is formed in the field insulating film to reach the fourth semiconductor region. Inside the fourth contact hole, the interlayer insulating film is in contact with the fourth semiconductor region, and the third contact hole is located inside the fourth contact hole. In this case, the electric field concentration in the interlayer insulating film can be further mitigated.

[0049] [5] In [3] or [4], it may also have a source channel electrically connected to the source pad and electrically connected to the fourth semiconductor region via the third contact hole. When viewed from a cross-section parallel to the first main surface, the side of the source channel away from the gate pad is located on the boundary line between the third semiconductor region and the fourth semiconductor region, or closer to the gate pad than the boundary line. In this case, it is easier to mitigate the electric field concentration in the interlayer insulating film below the source channel.

[0050] [6] In any of [3] to [5], it may also include: a first gate channel electrically connected to the gate pad and extending in a first direction parallel to the first main surface, and configured to be closer to the terminal region than the gate pad; and a second gate channel electrically connected to the gate pad, extending in the first direction and away from the first gate channel, and configured to be closer to the terminal region than the gate pad, the fourth semiconductor region including a fifth semiconductor region, which, when viewed from a direction perpendicular to the first main surface, is disposed between the first gate channel and the second gate channel, and is connected to the first semiconductor region in the first main surface, the second contact hole including a fifth contact hole reaching the fifth semiconductor region. In this case, the contact resistance between the source pad and the fourth semiconductor region can be further reduced near the gate pad.

[0051] [7] In any of [3] to [5], it may also be that a third gate channel is provided, which is electrically connected to the gate pad and extends in a first direction parallel to the first main surface, and is configured to be closer to the terminal region than the gate pad. The fourth semiconductor region includes a sixth semiconductor region, which, when viewed from a direction perpendicular to the first main surface, is disposed between the gate pad and the third gate channel and is connected to the first semiconductor region in the first main surface. The second contact hole includes a sixth contact hole reaching the sixth semiconductor region. In this case, the degree of freedom in the configuration of the gate pad can be increased.

[0052] [8] In any of [3] to [7], the plurality of unit cells may extend in a first direction parallel to the first main surface and be arranged in a second direction perpendicular to the first direction. The gate pad has a planar shape that is rectangular with the first direction as its long side when viewed from a direction perpendicular to the first main surface. The second semiconductor region includes a seventh semiconductor region disposed in the second direction, sandwiching the gate pad between the gate pad and the fourth semiconductor region. The second contact hole includes a seventh contact hole reaching the seventh semiconductor region. In this case, the contact resistance between the source pad and the second semiconductor region can be further reduced.

[0053] [9] In [8], when viewed from a cross-section parallel to the first main surface, the third dimension in the short side direction of the third contact hole can also be equal to the fourth dimension in the short side direction of the seventh contact hole. In this case, the current generated in the first semiconductor region can easily flow equally to the third contact hole and the seventh contact hole.

[0054]

[10] In [8] or [9], the fifth dimension of the third contact hole in the first direction may also be larger than the sixth dimension of the gate pad in the first direction. In this case, it is easier to reduce the contact resistance.

[0055]

[11] In any of [8] to

[10] , the silicon carbide substrate may also have a rectangular shape in the top view having a first and a second side parallel to each other, and a third and a fourth side perpendicular to the first and the second sides. The silicon carbide semiconductor device has: a fourth gate channel extending along the first side; a fifth gate channel extending along the second side; and a sixth gate channel extending from the gate pad toward the fourth side between the fourth and the fifth gate channels, wherein the fourth, the fifth, and the sixth gate channels are electrically connected to the gate pad. In this case, it is easy to apply a gate voltage equally to each unit cell from the fourth, fifth, and sixth gate channels.

[0056]

[12] In

[11] , the seventh dimension of the seventh contact hole, in the portion between the fourth gate channel and the sixth gate channel when viewed from above, in the first direction, may also be more than 1 / 2 of the distance between the fourth gate channel and the sixth gate channel. In this case, in the portion between the fourth gate channel and the sixth gate channel, the dimension in the first direction of the unit cell disposed on the extension line of the seventh contact hole is less than 1 / 2 of the distance between the fourth gate channel and the sixth gate channel. Therefore, it is easy to apply the same gate voltage as other unit cells to this unit cell.

[0057]

[13] In

[11] or

[12] , the eighth dimension of the seventh contact hole in the first direction of the portion between the fifth gate channel and the sixth gate channel when viewed from above may also be more than 1 / 2 of the distance between the fifth gate channel and the sixth gate channel. In this case, the dimension of the unit cell disposed on the extension line of the seventh contact hole in the portion between the fifth gate channel and the sixth gate channel in the first direction is less than 1 / 2 of the distance between the fifth gate channel and the sixth gate channel. Therefore, it is easy to apply the same gate voltage as other unit cells to this unit cell.

[0058]

[14] In any of

[11] to

[13] , among the plurality of unit cells located closer to the fourth side compared to the seventh semiconductor region, a portion of the unit cells located closer to the third side may also be further away from the sixth gate channel in the second direction than the remaining unit cells. In this case, the electric field concentration near the sixth gate channel can be mitigated.

[0059] [Implementation of this disclosure]

[0060] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. It should be noted that in this specification and accompanying drawings, elements having substantially the same functional structure are sometimes omitted from repeated descriptions by using the same reference numerals. In this specification and accompanying drawings, the X1-X2 direction, Y1-Y2 direction, and Z1-Z2 direction are defined as mutually orthogonal directions. A surface including the X1-X2 and Y1-Y2 directions is referred to as the XY surface, a surface including the Y1-Y2 and Z1-Z2 directions is referred to as the YZ surface, and a surface including the Z1-Z2 and X1-X2 directions is referred to as the ZX surface. It should be noted that, for convenience, the Z1-Z2 direction is defined as the vertical direction, the Z1 side as the upper side, and the Z2 side as the lower side. Furthermore, top view refers to viewing the object from the Z1 side, and planar shape refers to the shape of the object when viewed from the Z1 side.

[0061] (First Implementation)

[0062] The first embodiment will be described. The first embodiment relates to a so-called vertical MOSFET (silicon carbide semiconductor device). Figure 1 This is a top view showing the silicon carbide semiconductor device according to the first embodiment. Figure 2 This is a diagram showing the regions within the silicon carbide substrate of the silicon carbide semiconductor device according to the first embodiment. Figure 3 It is shown through the passivation film, gate pads and source pads. Figure 1 and Figure 2 Top view of region 221 in the image. Figure 4 It is shown Figure 2 A top view of the structure of the first main surface of the silicon carbide substrate in region 221. Figure 5 It is shown through the passivation film, gate pads and source pads. Figure 2 Top view of area 222 in the image. Figure 6 It is shown through the passivation film, gate pads and source pads. Figure 2 Top view of area 222 in the image. Figure 7 This is a cross-sectional view showing the silicon carbide semiconductor device according to the first embodiment. Figure 7 Equivalent to along Figure 1 and Figure 2 A cross-sectional view of line VII-VII in the diagram. Figure 8 This is a cross-sectional view showing the structure of a unit cell. In Figure 7 and Figure 8 In this paper, the passivation film is omitted.

[0063] like Figures 1 to 8 As shown, the MOSFET 201 according to the first embodiment has a silicon carbide substrate 10, a gate insulating film 43, a gate electrode 51, an interlayer insulating film 44, a contact electrode 52, a passivation film 80, and a drain electrode 53. The MOSFET 201 further has a gate pad 61, a source pad 62, gate channels (gate wiring) 61A, 61B, 61C, 61D, 61E, and a source channel (source wiring) 62C. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 20 and a silicon carbide epitaxial layer 30 located on the silicon carbide single crystal substrate 20. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 30 constitutes the first main surface 1, and the silicon carbide single crystal substrate 20 constitutes the second main surface 2. The silicon carbide single crystal substrate 20 and the silicon carbide epitaxial layer 30 are, for example, made of polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 20 contains, for example, n-type impurities such as nitrogen (N) and has n-type (first conductivity type).

[0064] The first principal surface 1 is the {0001} surface or a surface with an inclination angle of less than 8° in the inclination direction. Preferably, the first principal surface 1 is the (000-1) surface or a surface with an inclination angle of less than 8° in the inclination direction. The inclination direction can be, for example, the <11-20> direction or the <1-100> direction. The inclination angle can be, for example, more than 1° or more than 2°. The inclination angle can be less than 6° or less than 4°.

[0065] When viewed from above, the silicon carbide substrate 10 has a rectangular shape with a first side 91 and a second side 92 that are parallel to each other, and a third side 93 and a fourth side 94 that are perpendicular to the first side 91 and the second side 92. The first side 91 and the second side 92 are parallel to the Y1-Y2 direction, and the third side 93 and the fourth side 94 are parallel to the X1-X2 direction. The first side 91 is located on the X2 side of the second side 92, and the second side 92 is located on the X1 side of the first side 91. The third side 93 is located on the Y1 side of the fourth side 94, and the fourth side 94 is located on the Y2 side of the third side 93.

[0066] The silicon carbide substrate 10 has an active region 41 and a terminal region 42 disposed around the active region 41 when viewed from above.

[0067] The active region 41 has a first region 101, a second region 102, and a third region 103. The first region 101 is the region where a plurality of unit cells 40 are disposed. The second region 102 is the region that overlaps with the gate pad 61 when viewed from above. The unit cells 40 are arranged in the Y1-Y2 direction with the X1-X2 direction as their length direction. The dimensions of each unit cell 40 in the Y1-Y2 direction are the same. Each unit cell 40 has a set of gate trenches and gate electrodes. The unit cells 40 are arranged at a certain pitch P1 in the Y1-Y2 direction. The X1-X2 direction is an example of the first direction, and the Y1-Y2 direction is an example of the second direction.

[0068] The silicon carbide epitaxial layer 30 mainly comprises a drift region 31, a body region 32, a source region 33, a contact region 34, a buried region 35, a buried junction termination extension (JTE) region 36, and a surface JTE region 37. The drift region 31 spans the active region 41 and the termination region 42. The body region 32, source region 33, contact region 34, and buried region 35 are located within the active region 41. The buried JTE region 36 and the surface JTE region 37 are located within the termination region 42. A portion of the contact region 34 and the buried region 35 may also be located within the termination region 42.

[0069] A drift region 31 is disposed on a silicon carbide single crystal substrate 20. The drift region 31 is located closer to the first main surface 1 than the silicon carbide single crystal substrate 20. The drift region 31 may also be connected to the silicon carbide single crystal substrate 20. The drift region 31 may contain, for example, n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity.

[0070] The body region 32 is disposed on the drift region 31. The body region 32 contains, for example, p-type impurities such as aluminum (Al) and has p-type conductivity (second conductivity type). The body region 32 is located closer to the first main surface 1 than the drift region 31. The drift region 31 is located closer to the second main surface 2 than the body region 32. The body region 32 is connected to the drift region 31.

[0071] Source region 33 is disposed on body region 32. Source region 33 is separated from drift region 31 by body region 32. Source region 33 contains, for example, n-type impurities such as nitrogen or phosphorus, and has n-type conductivity. Source region 33 is located closer to the first main surface 1 than body region 32. Body region 32 is located closer to the second main surface 2 than source region 33. Source region 33 is connected to body region 32. Source region 33 constitutes the first main surface 1. Source region 33 is covered by gate insulating film 43. Source region 33 is directly connected to gate insulating film 43.

[0072] Contact region 34 contains, for example, p-type impurities such as aluminum, and has p-type conductivity. The concentration of p-type impurities in contact region 34 is, for example, higher than the concentration of p-type impurities in body region 32. Contact region 34 penetrates source region 33 and body region 32. Contact region 34 is in contact with body region 32. Contact region 34 constitutes the first main surface 1.

[0073] like Figure 8 As shown, within the first region 101, a gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided on the first main surface 1. The side surface 3 penetrates the source region 33 and the body region 32 to reach the drift region 31. The bottom surface 4 is connected to the side surface 3. The source region 33, the body region 32, and the drift region 31 are in contact with the side surface 3. The bottom surface 4 is located in the drift region 31. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 relative to the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may also be, for example, 50° or more. The angle θ1 may also be, for example, 60° or less. Preferably, the side surface 3 has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that can obtain excellent mobility.

[0074] When viewed from above, the gate trenches 5 extend in the X1-X2 direction, parallel to the first main surface 1. Furthermore, when viewed from above, the multiple gate trenches 5 are arranged at certain intervals in the Y1-Y2 direction. The gate trenches 5 are not provided in the second region 102 or the third region 103.

[0075] The buried region 35 contains, for example, p-type impurities such as aluminum and has p-type conductivity. The buried region 35 is located closer to the second main surface 2 than the contact region 34. The contact region 34 is located closer to the first main surface 1 than the buried region 35. The buried region 35 is in contact with the contact region 34. The buried region 35 is formed at a depth deeper than the gate trench 5. The upper surface of the buried region 35 is located closer to the second main surface 2 than the bottom surface 4 of the gate trench 5.

[0076] The embedded JTE region 36 is connected to the embedded region 35 in a direction parallel to the first main surface 1. The embedded JTE region 36 forms a ring shape when viewed from above. The embedded JTE region 36 contains, for example, p-type impurities such as aluminum and has p-type conductivity. The embedded JTE region 36 is located away from the first main surface 1 and the second main surface 2. The upper end face of the embedded JTE region 36 is connected to the lower end face of the contact region 34.

[0077] Surface JTE region 37 is in contact with contact region 34 in a direction parallel to the first main surface 1. Surface JTE region 37 is formed in a ring shape when viewed from above. Surface JTE region 37 contains, for example, p-type impurities such as aluminum and has p-type conductivity. Surface JTE region 37 is disposed above buried JTE region 36. Surface JTE region 37 is located away from buried JTE region 36. Surface JTE region 37 is located closer to the first main surface 1 than buried JTE region 36. Buried JTE region 36 is located closer to the second main surface 2 than surface JTE region 37. Surface JTE region 37 constitutes the first main surface 1. A portion of drift region 31 exists between surface JTE region 37 and buried JTE region 36. For example, the concentration of p-type impurities in surface JTE region 37 is lower than the concentration of p-type impurities in contact region 34. Surface JTE region 37 is an example of third semiconductor region 113.

[0078] The gate insulating film 43 is, for example, an oxide film. The gate insulating film 43 is, for example, made of a material containing silicon dioxide. The gate insulating film 43 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 43 is in contact with the drift region 31 on the bottom surface 4. The gate insulating film 43 is in contact with the source region 33, the body region 32, and the drift region 31 on the side surface 3, respectively. The gate insulating film 43 may also be in contact with the source region 33, the contact region 34, and the surface JTE region 37 in the first main surface 1.

[0079] A gate electrode 51 is disposed on a gate insulating film 43. The gate electrode 51 is, for example, made of polysilicon (polySi) containing conductive impurities. A portion of the gate electrode 51 is disposed inside the gate trench 5. A portion of the gate electrode 51 is disposed above the first main surface 1.

[0080] An interlayer insulating film 44 is disposed in contact with the gate electrode 51 and the gate insulating film 43. The interlayer insulating film 44 is, for example, an oxide film. The interlayer insulating film 44 is, for example, made of a material containing silicon dioxide. The interlayer insulating film 44 electrically insulates the gate electrode 51 from the contact electrode 52 and the source pad 62.

[0081] A contact hole 70 for the gate electrode is formed on the interlayer insulating film 44. The gate electrode 51 is exposed from the interlayer insulating film 44 through the contact hole 70.

[0082] The gate pad 61 is disposed on the interlayer insulating film 44 and is connected to the gate electrode 51 within the contact hole 70. The gate pad 61 is made of, for example, a material containing aluminum.

[0083] A contact hole 71 for the active electrode is formed on the interlayer insulating film 44 and the gate insulating film 43. Through the contact hole 71, the source region 33 and the contact region 34 in the first region 101 are exposed from the interlayer insulating film 44 and the gate insulating film 43. The contact hole 71 is an example of a first contact hole.

[0084] Contact holes 72 are formed on the interlayer insulating film 44 and the gate insulating film 43. Through the contact holes 72, the contact region 34 within the third region 103 is exposed from the interlayer insulating film 44 and the gate insulating film 43. A portion of the source region 33 can also be exposed through the contact holes 72. When viewed from a cross-section parallel to the first main surface 1, the dimension W2 of the contact hole 72 in the short side direction is larger than the dimension W1 of the contact hole 71 in the short side direction. Dimension W1 is the dimension of the contact hole 71 in the Y1-Y2 direction, and dimension W2 is the dimension of the contact hole 72 in the Y1-Y2 direction. The contact hole 72 is an example of a second contact hole. Dimension W1 is an example of a first dimension, and dimension W2 is an example of a second dimension.

[0085] Contact electrode 52 is connected to source region 33 and contact region 34 within contact hole 71. Contact electrode 52 is made of, for example, a material containing nickel silicide (NiSi). Contact electrode 52 may also be made of a material containing titanium, aluminum, and silicon. Contact electrode 52 makes ohmic contact with source region 33 and contact region 34.

[0086] Source pad 62 is disposed on the interlayer insulating film 44 and is connected to contact electrode 52 within contact hole 71. Source pad 62 is, for example, made of a material containing aluminum. Source pad 62 may also include a barrier metal film (not shown) covering the surface of interlayer insulating film 44. Figure 1 As shown, the source pad 62 may also include source pads 62A and 62B. For example, source pad 62A is located on the X2 side of the center in the X1-X2 direction of the silicon carbide substrate 10, and source pad 62B is located on the X1 side of the center in the X1-X2 direction of the silicon carbide substrate 10.

[0087] Gate pad 61 is located on the Y1 side of source pad 62, and its planar shape is rectangular. For example, the dimension of gate pad 61 in the X1-X2 direction is larger than its dimension in the Y1-Y2 direction. Source pad 62 is located on the Y2 side of gate pad 61, and its planar shape is rectangular. The distance of gate pad 61 from the first side 91 is the same as its distance from the second side 92. The distance of gate pad 61 from the third side 93 is smaller than its distance from the fourth side 94. The distance of source pad 62 from the first side 91 is the same as its distance from the second side 92. The distance of source pad 62 from the third side 93 is larger than its distance from the fourth side 94. The dimension of the gate pad 61 in the X1-X2 direction can also be smaller than the dimension of the source pad 62 in the X1-X2 direction, and the dimension of the gate pad 61 in the Y1-Y2 direction can also be smaller than the dimension of the source pad 62 in the Y1-Y2 direction. The source pad 62 is configured such that it includes a centerline that divides the silicon carbide substrate 10 in two in the Y1-Y2 direction when viewed from above.

[0088] Gate channel 61A extends along the first side 91 in the Y1-Y2 direction. Gate channel 61B extends along the second side 92 in the Y1-Y2 direction. Gate channels 61C and 61D are connected to gate pad 61. Gate channels 61C and 61D extend along the third side 93 in the X1-X2 direction. Gate channel 61C is located on the X2 side of gate pad 61, and gate channel 61D is located on the X1 side of gate pad 61. The Y1 side end of gate channel 61A is connected to the X2 side end of gate channel 61C. The Y1 side end of gate channel 61B is connected to the X1 side end of gate channel 61D. Gate channel 61A is located on the X2 side of source pad 62A, and gate channel 61B is located on the X1 side of source pad 62B. As shown, gate pad 61 is continuous with gate channels 61C and 61D, gate channel 61A is continuous with gate channel 61C, and gate channel 61B is continuous with gate channel 61D. Gate channels 61A and 61B are located away from gate pad 61 in the X1-X2 direction. Gate channel 61E is connected to gate pad 61 and extends in the Y1-Y2 direction between source pads 62A and 62B. Gate channels 61A, 61B, 61C, 61D, and 61E are made of the same material as gate pad 61. Gate channel 61C is an example of a first gate channel, and gate channel 61D is an example of a second gate channel. Gate channel 61A is an example of a fourth gate channel, gate channel 61B is an example of a fifth gate channel, and gate channel 61E is an example of a sixth gate channel.

[0089] When viewed from above, the source channel 62C is arranged in a ring shape outside the source pad 62 and the gate channels 61A, 61B, 61C, and 61D. The source channel 62C is connected to and continuous with the source pad 62. The source channel 62C is made of the same material as the source pad 62. The contact holes for the source channel 62C are formed in a ring shape on the interlayer insulating film 44 and the gate insulating film 43, and the source channel 62C is electrically connected to the contact area 34 through the ring-shaped contact holes. When viewed from a cross-section parallel to the first main surface 1, it is preferable that the side 64 of the source channel 62C away from the gate pad 61 is located on the boundary line between the contact area 34 and the surface JTE region 37, or closer to the gate pad 61 than this boundary line. This is because it is easier to mitigate the electric field concentration towards the interlayer insulating film 44 below the source channel 62C.

[0090] A passivation film 80 covers the gate pad 61, the source pad 62, and the interlayer insulating film 44. The passivation film 80 is in contact with the gate pad 61, the source pad 62, and the interlayer insulating film 44. The passivation film 80 also covers gate channels 61A, 61B, 61C, 61D, and 61E, and the source channel 62C. The passivation film 80 is made, for example, of a material containing silicon nitride or polyimide. An opening 81 is formed on the passivation film 80 that exposes a portion of the upper surface of the gate pad 61, and an opening 82 that exposes a portion of the upper surface of the source pad 62.

[0091] The drain electrode 53 is connected to the second main surface 2. The drain electrode 53 is connected to the silicon carbide single crystal substrate 20 on the second main surface 2. The drain electrode 53 is electrically connected to the drift region 31. The drain electrode 53 is, for example, made of a material containing nickel silicide. The drain electrode 53 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 53 has an ohmic contact with the silicon carbide single crystal substrate 20. A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may also be provided between the silicon carbide single crystal substrate 20 and the drift region 31.

[0092] The second region 102 is located on the Z2 side of the gate pad 61. The third region 103 is connected to the second region 102. The third region 103 has a fourth region 104 and a seventh region 107. The fourth region 104 is located on the Z2 side of the gate channel 61C, the Z2 side of the gate channel 61D, and on the Y1 side of the gate pad 61, the gate channel 61C, and the gate channel 61D when viewed from above. The seventh region 107 is located on the Y2 side of the gate pad 61 when viewed from above. The first region 101 is located on the Y2 side of the seventh region 107 and on the Y2 side of the gate channels 61C and 61D when viewed from above. The first region 101 is located from the vicinity of the gate channel 61A to the vicinity of the gate channel 61B in the X1-X2 direction.

[0093] As described above, the gate trench 5 is disposed in the first region 101, but not in the second region 102 and the third region 103. The source region 33 is also disposed in the first region 101, but not in the second region 102 and the third region 103. Therefore, in the second region 102 and the third region 103, the first main surface 1 is composed of contact regions 34. The contact regions 34 in the first region 101, the second region 102, and the third region 103 are connected to each other in the first main surface 1. In this embodiment, the source region 33 is disposed between adjacent gate trenches 5 in the Y1-Y2 direction. Each unit cell 40 includes a set of gate trenches 5 and a gate electrode 51. In the first region 101, multiple unit cells 40 are arranged with a certain pitch P1 in the Y1-Y2 direction. The contact region 34 in the second region 102 is an example of the first semiconductor region 111, and the contact region 34 in the third region 103 is an example of the second semiconductor region 112. The contact area 34 in the fourth region 104 is an example of the fourth semiconductor region 114, and the contact area 34 in the seventh region 107 is an example of the seventh semiconductor region 117.

[0094] On the Z1 side of the first region 101, the source contact holes 71 formed on the interlayer insulating film 44 are arranged in the Y1-Y2 direction at a certain pitch P2 equal to the pitch P1.

[0095] On the Z1 side of the second region 102, a gate contact hole 70 is formed on the interlayer insulating film 44, but contact holes 71 and 72 are not formed. The gate contact hole 70 is also formed in the portion between the gate channels 61A, 61B, 61C, 61D and 61E of the interlayer insulating film 44 and the gate electrode 51.

[0096] On the Z1 side of the third region 103, the contact hole 72 includes a contact hole 73 extending to the contact area 34 within the fourth region 104, and a contact hole 77 extending to the contact area 34 within the seventh region 107. When viewed from a cross-section parallel to the first main surface 1, the dimensions W3 of the short side of the contact hole 73 and W7 of the short side of the contact hole 77 are larger than the dimension W1 of the short side of the contact hole 71. Dimension W3 is the dimension of the contact hole 73 in the Y1-Y2 direction, and dimension W7 is the dimension of the contact hole 77 in the Y1-Y2 direction. Dimensions W3 and W7 can also be equal. The contact hole 73 is an example of a third contact hole, and the contact hole 77 is an example of a seventh contact hole. Dimension W3 is an example of a third dimension, and dimension W7 is an example of a fourth dimension. The contact hole 73 is part of the contact hole used in the source channel 62C.

[0097] Contact electrode 52 is connected to contact area 34 within contact holes 73 and 77. Contact electrode 52 and contact area 34 are in ohmic contact. Source pad 62 is also connected to contact electrode 52 within contact hole 77. Source channel 62C is connected to contact electrode 52 within contact hole 73.

[0098] In the first embodiment, a third region 103 connected to the second region 102 is provided, and contact areas 34 are connected in the second region 102 and the third region 103. Furthermore, when viewed from a cross-section parallel to the first main surface 1, the dimension W2 of the short side of the contact hole 72 is larger than the dimension W1 of the short side of the contact hole 71. Therefore, the contact resistance between the source pad 62 and the contact area 34 can be reduced, and even in the event of a surge, the electric field concentration towards the interlayer insulating film 44 in the second region 102 can be mitigated.

[0099] In addition, since the contact area 34 is connected to the surface JTE area 37, even if a large voltage is applied between the drain electrode 53 and the source channel 62C, the electric field concentration to the interlayer insulating film 44 below the source channel 62C can be mitigated.

[0100] Furthermore, in this embodiment, the third region 103 includes the fourth region 104 and the seventh region 107. The third region 103 may also include only one of the fourth region 104 or the seventh region 107, but by including both the fourth region 104 and the seventh region 107, the contact resistance between the source pad 62 and the contact area 34 can be further reduced. Additionally, when the dimensions W3 of the short side of the contact hole 73 and W7 of the contact hole 77 are equal, the current generated in the contact area 34 within the second region 102 can easily flow equally to the contact hole 73 and the contact hole 77.

[0101] In addition, since gate channels 61A, 61B and 61E extending in the Y1-Y2 direction are provided, it is easy to apply gate voltage equally to each unit cell 40 from the gate channels 61A, 61B and 61E.

[0102] Furthermore, since the contact area 34 in the first region 101 and the contact area 34 in the third region 103 are connected to each other, it is easy to control them to the same potential.

[0103] It should be noted that the dimension L1 of the contact hole 73 in the X1-X2 direction is preferably larger than the dimension L2 of the gate pad 61 in the X1-X2 direction. This is because it is easier to reduce the contact resistance in the fourth region 104. Dimension L1 is an example of a fifth dimension, and dimension L2 is an example of a sixth dimension.

[0104] Furthermore, it is preferable that the dimension L3 of the portion of the contact hole 77 between the gate channels 61A and 61E, when viewed from above, in the X1-X2 direction, is more than half the distance between the gate channels 61A and 61E. In this case, the dimension L3 of the unit cell 40 disposed on the extension line of the contact hole 77 in the portion between the gate channels 61A and 61E, in the X1-X2 direction, is less than half the distance between the gate channels 61A and 61E. Therefore, it is easy to apply the same gate voltage as the other unit cells 40 to this unit cell 40. Dimension L3 is an example of the seventh dimension.

[0105] Similarly, it is preferable that the dimension L4 of the portion of the contact hole 77 between the gate channel 61B and the gate channel 61E, when viewed from above, is at least half the distance between the gate channel 61B and the gate channel 61E. In this case, the dimension L4 of the unit cell 40 disposed on the extension line of the contact hole 77 in the portion between the gate channel 61B and the gate channel 61E, in the X1-X2 direction, is less than half the distance between the gate channel 61B and the gate channel 61E. Therefore, it is easy to apply the same gate voltage as the other unit cells 40 to this unit cell 40. Dimension L4 is an example of an eighth dimension.

[0106] (Second Implementation)

[0107] Next, the second embodiment will be described. The second embodiment differs from the first embodiment mainly in that it has a field insulating film. Figure 9 This is a cross-sectional view showing the silicon carbide semiconductor device according to the second embodiment. Figure 9 and Figure 7 Similarly, equivalent to along Figure 1 and Figure 2 A cross-sectional view of line VII-VII in the diagram. Figure 9 In this paper, the passivation film is omitted.

[0108] like Figure 9As shown, the MOSFET 202 according to the second embodiment has a field insulating film 45. The field insulating film 45 is disposed on the second region 102, the fourth region 104, and the terminal region 42. On the field insulating film 45, when viewed from above, a contact hole 74 is formed on the Y1 side, which extends into the contact region 34 in the fourth region 104. An interlayer insulating film 44 is disposed on the field insulating film 45 above the second region 102, the fourth region 104, and the terminal region 42. The interlayer insulating film 44 is also disposed inside the contact hole 74. Inside the contact hole 74, there is a gate insulating film 43 between the interlayer insulating film 44 and the contact region 34. The contact hole 73 is smaller than the contact hole 74 and is located inside the contact hole 74. Above the second region 102, a gate electrode 51 is disposed on the field insulating film 45. The contact hole 74 is an example of a fourth contact hole.

[0109] The other structures are the same as in the first embodiment.

[0110] According to the second embodiment, since a field insulating film 45 is provided, the electric field concentration in the interlayer insulating film 44 can be further mitigated.

[0111] (Third Implementation)

[0112] Next, the third embodiment will be described. The main difference between the third embodiment and the first embodiment is in the arrangement of the gate pad 61. Figure 10 This is a top view showing the silicon carbide semiconductor device according to the third embodiment. Figure 11 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the third embodiment. Figure 12 and Figure 13 This is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment. Figure 12 Equivalent to along Figure 10 and Figure 11 A cross-sectional view of line XII-XII in the diagram. Figure 13 Equivalent to along Figure 10 and Figure 11 A cross-sectional view of line XIII-XIII in [the image / data]. Figure 12 and Figure 13 In this paper, the passivation film is omitted.

[0113] like Figures 10 to 13 As shown, in the MOSFET 203 according to the third embodiment, the gate pad 61 is connected to the gate channels 61C and 61D, but the gate pad 61 is disposed on the Y2 side closer to the gate channels 61C and 61D. Therefore, there is no gate pad 61 between the gate channels 61C and 61D. The gate channels 61C and 61D are far apart from each other.

[0114] The fourth region 104 includes a fifth region 105 disposed between gate channels 61C and 61D when viewed from above. The fifth region 105 is connected to the second region 102 in the first main surface 1. That is, the contact region 34 within the fourth region 104 includes a contact region 34 between gate channels 61C and 61D when viewed from above. When viewed from above, the contact region 34 between gate channels 61C and 61D is connected to the contact region 34 in the second region 102 in the first main surface 1. The contact region 34 in the fifth region 105 is an example of a fifth semiconductor region 115.

[0115] Contact hole 72 includes contact hole 75 that, when viewed from above, reaches the contact area 34 between gate channel 61C and gate channel 61D. Contact hole 75, when viewed from above, is located on the Y1 side of gate pad 61 and between gate channel 61C and gate channel 61D. When viewed from a cross-section parallel to the first main surface 1, the dimension W5 of contact hole 75 in the short side direction is larger than the dimension W1 of contact hole 71 in the short side direction. Contact hole 75 may also be part of contact hole 73. Dimension W5 may also be larger than the dimension W3 of other parts of contact hole 73. Contact hole 75 is an example of a fifth contact hole.

[0116] Within the contact hole 75, the contact electrode 52 is connected to the contact area 34. The contact electrode 52 and the contact area 34 are in ohmic contact. The source pad 62 is also connected to the contact electrode 52 within the contact hole 75.

[0117] The other structures are the same as in the first embodiment.

[0118] According to the third embodiment, the same effects as the first embodiment can also be obtained. In addition, the contact resistance between the source channel 62C connected to the source pad 62 and the contact area 34 in the fourth region 104 can be further reduced near the gate pad 61.

[0119] (Fourth Implementation)

[0120] Next, the fourth embodiment will be described. The fourth embodiment differs from the first embodiment mainly in the arrangement of the gate pad 61. Figure 14 This is a top view showing the silicon carbide semiconductor device according to the fourth embodiment. Figure 15 This is a diagram showing the regions within the silicon carbide substrate of the silicon carbide semiconductor device according to the fourth embodiment. Figure 16 This is a cross-sectional view showing the silicon carbide semiconductor device according to the fourth embodiment. Figure 16 Equivalent to along Figure 14 and Figure 15 A cross-sectional view of the XVI-XVI line. Figure 16 In this paper, the passivation film is omitted.

[0121] like Figures 14 to 16 As shown, the MOSFET 204 according to the fourth embodiment has a gate channel 61F instead of gate channels 61C and 61D. Gate channel 61F extends along the third side 93 in the X1-X2 direction. The Y1-side end of gate channel 61A is connected to the X2-side end of gate channel 61F. The Y1-side end of gate channel 61B is connected to the X1-side end of gate channel 61F. In the Y1-Y2 direction, gate pad 61 is located away from gate channel 61F. MOSFET 204 further has a gate channel 61G. Gate channel 61G extends in the Y1-Y2 direction, connecting gate channel 61F to gate pad 61. Gate channels 61F and 61G are made of the same material as gate pad 61. Gate channel 61F is an example of a third gate channel.

[0122] The fourth region 104 includes a sixth region 106 disposed between the gate pad 61 and the gate channel 61F when viewed from above. The sixth region 106 is connected to the second region 102 in the first main surface 1. That is, the contact area 34 in the fourth region 104 includes the portion between the gate pad 61 and the gate channel 61F when viewed from above. When viewed from above, the contact area 34 between the gate pad 61 and the gate channel 61F is connected to the contact area 34 in the second region 102 in the first main surface 1. The contact area 34 in the sixth region 106 is an example of the sixth semiconductor region 116.

[0123] Contact hole 72 includes contact hole 76 that, when viewed from above, reaches the contact area 34 between gate pad 61 and gate channel 61F. Contact hole 76 is located on the Y1 side of gate pad 61 and the Y2 side of gate channel 61F when viewed from above. When viewed from a cross-section parallel to the first main surface 1, the dimension W6 of contact hole 76 in the short side direction is larger than the dimension W1 of contact hole 71 in the short side direction. Contact hole 76 is an example of a sixth contact hole.

[0124] Within the contact hole 76, the contact electrode 52 is connected to the contact area 34. The contact electrode 52 and the contact area 34 are in ohmic contact. The source pad 62 is also connected to the contact electrode 52 within the contact hole 76.

[0125] The other structures are the same as in the first embodiment.

[0126] According to the fourth embodiment, the same effects as the first embodiment can be obtained. Furthermore, according to the fourth embodiment, the degree of freedom in the arrangement of the gate pad 61 can be increased.

[0127] (Fifth Implementation)

[0128] Next, the fifth embodiment will be described. The fifth embodiment differs from the fourth embodiment mainly in the arrangement of the gate pad 61. Figure 17 This is a top view showing the silicon carbide semiconductor device according to the fifth embodiment. Figure 18 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the fifth embodiment.

[0129] like Figure 17 and Figure 18 As shown, the MOSFET 205 in the fifth embodiment does not have a gate channel 61G, and the gate channel 61E is connected to the gate channel 61F. Furthermore, the gate pad 61 is located on the X2 side of the gate channel 61E, but not on the X1 side. Similar to the fourth embodiment, the contact hole 72 includes a contact hole 76 (see reference 1) that, when viewed from above, reaches the contact area 34 between the gate pad 61 and the gate channel 61F. Figure 16 ).

[0130] The other structures are the same as in the fourth embodiment.

[0131] According to the fifth embodiment, the same effect as the fourth embodiment can also be obtained.

[0132] (Sixth Implementation Method)

[0133] Next, the sixth embodiment will be described. The sixth embodiment differs from the fifth embodiment mainly in the arrangement of the gate pad 61. Figure 19 This is a top view showing the silicon carbide semiconductor device according to the sixth embodiment. Figure 20 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the sixth embodiment.

[0134] like Figure 19 and Figure 20 As shown, in the MOSFET 206 according to the sixth embodiment, the gate pad 61 is connected to the gate channel 61A instead of the gate channel 61E. Similarly to the fourth embodiment, the contact hole 72 includes a contact hole 76 (see reference 1) that extends to the contact area 34 between the gate pad 61 and the gate channel 61F when viewed from above. Figure 16 ).

[0135] The other structures are the same as in the fifth embodiment.

[0136] According to the sixth embodiment, the same effect as the fifth embodiment can also be obtained.

[0137] (Seventh Implementation)

[0138] Next, the seventh embodiment will be described. The main difference between the seventh embodiment and the sixth embodiment lies in the arrangement of the gate pad 61. Figure 21 This is a top view showing the silicon carbide semiconductor device according to the seventh embodiment. Figure 22 This is a diagram showing the regions within the silicon carbide substrate in the silicon carbide semiconductor device according to the seventh embodiment.

[0139] like Figure 21 and Figure 22 As shown, in the MOSFET 207 according to the seventh embodiment, the gate pad 61 is connected to the gate channels 61E and 61A. The gate pad 61 is disposed on the Y2 side of the gate channel 61F. Therefore, there is no gate pad 61 on the X2 side of the gate channel 61F. On the X2 side of the gate channel 61F, the dimension of the contact hole 73 in the short side direction is larger than the dimension of the other portion in the short side direction. It should be noted that the contact hole 72 may also not include the contact hole 76.

[0140] The other structures are the same as in the sixth embodiment.

[0141] According to the seventh embodiment, the same effect as the sixth embodiment can also be obtained.

[0142] (Eighth Implementation Method)

[0143] Next, the eighth embodiment will be described. The eighth embodiment differs from the first embodiment mainly in the structure of the contact area 34 on the Y2 side of the second region 102. Figure 23 This is a top view showing the silicon carbide semiconductor device according to the eighth embodiment. Figure 24 It is shown Figure 23 A top view of the structure of the first main surface of the silicon carbide substrate in region 223. Figures 25 to 27 This is a cross-sectional view showing the silicon carbide semiconductor device according to the eighth embodiment. Figure 25 Equivalent to along Figure 24 Cross-sectional view of the XXV-XXV line. Figure 26 Equivalent to along Figure 24 Cross-sectional view of line XXVI-XXVI in the diagram. Figure 27 Equivalent to along Figure 24 A cross-sectional view of the XXVII-XXVII line. Figures 25 to 27 In this paper, the passivation film is omitted.

[0144] like Figures 23 to 27As shown, in the MOSFET 208 according to the eighth embodiment, among the plurality of unit cells 40 located closer to the fourth side 94 than the seventh region 107, a portion of the unit cells 40 located closer to the third side 93 are further away from the gate channel 61E in the X1-X2 direction than the remaining unit cells 40. For example, in the plurality of gate trenches 5 arranged in the Y1-Y2 direction at a position closer to the fourth side 94 than the seventh region 107 (Y2 side), the first trench group 5A of a portion of the gate trenches 5 located on the Y1 side is further away from the gate channel 61E when viewed from above than the second trench group 5B of other gate trenches 5 located on the Y2 side of the first trench group 5A. When viewed from above, the size of the contact area 34 between the first trench group 5A and the gate channel 61E in the X1-X2 direction is larger than the size of the contact area 34 between the second trench group 5B and the gate channel 61E in the X1-X2 direction.

[0145] The other structures are the same as in the first embodiment.

[0146] According to the eighth embodiment, the same effects as in the first embodiment can also be obtained. In addition, according to the eighth embodiment, the electric field concentration in the interlayer insulating film 44 near the gate channel 61E of the first trench group 5A can be mitigated.

[0147] (A variation of the first region)

[0148] Here, a modified example of the first region will be described. In this modified example, the structure of the unit cell differs from that of the first embodiment, etc. Figure 28 This is a top view showing a modified example of the first region. Figure 28 and Figure 4 Similarly, the structure of the first main surface of the silicon carbide substrate is shown.

[0149] In this modified example, in the first region 101, a plurality of gate trenches 5 are formed between two adjacent gate channels in the X1-X2 direction. In addition, in the first region 101, a contact region 34 is disposed between adjacent gate trenches 5 in the X1-X2 direction and extends in the Y1-Y2 direction.

[0150] The embodiments have been described in detail above, but are not limited to specific embodiments. Various modifications and alterations can be made within the scope of the claims.

[0151] Explanation of reference numerals in the attached figures

[0152] 1 First main surface; 2 Second main surface; 3 Side surface; 4 Bottom surface; 5 Gate trench; 5A First trench group; 5B Second trench group; 10 Silicon carbide substrate; 20 Silicon carbide single crystal substrate; 30 Silicon carbide epitaxial layer; 31 Drift region; 32 Body region; 33 Source region; 34 Contact region; 35 Buried region; 36 Buried JTE region; 37 Surface JTE region (third semiconductor region); 40 Unit cell; 41 Active region; 42 Termination region; 43 Gate insulating film; 44 Interlayer insulating film; 45 Field insulating film; 51 Gate electrode; 52 Contact electrode; 53 Drain electrode; 61 Gate pad; 61A, 61B, 61C, 61D, 61E, 61F, 61G Gate channels; 62, 62A, 62B Source pads; 62C Source channel; 64 Side view; 70, 71, 72, 73, 74, 75, 76, 77 contact holes; 80 passivation film; 81, 82 openings; 91 first side; 92 second side; 93 third side; 94 fourth side; 101 first region; 102 second region; 103 third region; 104 fourth region; 105 fifth region; 106 sixth region; 107 seventh region; 111 first semiconductor region; 112 second semiconductor region; 113 third semiconductor region; 114 fourth semiconductor region; 115 fifth semiconductor region; 116 sixth semiconductor region; 117 seventh semiconductor region; 201, 202, 203, 204, 205, 206, 207, 208 MOSFETs; 221, 222, 223 regions.

Claims

1. A silicon carbide semiconductor device, comprising: A silicon carbide substrate having a first principal surface; Interlayer insulating film, covering the first main surface; and Gate pads and source pads are disposed on the interlayer insulating film. When viewed from above in a direction perpendicular to the first main surface, the silicon carbide substrate has: The first region comprises multiple unit areas; The second region overlaps with the gate pad; The third region is connected to the second region; The active region includes the plurality of unit cells; as well as The terminal area is located around the active area. The plurality of unit units each have: The drift region has a first conductivity type; The body region has a second conductivity type different from the first conductivity type; The source region is disposed on the first main surface, separated from the drift region by the body region, and has the first conductivity type; A contact area is disposed on the first main surface, electrically connected to the body area, and has the second conductivity type; The gate electrode is electrically connected to the gate pad. as well as A gate insulating film is disposed between the drift region, the body region, the source region, and the gate electrode. The second region has a first semiconductor region, and the first semiconductor region has the second conductivity type. The third region has a second semiconductor region, and the second semiconductor region has the second conductivity type. The first semiconductor region and the second semiconductor region are connected to each other in the first main surface. The following are formed on the interlayer insulating film: The first contact hole reaches the source region and the contact region; as well as The second contact hole reaches the second semiconductor region. The source pad is electrically connected to the source region and the contact region via the first contact hole. The source pad is electrically connected to the second semiconductor region via the second contact hole. When viewed from a cross-section parallel to the first main surface, the second dimension of the second contact hole in the short side direction is larger than the first dimension of the first contact hole in the short side direction. The terminal region has a third semiconductor region, and the third semiconductor region has the second conductivity type. The second semiconductor region includes a fourth semiconductor region. When viewed from a direction perpendicular to the first main surface, the fourth semiconductor region is disposed between the gate pad and the terminal region, and is connected to the first semiconductor region and the third semiconductor region in the first main surface. The concentration of the second conductivity type impurity in the third semiconductor region is lower than the concentration of the second conductivity type impurity in the fourth semiconductor region. The second contact hole includes a third contact hole that extends into the fourth semiconductor region.

2. The silicon carbide semiconductor device according to claim 1, wherein, The contact area and the second semiconductor area are connected to each other in the first main surface.

3. The silicon carbide semiconductor device according to claim 1, wherein, The silicon carbide semiconductor device has a field insulating film disposed between the first semiconductor region, the fourth semiconductor region, the third semiconductor region, and the interlayer insulating film. A fourth contact hole is formed on the field insulating film, extending to the fourth semiconductor region. Inside the fourth contact hole, the interlayer insulating film is in contact with the fourth semiconductor region. The third contact hole is located inside the fourth contact hole.

4. The silicon carbide semiconductor device according to claim 1, wherein, The silicon carbide semiconductor device has a source channel electrically connected to the source pad and electrically connected to the fourth semiconductor region via the third contact hole. When viewed from a cross-section parallel to the first main surface, the side of the source channel away from the gate pad is located on the boundary line between the third semiconductor region and the fourth semiconductor region, or closer to the gate pad than the boundary line.

5. The silicon carbide semiconductor device according to claim 1, wherein, The silicon carbide semiconductor device has: A first gate channel is electrically connected to the gate pad and extends in a first direction parallel to the first main surface, and is configured to be closer to the terminal region than the gate pad; as well as A second gate channel, electrically connected to the gate pad, extends in the first direction and is located away from the first gate channel, and is configured to be closer to the termination region than the gate pad. The fourth semiconductor region includes a fifth semiconductor region. When viewed from a direction perpendicular to the first main surface, the fifth semiconductor region is disposed between the first gate channel and the second gate channel, and is connected to the first semiconductor region in the first main surface. The second contact hole includes a fifth contact hole that reaches the fifth semiconductor region.

6. The silicon carbide semiconductor device according to claim 1, wherein, The silicon carbide semiconductor device has a third gate channel electrically connected to the gate pad and extending in a first direction parallel to the first main surface, and configured to be closer to the termination region than the gate pad. The fourth semiconductor region includes a sixth semiconductor region. When viewed from a direction perpendicular to the first main surface, the sixth semiconductor region is disposed between the gate pad and the third gate channel, and is connected to the first semiconductor region in the first main surface. The second contact hole includes a sixth contact hole that reaches the sixth semiconductor region.

7. The silicon carbide semiconductor device according to claim 1, wherein, The plurality of unit cells extend in a first direction parallel to the first main surface and are arranged in a second direction perpendicular to the first direction. The gate pad has a rectangular planar shape with the first direction as the long side when viewed from a direction perpendicular to the first main surface. The second semiconductor region includes a seventh semiconductor region, which is disposed in the second direction at a position sandwiching the gate pad between the seventh semiconductor region and the fourth semiconductor region. The second contact hole includes a seventh contact hole that reaches the seventh semiconductor region.

8. The silicon carbide semiconductor device according to claim 7, wherein, When viewed from a cross-section parallel to the first main surface, the third dimension of the third contact hole in the short side direction is equal to the fourth dimension of the seventh contact hole in the short side direction.

9. The silicon carbide semiconductor device according to claim 7 or 8, wherein, The fifth dimension of the third contact hole in the first direction is larger than the sixth dimension of the gate pad in the first direction.

10. The silicon carbide semiconductor device according to claim 7 or 8, wherein, When viewed from above, the silicon carbide substrate has a rectangular shape with a first and a second side that are parallel to each other, and a third and a fourth side that are perpendicular to the first and the second sides. The silicon carbide semiconductor device has: The fourth gate flow channel extends along the first side; The fifth gate flow channel extends along the second side; and The sixth gate channel, located between the fourth and fifth gate channels, extends from the gate pad toward the fourth side. The fourth gate channel, the fifth gate channel, and the sixth gate channel are electrically connected to the gate pad.

11. The silicon carbide semiconductor device according to claim 10, wherein, The seventh dimension of the seventh contact hole, in the first direction of the portion between the fourth gate channel and the sixth gate channel when viewed from above, is: The distance between the fourth gate channel and the sixth gate channel is more than 1 / 2.

12. The silicon carbide semiconductor device according to claim 10, wherein, The eighth dimension of the seventh contact hole, in the first direction of the portion between the fifth gate channel and the sixth gate channel when viewed from above, is: The distance between the fifth gate channel and the sixth gate channel is more than 1 / 2.

13. The silicon carbide semiconductor device according to claim 10, wherein, Of the plurality of unit cells located closer to the fourth side than the seventh semiconductor region, a portion of the unit cells located closer to the third side are further away from the sixth gate channel in the second direction than the remaining unit cells.

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