Inkjet head and head control circuit

Abstract

The present invention provides an inkjet head and a head control circuit capable of performing serial communication between a plurality of inkjet heads whose serial communication device addresses can collide without providing a special component in a head control circuit. An intrinsic identification information reading section of an FPGA constituting the inkjet head transmits unique identification information stored in a storage section to the head control circuit in response to a read code from the head control circuit via a serial communication path. An address switching section switches the serial communication device address of the inkjet head to a new serial communication device address specified by an address setting instruction from the head control circuit via a data transmission path. A serial communication section performs serial communication with the head control circuit in response to a serial communication request for the new serial communication device address from the head control circuit via the serial communication path.

Description

Technical Field

[0001] Embodiments of the present invention relate to an inkjet printhead and a printhead control circuit. Background Technology

[0002] As an image forming apparatus, an inkjet printer is known to eject ink onto a printing medium and form an image. An inkjet printer, for example, includes an inkjet head and a head control circuit for controlling the inkjet head.

[0003] An inkjet head may include, for example, a head unit and an internal control circuit. The head unit includes an actuator with a capacitive load connected to multiple capacitive elements, and various sensors for detecting ink temperature, etc. The internal control circuit includes: a driver IC that drives the actuator; an AD converter circuit that converts analog detection signals from sensors that detect ink temperature, etc., into digital values; and a serial communication unit for serial communication (I2C, etc.) between the head control circuit and the AD converter circuit.

[0004] Inkjet printers also include models with multiple printheads. Each printhead has its own unique serial communication device address for serial communication. This serial communication device address is arbitrarily assigned during the manufacturing process of the printhead. Therefore, it is possible for printheads in an inkjet printer to have the same serial communication device address as each other.

[0005] When the printhead control circuit accesses the inkjet head via serial communication, even if it wants to communicate serially with the AD conversion circuits inside multiple printheads, the same serial communication device address will conflict, preventing access. Therefore, by additionally setting an I2C switch IC or similar device on the serial communication master controller side, i.e., the printhead control circuit, a single serial communication device address can be used to switch between multiple printheads.

[0006] Therefore, when multiple inkjet heads are used, components such as I2C switch ICs are required, incurring additional costs.

[0007] Furthermore, when accessing an AD conversion circuit inside a specific inkjet head from the head control circuit, the I2C switch IC temporarily selects that AD conversion circuit before accessing it. The same sequence is required when accessing AD conversion circuits inside other inkjet heads from there. Therefore, the switching time of the I2C switch IC is consumed when acquiring detection data from the targeted AD conversion circuit, hindering high-speed access. Summary of the Invention

[0008] The technical problem to be solved by the embodiments of the present invention is to provide an inkjet head and a head control circuit that enable serial communication between multiple inkjet heads that may conflict with the address of a serial communication device, without setting components such as I2C switch ICs in the head control circuit.

[0009] In one embodiment, the inkjet head includes: a head unit equipped with a plurality of actuators that eject ink, and a control circuit for controlling the head unit. The control circuit includes: a driver IC, an AD conversion circuit, and an FPGA. The driver IC drives the plurality of actuators of the head unit. The AD conversion circuit converts analog detection signals from sensors disposed on the head unit into digital detection data. The FPGA controls the driver IC based on drive commands from a head control circuit disposed outside the inkjet head via a data transmission path, and controls serial communication via a serial communication path between the head control circuit and the AD conversion circuit. The FPGA is configured to include: a storage unit, a unique identification information reading unit, an address switching unit, and a serial communication unit. The storage unit stores unique identification information of the inkjet head. The unique identification information reading unit, in response to a readout code of the unique identification information from the head control circuit via the serial communication path, transmits the unique identification information stored in the storage unit to the head control circuit via the serial communication path. The address switching unit, when a new serial communication device address is specified by an address setting command from the head control circuit via the data transmission path, switches the serial communication device address of the inkjet head from an initial serial communication device address to the specified new serial communication device address. The serial communication unit responds to a serial communication request for a new serial communication device address from the head control circuit via the serial communication path, and performs serial communication between the head control circuit and the AD conversion circuit via the serial communication path.

[0010] In another embodiment, a head control circuit that controls the operation of multiple inkjet heads by assigning instructions to them via a data transmission path includes: a unique address acquisition unit, an instruction unit, an address association unit, and a serial communication unit. The unique address acquisition unit acquires unique identification information for each inkjet head from each inkjet head via a serial communication path. The instruction unit assigns a new serial communication device address, independent of the initial serial communication device address, to each inkjet head and sends address setting instructions to each inkjet head to switch to the new serial communication device address via the data transmission path. The address association unit associates and maintains the unique identification information and the new serial communication device address for each inkjet head. The serial communication unit transmits the new serial communication device address maintained by the address association unit via the serial communication path, enabling serial communication between the inkjet head that has switched to the new serial communication device address and the AD conversion circuit that converts analog detection signals from sensors in a head unit equipped with multiple ink-ejecting actuators into digital detection data. Attached Figure Description

[0011] Figure 1 This is an explanatory diagram showing an example of the configuration of the inkjet printer in the first embodiment.

[0012] Figure 2 This is a diagram illustrating an example of the configuration of the inkjet head according to the first embodiment.

[0013] Figure 3 This is a diagram showing an example of the configuration of a head controller as a head control circuit according to the first embodiment.

[0014] Figure 4 This diagram illustrates an example of the contents of an address table stored in the internal memory of a head control circuit.

[0015] Figure 5 This is a flowchart illustrating an example of the address switching process sequence in a head control circuit.

[0016] Figure 6 This is a diagram illustrating an example of the configuration of the inkjet head according to the second embodiment.

[0017] Explanation of reference numerals in the attached figures

[0018] 1…Inkjet printer; 2…PC; 3…Network; 11…Control unit; 12…Display; 13…Operation unit; 14…Communication interface; 15…Conveyor motor; 16…Motor drive circuit; 17…Pump; 18…Pump drive circuit; 19, 19-1 to 19-n…Inkjet head; 20…Head controller; 21…Power supply; 22…Processor; 23…Memory; 24…In-head control circuit; 25…Head unit; 26…ADC with built-in FPGA; 27…DrIC; 28…ADC; 29…High-speed data transmission receiver; 30…Data processing unit; 31…Data transmission circuit section; 32…Data receiving circuit section; 33…Intrinsic ID storage section; 34…Intrinsic ID interface section; 35…ADC read register section; 36, 48…Serial communication section; 37…AND circuit section; 38…Command analysis section; 39…Device address update control circuit section; 40…Device address register section; 41…Reset generation section; 42…OR circuit section; 43…MCU; 44…Header interface high-speed data transmission section; 45…Internal memory; 46…FPGA; 47…ADCIC; 49…Serial communication control section. Detailed Implementation

[0019] Hereinafter, the inkjet head and head control circuit according to the embodiments will be described with reference to the accompanying drawings.

[0020] [First Implementation Method]

[0021] Figure 1This is an explanatory diagram showing an example of the configuration of the inkjet printer 1 in the first embodiment. The inkjet printer 1 forms an image on the printing medium while conveying the recording medium, i.e., the printing medium.

[0022] The inkjet printer 1 includes: a control unit 11, a display 12, an operation unit 13, a communication interface 14, a transport motor 15, a motor drive circuit 16, a pump 17, a pump drive circuit 18, multiple inkjet heads 19-1, 19-2, ..., 19-n according to the first embodiment, a head controller 20 serving as the head control circuit according to the first embodiment, and a power supply 21. The inkjet printer 1 also includes a transport mechanism (not shown), a paper tray, and a paper output tray. It should be noted that in the accompanying drawings, the interface may be abbreviated as "IF". Furthermore, in the following description, unless otherwise specified, the multiple inkjet heads 19-1 to 19-n will be referred to as "inkjet head 19".

[0023] The control unit 11 includes a processor 22 and a memory 23, and performs various controls on the inkjet printer 1. The processor 22 is an arithmetic element that performs arithmetic processing. The processor 22 performs various processing based on, for example, the program stored in the memory 23 and the data used in the program. The memory 23 stores programs, data used in the program, etc., in a rewritable manner.

[0024] The display 12 is a display device such as a liquid crystal display, which displays images based on image signals input from the processor 22 or a graphics controller (not shown) for image processing.

[0025] The operation unit 13 has an operation unit that generates operation signals based on user operations. The operation unit 13 may be, for example, a touch sensor, numeric keypad, power button, paper feed button, various function keys, or a keyboard. The touch sensor may be, for example, a resistive film touch sensor or an electrostatic capacitive touch sensor. The touch sensor acquires information indicating a specified position within a certain area. Alternatively, the touch sensor may be used as a touch panel integrally formed on the display 12. In this case, the touch sensor generates a signal indicating the position of the touch on the screen displayed on the display 12.

[0026] Communication interface 14 is an interface for communicating with external devices. In this embodiment, communication interface 14 is used, for example, to communicate with at least one host PC 2 that sends printing data to inkjet printer 1. Communication interface 14 communicates with host PC 2 via a network 3 consisting of wired or wireless connections, such as a LAN (Local Area Network).

[0027] The conveyor motor 15, by rotating, becomes the drive source for a conveyor mechanism (not shown) used to convey printing media. The conveyor mechanism consists of a conveyor belt for conveying the printing media, multiple rollers (drive rollers and slave rollers) mounted on the conveyor belt, guides, etc. The conveyor motor 15 rotates the drive rollers, causing the conveyor belt to move. The printing media moves along a conveying path defined by the guides positioned near the conveyor belt.

[0028] The motor drive circuit 16 drives the transport motor 15 according to the transport control signal input from the control unit 11. Through the motor drive circuit 16, the transport motor 15, and the transport mechanism, the printed media taken from the paper feed cassette (not shown) is transported via multiple inkjet heads 19 to the paper discharge tray (not shown). It should be noted that the paper feed cassette is a box that holds multiple printed media. The paper discharge tray is a tray that holds the printed media discharged from the inkjet printer 1.

[0029] Pump 17 supplies ink from the ink tank to the ink chamber of the printhead 19 via the ink supply path. Pump 17 is positioned on the ink supply path, which is formed by a tube (not shown) connecting the ink tank and the ink chamber (pressure chamber of the capacitive element described later) of the printhead 19.

[0030] The pump drive circuit 18 drives the pump 17 according to the ink supply control signal input from the processor 22.

[0031] The inkjet head 19 ejects ink onto the printing medium and forms an image. Based on the drive power and control signals supplied by the head controller 20, ink is ejected from the printing medium conveyed by the transport mechanism to form an image. The inkjet head 19 is provided with multiple inks corresponding to each color, such as cyan, magenta, yellow, and black.

[0032] The printhead controller 20 is a circuit connected to the control unit 11, the power supply 21, and the host PC2, controlling multiple connected printheads 19. The printhead controller 20 actuates the printheads 19, causing ink to be ejected from actuators within the printheads 19, forming an image on the printing medium.

[0033] Power supply 21 converts AC power supplied from commercial power supply into DC power (DC voltage DCV). Power supply 21 uses DC power as a drive power source to supply the various components within inkjet printer 1.

[0034] The inkjet head 19 and the head controller 20 will be described in detail below. First, refer to... Figure 2 The inkjet head 19 will be described. Figure 2 This is a diagram showing an example of the configuration of the inkjet head 19 according to the first embodiment.

[0035] The inkjet head 19 has an in-head control circuit 24 and a head unit 25. Multiple actuators for ejecting ink are disposed within the head unit 25. Sensors for detecting ink temperature, etc., are also disposed within the head unit 25. Furthermore, the in-head control circuit 24 is a control circuit that controls the head unit 25.

[0036] The head-mounted control circuit 24 has an ADC built-in FPGA (Field Programmable Gate Array) 26 and DrIC 27.

[0037] Within the FPGA 26 built into the ADC, an AD conversion circuit, namely ADC 28, is formed as a functional block to convert the analog detection signal from the sensor set in the head unit 25 into digital value detection data.

[0038] The ADC-embedded FPGA 26 also includes a configuration for controlling the DrIC 27 based on drive commands from the head controller 20 via the high-speed data transmission path (data transmission path) of the inkjet head. Specifically, the ADC-embedded FPGA 26 comprises a high-speed data transmission receiving unit 29, a data processing unit 30, and a data transmission circuit unit 31 as functional blocks. Furthermore, the high-speed data transmission receiving unit 29 is configured to include a data receiving circuit unit 32 as a functional block.

[0039] The data receiving circuit 32 receives various instructions from the printhead controller 20 via the high-speed data transmission path of the inkjet head. If a printing instruction is received, it transmits the printing instruction to the data processing unit 30. The data processing unit 30 processes the printing instruction and determines the operating mode of each of the multiple actuators of the printhead unit 25, generating a control signal to implement the determined operating mode. The data transmission circuit 31 transmits the control signal generated by the data processing unit 30 to the DrIC 27.

[0040] DrIC27 is a driver IC that integrates a dedicated drive circuit for multiple actuators in the drive head unit 25. DrIC27 drives each actuator by applying a drive voltage from the head controller 20 to each actuator based on a control signal from the data processing unit 30. It should be noted that when the initial setup is completed and the device is ready for use, DrIC27 outputs a configuration completion signal.

[0041] The ADC-embedded FPGA 26 also includes a configuration for serial communication with the head controller 20 via a serial communication path. Specifically, the ADC-embedded FPGA 26 includes, as functional blocks, an intrinsic ID storage unit 33, an intrinsic ID interface unit 34, an ADC read register unit 35, a serial communication unit 36, and an AND circuit unit 37.

[0042] The intrinsic ID storage unit 33 stores the FPGA intrinsic ID of the inkjet head 20 for identification. The FPGA intrinsic ID is a unique identification information assigned during the manufacturing of the inkjet head 19.

[0043] The Intrinsic ID Interface Section 34 is an interface for reading the FPGA Intrinsic ID stored in the Intrinsic ID Storage Section 33 to the ADC Read Register Section 35.

[0044] The ADC read register unit 35 temporarily stores digital detection data such as ink temperature from the head unit 25 converted by the ADC 28. Furthermore, the ADC read register unit 35 can store the FPGA's intrinsic ID read from the intrinsic ID storage unit 33 by the intrinsic ID interface unit 34, the status of the DrIC 27 indicated by the configuration completion signal from the DrIC 27, and so on.

[0045] The serial communication unit 36 ​​is an I2C slave interface unit that uses the head controller 20 as an I2C master. Specifically, in response to receiving the serial communication device address from the inkjet head 19 of the head controller 20 via the serial communication path (SCL, SDA), the serial communication unit 36 ​​performs serial communication with the head controller 20 via the serial communication path. Through this serial communication unit 36, the head controller 20 can communicate with the ADC read register unit 35, and can obtain the digital detection data of the ADC 28 and the FPGA-specific ID of the inkjet head 19 stored in the ADC read register unit 35 via the serial communication path.

[0046] The AND circuit section 37 performs a logical product of the serial communication valid signal and error detection signal from the ADC read register section 35 and the configuration completion signal from the DrIC 27. When a predetermined condition is met, the ADC read register section 35 outputs a serial communication valid signal indicating that the inkjet head 19 is capable of serial communication with the head controller 20 via the serial communication path in the serial communication section 36. Additionally, the ADC read register section 35 outputs an error detection signal indicating an abnormal state from the digital detection data of the ADC 28. It should be noted that the predetermined condition, for example, is that during reset release, since it is the initial serial communication device address, it becomes invalid by reading the serial communication valid and unique identification information, i.e., the FPGA's inherent ID. It becomes valid again through the address switching authentication signal from the device address register section 40. The AND circuit section 37 sends a CFG_DONE signal to the head controller 20 when the DrIC 27 is usable, the inkjet head 19 is capable of serial communication, and when an error is not detected. The head controller 20 can thus know that the inkjet head 19 is usable.

[0047] Furthermore, the ADC-embedded FPGA 26 also includes a configuration for switching the serial communication device address of the inkjet head 19 from an initial serial communication device address to a new serial communication device address. Specifically, the high-speed data transmission receiving unit 29 includes a command analysis unit 38 and a device address update control circuit unit 39 as functional blocks. The ADC-embedded FPGA 26 also includes a device address register unit 40 as a functional block.

[0048] When switching to a new serial communication device address, the printhead controller 20 sends a serial communication device address setting code via the high-speed data transmission path of the printhead. The data receiving circuit 32 of the high-speed data transmission receiving unit 29 receives the serial communication device address setting code, and when it recognizes the "device address selection" command contained in the code, it transmits the data to be sent after the command to the command analysis unit 38.

[0049] Command analysis unit 38 analyzes the data sent after the "device address selection" command transmitted from data receiving circuit unit 32. Then, command analysis unit 38 transmits the analyzed information to device address update control circuit unit 39.

[0050] Based on the information transmitted from the command analysis unit 38, the device address update control circuit unit 39 outputs a device address selection signal [3:0] and an update timing signal (UPDATE) to the device address register unit 40. The device address selection signal [3:0] indicates the value of the selected 4-bit new serial communication device address.

[0051] The device address register unit 40 initializes the device address by outputting `reset_out` from the reset generation unit 41. In response to the update timing signal output from the device address update control circuit unit 39, it stores the new serial communication device address selected by the device address selection signals [3:0] output from the same device address update control circuit unit 39. Additionally, the ADC read register unit 35 outputs an address switching authentication signal indicating the status of the updated new serial communication device address.

[0052] When the I2C slave interface unit, i.e., the serial communication unit 36, stores a new serial communication device address in the device address register unit 40, it switches the serial communication device address of the inkjet head 19 from the initial serial communication device address to the new serial communication device address. That is, even if the serial communication unit 36 ​​receives a serial communication request from the head controller 20 via the serial communication path that corresponds to the initial serial communication device address, it ignores it. Furthermore, the serial communication unit 36 ​​only initiates serial communication via the serial communication path with the head controller 20 when the head controller 20 receives a serial communication request via the serial communication path that corresponds to the new serial communication device address.

[0053] Furthermore, the ADC-embedded FPGA 26 is configured to include various components within the reset head control circuit 24. Specifically, the ADC-embedded FPGA 26 includes a reset generation unit 41 and an OR circuit unit 42 as functional blocks.

[0054] When the reset generation unit 41 is supplied with the inkjet head logic power supply HEAD_VDD and the head clock HEAD_CLK from the head controller 20, it generates and outputs an internal reset signal rest_out. This internal reset signal rest_out resets the functional blocks of the data processing unit 30, data transmission circuit unit 31, data receiving circuit unit 32, intrinsic ID interface unit 34, ADC read register unit 35, serial communication unit 36, and device address register unit 40. Additionally, the internal reset signal rest_out is also input to the OR circuit unit 42.

[0055] Additionally, the head reset signal hd_rst_out is input from the ADC read register section 35 to the OR circuit section 42. The head controller 20 outputs the head reset signal hd_rst_out from the ADC read register section 35 via the serial communication section 36. It should be noted that in this case, a software reset of DrIC27 is performed. The OR circuit section 42 performs a logical sum of the internal reset signal rest_out and the head reset signal hd_rst_out. When the internal reset signal rest_out or the head reset signal hd_rst_out is input, the OR circuit section 42 outputs the driver IC reset signal dric_rest to DrIC27, resetting DrIC27.

[0056] Next, refer to Figure 3 The head controller 20 will be described. Figure 3 This diagram illustrates an example of the configuration of the head controller 20, which is part of the head control circuit according to the first embodiment. It should be noted that... Figure 3 Only the components involved in the high-speed data transmission path and serial communication path of the inkjet head are shown.

[0057] The printhead controller 20 is a printhead control circuit that controls the operation of the multiple printheads 19 by giving instructions to the multiple printheads 19 via separate high-speed printhead data transmission paths (DOnP-DOnN). The printhead controller 20 includes an MCU 43 and a printhead interface high-speed data transmission unit 44.

[0058] MCU43 is a microcomputer with internal memory 45. MCU43 is connected to each inkjet head 19 via a common serial communication path (SCL, SDA). That is, MCU43 acts as an I2C master relative to the I2C slave interface section (serial communication section 36) within the ADC built into the FPGA 26 of each inkjet head 19. Furthermore, MCU43 is connected to the high-speed data transmission unit 44 of the printhead interface via the register read / write line REG (R / W) and the data line DATA.

[0059] The printhead interface high-speed data transmission unit 44 is a serializer / deserializer connected to multiple printheads 19 via their respective high-speed data transmission paths (DOnP-DOnN). The printhead interface high-speed data transmission unit 44 transmits data from the MCU 43 to the destination printhead 19 via the high-speed data transmission path.

[0060] It should be noted that the internal memory 45 of the MCU 43 stores, for example, the association between the unique identification information of each inkjet head 19 and the address of the new serial communication device. This association can be stored in the internal memory 45, for example, in the form of an address table.

[0061] Figure 4 This diagram illustrates an example of the contents of the address table stored in internal memory 45. The address table treats each inkjet head 19 as a record, recording the head ID, device address, and FPGA intrinsic ID. The head ID is a unique identifier used to identify multiple inkjet heads 19. The device address is a new serial communication device address set for each inkjet head 19 from the head controller 20 side. The FPGA intrinsic ID is a unique identification information set for each inkjet head 19, serving as the FPGA intrinsic ID. Figure 4 The FPGA's unique ID, "4884E61C49429880", does not conflict across multiple inkjet heads 19.

[0062] The following is for reference Figure 5 This describes the actions involved in switching the serial communication device address of each inkjet head 19 via MCU43. Figure 5 This is a flowchart illustrating an example of the address switching process sequence in the MCU43 of the head controller 20, which is part of the head control circuit according to the first embodiment. The sequence shown in this flowchart is performed on each of the multiple inkjet heads 19 as an initial setting operation when the inkjet printer 1 is powered on. It should be noted that if any inkjet head 19 is replaced due to a malfunction, the power supply to the head controller 20 and each inkjet head 19 is disconnected even if the inkjet printer 1 is powered on. Therefore, after power to the inkjet heads 19 is restored, the sequence shown in this flowchart is performed on each of the multiple inkjet heads 19.

[0063] First, the MCU43 executes the processing sequence to read the unique identification information of the inkjet head 19 of the object being processed, namely the FPGA's inherent ID.

[0064] That is, firstly, MCU43 turns on the printhead logic power supply HEAD_VDD to the printhead 19 being processed from the dedicated printhead logic power supply HEAD_VDD for each of the multiple printheads 19, and supplies a common printhead clock HEAD_CLK (ACT11) to the multiple printheads 19.

[0065] Therefore, in the inkjet head 19, the reset generation unit 41 within the ADC-embedded FPGA 26 generates an internal reset signal rest_out, which is output to each functional block within the ADC-embedded FPGA 26. The ADC read register unit 35 and the device address register unit 40, which have received the internal reset signal rest_out, are reset, and their stored serial communication device addresses are initialized, becoming a specific initial serial communication device address common to multiple inkjet heads 19. This initial serial communication device address is unavailable in other inkjet heads 19 that are not supplied with inkjet head logic power.

[0066] When the unique identification information of the inkjet head 19, i.e., the FPGA intrinsic ID, is read through the serial communication path, the intrinsic ID cannot be read unless a specific code (value) is written to the access code register of the ADC read register section 35 within the ADC built-in FPGA 26. In other words, the intrinsic ID cannot be read unless the register is set to be valid. Therefore, the MCU 43 sends the FPGA intrinsic ID access code (ACT12) to the aforementioned initial serial communication device address through the serial communication path to make the access code register set to be valid.

[0067] The FPGA intrinsic ID access code is received by the serial communication unit 36 ​​of the inkjet head 19, which is initialized with the initial serial communication device address, and the access code register of the ADC read register unit 35 is set to valid. By setting this register to valid, the FPGA intrinsic ID stored in the intrinsic ID storage unit 33 is written to the ADC read register unit 35 via the intrinsic ID interface unit 34. Then, the ADC read register unit 35 sends the written FPGA intrinsic ID to the MCU 43 via the serial communication path through the serial communication unit 36.

[0068] MCU43 reads the FPGA's intrinsic ID (ACT13) sent via the serial communication path.

[0069] Then, MCU43 determines whether to read the FPGA's intrinsic ID (ACT14). If it is determined that it cannot be read (no for ACT14), MCU43 repeats the process from ACT11 above.

[0070] If it is determined that an FPGA intrinsic ID has been read (as in ACT14), MCU43 stores the read FPGA intrinsic ID in internal memory 45 (ACT15). For example, the read FPGA intrinsic ID is written to the record in the address table that has the head ID of the object inkjet head 19.

[0071] Then, MCU43 sends the FPGA intrinsic ID access code that invalidates the access code register setting to the aforementioned initial serial communication device address (ACT16) via the serial communication path. As a result, in the inkjet head 19 initialized to the initial serial communication device address, the access code register setting of the ADC read register unit 35 is invalidated, and the ADC read register unit 35 terminates the transmission of the FPGA intrinsic ID via the serial communication path through the serial communication unit 36.

[0072] Next, MCU43 sends setting data to DrIC27. After confirming that the CFG_DONE signal is active, it executes the processing sequence to switch the serial communication device address of the inkjet head 19 to the new serial communication device address.

[0073] That is, firstly, the MCU43 causes the head interface high-speed data transmission unit 44 to send the serial communication device address setting code for switching the target inkjet head 19 to a new serial communication device address to the target inkjet head 19 via the inkjet head high-speed data transmission path (ACT17).

[0074] Then, MCU43 associates the new serial communication device address set by the serial communication device address setting code with the FPGA intrinsic ID of the inkjet head 19 (ACT18). That is, MCU43 stores the new serial communication device address corresponding to the FPGA intrinsic ID stored in internal memory 45 in ACT15 above. For example, in the address table of internal memory 45, the new serial communication device address is written into the record that has the head ID of the inkjet head 19 and is written with the FPGA intrinsic ID.

[0075] In the inkjet head 19 that receives the serial communication device address setting code, the high-speed data transmission receiving unit 29 within the ADC-built FPGA 26 analyzes the code and stores the new serial communication device address in the device address register unit 40. While storing the new serial communication device address, the device address register unit 40 sends a message to the ADC read register unit 35 indicating that the device address update order has been verified. It should be noted that if the code analysis by the high-speed data transmission receiving unit 29 is inconsistent, the serial communication device address setting code is ignored. Therefore, in this case, the new serial communication device address is not stored; that is, the serial communication device address is not updated, and no address switching authentication signal is sent.

[0076] MCU43 determines whether the authentication signal has been received, that is, whether the CFG_DONE signal is OK (ACT19). If the authentication is not OK (no in ACT19), it returns to the process described in ACT17 above and issues the serial communication device address setting code to switch to a different new serial communication device address. Alternatively, MCU43 can restart from the process sequence described in ACT11 above.

[0077] If the authentication is deemed OK (ACT19 is OK), the MCU43 performs a device address scan operation via the serial communication path to confirm that the serial communication device address has been updated (ACT20). The device address scan operation uses a structure that sends (requests) and returns (confirms) responses to serial communication device addresses from the MCU43 via serial communication to scan a specific range of serial communication device addresses and investigate which serial communication device address has a response.

[0078] Then, MCU43 checks whether the association between the FPGA intrinsic ID stored in internal memory 45 and the updated serial communication device address is OK (ACT21). For example, MCU43 can confirm this by checking whether the serial communication device address that received a reply in the device address scan of ACT20 corresponds to the FPGA intrinsic ID and is stored in internal memory 45. If the association is determined to be OK (no in ACT21), MCU43 returns to the process described in ACT17 above and issues a serial communication device address setting code for switching to another new serial communication device address.

[0079] If the association is determined to be OK (as in ACT21), MCU43 implements a processing sequence to verify whether the association is correct.

[0080] That is, firstly, MCU43 sends the FPGA intrinsic ID access code (ACT22) that enables the access code register to be set to valid via the new serial communication device address of the inkjet head 19 of the associated object through the serial communication path.

[0081] Then, the FPGA intrinsic ID access code is received by the serial communication unit 36 ​​of the inkjet head 19, which has switched to the new serial communication device address, and the register setting of the access code register of the ADC read register unit 35 is valid. As a result, the ADC read register unit 35 sends the FPGA intrinsic ID to the MCU 43 via the serial communication path through the serial communication unit 36.

[0082] MCU43 reads the FPGA's intrinsic ID (ACT23) sent via the serial communication path.

[0083] Then, MCU43 determines whether to read the FPGA's intrinsic ID (ACT24). If it is determined that it cannot be read (no for ACT24), MCU43 repeats the process from ACT22 above.

[0084] If it is determined that the FPGA's intrinsic ID has been read (ACT24), the MCU43 sends an FPGA intrinsic ID access code (ACT25) to the new serial communication device address via the serial communication path, which invalidates the access code register setting. As a result, in the inkjet head 19, the access code register setting of the ADC read register unit 35 is invalidated, and the ADC read register unit 35 stops sending the FPGA intrinsic ID via the serial communication path through the serial communication unit 36.

[0085] Then, MCU43 determines whether the association is OK, that is, whether the FPGA intrinsic ID read in ACT23 above is correctly associated with the new serial communication device address of the inkjet head 19 of the object (ACT26). If the association is determined to be not OK (no in ACT26), MCU43 restarts from the processing sequence of ACT11 above.

[0086] If the association is determined to be OK (as in ACT26), MCU43 terminates the processing sequence shown in the flowchart. Then, the other inkjet heads 19 are processed, and the processing sequence shown in the flowchart is executed.

[0087] As described above, the inkjet head 19 according to the first embodiment includes: a head unit 25 configured with a plurality of actuators for ejecting ink and an in-head control circuit 24 for controlling the head unit 25. The in-head control circuit 24 includes: a drive IC, namely DrIC 27, for driving the plurality of actuators of the head unit 25; an AD conversion circuit, namely ADC 28, for converting analog detection signals from sensors provided in the head unit 25 into digital detection data; and an ADC-embedded FPGA 26 for controlling the drive IC based on drive commands from a head control circuit, namely head controller 20, provided outside the inkjet head 19, via a high-speed data transmission path of the inkjet head, and controlling serial communication via a serial communication path between the head controller 20 and the ADC 28. Then, the ADC built-in FPGA 26 is configured to have: an intrinsic ID storage unit 33 that stores the unique identification information of the inkjet head 19, namely the FPGA intrinsic ID; an intrinsic ID interface unit 34 that, in response to an FPGA intrinsic ID access code which is a read code of the FPGA intrinsic ID from the head controller 20 via a serial communication path, sends the FPGA intrinsic ID stored in the intrinsic ID storage unit 33 to the intrinsic identification information reading unit of the head controller 20 via a serial communication path; an ADC read register unit 35; and a serial communication unit 36 ​​that, when transmitting high-speed data from the head controller 20 via the inkjet head... When the serial communication device address setting code of the address setting instruction of the output path specifies a new serial communication device address, the data receiving circuit section 32, command analysis section 38, device address update control circuit section 39, and device address register section 40 of the address switching section switch the serial communication device address of the inkjet head 19 to the specified new serial communication device address, and the ADC read register section 35 and serial communication section 36 of the serial communication section perform serial communication between the head controller 20 and the ADC 28 via the serial communication path in response to a serial communication request for a new serial communication device address from the head controller 20 via the serial communication path.

[0088] Furthermore, the head controller 20, which is part of the head control circuit according to the first embodiment, controls the operation of multiple inkjet heads 19 by assigning instructions to them via the inkjet head high-speed data transmission path. It includes a microcomputer MCU 43 that operates as an address acquisition unit, an instruction unit, an address association unit, and a serial communication unit. The address acquisition unit obtains unique identification information for each inkjet head 19 from each inkjet head 19 via the serial communication path. The instruction unit assigns a new serial communication device address, independent of the FPGA's inherent ID, to each inkjet head 19, and assigns instructions to each inkjet head 19. The address setting instruction for switching to the new serial communication device address is sent via the inkjet head high-speed data transmission path. The address association unit associates the FPGA's inherent ID and the new serial communication device address with the multiple inkjet heads 19 respectively and stores them in the internal memory 45 of the MCU 43. The serial communication unit sends the new serial communication device address stored in the internal memory 45 via the serial communication path. Serial communication is performed between the inkjet head that has switched to the new serial communication device address and the ADC 28 that converts analog detection signals from sensors in the head unit equipped with multiple actuators that eject ink into digital detection data via the serial communication path.

[0089] Thus, in the first embodiment, when serial communication such as I2C is used in the inkjet head 19 equipped with an FPGA for control of an ADC or the like, a serial communication device address setting code for switching to a new serial communication device address is sent from the MCU43 of the head controller 20, which is the serial communication master controller, through the inkjet head high-speed data transmission path, which is different from the serial communication path. Through the high-speed data transmission receiving unit 29 inside the inkjet head 19, the device address of the serial communication unit 36 ​​of the I2C slave interface unit will be intentionally switched to a new serial communication device address based on the received serial communication device address setting code.

[0090] Therefore, the serial communication device address can be updated at high speed. Furthermore, the MCU43 of the head controller 20 can directly control the ADC and other components mounted on the multiple inkjet heads 19 by specifying the serial communication device address. Therefore, according to the first embodiment, it is not necessary to include components such as switch ICs in the head control circuit, and serial communication can be performed between multiple inkjet heads that may conflict with the serial communication device address.

[0091] Furthermore, by mounting an FPGA in the in-head control circuit 24 of the inkjet head 19, it can be recognized as a device by the head controller 20. Therefore, the internal structure of the in-head control circuit 24 can be customized to a certain extent, and each component can be made as a functional block in the FPGA 26 built into the ADC.

[0092] Furthermore, since the FPGA's intrinsic ID stored in the intrinsic ID storage unit 33 mounted on the inkjet head 19 can be read, the MCU 43 of the head controller 20 can easily manage and control the new device address associated with the unchanged FPGA intrinsic ID.

[0093] [Second Implementation]

[0094] Next, the second embodiment will be described. Here, the description of the parts that are the same as those in the first embodiment will be omitted, and only the parts that are different from those in the first embodiment will be described.

[0095] Figure 6 This is a diagram illustrating an example of the configuration of the inkjet head 19 according to the second embodiment. (See diagram below.) Figure 6 As shown, in the inkjet head 19 according to the second embodiment, the in-head control circuit 24 replaces the ADC-built FPGA 26 in the first embodiment, and includes an FPGA 46 and an ADCIC 47. In the FPGA 46, instead of the ADC 28, a serial communication unit 48 and a serial communication control unit 49 are formed as functional blocks.

[0096] ADCIC47 is an IC that performs AD conversion.

[0097] The serial communication unit 48 within FPGA 46 acts as a host unit opposite to ADCIC 47, using a fixed address owned by ADCIC 47 to perform serial communication with ADCIC 47. The serial communication control unit 49 within FPGA 46 intervenes in the ADC read register unit 35 to control the MCU 43 of the head controller 20, and mediates between the ADC read register unit 35 and the serial communication unit 48.

[0098] As described above, the inkjet head 19 in the second embodiment is the same as in the first embodiment, except that the AD conversion circuit is external to the FPGA 46 and a functional block for communicating with the AD conversion circuit is formed within the FPGA 46. Therefore, it achieves the same effect as the first embodiment.

[0099] It should be noted that the order and content of the flowcharts shown in the implementation methods and variations are merely examples. If the same effect can be achieved, the order and content can be appropriately changed.

[0100] Additionally, the serial communication device address is shown as an example of 4 bits, but it can also be other numbers of bits.

[0101] While several embodiments of the invention have been described, these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, with various omissions, substitutions, and modifications made without departing from the spirit of the invention. These embodiments, and their variations, are included within the scope and spirit of the invention, and within the scope of the invention as described in the claims and its equivalents.

Claims

1. An inkjet head comprising a head unit equipped with a plurality of actuators for ejecting ink and a control circuit for controlling said head unit, characterized in that, The control circuit includes: The driver IC that drives the plurality of actuators of the head unit An AD conversion circuit that converts analog detection signals from sensors located in the head unit into digital detection data, and... The FPGA controls the driver IC based on drive commands from a head control circuit located outside the inkjet head via a data transmission path, and also controls serial communication via a serial communication path between the head control circuit and the AD conversion circuit. The FPGA is configured to have: Storage unit that stores the unique identification information of the inkjet head An inherent identification information reading unit, in response to a readout code for the unique identification information from the head control circuit via the serial communication path, transmits the unique identification information stored in the storage unit to the head control circuit via the serial communication path. The address switching unit, when a new serial communication device address is specified by an address setting instruction from the head control circuit via the data transmission path, switches the serial communication device address of the inkjet head from the initial serial communication device address to the specified new serial communication device address. A serial communication unit, in response to a serial communication request for the new serial communication device address from the head control circuit via the serial communication path, performs serial communication between the head control circuit and the AD conversion circuit via the serial communication path.

2. The inkjet head according to claim 1, characterized in that, The FPGA is configured to have the AD conversion circuit built in.

3. The inkjet head according to claim 1, characterized in that, The AD conversion circuit is an AD conversion IC configured externally to the FPGA. The FPGA is configured to also have a communication unit for serial communication with the AD conversion IC.

4. The inkjet head according to any one of claims 1 to 3, characterized in that, The address switching unit of the FPGA is configured to have: The device address register section used to store the address of the new serial communication device The command analysis unit analyzes the address setting instruction from the head control circuit via the data transmission path to obtain the address of the new serial communication device, and... The address update control unit stores the new serial communication device address obtained by the command analysis unit in the device address register.

5. The inkjet head according to any one of claims 1 to 3, characterized in that, The FPGA has a reset generation section and an OR circuit section.

6. The inkjet head according to claim 4, characterized in that, The FPGA has a reset generation section and an OR circuit section.

7. The inkjet head according to any one of claims 1 to 3, characterized in that, The FPGA is equipped with a high-speed data transmission receiving unit and a data processing unit.

8. The inkjet head according to claim 4, characterized in that, The FPGA is equipped with a high-speed data transmission receiving unit and a data processing unit.

9. The inkjet head according to claim 5, characterized in that, The FPGA is equipped with a high-speed data transmission receiving unit and a data processing unit.

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