Detector training method based on phase compensation of accompanying clock and timing reset signal

Abstract

The present application relates to the technical field of detector training, and particularly relates to a detector training method based on phase compensation of accompanying clock and timing reset signal, which adopts high-frequency accompanying clock output by a detector to sample serial image data, can avoid sampling error influence caused by temperature change, and can realize stable and reliable sampling in a large temperature change range; an imaging controller obtains the temperature of the detector and the temperature near the temperature sensor by polling the remote temperature and the local temperature of the temperature sensor, and then obtains the temperature change of the timing and reset driver, adjusts the phase of the timing reset signal according to the temperature change of the timing and reset driver, so that the sampling of the internal timing reset signal of the detector will not appear metastable state.

Description

Technical Field

[0001] This invention relates to the field of detector training technology, and in particular to a detector training method based on phase compensation of accompanying clock and timing reset signal. Background Technology

[0002] For high-frequency, high-power detectors with rapid temperature rise, the temperature during serial image data conditioning may differ significantly from the temperature during image capture. Furthermore, the temperature may fluctuate considerably during conditioning, leading to a large deviation between the conditioned bit correction information and the operational temperature. Additionally, the rapid temperature change during conditioning causes correction deviations, resulting in poor temperature adaptability after training, limiting operation to a narrow temperature range. Moreover, changes in ambient temperature can alter the phase of the detector's timing reset signal, potentially altering the serial data combination order and causing errors in the received parallel data combination.

[0003] The Chinese patent application with publication number CN115936147A and publication date of April 7, 2023, entitled "A High-Power Fast Temperature Rise Detector Training Method", mainly uses a dual data rate input register (IDDR) to widen the sampling range for low-frequency applications. It optimizes the switching of sampling clock edges and the determination of the number of detected transition edges, but does not meet the requirements of high-frequency applications.

[0004] Chinese patent publication number CN115190258A, published on October 14, 2022, entitled "A Serial Image Data Training Method with Low Resource Utilization and Time-Reset Per Line," describes a method that, after power-on training, combines the four synchronization words before the detector outputs valid data, simultaneously performing word correction and channel correction to ensure that the image data received after each line timing reset is the trained image data. This method is suitable for applications with high-frequency, high-power, and fast-temperature-rise detectors, but it requires parallel training of all detector channels, consuming significant system resources. Summary of the Invention

[0005] In view of the above-mentioned technical problems, the present invention proposes a detector training method based on the phase compensation of the accompanying clock and the timing reset signal. By using the accompanying clock with low temperature drift between serial data and serial data, the sampling error of serial image data caused by temperature changes is avoided. The ambient temperature changes are monitored by a temperature sensor, and the phase of the timing reset signal is adjusted according to the temperature change, thereby ensuring that the sampling of the timing reset signal inside the detector will not be metastable.

[0006] The detector training method based on phase compensation of accompanying clock and timing reset signal provided by this invention is implemented based on a serial image data conditioning system. The serial image data conditioning system includes an imaging controller, a detector, a temperature sensor, a first level converter, and a second level converter group; wherein...

[0007] The imaging controller includes a clock LVDS transmitter, a clock LVDS receiver, a data LVDS receiver, a control timing generator, a single-channel multiplexer, a serial image data conditioning controller, a clock element, at least two D flip-flops, and at least two data channels, each of which includes a delay-controllable delay unit, a sampler, and a serial-to-parallel converter.

[0008] The detector includes a clock LVDS transmitter, a clock LVDS receiver, a data LVDS transmitter, a frequency divider, a frequency divider by two, a timing generator, a digital-to-analog converter, and a parallel-to-serial converter;

[0009] The clock element generates the high-frequency clock of the imaging controller, the pixel clock of the imaging controller, the pixel delay clock of the imaging controller, and the reference clock of the delay unit based on the external input signal;

[0010] The high-frequency clock of the imaging controller is output in differential form to the clock LVDS receiver in the detector through the clock LVDS transmitter in the imaging controller, and converted into the high-frequency clock of the detector. The pixel clock of the detector is generated by the frequency divider and sent to the timing generator. At the same time, the high-frequency clock of the detector generates the accompanying clock of the serial image data through the frequency divider. The accompanying clock is output in differential form to the clock LVDS receiver in the imaging controller through the clock LVDS transmitter in the detector.

[0011] The clock LVDS receiver sends the accompanying clock of the received serial image data to the sampler and serial-to-parallel converter of each data channel, and sends the accompanying clock of the received serial image data to the frequency divider element for frequency division, and sends the pixel clock obtained after frequency division to the serial-to-parallel converter; the parallel image data output from each data channel is sent to a single-channel multiplexer. Under the control of the serial image data conditioning controller, the parallel image data of the corresponding channel is selected by the single-channel multiplexer according to the channel number for bit correction, word correction and channel correction, and the correction control signals are sent to the delay unit and serial-to-parallel converter respectively.

[0012] The timing generator generates synchronous drive control signals and timing reset signals based on the pixel clock of the imaging controller. The drive control signals and timing reset signals are converted into the levels required by the detector by the first level converter and the second level converter, respectively, and then enter the timing generator. Under the control of the timing generator, the analog image data after photoelectric conversion is converted into serial image data by the analog-to-digital converter and the parallel-to-serial converter in sequence, and then output to the data LVDS receiver in differential form by the data LVDS transmitter.

[0013] The imaging controller obtains the temperature change of the first level converter through a temperature sensor, and adjusts the phase of the timing reset signal according to the temperature change of the first level converter;

[0014] The phase adjustment method is as follows:

[0015] The input-output delay values ​​of the timing reset signal are measured at the lowest and highest operating temperatures of the first level converter to obtain the maximum delay deviation value t within the operating temperature range of the first level converter. delay_max ; where t delay_max =t delay_max_temp -t delay_min_temp , t delay_max_temp The highest temperature t max_temp The input / output delay value, t delay_min_temp The lowest temperature t min_temp The input / output delay values ​​are as follows;

[0016] Based on the maximum delay deviation value t within the operating temperature range of the first level converter delay_max The period length t of the detector's high-frequency clock sensor_clk The maximum value of the setup and hold time of the internal sampling circuit of the detector. d_hold_setup Divide the temperature range into m segments:

[0017]

[0018] Based on the number of temperature zones m, the operating temperature range t of the first level converter is determined. delay_min_temp ~t delay_max_temp Divide into m segments; when a temperature change exceeds one segment, the pixel delay clock phase change of the imaging controller corresponding to the timing reset signal will be adjusted.

[0019] Preferably, the timing reset signal under the pixel clock synchronization of the imaging controller is obtained by passing through all D flip-flops and sampling the pixel delay clock of the imaging controller.

[0020] Preferably, the clock element is a combination or hybrid clock management element of a digital clock management unit and a phase-locked loop.

[0021] Preferably, the external input signals include a low-frequency clock signal input from the imaging controller and a phase control signal for the pixel delay clock.

[0022] Preferably, the first level converter is positioned close to the temperature sensor and away from the detector.

[0023] Compared with the prior art, the present invention can achieve the following beneficial effects:

[0024] 1. By using the local temperature measurement function of the temperature sensor, the temperature change of the control timing generator can be obtained based on the temperature change of the detector. By monitoring the temperature change of the control timing generator, the phase of the timing reset signal is adjusted to ensure that the sampling of the timing reset signal inside the detector does not exhibit metastability. This eliminates the need for reconditioning of serial image data and parallel conditioning of all channels, saving logic and power resources.

[0025] 2. Using a high-frequency accompanying clock output by the detector to sample serial image data can avoid sampling errors caused by temperature changes and achieve stable and reliable sampling even within a large temperature range. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of a serial image data conditioning system provided according to an embodiment of the present invention;

[0027] Figure 2 This is a schematic diagram of detector operating clock generation according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the generation of a timing reset signal according to an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of multi-channel serial image data conditioning inside an imaging controller according to an embodiment of the present invention. Detailed Implementation

[0030] In the following description, embodiments of the invention will be described with reference to the accompanying drawings. In the description below, the same modules are denoted by the same reference numerals. Where the same reference numerals are used, their names and functions are also the same. Therefore, their detailed description will not be repeated.

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.

[0032] The detector training method based on phase compensation of accompanying clock and timing reset signal provided by this invention is implemented based on a serial image data conditioning system, the structure of which is as follows: Figure 1 As shown, it mainly includes an imaging controller, a detector, a temperature sensor, and external level converters (level converter 1 and level converter group 2).

[0033] The imaging controller includes a clock element, a clock LVDS transmitter, a clock LVDS receiver, a data LVDS receiver, and a control timing generator.

[0034] The detector includes a clock LVDS transmitter, a clock LVDS receiver, a data LVDS transmitter, a frequency divider, a frequency divider by two, a timing generator, a digital-to-analog converter, and a parallel-to-serial converter.

[0035] The LVDS clock transmitter in the imaging controller outputs a differential high-frequency clock to the LVDS clock receiver in the detector. After being converted into a high-frequency clock inside the detector, it is divided by a frequency divider to generate the pixel clock inside the detector. This pixel clock then enters the timing generator to coordinate the relevant timing operations inside the detector. At the same time, the high-frequency clock inside the detector is divided by two to generate a clock accompanying the output serial image data. This clock is then converted into a differential image clock by the LVDS clock transmitter in the detector and sent to the imaging controller, where it is received by the LVDS clock receiver.

[0036] The generation diagram of the detector's operating clock is shown below. Figure 2 As shown, the phase control signals of the low-frequency clock and pixel delay clock input from the external imaging controller are processed by the internal clock element of the imaging controller to generate the high-frequency clock of the imaging controller, the reference clock of the delay unit, the pixel clock of the imaging controller, and the pixel delay clock of the imaging controller. The pixel delay clock of the imaging controller has the same frequency as the pixel clock of the detector, but different phases, and the output phase is controlled by the phase control signal of the pixel delay time.

[0037] The clock element can be a combination of a digital clock management unit (DCM) and a phase-locked loop (PLL), or a hybrid mode clock management (MMCM) element. It is required that the pixel delay clock phase of the detector can be adjusted and controlled by an external digital control signal.

[0038] The high-frequency clock of the imaging controller is output to the detector in differential form, generating a high-frequency clock inside the detector, which is then converted into a pixel clock inside the detector after being divided by a frequency divider.

[0039] The timing generator generates synchronized drive control signals and timing reset signals based on the pixel clock of the imaging controller. These signals are then converted to the levels required by the detector by level converters 1 and 2, enabling detector timing and phase control. The analog image data generated by the timing generator is converted into parallel data by the detector's analog-to-digital converter, then into serial image data by a parallel-to-serial converter, and finally into differential serial image data by a data LVDS transmitter before being sent to the imaging controller and received by the data LVDS receiver within the imaging controller.

[0040] The flowchart for generating the timing reset signal is as follows: Figure 3 As shown, the timing reset signal under the pixel clock synchronization of the imaging controller is obtained by passing through two or more D flip-flops in the imaging controller and sampling the pixel delay clock of the imaging controller.

[0041] Multi-channel serial image data conditioning within the imaging controller, such as Figure 4 As shown, the imaging controller internally includes n data channels, each containing a delay-controlled delay unit, a sampler, and a serial-to-parallel converter. Additionally, the imaging controller includes a single-channel multiplexer and a serial image data conditioning controller. The LVDS clock receiver within the imaging controller sends the accompanying clock of the received serial image data to the sampler and serial-to-parallel converter of each data channel, and also sends the accompanying clock to a frequency divider. The pixel clock obtained after frequency division is sent to the serial-to-parallel converter. The parallel image data output from each data channel is sent to the single-channel multiplexer. Under the control of the serial image data conditioning controller, the parallel image data of the corresponding channel is selected by the single-channel multiplexer according to the channel number. After correction according to the conventional bit correction, word correction, and channel correction process, the correction control signals are sent to the delay-controlled delay unit (corresponding to the bit correction control signal) and the serial-to-parallel converter (corresponding to the word correction and channel correction control signals), respectively.

[0042] Using a high-frequency accompanying clock output from the detector to sample serial image data can avoid sampling errors caused by temperature changes and achieve stable and reliable sampling even over a wide temperature range.

[0043] Level converter 1 is connected to a temperature sensor. The temperature change of level converter 1 is measured by the local temperature measurement function of the temperature sensor. The imaging controller can obtain the temperature change of level converter 1 by polling the local temperature of the temperature sensor. By monitoring the temperature change of level converter 1, the phase of the timing reset signal is adjusted.

[0044] The phase adjustment method for the timing reset signal is as follows:

[0045] Step 1: Measure the maximum delay deviation of level converter 1 within the temperature range.

[0046] The input and output delay values ​​of the timing reset signal are measured at the lowest and highest operating temperatures of level converter 1 to obtain the maximum delay deviation value t within the operating temperature range of the first level converter. delay_max ; where t delay_max =t delay_max_temp -t delay_min_temp , t delay_max_temp The highest temperature t max_temp The input / output delay values ​​are given below, where tdelay_min_temp is the minimum temperature t. min_temp The input / output delay values ​​below.

[0047] Step 2: Based on the maximum delay deviation value t within the operating temperature range of level converter 1. delay_max The period length t of the detector's high-frequency clock sensor_clk The maximum value of the setup and hold time of the internal sampling circuit of the detector. d_hold_setup Divide the temperature range into m segments:

[0048]

[0049] Step 3: Based on the number of temperature segments m, determine the operating temperature range t of level converter 1. delay_min_temp ~t delay_max_temp Divide into m segments; when a temperature change exceeds one segment, reset the pixel delay clock phase of the detector corresponding to the timing signal. As temperature increases, the phase value decreases; as temperature decreases, the phase value increases.

[0050] The temperature change of level converter 1 can be obtained through the local temperature measurement function of the temperature sensor. By monitoring the temperature change of level converter 1, the phase of the timing reset signal is adjusted to ensure that the sampling of the timing reset signal inside the detector will not be metastable. Therefore, it is not necessary to re-condition the serial image data or to perform parallel conditioning of all channels, thus saving logic and power resources.

[0051] By placing level converter 1 close to the temperature sensor and away from the detector, the temperature of level converter 1 is prevented from changing due to the heat generated by the detector, thereby reducing the input and output signal delay of level converter 1.

[0052] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0053] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A detector training method based on phase compensation of accompanying clock and timing reset signal, implemented using a serial image data conditioning system, the serial image data conditioning system comprising an imaging controller, a detector, a temperature sensor, a first level converter, and a second level converter group; wherein, The imaging controller includes a clock LVDS transmitter, a clock LVDS receiver, a data LVDS receiver, a control timing generator, a single-channel multiplexer, a serial image data conditioning controller, a clock element, at least two D flip-flops, and at least two data channels, each of which includes a delay-controllable delay unit, a sampler, and a serial-to-parallel converter. The detector includes a clock LVDS transmitter, a clock LVDS receiver, a data LVDS transmitter, a frequency divider, a frequency divider by two, a timing generator, a digital-to-analog converter, and a parallel-to-serial converter; Its features are: The clock element generates the high-frequency clock of the imaging controller, the pixel clock of the imaging controller, the pixel delay clock of the imaging controller, and the reference clock of the delay unit based on the external input signal; The high-frequency clock of the imaging controller is output in differential form to the clock LVDS receiver in the detector through the clock LVDS transmitter in the imaging controller, and converted into the high-frequency clock of the detector. The pixel clock of the detector is generated by the frequency divider and sent to the timing generator. At the same time, the high-frequency clock of the detector generates the accompanying clock of the serial image data through the frequency divider. The accompanying clock is output in differential form to the clock LVDS receiver in the imaging controller through the clock LVDS transmitter in the detector. The clock LVDS receiver sends the accompanying clock of the received serial image data to the sampler and serial-to-parallel converter of each data channel, and sends the accompanying clock of the received serial image data to the frequency divider element for frequency division, and sends the pixel clock obtained after frequency division to the serial-to-parallel converter; the parallel image data output from each data channel is sent to a single-channel multiplexer. Under the control of the serial image data conditioning controller, the parallel image data of the corresponding channel is selected by the single-channel multiplexer according to the channel number for bit correction, word correction and channel correction, and the correction control signals are sent to the delay unit and serial-to-parallel converter respectively. The timing generator generates synchronous drive control signals and timing reset signals based on the pixel clock of the imaging controller. The drive control signals and timing reset signals are converted into the levels required by the detector by the first level converter and the second level converter, respectively, and then enter the timing generator. Under the control of the timing generator, the analog image data after photoelectric conversion is converted into serial image data by the analog-to-digital converter and the parallel-to-serial converter in sequence, and then output to the data LVDS receiver in differential form by the data LVDS transmitter. The imaging controller obtains the temperature change of the first level converter through a temperature sensor, and adjusts the phase of the timing reset signal according to the temperature change of the first level converter; The phase adjustment method is as follows: The input-output delay values ​​of the timing reset signal are measured at the lowest and highest operating temperatures of the first level converter to obtain the maximum delay deviation value t within the operating temperature range of the first level converter. delay_max ; where t delay_max =t delay_max_temp -t delay_min_temp , t delay_max_temp The highest temperature t max_temp The input / output delay value, t delay_min_temp The lowest temperature t min_temp The input / output delay values ​​are as follows; Based on the maximum delay deviation value t within the operating temperature range of the first level converter delay_max The period length t of the detector's high-frequency clock sensor_clk The maximum value of the setup and hold time of the internal sampling circuit of the detector. d_hold_setup Divide the temperature range into m segments: Based on the number of temperature zones m, the operating temperature range t of the first level converter is determined. delay_min_temp ~t delay_max_temp Divide into m segments; when a temperature change exceeds one segment, the pixel delay clock phase change of the imaging controller corresponding to the timing reset signal will be adjusted.

2. The detector training method based on phase compensation of accompanying clock and timing reset signal according to claim 1, characterized in that: The timing reset signal under the pixel clock synchronization of the imaging controller is obtained by passing through all D flip-flops and sampling the pixel delay clock of the imaging controller.

3. The detector training method based on phase compensation of accompanying clock and timing reset signal according to claim 1, characterized in that: The clock element is a combination or hybrid clock management element of a digital clock management unit and a phase-locked loop.

4. The detector training method based on phase compensation of accompanying clock and timing reset signal according to claim 1, characterized in that: The external input signals include the low-frequency clock signal from the external input of the imaging controller and the phase control signal of the pixel delay clock.

5. The detector training method based on phase compensation of accompanying clock and timing reset signal according to claim 1, characterized in that: The first level shifter is positioned close to the temperature sensor and away from the detector.

Images