Method for calibrating electrical energy error, chip and error board
By combining the first and third timers with the internal event triggering function, the deviation problem caused by counting delay in traditional power error calculation is solved, thereby achieving accuracy in power error calculation and optimization of hardware resources.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN CLOU ELECTRONICS
- Filing Date
- 2023-12-19
- Publication Date
- 2026-07-21
Smart Images
Figure CN117706464B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electrical energy error measurement technology, and in particular to an electrical energy error verification method, chip, and error board. Background Technology
[0002] An error board is typically used when verifying energy error. This board receives both the standard energy pulse from the standard energy meter and the pulse from the meter under test. By combining the pulse constants of both the standard and under-test meters, the energy error of the under-test meter can be calculated. To ensure accurate energy error verification, the accuracy of pulse counting and synchronization during the verification process must be guaranteed. Traditionally, external interrupts to the MCU are triggered by the standard and under-test pulses respectively, and the pulse counts are accumulated in the corresponding interrupt response functions. However, the MCU's execution of the judgment command in each interrupt function introduces a delay, causing a deviation between the calculated and actual energy error values. Summary of the Invention
[0003] The main technical problem addressed by the embodiments of this application is that the calculated value of electrical energy error deviates from the actual value in traditional technologies.
[0004] To solve the above-mentioned technical problems, the first technical solution adopted in the embodiments of this application is: providing a method for verifying electrical energy error, including: setting a pulse constant to be tested, a number of pulses to be tested, a standard pulse constant, and a verification power value; and calculating a verification start count value and a verification end count value of a first timer; clearing the first count value of the first timer; starting the first timer to receive externally input pulses to be tested; and comparing the verification start count value and the first count value through a comparator of the first timer, wherein the first count value represents the number of pulses to be tested received by the first timer; when the first count value is equal to the verification start count value, starting a second timer and triggering the input capture function of the second channel of a third timer; and obtaining the first complete cycle of the standard pulse through the input capture function of the first channel of the third timer. A first-cycle value is obtained by acquiring the current second count value of the third timer through the input capture function of the second channel of the third timer, wherein the clock source of the second timer is a standard pulse and the clock source of the third timer is an internal clock; when the first count value is equal to the verification end count value, the current third count value of the second timer is obtained, and the second-cycle value of the previous complete cycle of the standard pulse is obtained through the input capture function of the first channel, and the current fourth count value of the third timer is obtained through the input capture function of the second channel; the number of received standard pulses is calculated using the first cycle value, the second count value, the second cycle value, the third count value, and the fourth count value; and the power error is calculated using the tested pulse constant, the number of tested pulses, the standard pulse constant, and the number of received standard pulses.
[0005] Optionally, after the step of starting the first timer to receive the externally input tested pulse and comparing the test start count value and the first count value through the comparator of the first timer, the method further includes: if the test end count value is greater than the maximum count value of the first timer, setting the overflow portion of the test end count value as the number of overflows to be recorded for the first timer; when the number of tested pulses is greater than the maximum count value of the first timer and the first count value is equal to the test start count value, disabling the comparison matching event output function of the comparator; when the second timer overflows, incrementing the overflow count value of the second timer by 1; when the first timer overflows, determining whether the number of overflows to be recorded for the first timer is greater than 0, and if it is greater than 0, decrementing the number of overflows to be recorded by 1; if the comparison matching event output function of the first timer is disabled, determining whether the number of overflows to be recorded for the first timer is less than or equal to 1 in the subsequent comparison matching interrupt response function of the first timer, and if it is less than or equal to 1, re-enabling the comparison matching event output function of the comparator.
[0006] Optionally, the step of calculating the verification start count value and verification end count value of the first timer includes: calculating the verification start count value according to formula (1):
[0007]
[0008] Wherein, P represents the verification power value, C represents the tested pulse constant, t represents the synchronization preparation time before the verification begins, and N... start This represents the count value at the start of the verification; the count value at the end of the verification is calculated according to formula (2), N. start An integer between 0 and the overflow value of the first timer:
[0009] N end =N start +N set (2)
[0010] Where, N set N represents the number of pulses being detected. end This indicates the count value at the end of the verification.
[0011] Optionally, the step of calculating the number of received standard pulses using the first period value, the second count value, the second period value, the third count value, and the fourth count value includes: calculating the integer part of the number of received standard pulses according to formula (3):
[0012] Cnt StdInt =Ovf T2 *N ovf +Cnt T2 (3)
[0013] Among them, Ovf T2 N represents the overflow count value of the second timer. ovf Cnt represents the number of overflows of the second timer. T2 This represents the third count value, Cnt. StdInt The integer part of the number of received standard pulses is represented; the fractional part of the number of received standard pulses is calculated according to formula (4):
[0014]
[0015] Where Per1 represents the first period value, Cap1 represents the second count value, Per2 represents the second period value, Cap2 represents the third count value, and Cnt represents the third count value. StdDec The fractional part of the number of received standard pulses is represented; the number of received standard pulses is calculated according to formula (5):
[0016] CntStd =Cnt StdInt +Cnt StdDec (5)
[0017] Among them, Cnt Std This indicates the number of received standard pulses.
[0018] Optionally, the step of calculating the power error using the detected pulse constant, the number of detected pulses, the standard pulse constant, and the number of received standard pulses includes:
[0019] The electrical energy error is calculated according to formula (6):
[0020]
[0021] Wherein, E represents the power error, C1 represents the detected pulse constant, C2 represents the standard pulse constant, N represents the number of detected pulses, and M represents the number of received standard pulses.
[0022] Optionally, the clock source frequency of the third timer and the frequency of the standard pulse satisfy formula (7):
[0023] f T3 ≤f Std *2 m (7)
[0024] Among them, f T3 f represents the clock source frequency of the third timer. Std The frequency of the standard pulse is represented by m, and the number of bits in the third timer is represented by m.
[0025] Optionally, the number of bits of the first timer is equal to the number of bits of the second timer, and the number of bits of the third timer is greater than or equal to 32.
[0026] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: providing a power error detection chip, including a first timer, a second timer, and a third timer; the external clock input port of the first timer is connected to an external detected pulse, and the count value of the first timer is used to accumulate the number of detected pulses. When the count value of the first timer is equal to the calculated detection start count value, a comparison matching interrupt of the first timer is triggered to output a detection start signal; when the count value of the first timer is equal to the calculated detection end count value, a comparison matching interrupt of the first timer is triggered to output a detection end signal; the external clock input port of the second timer is connected to an external standard pulse. The first timer starts counting when the verification start signal is received, accumulating the integer part of the standard pulse value during one verification process, and stops counting when the verification end signal is received. The clock source of the third timer is an internal clock, and the input port of the first channel of the third timer is connected to an external standard pulse. Through the input capture and automatic clearing function of the first channel, the first cycle value of the previous complete cycle of the standard pulse is continuously acquired. When the verification start signal is received, the input capture of the second channel is triggered to acquire the current count value of the third timer. The power error verification chip cooperates with the first timer, the second timer and the third timer to execute the power error verification method described above.
[0027] To solve the above-mentioned technical problems, the third technical solution adopted in the embodiments of this application is: to provide an error board, including the power error detection chip as described above.
[0028] To solve the above-mentioned technical problems, the fourth technical solution adopted in the embodiments of this application is: to provide a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by an electronic device, the electronic device performs the power error detection method as described above.
[0029] Unlike related technologies, this application sets the number of pulses to be tested, calculates the start and end count values of the verification, and starts a first timer to receive the pulses to be tested. When the first count value equals the start count value, a second timer is started, triggering the input capture function of the second channel of the third timer. The first cycle value of the previous complete cycle of the standard pulse is obtained through the first channel of the third timer, and the current second count value of the third timer is obtained through the second channel. When the first count value equals the end count value, the current third count value of the second timer is obtained, the second cycle value of the previous complete cycle of the standard pulse is obtained through the first channel, and the current fourth count value of the third timer is obtained through the second channel. The number of received standard pulses and the power error are calculated sequentially using the aforementioned data. This not only further simplifies the circuit used for power error verification and saves costs by using fewer hardware resources, but also increases the synchronization between the start and end of the power error verification by defining the start and end times of the power error verification through a comparison matching function and automatically synchronizing using an internal event triggering function, thereby improving the accuracy of power error calculation. Attached Figure Description
[0030] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0031] Figure 1 This is a schematic flowchart of an embodiment of the power error verification method provided in this application;
[0032] Figure 2 This is a pulse timing diagram of the tested pulse and the standard pulse in a conventional power error detection method provided in an embodiment of this application;
[0033] Figure 3 This is a schematic diagram illustrating the principle of calculating the fractional part of the number of standard pulses during power error detection according to an embodiment of this application;
[0034] Figure 4 This is a schematic diagram of the structure of a power error detection chip provided in an embodiment of this application;
[0035] Figure 5 This is a schematic diagram of the hardware structure of an error board for performing an electrical energy error verification method according to an embodiment of this application. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0037] It should be noted that, unless otherwise specified, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device schematic diagram or the order in the flowchart.
[0038] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.
[0039] In current power error measurement technology, to accurately calculate the power error value, it is first necessary to accurately count the pulses under test and to promptly start and stop counting the standard pulses at the beginning and end of the counting process. Secondly, it is necessary to accurately count the standard pulses during the power error verification process. However, in traditional power error verification processes, the pulses under test and the standard pulses are generally not perfectly aligned, such as... Figure 2 As shown, Figure 2 This is a pulse timing diagram of the tested pulse and the standard pulse in the traditional electrical energy error verification process. Figure 2 In the diagram, "Start" marks the beginning of the power error verification process, and "Stop" marks the end. This can be understood from... Figure 2 It is known that the number of standard pulses is overcounted at the beginning and undercounted at the end, and these overcounted and undercounted values do not cancel each other out. Therefore, to obtain an accurate number of standard pulses, in addition to obtaining the integer part of the number of standard pulses, it is also necessary to accurately calculate the phase difference between the standard pulses and the pulse under test at the beginning and end of the power error verification. This phase difference represents the fractional part of the number of standard pulses.
[0040] In addition, current power error measurement technologies typically trigger external interrupts on the MCU when counting the tested pulses and standard pulses. The corresponding interrupt handlers then accumulate the pulse counts. However, this leads to frequent interrupts from the MCU, impacting the real-time performance of the application layer code. Furthermore, the MCU's need to execute a judgment command in the interrupt function each time introduces a delay, which in turn introduces errors in the calculated standard pulse count, ultimately causing a deviation between the calculated and actual power error values.
[0041] The deficiencies of the aforementioned traditional technical solutions are the result of the applicant's practical experience and careful research. Therefore, the discovery process of the above problems and the solutions proposed in this application below should be considered as contributions made by the applicant to this application during the disclosure process.
[0042] Please see Figure 1 , Figure 1 This is a flowchart illustrating the power error verification method provided in this application embodiment, specifically including:
[0043] S10. Set the pulse constant under test, the number of pulses under test, the standard pulse constant, and the verification power value, and calculate the verification start count value and verification end count value of the first timer.
[0044] The pulse constant is used to characterize the number of energy pulses output by the energy meter during the accumulation of 1 kilowatt-hour of energy, and its unit is imp / kW·h. The choice of the pulse constant depends on the design and application requirements of the energy meter. Under the same power, the larger the pulse constant, the higher the frequency of the output energy pulses, and the higher the accuracy of the measured energy error.
[0045] The calibration power value represents the current power value measured by the energy meter under test. For example, a power source with the calibration power value is connected to the energy meter under test. The calibration time represents the time difference between the end time and the start time of the error calibration process for the tested pulse.
[0046] Preferably, the steps of calculating the verification start count value and verification end count value of the first timer include: first, calculating the verification start count value according to formula (1):
[0047]
[0048] Where P represents the verification power value, C represents the pulse constant under test, t represents the synchronization preparation time before the verification measurement begins, and N... start N represents the count value at the start of the verification. start It is an integer between 0 and the overflow value of the first timer. Then, the verification end count value is calculated according to formula (2):
[0049] N end =N start +N set (2)
[0050] Where, N set N represents the number of pulses detected. end This indicates the count value at the end of the verification process.
[0051] As an optional implementation, the first timer can be 16 bits, in which case the first timer can count from 1 to 65536, and the check start count value N can be set. start It is an integer less than 50,000, which is sufficient to count the number of pulses N being detected within the counting range of the first timer. set By retaining a certain margin, the pulse under test can be maintained in a stable output state for a certain period of time before the power error verification begins.
[0052] As another optional implementation, if the calculated verification end count value N... end The count has exceeded the range of the first timer; for example, when the first timer is 16-bit, the check ends with the count value N. end The value is 70000. At this point, the verification end count value N is set. end The high 16 bits are set as the overflow count for the first timer, and then the calculated test end count value N is used. end Update the lower 16 bits of the test end count value N. end .
[0053] S20. Clear the first count value of the first timer, start the first timer to receive the externally input pulses being tested, and compare the test start count value and the first count value through the comparator of the first timer. The first count value represents the number of pulses being tested received by the first timer.
[0054] To prevent the first count value of the first timer from interfering with the power error verification process, the first count value of the first timer can be reset to zero before starting the first timer. Then, by receiving the externally input pulse being tested through the external clock input port of the first timer, the clock source of the first timer is set to the external input clock (i.e., the externally input pulse being tested). This external input clock can be undivided and can be set to increment the count value by 1 on the rising edge of the pulse being tested. Simultaneously, the internal comparator of the timer is enabled, which compares the count value with the number of received pulses using the comparator built into the first timer. It should be noted that using this comparator does not require configuring the corresponding hardware output pin for the comparator function; only the comparator interrupt and the count overflow interrupt need to be enabled.
[0055] As an optional implementation, after starting the first timer to receive the externally input tested pulses and comparing the test start count value and the first count value using the comparator of the first timer, the method further includes: if the test end count value is greater than the maximum count value of the first timer, setting the overflow portion of the test end count value as the number of overflows to be recorded for the first timer. When the number of tested pulses is greater than the maximum count value of the first timer and the first count value is equal to the test start count value, the comparator's comparison matching event output function is disabled. Then, when the second timer overflows, the overflow count value of the second timer is incremented by 1. Simultaneously, when the first timer overflows, it is determined whether the number of overflows to be recorded for the first timer is greater than 0. If it is greater than 0, the number of overflows to be recorded is decremented by 1, indicating that the accumulated number of received tested pulses exceeds the maximum count value of the first timer. Finally, if the comparison matching event output function of the first timer is disabled, the subsequent comparison matching interrupt response function of the first timer determines whether the number of overflows to be recorded for the first timer is less than or equal to 1. If it is less than or equal to 1, the comparator's comparison matching event output function is re-enabled.
[0056] The power error verification process begins when the first timer starts, triggered by a comparator-outputted comparison match event. It ends when the second comparison match event is output by the comparator. However, if the first timer has a non-zero overflow count, the comparison match event output function will be triggered before the number of received pulses reaches the set total number of pulses. This causes the power error verification process to end due to insufficient received pulses. Therefore, the comparison match event output function of the first timer needs to be disabled when there is an overflow count, and enabled when there is no overflow count, so that the first timer triggers the power error verification process to end only after receiving a sufficient preset total number of pulses.
[0057] S30. When the first count value equals the verification start count value, start the second timer and trigger the input capture function of the second channel of the third timer. Obtain the first cycle value of the previous complete cycle of the standard pulse through the input capture function of the first channel of the third timer, and obtain the current second count value of the third timer through the input capture function of the second channel of the third timer. The clock source of the second timer is the standard pulse, and the clock source of the third timer is the internal clock.
[0058] The function of the second timer is to accumulate the integer part of the standard count during one power error verification process. The number of bits of the second timer can be the same as the number of bits of the first timer. The external input clock port of the second timer is connected to an external standard pulse, which can be a non-divided pulse. The third count value of the second timer is incremented by 1 on the rising edge of the standard pulse.
[0059] As an optional implementation, after the input capture function of the first channel is triggered, the fourth count value of the third timer is cleared.
[0060] S40. When the first count value equals the verification end count value, obtain the current third count value of the second timer, obtain the second cycle value of the previous complete cycle of the standard pulse through the input capture function of the first channel, and obtain the current fourth count value of the third timer through the input capture function of the second channel.
[0061] The third timer is used to calculate the period value of the standard pulse using the capture function of the first channel, and to calculate the fractional part of the number of standard pulses using the capture function of the second channel. The count value of the third timer is incremented by 1 on the rising edge of the internal clock.
[0062] As an alternative implementation, the third timer can be a 32-bit timer.
[0063] It should be noted that the input capture functions of the first and second channels in the third timer do not require enabling the capture interrupt, that is, there will be no interrupt delay, which further improves the accuracy of power error detection.
[0064] S50: Calculate the number of received standard pulses using the first cycle value, the second count value, the second cycle value, the third count value, and the fourth count value.
[0065] As an optional implementation, step S50 specifically includes: First, calculating the integer part of the number of received standard pulses according to formula (3):
[0066] Cnt StdInt =Ovf T2 *N ovf +Cnt T2 (3)
[0067] Among them, Ovf T2 N represents the overflow count value of the second timer. ovf This represents the overflow value of the second timer, Cnt. T2 Indicates the third count value, Cnt StdInt The integer part represents the number of received standard pulses. Then, the fractional part of the number of received standard pulses is calculated according to formula (4):
[0068]
[0069] Where Per1 represents the first cycle value, Cap1 represents the second count value, Per2 represents the second cycle value, Cap2 represents the third count value, and Cnt represents the third count value. StdDec This represents the decimal part of the number of received standard pulses. Finally, the number of received standard pulses is calculated according to formula (5):
[0070] Cnt Std =Cnt StdInt +Cnt StdDec (5)
[0071] Among them, Cnt Std This indicates the number of standard pulses received.
[0072] S60. Calculate the power error using the tested pulse constant, the number of tested pulses, the standard pulse constant, and the number of received standard pulses.
[0073] As an optional implementation, step S60 specifically includes: First, calculating the power error according to formula (6):
[0074]
[0075] Where E represents the power error, C1 represents the tested pulse constant, C2 represents the standard pulse constant, N represents the number of tested pulses, and M represents the number of received standard pulses.
[0076] In a preferred embodiment, the clock source frequency of the third timer and the frequency of the standard pulse satisfy formula (7):
[0077] f T3 ≤f Std *2 m (7)
[0078] Among them, f T3 f represents the clock source frequency of the third timer. Std The value represents the frequency of the standard pulse, and m represents the number of bits in the third timer.
[0079] In another preferred embodiment, the number of bits of the first timer is equal to the number of bits of the second timer, and the number of bits of the third timer is greater than or equal to 32.
[0080] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the principle of calculating the fractional part of the standard pulse count during power error detection according to an embodiment of this application. CH1 represents the first channel of the third timer, and CH2 represents the second channel of the third timer. Figure 3As can be seen from the content, the power error verification method provided by the embodiments of this application can accurately measure the fractional part of the number of standard pulses. If the internal clock frequency of the third clock is further increased, the accuracy of the fractional part can be further improved, which can be used for power error verification scenarios with higher accuracy requirements.
[0081] The power error verification method provided in this application embodiment sets the number of pulses to be tested, calculates the start and end count values of the verification, and starts a first timer to receive the pulses to be tested. When the first count value equals the start count value, a second timer is started, triggering the input capture function of the second channel of a third timer. The first cycle value of the previous complete cycle of the standard pulse is obtained through the input capture function of the first channel of the third timer, and the current second count value of the third timer is obtained through the second channel. When the first count value equals the end count value, the current third count value of the second timer is obtained, the second cycle value of the previous complete cycle of the standard pulse is obtained through the first channel, and the current fourth count value of the third timer is obtained through the second channel. The number of received standard pulses and the power error are calculated sequentially using the aforementioned data. This method not only simplifies the circuit used for power error verification and saves costs by using fewer hardware resources, but also defines the start and end times of power error verification through a comparison matching function and automatically synchronizes using an internal event triggering function, increasing the synchronization between the start and end of the pulses to be tested and the standard pulses, and further improving the accuracy of power error calculation.
[0082] Please see Figure 4 This application provides a power error detection chip 400, which includes a first timer 410, a second timer 420 and a third timer 430;
[0083] The external clock input port of the first timer 410 is connected to the external pulse being tested. The count value of the first timer 410 is used to accumulate the number of pulses being tested. When the count value of the first timer 410 is equal to the calculated test start count value, the comparison match interrupt of the first timer 410 is triggered to output the test start signal. When the count value of the first timer 410 is equal to the calculated test end count value, the comparison match interrupt of the first timer 410 is triggered to output the test end signal.
[0084] The external clock input port of the second timer 420 is connected to an external standard pulse. When the verification start signal is received, counting starts and the integer part of the standard pulse value is accumulated during one verification process. When the verification end signal is received, counting stops.
[0085] The clock source of the third timer 430 is an internal clock. The input port of the first channel of the third timer 430 is connected to an external standard pulse. The first cycle value of the previous complete cycle of the standard pulse is continuously acquired through the input capture and automatic clearing function of the first channel. When the verification start signal is received, the input capture of the second channel is triggered to acquire the current count value of the third timer 430.
[0086] The power error detection chip 400 cooperates with the first timer 410, the second timer 420 and the third timer 430 to execute the power error detection method as described above.
[0087] It should be noted that the aforementioned power error detection chip 400 can execute the power error detection method provided in the embodiments of this application, and has the corresponding functional elements and beneficial effects for executing the method. Technical details not described in detail in the power error detection chip embodiments can be found in the power error detection method provided in the embodiments of this application.
[0088] Please see Figure 5 , Figure 5 This is a schematic diagram of the hardware structure of the error board 500 for performing the power error detection method according to an embodiment of this application. The error board 500 includes the aforementioned power error detection chip 400, and further includes:
[0089] One or more processors 510 and memory 520, Figure 5 Take the 510 processor as an example.
[0090] The processor 510 and the memory 520 can be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.
[0091] The memory 520, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions corresponding to the power error detection method in the embodiments of this application. The processor 510 executes various functional applications and data processing of the error board 500 by running the non-volatile software programs, instructions, and modules stored in the memory 520, thereby implementing the power error detection method of the above-described method embodiments.
[0092] The memory 520 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function. The data storage area may store data created based on the use of the power error detection chip 400. In addition, the memory 520 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device.
[0093] The one or more modules are stored in the memory 520. When executed by the one or more processors 510, they perform the power error detection method in any of the above method embodiments, for example, the method described above. Figure 1 Steps S10 to S60 in the method are implemented. Figure 4 The functions of the first, second, and third timers.
[0094] The above-described product can perform the methods provided in the embodiments of this application, and has the corresponding functional elements and beneficial effects for performing the methods. Technical details not described in detail in this embodiment can be found in the methods provided in the embodiments of this application.
[0095] This application provides a non-volatile computer-readable storage medium storing computer-executable instructions that are executed by one or more processors, for example... Figure 5 One of the processors 510 can enable the one or more processors to execute the power error detection method in any of the above method embodiments, for example, to perform the above-described... Figure 1 Steps S10 to S60 in the method are implemented. Figure 4 The functions of the first, second, and third timers.
[0096] This application provides a computer program product, which includes a computer program stored on a non-volatile computer-readable storage medium. The computer program includes program instructions that, when executed by the power error detection chip or the error board, enable the power error detection chip or the error board to perform the power error detection method in any of the above-described method embodiments, for example, to perform the above-described... Figure 1 Steps S10 to S60 in the method are implemented. Figure 4 The functions of the first, second, and third timers.
[0097] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software and a general-purpose hardware platform, or of course, using hardware. Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for detecting electrical energy error, characterized in that, include: Set the pulse constant under test, the number of pulses under test, the standard pulse constant, and the verification power value, and calculate the verification start count value and verification end count value of the first timer; The first count value of the first timer is cleared to zero, the first timer is started to receive the externally input test pulse, and the test start count value and the first count value are compared by the comparator of the first timer, wherein the first count value represents the number of test pulses received by the first timer; When the first count value is equal to the verification start count value, the second timer is started and the input capture function of the second channel of the third timer is triggered. The first cycle value of the previous complete cycle of the standard pulse is obtained through the input capture function of the first channel of the third timer, and the current second count value of the third timer is obtained through the input capture function of the second channel of the third timer. The clock source of the second timer is the standard pulse, and the clock source of the third timer is the internal clock. When the first count value is equal to the verification end count value, the current third count value of the second timer is obtained, the second cycle value of the previous complete cycle of the standard pulse is obtained through the input capture function of the first channel, and the current fourth count value of the third timer is obtained through the input capture function of the second channel. The number of received standard pulses is calculated using the first period value, the second count value, the second period value, the third count value, and the fourth count value. The power error is calculated using the tested pulse constant, the number of tested pulses, the standard pulse constant, and the number of received standard pulses.
2. The method for detecting electrical energy error according to claim 1, characterized in that, After the steps of starting the first timer to receive the externally input pulse to be tested, and comparing the test start count value and the first count value through the comparator of the first timer, the method further includes: If the verification end count value is greater than the maximum count value of the first timer, the overflow portion of the verification end count value is set as the overflow count of the first timer; When the number of detected pulses is greater than the maximum count value of the first timer, and the first count value is equal to the detection start count value, the comparator's comparison matching event output function is turned off. When the second timer overflows, the overflow count value of the second timer is incremented by 1; When the first timer overflows, it is determined whether the number of overflows of the first timer is greater than 0. If it is greater than 0, the number of overflows is decremented by 1. If the comparison matching event output function of the first timer is disabled, then in the subsequent comparison matching interrupt response function of the first timer, it is determined whether the number of overflows of the first timer is less than or equal to 1. If it is less than or equal to 1, then the comparison matching event output function of the comparator is re-enabled.
3. The method for detecting electrical energy error according to claim 1, characterized in that, The steps for calculating the start and end count values of the first timer include: Calculate the starting count value for the test according to formula (1): Wherein, P represents the verification power value, C represents the tested pulse constant, t represents the synchronization preparation time before the verification begins, and N... start N represents the start count value of the test. start It is an integer between 0 and the overflow value of the first timer; Calculate the end count value of the verification according to formula (2): N end =N start +N set (2) Where, N set N represents the number of pulses being detected. end This indicates the count value at the end of the verification.
4. The method for detecting electrical energy error according to claim 2, characterized in that, The step of calculating the number of received standard pulses using the first period value, the second count value, the second period value, the third count value, and the fourth count value includes: Calculate the integer part of the number of received standard pulses according to formula (3): Hundreds stdσnt =Ovf T2 *N ovf +Cnt T2 (3) Among them, Ovf T2 N represents the overflow count value of the second timer. ovf Cnt represents the number of overflows of the second timer. T2 This represents the third count value, Cnt. stdInt The integer part of the value represents the number of received standard pulses; Calculate the fractional part of the number of received standard pulses according to formula (4): Where Per1 represents the first period value, Cap1 represents the second count value, Per2 represents the second period value, Cap2 represents the third count value, and Cnt represents the third count value. StdDec This represents the fractional part of the number of received standard pulses; The number of received standard pulses is calculated according to formula (5): Cnt Std =Cnt StdInt +Cnt StdDec (5) Among them, Cnt Std This indicates the number of received standard pulses.
5. The method for detecting electrical energy error according to claim 1, characterized in that, The step of calculating the power error using the tested pulse constant, the number of tested pulses, the standard pulse constant, and the number of received standard pulses includes: The electrical energy error is calculated according to formula (6): Wherein, E represents the power error, C1 represents the detected pulse constant, C2 represents the standard pulse constant, N represents the number of detected pulses, and M represents the number of received standard pulses.
6. The method for detecting electrical energy error according to claim 1, characterized in that, The clock source frequency of the third timer and the frequency of the standard pulse satisfy formula (7): f T3 ≤f Std *2 m (7) Among them, f T3 f represents the clock source frequency of the third timer. Std The frequency of the standard pulse is represented by m, and the number of bits in the third timer is represented by m.
7. The method for detecting electrical energy error according to claim 1, characterized in that, The number of bits in the first timer is equal to the number of bits in the second timer, and the number of bits in the third timer is greater than or equal to 32.
8. A power error detection chip, characterized in that, Including the first timer, the second timer, and the third timer; The external clock input port of the first timer is connected to the external pulse being tested. The count value of the first timer is used to accumulate the number of pulses being tested. When the count value of the first timer is equal to the calculated test start count value, the comparison match interrupt of the first timer is triggered to output the test start signal. When the count value of the first timer is equal to the calculated test end count value, the comparison match interrupt of the first timer is triggered to output the test end signal. The external clock input port of the second timer is connected to an external standard pulse. When the verification start signal is received, the counting starts and the integer part of the standard pulse value is accumulated during one verification process. When the verification end signal is received, the counting stops. The clock source of the third timer is an internal clock. The input port of the first channel of the third timer is connected to an external standard pulse. The first cycle value of the previous complete cycle of the standard pulse is continuously acquired through the input capture and automatic clearing function of the first channel. When the verification start signal is received, the input capture of the second channel is triggered to acquire the current count value of the third timer. The power error detection chip cooperates with the first timer, the second timer and the third timer to execute the power error detection method according to any one of claims 1-7.
9. An error plate, characterized in that, Includes the power error detection chip as described in claim 8.
10. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores computer-executable instructions, which, when executed by the error board according to claim 9, cause the error board to perform the power error verification method according to any one of claims 1-7.