Reference generation circuit and electronic device

Abstract

This invention provides a reference generation circuit and an electronic device. The reference generation circuit includes a main module, an output module, an overshoot suppression module, an output control module, and a startup module. The main module generates a positive temperature coefficient (PTC) current and outputs it to the output module. The output module converts the PTC current into a PTC voltage and generates a negative TTC voltage, then superimposes the PTC and negative TTC voltages to generate a reference voltage. The overshoot suppression module raises the node voltage within the main module to prevent the reference voltage generated by the output module from exceeding a first preset range. The output control module controls the output module to output when the reference voltage is stable. The startup module starts the main module, controls the overshoot suppression module, and controls the output control module to output. This invention suppresses overshoot by simultaneously controlling the range of change of the initial startup voltage and the output value, without slowing down the startup speed or increasing additional power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a reference generation circuit and electronic device. Background Technology

[0002] Reference generation circuits, such as bandgap reference sources, primarily serve to provide a stable voltage or current to the system, unaffected by external factors. Therefore, the output of such circuits must reach the expected voltage or current value within a limited time. Overshoot refers to a peak voltage or current exceeding the expected value that occurs at the beginning of the output, typically appearing as a spike pulse. If the output peak value exceeds the voltage and current withstand limits of subsequent circuits, it can damage the subsequent circuits or cause peak values ​​in their outputs, thus propagating the overshoot phenomenon within the system.

[0003] The overshoot phenomenon is mainly related to rapid power-up and the start-up and settling time of the circuit, making it difficult to completely eliminate. To avoid the adverse effects of overshoot on system operation, existing reference generation circuits often use separate delay control outputs or control of the initial startup voltage to suppress or mitigate overshoot. However, the effectiveness of separate control methods in suppressing overshoot is limited. Relying solely on filtering and delaying to filter overshoot caused by rapid power-up will affect the startup of subsequent circuits, thus slowing down the startup speed of the entire system. Introducing other power-up timing sequences to control the output will increase the complexity of the system. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the limitation of the overshoot suppression effect of the reference generation circuit using a separate control method in the prior art, and to provide a reference generation circuit and electronic device.

[0005] The present invention solves the above-mentioned technical problems through the following technical solution:

[0006] In a first aspect, the present invention provides a reference generation circuit, the reference generation circuit comprising: a main module, an output module, an overshoot suppression module, an output control module, and a startup module;

[0007] The main module is used to generate a positive temperature coefficient current and output the positive temperature coefficient current to the output module;

[0008] The output module is used to convert the positive temperature coefficient current into a positive temperature coefficient voltage and generate a negative temperature coefficient voltage, and to superimpose the positive temperature coefficient voltage and the negative temperature coefficient voltage to generate a reference voltage;

[0009] The overshoot suppression module is used to raise the node voltage within the main module to prevent the reference voltage generated by the output module from exceeding a first preset range;

[0010] The output control module is used to control the output module to output when the reference voltage is in a stable state; wherein, the reference voltage being in a stable state indicates that the reference voltage is within a second preset range within a preset time period, and the first preset range includes the second preset range;

[0011] The startup module is used to start the main module, control the overshoot suppression module, and simultaneously control the output control module to enable the output module to output.

[0012] Optionally, the output terminal of the startup module is electrically connected to the input terminal of the overshoot suppression module and the first input terminal of the output control module, respectively. The output terminal of the overshoot suppression module is electrically connected to the output terminal of the operational amplifier in the main module, the second input terminal of the output control module, and the first input terminal of the output module, respectively. The output terminal of the output control module is electrically connected to the second input terminal of the output module, and the output terminal of the output module outputs the reference voltage.

[0013] Optionally, the main module further includes: a first PMOS (P-channel metal-oxide-semiconductor) transistor, a second PMOS transistor, a first resistor, a first transistor, and a second transistor;

[0014] The gates of the first PMOS transistor, the second PMOS transistor, and the output of the operational amplifier are connected together as the port of the main module to transmit the node voltage.

[0015] The gate of the first PMOS transistor is also electrically connected to the gate of the second PMOS transistor and the output terminal of the operational amplifier. The source of the first PMOS transistor and the source of the second PMOS transistor are both electrically connected to the power supply voltage. The drain of the first PMOS transistor is electrically connected to the emitter of the first transistor and the inverting input terminal of the operational amplifier. The drain of the second PMOS transistor is electrically connected to the first end of the first resistor and the non-inverting input terminal of the operational amplifier. The second end of the first resistor is electrically connected to the emitter of the second transistor. The collector and base of the first transistor and the collector and base of the second transistor are both grounded.

[0016] Optionally, the output module includes: a third PMOS transistor, a sixth PMOS transistor, a third transistor, and a second resistor;

[0017] The gate of the third PMOS transistor is electrically connected as the first input terminal of the output module, the gate of the sixth PMOS transistor is used as the second input terminal of the output module, and the drain of the sixth PMOS transistor is used as the output terminal of the output module.

[0018] The source of the third PMOS transistor is connected to the power supply voltage, the drain of the third PMOS transistor is electrically connected to the source of the sixth PMOS transistor, the drain of the sixth PMOS transistor is also electrically connected to the first end of the second resistor, and the second end of the second resistor is electrically connected to the emitter of the third transistor.

[0019] The base and collector of the third transistor are both grounded.

[0020] Optionally, the overshoot suppression module includes: a first NMOS (N-channel metal-oxide-semiconductor) transistor and a third resistor;

[0021] The gate of the first NMOS transistor is used as the input terminal of the overshoot suppression module, and the drain of the first NMOS transistor is used as the output terminal of the overshoot suppression module.

[0022] The source of the first NMOS transistor is electrically connected to the first terminal of the third resistor, and the second terminal of the third resistor is grounded.

[0023] Optionally, the output control module includes: a fourth PMOS transistor, a fifth PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a first capacitor;

[0024] The gate of the second NMOS transistor is used as the first input terminal of the output control module, the gate of the fourth PMOS transistor is used as the second input terminal of the output control module, and the drain of the fifth PMOS transistor is used as the output terminal of the output control module.

[0025] The drain of the second NMOS transistor is electrically connected to the drain of the fourth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the third NMOS transistor, and the first terminal of the first capacitor, respectively.

[0026] The source of the fourth PMOS transistor and the source of the fifth PMOS transistor are both electrically connected to the power supply voltage, and the drain of the fifth PMOS transistor is electrically connected to the drain of the third NMOS transistor.

[0027] The source of the second NMOS transistor, the source of the third NMOS transistor, and the second terminal of the first capacitor are all grounded.

[0028] Optionally, the emitter of the third transistor outputs the negative temperature coefficient voltage.

[0029] Optionally, the third transistor is a PNP (positive-negative-positive) transistor.

[0030] Optionally, both the first transistor and the second transistor are PNP transistors.

[0031] In a second aspect, the present invention provides an electronic device comprising the aforementioned reference generation circuit.

[0032] The positive and progressive effects of this invention are as follows:

[0033] This invention suppresses overshoot by simultaneously controlling the range of change of the initial startup voltage and the output value, without slowing down the startup speed or increasing additional power consumption. During startup, the overshoot suppression module controls the startup voltage to vary within a limited range, preventing the output circuit from generating large currents and thus suppressing overshoot. At the same time, the output control module provides switching control, ensuring that the reference voltage is only output when it is stable, further preventing overshoot. Attached Figure Description

[0034] Figure 1 This is a circuit diagram of the reference generation circuit in Embodiment 1 of the present invention.

[0035] Figure 2 This is a circuit diagram of an example of a conventional standalone output using delay control in the reference generation circuit of Embodiment 1 of the present invention.

[0036] Figure 3 This is a circuit structure diagram of an example of a conventional method for separately controlling the initial value of the start-up voltage in the reference generation circuit of Embodiment 1 of the present invention. Detailed Implementation

[0037] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.

[0038] Example 1

[0039] This embodiment provides a reference generation circuit, referring to... Figure 1 The reference generation circuit includes: a main module 101, an output module 102, an overshoot suppression module 103, an output control module 104, and a start module 105.

[0040] The main module 101 is used to generate positive temperature coefficient current and output the positive temperature coefficient current to the output module 102.

[0041] The output module 102 is used to convert positive temperature coefficient current into positive temperature coefficient voltage and generate negative temperature coefficient voltage, and to superimpose the positive temperature coefficient voltage and negative temperature coefficient voltage to generate a reference voltage Vref.

[0042] The overshoot suppression module 103 is used to raise the node voltage X in the main module 101 to prevent the reference voltage Vref generated by the output module 102 from exceeding the first preset range.

[0043] The output control module 104 controls the output module 102 to output when the reference voltage Vref is in a stable state. Here, the reference voltage Vref being in a stable state indicates that the reference voltage Vref is within a second preset range within a preset time period, and the first preset range includes the second preset range.

[0044] The startup module 105 is used to start the main module 101, control the overshoot suppression module 103, and simultaneously control the output control module 104 to enable the output module 102 to output.

[0045] in, Figure 2 (Using delay control output separately) and Figure 3 (Using a separate control method for the initial startup voltage) Two examples of reference generation circuits in the prior art using a separate control method are shown to suppress or mitigate overshoot. However, the effect of a separate control method on overshoot suppression is limited. Relying solely on filtering and delaying to filter overshoot caused by rapid power-up will affect the startup of subsequent circuits, thus slowing down the startup speed of the entire system. Introducing other power-up sequences to control the output will increase the complexity of the system.

[0046] The main module 101 generates a positive temperature coefficient current, which passes through the output module 102 to generate a voltage with a positive temperature coefficient (positive temperature coefficient voltage). In the output module 102, the positive temperature coefficient voltage and the negative temperature coefficient voltage are superimposed to generate and output a reference voltage Vref. The positive and negative voltages cancel each other out, and the reference voltage Vref is independent of temperature.

[0047] The overshoot suppression module 103 raises the input node voltage X so that the node voltage X does not drop to a very low level instantaneously, thereby preventing the output module 102 from generating a large current and suppressing overshoot.

[0048] The start signal simultaneously controls the output control circuit 104, enabling the output module 102 to output when the reference is stable, further avoiding overshoot.

[0049] The overshoot suppression module 103 and the output control module 104 work together to effectively suppress overshoot.

[0050] In this embodiment, overshoot is suppressed by simultaneously controlling the range of change of the initial value of the startup voltage and the output value, without slowing down the startup speed or increasing additional power consumption. During startup, the overshoot suppression module controls the value of the startup voltage to vary within a limited range, avoiding the generation of large current in the output circuit and thus suppressing overshoot; at the same time, the output control module provides switching control, so that the reference voltage is only output when it is stable, further avoiding overshoot.

[0051] In one embodiment, the output terminal of the startup module 105 is electrically connected to the input terminal of the overshoot suppression module 103 and the first input terminal of the output control module 104, respectively. The output terminal of the overshoot suppression module 103 is electrically connected to the output terminal of the operational amplifier OP in the main module 101, the second input terminal of the output control module 104, and the first input terminal of the output module 102, respectively. The output terminal of the output control module 104 is electrically connected to the second input terminal of the output module 102, and the output terminal of the output module 102 outputs the reference voltage Vref.

[0052] The startup module 105 outputs a su signal to the overshoot suppression module 103 and the output control module 104 through its output terminal.

[0053] In one embodiment, the main module 101 further includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a first resistor R1, a first transistor Q1, and a second transistor Q2.

[0054] The gates of the first PMOS transistor PM1, the second PMOS transistor PM2, and the output of the operational amplifier OP are connected together as the port of the main module 101 to transmit node voltage.

[0055] The gate of the first PMOS transistor PM1 is also electrically connected to the gate of the second PMOS transistor PM2 and the output terminal of the operational amplifier OP. The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are both electrically connected to the power supply voltage. The drain of the first PMOS transistor PM1 is electrically connected to the emitter of the first transistor Q1 and the inverting input terminal of the operational amplifier OP. The drain of the second PMOS transistor PM2 is electrically connected to the first terminal of the first resistor R1 and the non-inverting input terminal of the operational amplifier OP. The second terminal of the first resistor R1 is electrically connected to the emitter of the second transistor Q2. The collector and base of the first transistor Q1 and the collector and base of the second transistor Q2 are both grounded.

[0056] The operational amplifier OP is used to provide the suppressed node voltage X for startup.

[0057] The area of ​​the second transistor Q2 is N times the area of ​​the first transistor Q1 (N is greater than 1), and the width-to-length ratio of the first PMOS transistor PM1 is the same as that of the second PMOS transistor PM2. In this embodiment, a current with a positive temperature coefficient is generated by the area ratio N of the second transistor Q2 and the first transistor Q1 and the first resistor R1.

[0058] In one embodiment, the output module 102 includes: a third PMOS transistor PM3, a sixth PMOS transistor PM6, a third transistor Q3, and a second resistor R2.

[0059] The gate of the third PMOS transistor PM3 is electrically connected as the first input terminal of the output module 102, the gate of the sixth PMOS transistor PM6 is used as the second input terminal of the output module 102, and the drain of the sixth PMOS transistor PM6 is used as the output terminal of the output module 102.

[0060] The source of the third PMOS transistor PM3 is connected to the power supply voltage. The drain of the third PMOS transistor PM3 is electrically connected to the source of the sixth PMOS transistor PM6. The drain of the sixth PMOS transistor PM6 is also electrically connected to the first end of the second resistor R2. The second end of the second resistor R2 is electrically connected to the emitter of the third transistor Q3.

[0061] The base and collector of the third transistor Q3 are both grounded.

[0062] The current with a positive temperature coefficient generated by the main module 101 is mirrored by the third PMOS transistor PM3, and then converted into a voltage with a positive temperature coefficient by the second resistor R2. This voltage is then superimposed with the voltage with a negative temperature coefficient generated by the third transistor Q3 to generate and output a reference voltage Vref that is independent of temperature coefficient. The sixth PMOS transistor PM6 acts as the output switch, controlling the output of the reference voltage Vref only after overshoot has been mitigated.

[0063] Positive temperature coefficient current = ΔVbe / R1, (ΔVbe is generated by Q1 and Q2).

[0064] Positive temperature coefficient voltage = Positive temperature coefficient current * resistance = ΔVbe / R1 * R2

[0065] Negative temperature coefficient voltage = Vbe3 (Vbe3 is generated by Q3).

[0066] vref = positive temperature coefficient voltage + negative temperature coefficient voltage = △Vbe / R1*R2+Vbe3 (the voltage values ​​are added together, and the influence of the temperature coefficient is canceled out).

[0067] In one embodiment, the overshoot suppression module 103 includes a first NMOS transistor NM1 and a third resistor R3.

[0068] The gate of the first NMOS transistor NM1 is used as the input terminal of the overshoot suppression module 103, and the drain of the first NMOS transistor NM1 is used as the output terminal of the overshoot suppression module 103.

[0069] The source of the first NMOS transistor NM1 is electrically connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is grounded.

[0070] When the startup signal su of the startup module 105 turns on the first NMOS transistor NM1, the generated current acts on the third resistor R3, reducing the range of the node voltage X drop, thereby reducing the gate-source voltage of the first PMOS transistor PM1 and the second PMOS transistor PM2 in the main module 101, and suppressing the magnitude of the generated current with a positive temperature coefficient.

[0071] In one embodiment, the output control module 104 includes: a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a second NMOS transistor NM2, a third NMOS transistor NM3, and a first capacitor C1.

[0072] The gate of the second NMOS transistor NM2 is used as the first input terminal of the output control module 104, the gate of the fourth PMOS transistor PM4 is used as the second input terminal of the output control module 104, and the drain of the fifth PMOS transistor PM5 is used as the output terminal of the output control module 104.

[0073] The drain of the second NMOS transistor NM2 is electrically connected to the drain of the fourth PMOS transistor PM4, the gate of the fifth PMOS transistor PM5, the gate of the third NMOS transistor NM3, and the first terminal of the first capacitor C1.

[0074] The source of the fourth PMOS transistor PM4 and the source of the fifth PMOS transistor PM5 are both electrically connected to the power supply voltage, and the drain of the fifth PMOS transistor PM5 is electrically connected to the drain of the third NMOS transistor NM3.

[0075] The source of the second NMOS transistor NM2, the source of the third NMOS transistor NM3, and the second terminal of the first capacitor C1 are all grounded.

[0076] When the startup signal su of the startup module 105 turns on the second NMOS transistor and turns off NM2, the current flowing through the fourth PMOS transistor PM4, which has a positive temperature coefficient, is relatively large. Utilizing the principle that the voltage across a capacitor does not change abruptly, the voltage across the first capacitor C1 is low. This voltage, through the inverter formed by the fifth PMOS transistor PM5 and the third NMOS transistor NM3, turns off the sixth PMOS transistor PM6, preventing the output module 102 from outputting when the current is high. When the current flowing through the fourth PMOS transistor PM4 charges the first capacitor C1, causing the inverter formed by the fifth PMOS transistor PM5 and the third NMOS transistor NM3 to flip, the sixth PMOS transistor PM6 is turned on for output. At this point, the overshoot phenomenon of the current with a positive temperature coefficient is suppressed again.

[0077] In one embodiment, the emitter of the third transistor Q3 outputs a negative temperature coefficient voltage.

[0078] In one embodiment, the third transistor Q3 is a PNP transistor.

[0079] In one embodiment, both the first transistor Q1 and the second transistor Q2 are PNP transistors.

[0080] Example 2

[0081] This embodiment provides an electronic device, which includes the reference generation circuit in Embodiment 1.

[0082] In this embodiment, overshoot is suppressed by simultaneously controlling the range of change of the initial value of the startup voltage and the output value, without slowing down the startup speed or increasing additional power consumption. During startup, the overshoot suppression module controls the value of the startup voltage to vary within a limited range, avoiding the generation of large current in the output circuit and thus suppressing overshoot; at the same time, the output control module provides switching control, so that the reference voltage is only output when it is stable, further avoiding overshoot.

[0083] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.

Claims

1. A reference generation circuit, characterized in that, The reference generation circuit includes: a main module (101), an output module (102), an overshoot suppression module (103), an output control module (104), and a startup module (105). The main module (101) is used to generate a positive temperature coefficient current and output the positive temperature coefficient current to the output module (102). The output module (102) is used to convert the positive temperature coefficient current into a positive temperature coefficient voltage and generate a negative temperature coefficient voltage, and to superimpose the positive temperature coefficient voltage and the negative temperature coefficient voltage to generate a reference voltage; The overshoot suppression module (103) is used to raise the node voltage in the main module (101) to prevent the reference voltage generated by the output module (102) from exceeding the first preset range; The output control module (104) is used to control the output module (102) to output when the reference voltage is in a stable state; wherein, the reference voltage being in a stable state indicates that the reference voltage is within a second preset range within a preset time period, and the first preset range includes the second preset range; The startup module (105) is used to start the main module (101), control the overshoot suppression module (103), and simultaneously control the output control module (104) to make the output module (102) output; The output terminal of the startup module (105) is electrically connected to the input terminal of the overshoot suppression module (103) and the first input terminal of the output control module (104), respectively. The output terminal of the overshoot suppression module (103) is electrically connected to the output terminal of the operational amplifier (OP) in the main module (101), the second input terminal of the output control module (104), and the first input terminal of the output module (102), respectively. The output terminal of the output control module (104) is electrically connected to the second input terminal of the output module (102), and the output terminal of the output module (102) outputs the reference voltage. The output control module (104) includes: a fourth PMOS transistor (PM4), a fifth PMOS transistor (PM5), a second NMOS transistor (NM2), a third NMOS transistor (NM3), and a first capacitor (C1); The gate of the second NMOS transistor (NM2) is used as the first input terminal of the output control module (104), the gate of the fourth PMOS transistor (PM4) is used as the second input terminal of the output control module (104), and the drain of the fifth PMOS transistor (PM5) is used as the output terminal of the output control module (104). The drain of the second NMOS transistor (NM2) is electrically connected to the drain of the fourth PMOS transistor (PM4), the gate of the fifth PMOS transistor (PM5), the gate of the third NMOS transistor (NM3), and the first terminal of the first capacitor (C1), respectively. The source of the fourth PMOS transistor (PM4) and the source of the fifth PMOS transistor (PM5) are both electrically connected to the power supply voltage, and the drain of the fifth PMOS transistor (PM5) is electrically connected to the drain of the third NMOS transistor (NM3). The source of the second NMOS transistor (NM2), the source of the third NMOS transistor (NM3), and the second terminal of the first capacitor (C1) are all grounded.

2. The reference generation circuit as described in claim 1, characterized in that, The main module (101) also includes: a first PMOS transistor (PM1), a second PMOS transistor (PM2), a first resistor (R1), a first transistor (Q1), and a second transistor (Q2); The gate of the first PMOS transistor (PM1), the gate of the second PMOS transistor (PM2), and the output of the operational amplifier (OP) are connected together as the port of the main module (101) to transmit the node voltage; The gate of the first PMOS transistor (PM1) is also electrically connected to the gate of the second PMOS transistor (PM2) and the output terminal of the operational amplifier (OP). The source of the first PMOS transistor (PM1) and the source of the second PMOS transistor (PM2) are both electrically connected to the power supply voltage. The drain of the first PMOS transistor (PM1) is electrically connected to the emitter of the first transistor (Q1) and the inverting input terminal of the operational amplifier (OP). The drain of the second PMOS transistor (PM2) is electrically connected to the first terminal of the first resistor (R1) and the non-inverting input terminal of the operational amplifier (OP). The second terminal of the first resistor (R1) is electrically connected to the emitter of the second transistor (Q2). The collector and base of the first transistor (Q1) and the collector and base of the second transistor (Q2) are both grounded.

3. The reference generation circuit as described in claim 1, characterized in that, The output module (102) includes: a third PMOS transistor (PM3), a sixth PMOS transistor (PM6), a third transistor (Q3), and a second resistor (R2); The gate of the third PMOS transistor (PM3) is electrically connected as the first input terminal of the output module (102), the gate of the sixth PMOS transistor (PM6) is used as the second input terminal of the output module (102), and the drain of the sixth PMOS transistor (PM6) is used as the output terminal of the output module (102). The source of the third PMOS transistor (PM3) is connected to the power supply voltage, the drain of the third PMOS transistor (PM3) is electrically connected to the source of the sixth PMOS transistor (PM6), the drain of the sixth PMOS transistor (PM6) is also electrically connected to the first end of the second resistor (R2), and the second end of the second resistor (R2) is electrically connected to the emitter of the third transistor (Q3). The base and collector of the third transistor (Q3) are both grounded.

4. The reference generation circuit as described in claim 1, characterized in that, The overshoot suppression module (103) includes: a first NMOS transistor (NM1) and a third resistor (R3); The gate of the first NMOS transistor (NM1) is used as the input terminal of the overshoot suppression module (103), and the drain of the first NMOS transistor (NM1) is used as the output terminal of the overshoot suppression module (103). The source of the first NMOS transistor (NM1) is electrically connected to the first terminal of the third resistor (R3), and the second terminal of the third resistor (R3) is grounded.

5. The reference generation circuit as described in claim 3, characterized in that, The emitter of the third transistor (Q3) outputs the negative temperature coefficient voltage.

6. The reference generation circuit as described in claim 3, characterized in that, The third transistor (Q3) is a PNP transistor.

7. The reference generation circuit as described in claim 2, characterized in that, Both the first transistor (Q1) and the second transistor (Q2) are PNP transistors.

8. An electronic device, characterized in that, The electronic device includes a reference generation circuit as described in any one of claims 1-7.

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