Mirror start method, control device, embedded system, storage medium

Abstract

The application discloses a mirror image starting method, a control device, an embedded system and a storage medium. The method comprises the following steps: when starting Bootrom, reading Header information which is checked by crc in an APP image from an spi flash chip; when a pll high-speed clock enabling identifier indicates enabling the pll, configuring a current system clock according to system high-speed clock configuration information; when a spi quad transmission mode enabling identifier indicates enabling the spi quad transmission mode, configuring an spi interface according to four-wire transmission mode configuration information; when a dma transmission mode enabling identifier indicates enabling the dma transmission mode, configuring the spi interface according to dma transmission configuration information; the Bootrom migrates the APP image from the spi flash chip to a RAM memory through the spi interface; when the migrated APP image is checked by crc, the PC pointer of a control processor is jumped to the first address of the migrated APP image. The Header information of the APP image is configured to support the acceleration starting configuration item of the embedded system, and the starting speed of the embedded system is improved.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of embedded system boot technology, and particularly to an image boot method, control device, embedded system, and storage medium. Background Technology

[0002] Bootrom is a small mask ROM or write-protected flash memory embedded within the processor chip. It ensures the MCU can boot correctly and provides a stable boot environment. The typical boot process for a Bootrom-based embedded system is as follows: system power-on, interrupts disabled, and instruction and data caches disabled. Then, the Bootrom uses the standard SPI interface to load the application program from the SPI flash chip into the MCU's internal RAM. CRC checks are performed on the application program in RAM. If the CRC check passes, the program counter (PC) jumps to the application's starting address, completing the system boot process. However, due to the limitations of low clock speeds, slow SPI speeds, and slow CRC checks in MCU embedded systems, system boot times often reach one second or even longer. In scenarios with strict boot time requirements, such as electric vehicles equipped with door anti-collision systems, the time from power-on to completion of all functional initialization needs to be less than 200ms. If this time exceeds this, the vehicle's infotainment system may not have enough time to alert passengers when the door opens, potentially causing the door to collide with a person or obstacle, leading to a serious safety accident. In conclusion, the boot time of existing embedded systems cannot meet customer requirements. Summary of the Invention

[0003] This application provides an image boot method, control device, embedded system, and storage medium, which can effectively improve the boot speed of embedded systems.

[0004] In a first aspect, embodiments of this application provide an image boot method applied to an embedded system. The embedded system includes a Bootrom, an SPI flash chip, and a control processor. The control processor has a built-in RAM memory. The Bootrom is communicatively connected to the SPI flash chip via an SPI interface. The control processor is communicatively connected to both the Bootrom and the SPI flash chip. The SPI flash chip stores an APP image, which includes Header information. The Header information is used to indicate the configuration attribute information of the APP image. The method includes:

[0005] When the control processor is powered on and reset, the Bootrom is started.

[0006] Initialize the SPI interface, and read the Header information of the APP image from the SPI flash chip through the SPI interface. The Header information includes the PLL high-speed clock enable flag, the SPI quad transmission mode enable flag, and the DMA transmission mode enable flag.

[0007] The header information is CRC checked. When the header information passes the CRC check, the embedded system is reinitialized using the header information.

[0008] Determine the first enable state of the PLL high-speed clock enable flag. When the first enable state indicates that the PLL is enabled, obtain the system high-speed clock configuration information from the PLL high-speed clock enable flag, and configure the current system clock according to the system high-speed clock configuration information.

[0009] Determine the second enable state of the SPI quad transmission mode enable identifier. When the second enable state indicates that the SPI quad transmission mode is enabled, obtain the four-wire transmission mode configuration information from the SPI quad transmission mode enable identifier, and configure the SPI interface according to the four-wire transmission mode configuration information.

[0010] The third enable state of the DMA transmission mode enable identifier is determined. When the third enable state indicates that the DMA transmission mode is enabled, DMA transmission configuration information is obtained from the DMA transmission mode enable identifier, and the control processor is configured according to the DMA transmission configuration information.

[0011] The Bootrom uses the configured SPI interface to migrate the APP image from the SPI flash chip to the RAM memory;

[0012] The migrated APP image in the RAM memory is subjected to CRC verification. When the migrated APP image passes the CRC verification, the PC pointer of the control processor is jumped to the starting address of the migrated APP image.

[0013] In some embodiments, the Header information further includes app CRC verification information, the control processor includes a hardware CRC module, and the CRC verification of the migrated app image in the RAM memory includes:

[0014] Enable the hardware CRC module;

[0015] The hardware CRC module performs CRC verification on the migrated APP image in the RAM memory based on the APP CRC verification information.

[0016] In some embodiments, the DMA transport configuration information includes a DMA transport source address and a DMA transport destination address, and the control processor further includes a DMA controller. The step of configuring the SPI interface according to the DMA transport configuration information includes:

[0017] Configure the DMA transmission source address as the SPI receive data register, and configure the DMA transmission destination address as the address of the RAM memory;

[0018] Configure the DMA controller according to the DMA transmission source address and DMA transmission destination address after configuration.

[0019] In some embodiments, the Header information further includes SPI rate configuration information, and the method further includes:

[0020] Upon receiving SPI rate update information, new SPI rate configuration information is determined based on the circuit trace attribute information and the SPI rate update information.

[0021] Configure the SPI protocol clock of the SPI interface according to the new SPI rate configuration information.

[0022] In some embodiments, before reading the Header information of the APP image from the SPI flash chip via the SPI interface, the method further includes:

[0023] Obtain the first clock parameter, which indicates the low-speed clock parameter;

[0024] Configure the SPI protocol clock of the SPI interface according to the first clock parameter.

[0025] In some embodiments, after enabling the pll, the method further includes:

[0026] Obtain a second clock parameter, wherein the rate corresponding to the second clock parameter is higher than the rate corresponding to the first clock parameter;

[0027] Configure the SPI protocol clock of the SPI interface according to the second clock parameter.

[0028] In a second aspect, embodiments of this application provide a control device, including at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, which, when executed by the at least one control processor, enable the at least one control processor to perform the image boot method as described in the first aspect.

[0029] Thirdly, embodiments of this application provide an embedded system including the control device described in the second aspect of the above-described embodiment.

[0030] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions for performing the image booting method as described in the first aspect.

[0031] This application provides an image boot method, control device, embedded system, and storage medium. The method includes: when the control processor is powered on and reset, booting the Bootrom; initializing the SPI interface, reading the Header information of the APP image from the Spiiflash chip, wherein the Header information includes a PLL high-speed clock enable flag, an SPI quad transmission mode enable flag, and a DMA transmission mode enable flag; performing CRC verification on the Header information, and when the Header information passes the CRC verification, reinitializing the embedded system using the Header information; determining a first enable state of the PLL high-speed clock enable flag, and when the first enable state indicates that the PLL is enabled, obtaining system high-speed clock configuration information from the PLL high-speed clock enable flag, and configuring the current system clock according to the system high-speed clock configuration information; determining a second enable state of the SPI quad transmission mode enable flag, and when the second enable state indicates that the SPI quad transmission mode is enabled, obtaining system high-speed clock configuration information from the SPI interface; and determining a second enable state of the SPI quad transmission mode enable flag, and when the second enable state indicates that the SPI quad transmission mode is enabled, obtaining system high-speed clock configuration information from the SPI interface. The system retrieves four-wire transmission mode configuration information from the quad transmission mode enable flag and configures the SPI interface according to the four-wire transmission mode configuration information; it determines the third enable state of the DMA transmission mode enable flag, and when the third enable state indicates that the DMA transmission mode is enabled, it retrieves DMA transmission configuration information from the DMA transmission mode enable flag and configures the control processor according to the DMA transmission configuration information; the Bootrom uses the configured SPI interface to migrate the APP image from the SPI flash chip to the RAM memory; it performs CRC verification on the migrated APP image in the RAM memory, and when the migrated APP image passes the CRC verification, it jumps the PC pointer of the control processor to the migrated APP image. According to the solution provided in the embodiments of this application, by pre-setting the header information in the APP image and configuring accelerated boot configuration items such as PLL high-speed clock, SPI quad transmission mode or DMA transmission mode supported by the embedded system, the boot speed of the embedded system is effectively improved, and the user experience is enhanced. Attached Figure Description

[0032] Figure 1This is a flowchart of the steps of an image booting method provided in one embodiment of this application;

[0033] Figure 2 This is a flowchart of the steps for performing CRC verification on a migrated APP image, provided in another embodiment of this application;

[0034] Figure 3 This is a flowchart of the steps for configuring a DMA controller based on DMA transmission configuration information, provided in another embodiment of this application.

[0035] Figure 4 This is a flowchart of the steps for configuring the SPI protocol clock of the SPI interface according to another embodiment of this application;

[0036] Figure 5 This is a flowchart of the steps for configuring the SPI protocol clock of the SPI interface according to another embodiment of this application;

[0037] Figure 6 This is a flowchart of the steps for configuring the SPI protocol clock of the SPI interface according to another embodiment of this application;

[0038] Figure 7 This is a schematic diagram of APP data migration provided in another embodiment of this application;

[0039] Figure 8 This is a structural diagram of a control device provided in another embodiment of this application. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0041] It is understandable that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0042] Bootrom is a small mask ROM or write-protected flash memory embedded within the processor chip. It ensures the MCU can boot correctly and provides a stable boot environment. The typical boot process for a Bootrom-based embedded system is as follows: system power-on, interrupts disabled, and instruction and data caches disabled. Then, the Bootrom uses the standard SPI interface to load the application program from the SPI flash chip into the MCU's internal RAM. CRC checks are performed on the application program in RAM. If the CRC check passes, the program counter (PC) jumps to the application's starting address, completing the system boot process. However, due to the limitations of low clock speeds, slow SPI speeds, and slow CRC checks in MCU embedded systems, system boot times often reach one second or even longer. In scenarios with strict boot time requirements, such as electric vehicles equipped with door anti-collision systems, the time from power-on to completion of all functional initialization needs to be less than 200ms. If this time exceeds this, the vehicle's infotainment system may not have enough time to alert passengers when the door opens, potentially causing the door to collide with a person or obstacle, leading to a serious safety accident. In conclusion, the boot time of existing embedded systems cannot meet customer requirements.

[0043] To address the aforementioned problems, this application provides an image boot method, control device, embedded system, and storage medium. The method includes: when the control processor is powered on and reset, booting the Bootrom; initializing the SPI interface, reading the Header information of the APP image from the SPI flash chip, wherein the Header information includes a PLL high-speed clock enable flag, an SPI quad transmission mode enable flag, and a DMA transmission mode enable flag; performing CRC verification on the Header information, and when the Header information passes the CRC verification, reinitializing the embedded system using the Header information; determining a first enable state of the PLL high-speed clock enable flag, and when the first enable state indicates that the PLL is enabled, obtaining system high-speed clock configuration information from the PLL high-speed clock enable flag, and configuring the current system clock according to the system high-speed clock configuration information; determining a second enable state of the SPI quad transmission mode enable flag, and when the second enable state indicates that the SPI quad transmission mode is enabled, obtaining system high-speed clock configuration information from the SPI interface; and determining a second enable state of the SPI quad transmission mode enable flag, and when the second enable state indicates that the SPI quad transmission mode is enabled, obtaining system high-speed clock configuration information from the SPI interface. The system obtains four-wire transmission mode configuration information from the quad transmission mode enable flag and configures the SPI interface according to the four-wire transmission mode configuration information; determines the third enable state of the DMA transmission mode enable flag; when the third enable state indicates that the DMA transmission mode is enabled, obtains DMA transmission configuration information from the DMA transmission mode enable flag and configures the SPI interface according to the DMA transmission configuration information; the Bootrom uses the configured SPI interface to migrate the APP image from the Spiiflash chip to the RAM memory; performs CRC verification on the migrated APP image in the RAM memory; when the migrated APP image passes the CRC verification, the PC pointer of the control processor jumps to the migrated APP image. According to the solution provided in the embodiments of this application, by configuring accelerated boot configuration items such as PLL high-speed clock, SPI quad transmission mode or DMA transmission mode supported by the embedded system in the header information of the APP image, the boot speed of the embedded system is effectively improved and the user experience is enhanced.

[0044] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0045] refer to Figure 1 , Figure 1Yes, this application provides an image boot method applied to an embedded system. The embedded system includes a Bootrom, an SPI flash chip, and a control processor. The control processor has a built-in RAM memory. The Bootrom communicates with the SPI flash chip via an SPI interface. The control processor communicates with both the Bootrom and the SPI flash chip. The SPI flash chip stores an APP image, which includes Header information indicating the configuration attribute information of the APP image. The method includes, but is not limited to, the following steps:

[0046] Step S110: When the control processor is powered on and reset, the Bootrom is started;

[0047] Step S120: Initialize the SPI interface and read the Header information of the APP image from the SPI flash chip through the SPI interface. The Header information includes the PLL high-speed clock enable flag, the SPI quad transmission mode enable flag, and the DMA transmission mode enable flag.

[0048] Step S130: Perform CRC verification on the Header information. When the Header information passes the CRC verification, reinitialize the embedded system using the Header information.

[0049] Step S140: Determine the first enable state of the PLL high-speed clock enable flag. When the first enable state indicates that the PLL is enabled, obtain the system high-speed clock configuration information from the PLL high-speed clock enable flag and configure the current system clock according to the system high-speed clock configuration information.

[0050] Step S150: Determine the second enable state of the SPI quad transmission mode enable flag. When the second enable state indicates that the SPI quad transmission mode is enabled, obtain the four-wire transmission mode configuration information from the SPI quad transmission mode enable flag and configure the SPI interface according to the four-wire transmission mode configuration information.

[0051] Step S160: Determine the third enable state of the DMA transmission mode enable identifier. When the third enable state indicates that the DMA transmission mode is enabled, obtain the DMA transmission configuration information from the DMA transmission mode enable identifier and configure the control processor according to the DMA transmission configuration information.

[0052] In step S170, the Bootrom uses the configured SPI interface to migrate the APP image from the SPI flash chip to the RAM memory.

[0053] Step S180: Perform CRC verification on the migrated APP image in RAM memory. When the migrated APP image passes the CRC verification, jump the PC pointer of the control processor to the migrated APP image.

[0054] It should be noted that this embodiment does not limit the method of obtaining the Header information in the APP image. It can be that during the process of compiling the binary program corresponding to the APP image using a script tool, an additional Header information is configured. This Header information includes configuration information such as PLL high-speed clock enable flag, SPI quad transmission mode enable flag, and DMA transmission mode enable flag, thereby compiling an APP image carrying Header information. When updating the APP image, the APP image carrying Header information is burned to the SPI flash 0 address using a burning tool.

[0055] It is understandable that, since the Bootrom contains the first piece of code that the control processor executes when it is powered on or reset, when the control processor of the embedded system is powered on and reset, the Bootrom and its contained code are started. At this time, the embedded system is powered on and the system clock comes from an external crystal oscillator clock. The embodiments of this application do not limit the specific parameters of the external crystal oscillator clock, which can be 50M.

[0056] It should be noted that the embodiments of this application do not limit the corresponding system clock configuration after enabling the PLL. In this embodiment, the system clock is configured to 400M by configuring the relevant registers of the PLL to enable the high-speed system clock.

[0057] Understandably, after booting the Bootrom, the SPI interface is initialized, and the header information of the APP image is read from the SPI flash chip. This header information indicates the configuration attributes of the APP image and can be used to configure the accelerated boot configuration items supported by the embedded system, making it crucial for improving the boot speed of the embedded system. Referring to the description of the above embodiment, since the header information in this embodiment is obtained by updating the APP image, CRC verification of the header information can determine whether data loss occurred during application configuration, ensuring the accuracy of the header information in system configuration. When the header information passes CRC verification, the embedded system is reinitialized using the header information. Next, it is sequentially determined whether the embedded system supports each accelerated boot configuration item in the header information. These accelerated boot configuration items include, but are not limited to, PLL high-speed clock enable flags, SPI quad transmission mode enable flags, and DMA transmission mode enable flags. The first enable state of the PLL high-speed clock enable flag is determined. If the first enable state indicates that the PLL is enabled, it means that the current embedded system supports the PLL high-speed clock. The system high-speed clock configuration information is obtained from the PLL high-speed clock enable flag, and the current system clock is configured according to the system high-speed clock configuration information, thereby accelerating code execution speed and effectively speeding up the startup of the embedded system. If the first enable state indicates that the PLL is not enabled, it means that the current embedded system does not support the PLL high-speed clock. The original system clock is maintained, and the second enable state is determined. Next, the second enable state of the SPI quad transmission mode enable flag is determined. If the second enable state indicates that the SPI quad transmission mode is enabled, it means that the current control processor supports the SPI quad four-wire transmission mode. The four-wire transmission mode configuration information is obtained from the SPI quad transmission mode enable flag, and the SPI interface is configured according to the four-wire transmission mode configuration information, which can effectively improve the data transmission rate of the SPI interface. If the second enable state indicates that the SPI is not enabled... The quad transmission mode indicates that the current embedded system does not support four-wire transmission. The original transmission mode is maintained, and the third enable state is checked. Next, the third enable state of the DMA transmission mode enable flag is determined. If the third enable state indicates that the DMA transmission mode is enabled, it means that the current embedded system supports the DMA transmission protocol. In this case, DMA transmission configuration information is obtained from the DMA transmission mode enable flag, and the control processor is configured according to the DMA transmission configuration information, thereby further improving the system boot speed. If the third enable state indicates that the DMA transmission mode is not enabled, it means that the current embedded system does not support the DMA transmission mode, and the original CPU transmission mode is maintained. After sequentially checking and configuring the configuration items indicated by the Header information, the Bootrom uses the configured SPI interface, such as... Figure 7 As shown, the APP image is migrated from the SPI flash chip to the RAM memory, and the migrated APP image in the RAM memory is verified by CRC. When the migrated APP image passes the CRC verification, the PC pointer of the control processor is jumped to the migrated APP image to complete the system boot and start the embedded system.

[0058] In summary, in application scenarios with relatively low MCU clock speeds, by pre-setting the header information in the APP image and configuring accelerated startup options such as PLL high-speed clock, SPI quad transmission mode, or DMA transmission mode supported by the embedded system, the startup speed of the embedded system can be effectively improved, thus enhancing the user experience.

[0059] Additionally, in some embodiments, the Header information also includes app CRC verification information, and the control processor includes a hardware CRC module, see reference. Figure 2 , Figure 1 Step S180 includes, but is not limited to, the following steps:

[0060] Step S210: Enable the hardware CRC module;

[0061] In step S220, the hardware CRC module performs CRC verification on the migrated APP image in the RAM memory based on the APP CRC verification information.

[0062] It should be noted that this embodiment does not limit the CRC verification method for the migrated APP image. It can utilize a hardware CRC module installed on the control processor to perform CRC verification on the migrated APP image based on the app CRC verification information in the header information. This effectively ensures the data integrity and reliability of the migrated APP image, avoids data corruption caused by environmental interference, and, by using the built-in hardware CRC module supported by the control processor, can significantly improve system startup time. This embodiment can also implement CRC verification for the migrated APP image by calling a software CRC verification algorithm.

[0063] Additionally, in some embodiments, the DMA transmission configuration information includes a DMA transmission source address and a DMA transmission destination address, and the control processor further includes a DMA controller, see reference. Figure 3 , Figure 1 Step S160 includes, but is not limited to, the following steps:

[0064] Step S310: Configure the DMA transmission source address as the SPI receive data register and configure the DMA transmission destination address as the address of the RAM memory;

[0065] Step S320: Configure the DMA controller according to the configured DMA transmission source address and DMA transmission destination address.

[0066] It is understood that the DMA transfer configuration information, including the DMA transfer source address and the DMA transfer destination address, is a data structure used to manage DMA operations and indicates the data transfer path. In this embodiment, the DMA transfer source address is configured as the SPI receive data register, and the DMA transfer destination address is configured as the address of the RAM memory. The DMA controller is configured according to the configured DMA transfer source address and DMA transfer destination address. When the amount of data in the migrated APP image is large, high-speed transmission can be guaranteed, thereby effectively improving the startup speed of the embedded system.

[0067] Additionally, in some embodiments, the Header information also includes SPI rate configuration information, see reference. Figure 4 The image boot method provided in this application includes, but is not limited to, the following steps:

[0068] Step S410: When SPI rate update information is received, new SPI rate configuration information is determined based on circuit trace attribute information and SPI rate update information.

[0069] Step S420: Configure the SPI protocol clock of the SPI interface according to the new SPI rate configuration information.

[0070] Understandably, after adding header information to the APP image, the SPI rate can be adjusted according to the needs of the embedded system in the actual application. This is because some circuit designs are unreasonable, causing the rate to fail to reach the SPI's maximum transmission rate. A flexible design ensures that the Bootrom can boot the system normally. In this embodiment, upon receiving SPI rate update information, new SPI rate configuration information is determined based on the circuit trace attributes and the SPI rate update information. The SPI protocol clock of the SPI interface is then configured according to the new SPI rate configuration information, thereby allowing the SPI protocol clock to be adjusted according to actual needs, ensuring that the Bootrom can boot the system normally.

[0071] Additionally, refer to Figure 5 In some embodiments, during execution Figure 1 Before step S120 shown, the image boot method provided in this application embodiment includes, but is not limited to, the following steps:

[0072] Step S510: Obtain the first clock parameter, which indicates the low-speed clock parameter;

[0073] Step S520: Configure the SPI protocol clock of the SPI interface according to the first clock parameter.

[0074] Additionally, refer to Figure 6 In some embodiments, during execution Figure 1 After step S140 is shown and the first enable state indicator is enabled (pll), the image boot method provided in this application embodiment includes, but is not limited to, the following steps:

[0075] Step S610: Obtain the second clock parameter, wherein the rate corresponding to the second clock parameter is higher than the rate corresponding to the first clock parameter;

[0076] Step S620: Configure the SPI protocol clock of the SPI interface according to the second clock parameter.

[0077] It is understandable that before reading the APP image header information from the SPI flash chip via the SPI interface, to ensure the stable operation of the Bootrom, the SPI protocol clock of the SPI interface is configured using a first clock parameter with a low-speed clock to enable SPI to run at a low speed. This embodiment does not limit the rate of the SPI protocol clock configured based on the first clock parameter; it can be 1 MHz. After enabling the PLL and realizing the high-speed system clock, this embodiment configures the SPI protocol clock of the SPI interface according to a second clock parameter. The rate corresponding to the second clock parameter is higher than the rate corresponding to the first clock parameter, thereby achieving the migration of the APP image at a higher SPI rate, effectively improving the startup speed of the embedded system. This embodiment does not limit the rate of the SPI protocol clock configured based on the second clock parameter; it can be 100 MHz, which can be determined by those skilled in the art according to the actual situation.

[0078] like Figure 8 As shown, Figure 8 This is a structural diagram of a control device provided in one embodiment of this application. The present invention also provides a control device 700, comprising:

[0079] The processor 710 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0080] The memory 720 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 720 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 720 and is called and executed by the processor 710 using the image boot method of the embodiments of this application, for example, executing the above-described... Figure 1 Method steps S110 to S180, Figure 2 Method steps S210 to S220, Figure 3 Method steps S310 to S320 Figure 4 Method steps S410 to S420 Figure 5 Method steps S510 to S520 and Figure 6 Method steps S610 to S620;

[0081] The input / output interface 730 is used to implement information input and output;

[0082] The communication interface 740 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0083] Bus 750 transmits information between various components of the device (e.g., processor 710, memory 720, input / output interface 730, and communication interface 740);

[0084] The processor 710, memory 720, input / output interface 730 and communication interface 740 are connected to each other within the device via bus 750.

[0085] In addition, embodiments of this application also provide an embedded system, including as follows: Figure 7 The control device shown.

[0086] This application embodiment also provides a storage medium, which is a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the above-described image boot method, for example, executing the above-described... Figure 1 Method steps S110 to S180, Figure 2 Method steps S210 to S220, Figure 3 Method steps S310 to S320 Figure 4Method steps S410 to S420 Figure 5 Method steps S510 to S520 and Figure 6 Method steps S610 to S620.

[0087] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0089] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A method for booting from an image, characterized in that, This method is applied to an embedded system, which includes a Bootrom, an SPI flash chip, and a control processor. The control processor has built-in RAM. The Bootrom communicates with the SPI flash chip via an SPI interface. The control processor communicates with both the Bootrom and the SPI flash chip. The SPI flash chip stores an application image, which includes header information indicating the configuration attributes of the application image. When the control processor is powered on and reset, the Bootrom is started. Initialize the SPI interface, and read the Header information of the APP image from the SPI flash chip through the SPI interface. The Header information includes the PLL high-speed clock enable flag, the SPI quad transmission mode enable flag, and the DMA transmission mode enable flag. The header information is CRC checked. When the header information passes the CRC check, the embedded system is reinitialized using the header information. Determine the first enable state of the PLL high-speed clock enable flag. When the first enable state indicates that the PLL is enabled, obtain the system high-speed clock configuration information from the PLL high-speed clock enable flag and configure the current system clock according to the system high-speed clock configuration information; or, when the first enable state indicates that the PLL is not enabled, maintain the original system clock and continue to determine the second enable state. Determine the second enable state of the SPI quad transmission mode enable identifier. If the second enable state indicates that the SPI quad transmission mode is enabled, obtain the four-wire transmission mode configuration information from the SPI quad transmission mode enable identifier and configure the SPI interface according to the four-wire transmission mode configuration information; or, if the second enable state indicates that the SPI quad transmission mode is not enabled, maintain the original transmission mode and continue to determine the third enable state. The third enable state of the DMA transmission mode enable identifier is determined. When the third enable state indicates that the DMA transmission mode is enabled, the DMA transmission configuration information is obtained from the DMA transmission mode enable identifier, and the control processor is configured according to the DMA transmission configuration information; or, when the third enable state indicates that the DMA transmission mode is not enabled, the original CPU transmission mode is maintained. The Bootrom uses the configured SPI interface to migrate the APP image from the SPI flash chip to the RAM memory; The migrated APP image in the RAM memory is subjected to CRC verification. When the migrated APP image passes the CRC verification, the PC pointer of the control processor is jumped to the starting address of the migrated APP image.

2. The image boot method according to claim 1, characterized in that, The header information also includes app CRC verification information. The control processor includes a hardware CRC module. The CRC verification of the migrated app image in the RAM memory includes: Enable the hardware CRC module; The hardware CRC module performs CRC verification on the migrated APP image in the RAM memory based on the APP CRC verification information.

3. The image boot method according to claim 1, characterized in that, The DMA transmission configuration information includes a DMA transmission source address and a DMA transmission destination address. The control processor further includes a DMA controller. Configuring the control processor according to the DMA transmission configuration information includes: Configure the DMA transmission source address as the SPI receive data register, and configure the DMA transmission destination address as the address of the RAM memory; Configure the DMA controller according to the DMA transmission source address and DMA transmission destination address after configuration.

4. The image boot method according to claim 1, characterized in that, The header information also includes SPI rate configuration information, and the method further includes: Upon receiving SPI rate update information, new SPI rate configuration information is determined based on the circuit trace attribute information and the SPI rate update information. Configure the SPI protocol clock of the SPI interface according to the new SPI rate configuration information.

5. The image boot method according to claim 1, characterized in that, Before reading the Header information of the APP image from the spiflash chip via the SPI interface, the method further includes: Obtain the first clock parameter, which indicates the low-speed clock parameter; Configure the SPI protocol clock of the SPI interface according to the first clock parameter.

6. The image boot method according to claim 5, characterized in that, After enabling the PLL, the method further includes: Obtain a second clock parameter, wherein the rate corresponding to the second clock parameter is higher than the rate corresponding to the first clock parameter; Configure the SPI protocol clock of the SPI interface according to the second clock parameter.

7. A control device, characterized in that, It includes at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, the instructions being executed by the at least one control processor to enable the at least one control processor to perform the image boot method as described in any one of claims 1 to 6.

8. An embedded system, characterized in that, Includes the control device as described in claim 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the image boot method as described in any one of claims 1 to 6.

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