A communication method, device and equipment of BMC and custom FPGA, and a storage medium

Abstract

The application relates to a BMC and custom FPGA communication method, device, equipment and storage medium. The method comprises the following steps: based on edge computing, an I2C communication protocol between a BMC and a custom FPGA is built; based on the communication protocol, a read-write command is sent to the FPGA through an information acquisition function, original data of all board card information is acquired in one handshake interaction process, and the original data is stored in a buffer area of the BMC; and the original data in the buffer area is parsed and output. The method can realize stable communication between the BMC and the custom FPGA in the field of edge computing, can reduce the burden of the calculation and I / O resources of the custom FPGA, can reduce the amount of data to be transmitted, can improve the data transmission efficiency, and can meet the efficient and stable application requirements of BMC board card management in the field of edge computing.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication method, apparatus, device and storage medium between a BMC and a custom FPGA. Background Technology

[0002] Edge computing refers to providing services at the nearest edge by using an open platform that integrates network, computing, storage, and application capabilities, located close to the source of objects or data. Applications originate at the edge, resulting in faster network service responses and meeting the basic needs of industries in areas such as real-time business, application intelligence, security, and privacy protection. Customization is a key technical characteristic of edge computing; edge servers integrate various custom-designed boards. To manage these boards, the Baseboard Management Controller (BMC) needs to communicate with the FPGA (Field Programmable Gate Array) chips on these boards to obtain various board information. Each time information is obtained, a complete S->P handshake interaction process is required, which is repeated multiple times to obtain various board information. Furthermore, the boards need to complete all command responses, data collection, data processing, and data transmission operations within milliseconds.

[0003] Through actual testing, it was found that due to the limited computing power of the basic FPGA unit and the uneven design level of custom FPGAs in the edge computing field, there is often a certain gap in terms of computing and I / O performance compared with high-performance chips such as GPUs in the general computing field. Therefore, if the communication mode between the BMC and GPU in general computing is copied to communicate between the BMC and the custom FPGA in edge computing, the custom FPGA often has difficulty processing the BMC's read operation requests in a timely manner, causing the FPGA to "freeze" after running for a period of time, resulting in communication interruption and inability to establish efficient and stable data communication with the BMC.

[0004] Therefore, how to achieve efficient and stable communication between BMC and custom FPGA is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] Based on this, it is necessary to address the aforementioned technical issues by providing a communication method, apparatus, device, and storage medium between a BMC and a custom FPGA. By analyzing the incompatibility between the BMC board management protocol in the general computing field and the custom FPGA in the edge computing field, a BMC board management protocol suitable for the edge computing field is designed to achieve stable communication between the BMC and the custom FPGA in the edge computing field, thus meeting the application requirements of efficient and stable BMC board management in the edge computing field.

[0006] On the one hand, a communication method between a BMC and a custom FPGA is provided, the method comprising:

[0007] Establish an I2C communication protocol between BMC and custom FPGA based on edge computing;

[0008] Based on the communication protocol, read and write commands are sent to the FPGA through the information acquisition function. During a handshake interaction, the raw data of all board information is obtained and stored in the buffer of the BMC.

[0009] The original data in the buffer is parsed and output.

[0010] In one embodiment, the information acquisition function includes a data acquisition function and a pointer to the buffer. Before sending read / write commands to the FPGA through the information acquisition function, the following steps are included:

[0011] Check if the pointer is null; if so, return an error message.

[0012] Otherwise, the data acquisition function is called to send read / write commands to the FPGA to obtain the raw data of the board information.

[0013] In one embodiment, the parameters of the data acquisition function include the I2C bus number, slave device address, read / write command, pointer to the buffer, and the total length of all data. Calling the data acquisition function to send read / write commands to the FPGA includes:

[0014] The read / write command is sent to the slave device address according to the I2C bus number through the data acquisition function to obtain the original data of the board information, wherein the slave device address is the FPGA address.

[0015] Check the return value of the data acquisition function. If the return value is negative, the data acquisition failed and an error message is returned.

[0016] Otherwise, if the data acquisition function executes successfully, the return value is the length of the acquired data, which is stored in the buffer.

[0017] In one embodiment, the step of establishing an I2C communication protocol between the BMC and the custom FPGA based on edge computing includes:

[0018] By analyzing the incompatibility between the BMC board management protocol in the general computing field and the custom FPGA in the edge computing field, a communication protocol suitable for the BMC and custom FPGA in the edge computing field is designed, and data exchange between the BMC and the custom FPGA is realized through the communication protocol.

[0019] The communication protocol includes a start signal, an FPGA address, a read / write signal, a register address, and an end signal, wherein the register address includes the starting address of all registers in the custom FPGA that need to acquire data;

[0020] The data exchange between the BMC and the custom FPGA is transmitted in a specific byte format. The data includes a start byte, an address byte, multiple data bytes, a check byte, and an end byte. The address byte is used to indicate the register to be accessed, and the data bytes contain the raw data of the board information to be read or written.

[0021] Based on the communication protocol, a start bit, slave device address, and write flag are sent to the FPGA, and the FPGA generates a first response bit.

[0022] After receiving the first response bit returned by the FPGA, the starting address of all registers is sent to the FPGA, and the FPGA generates the second response bit;

[0023] After receiving the second response bit returned by the FPGA, the start bit, slave address and read flag are sent to the FPGA, and the FPGA generates the third response bit.

[0024] In one embodiment, the raw data for obtaining the board information includes:

[0025] In response to the FPGA sending corresponding register data based on the start address of all received registers, a non-response bit and a stop bit are sent to the FPGA; wherein, the register data includes board temperature, power consumption, voltage, manufacturer ID, device ID, firmware version and serial number, and each type of register data consists of one or more bytes.

[0026] In one embodiment, parsing and outputting the raw data in the buffer includes:

[0027] Define and initialize the buffer;

[0028] Define the offset of various board information in the buffer;

[0029] Based on the number of bytes occupied by the obtained raw data and the big / little endian rule, the raw data in the buffer is parsed and extracted into the corresponding memory variables;

[0030] The data in the memory variables is processed according to usage requirements or application scenarios to obtain the final readable data.

[0031] In one embodiment, parsing the original data in the buffer based on the number of bytes occupied by the obtained original data and the big / little endianness rule includes:

[0032] If the obtained raw data is a single byte, it is directly extracted into a memory variable;

[0033] If the obtained raw data is multi-byte, then the raw data is shifted left, shifted right, or merged according to the big / little endian rule.

[0034] On the other hand, a communication device between a BMC and a custom FPGA is provided, the device comprising:

[0035] The communication protocol building module is used to build an I2C communication protocol between the BMC and the custom FPGA based on edge computing.

[0036] The data acquisition module is used to send read and write commands to the FPGA through the information acquisition function based on the communication protocol, acquire the raw data of all board information in a handshake interaction process, and store it in the buffer of the BMC;

[0037] The data parsing module is used to parse and output the raw data in the buffer.

[0038] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0039] Establish an I2C communication protocol between BMC and custom FPGA based on edge computing;

[0040] Based on the communication protocol, read and write commands are sent to the FPGA through the information acquisition function. During a handshake interaction, the raw data of all board information is obtained and stored in the buffer of the BMC.

[0041] The original data in the buffer is parsed and output.

[0042] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0043] Establish an I2C communication protocol between BMC and custom FPGA based on edge computing;

[0044] Based on the communication protocol, read and write commands are sent to the FPGA through the information acquisition function. During a handshake interaction, the raw data of all board information is obtained and stored in the buffer of the BMC.

[0045] The original data in the buffer is parsed and output.

[0046] This application has the following beneficial effects:

[0047] 1. The I2C communication protocol between the BMC and the custom FPGA proposed in this application achieves stable communication between the BMC and the custom FPGA in the field of edge computing by optimizing the data transmission protocol. This meets the application requirements of efficient and stable BMC board management in the field of edge computing and provides favorable technical support for the company's server products to expand into the edge computing market.

[0048] 2. For BMC, only one handshake interaction process is needed to obtain all the board information of the custom FPGA. There is no need for frequent data interaction between BMC and custom FPGA, which significantly reduces the amount of data to be transmitted, improves the efficiency of data transmission, enables BMC to respond faster, and improves overall performance.

[0049] 3. For custom FPGAs, the workload of the custom FPGA is greatly reduced due to the reduction in data transmission volume, thereby reducing the burden on the computation and I / O resources of the custom FPGA. This allows the hardware to utilize resources more effectively, improves overall performance, and reduces the pressure on the hardware when processing data. This reduces the occurrence of communication failures or "crashes", making data communication more stable and improving reliability.

[0050] 4. By monitoring the status information of FPGA boards in real time through BMC, the data center can obtain more comprehensive equipment performance information. This data can be used to assist decision-making and take corresponding optimization measures to improve productivity and efficiency, such as selecting more suitable hardware equipment and formulating more effective operation strategies.

[0051] 5. This communication protocol can be easily extended to other types of information acquisition, such as more sensor data or status information of other devices, and is not limited to Intel platform servers. It has universal application value in other platform servers and computer platforms, thus having high flexibility and scalability. Attached Figure Description

[0052] Figure 1 This is a waveform diagram illustrating the communication protocol used by BMC in traditional general-purpose computing to obtain information about custom FPGA boards via the I2C bus.

[0053] Figure 2 This is an application environment diagram of a method for obtaining customized FPGA board information in one embodiment.

[0054] Figure 3 This is a flowchart illustrating a method for obtaining information about a custom FPGA board in one embodiment;

[0055] Figure 4 This is a schematic diagram of the communication protocol waveform for BMC to obtain information about a custom FPGA board via the I2C bus, suitable for edge computing applications in one embodiment.

[0056] Figure 5 This is a schematic diagram of the process by which the BMC sends read / write commands to a custom FPGA in one embodiment;

[0057] Figure 6 This is a schematic diagram of the process by which the BMC parses the raw data in one embodiment;

[0058] Figure 7 This is a structural block diagram of a device for acquiring information from a custom FPGA board in one embodiment.

[0059] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0061] As described in the background section, in existing technologies using the general-purpose computing BMC board management protocol, if the BMC wants to obtain a certain type of board information, such as board temperature data, it needs to perform a complete S->P handshake interaction process. The communication protocol used by traditional general-purpose computing BMCs to obtain board information via the I2C (Inter-Integrated Circuit, serial communication protocol) bus is shown in Table 1.

[0062] Table 1. Communication Protocols for BMCs to Obtain Board Information via I2C Bus in Traditional General-Purpose Computing Fields

[0063]

[0064] Specifically, such as Figure 1As shown, the BMC sends the start bit S, the slave device address (FPGA address), and the write flag W. Upon receiving this, the board sends a response bit A to the BMC. The BMC then sends the temperature register address to the board, and the board sends a response bit A again. The BMC sends the start bit S, the slave device address (FPGA address), and the read flag R. Upon receiving this, the board sends a response bit A again. The board then sends the temperature register data (one or more bytes) to the BMC. After completing the transmission, the BMC sends a non-response bit NA and a stop bit P to the board. If other data needs to be obtained, such as power consumption, voltage, VID, DID, FW, SN, etc., the above S->P handshake process must be repeated for each type of data obtained.

[0065] Therefore, when the BMC obtains information about a custom FPGA board, at least 4 x 8 + 9 = 41 bits of data must be transmitted on the I2C bus. If other information needs to be obtained, the S->P handshake interaction process needs to be repeated multiple times. Taking board temperature, power consumption, voltage, vendor ID, device ID, firmware version, and serial number as examples, a total of at least 41 x 7 = 288 bits of data will be processed and transmitted, and the board needs to complete all command response, data collection, data processing, and data transmission operations within a few milliseconds. Actual testing showed that edge custom FPGAs, due to limited computing and I / O resources, often experience "crashes" after running for a period of time, causing communication interruptions.

[0066] To address the aforementioned issues, this invention creatively proposes a communication method between a BMC and a custom FPGA. By analyzing the incompatibility between the BMC board management protocol in the general computing field and the custom FPGA in the edge computing field, a BMC board management protocol suitable for the edge computing field is designed, achieving stable communication between the BMC and the custom FPGA in the edge computing field and meeting the application requirements of efficient and stable BMC board management in the edge computing field.

[0067] The communication method between the BMC and the custom FPGA provided in this application can be applied to, for example... Figure 2In the application environment shown, terminal 102 communicates with server 104 via a network. Terminal 102 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. Server 104 can be a standalone server or a server cluster consisting of multiple servers. Terminal 102 can read and write the communication protocol of server 104. In other application environments, terminal 102 serves as an input device for server 104. Server 104 can be a personal computer or other computer device. The display screen of this computer device can be an LCD screen or an e-ink screen. The input device of this computer device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0068] In one embodiment, such as Figure 3 and Figure 4 As shown, a communication method between a BMC and a custom FPGA is provided, including the following steps:

[0069] Step S1: Establish an I2C communication protocol between the BMC and the custom FPGA based on edge computing.

[0070] It should be noted that BMC is typically used for server management, enabling the monitoring and control of server hardware status. I2C is a serial communication protocol widely used for communication between microcontrollers, sensors, memory, and other embedded devices. It supports multiple devices communicating on the same bus, with devices identified by addresses.

[0071] Specifically, by analyzing the incompatibility between the BMC board management protocol in the general computing field and the custom FPGA in the edge computing field, a BMC board management protocol suitable for the edge computing field is designed, as shown in Table 2.

[0072] Table 2. Communication Protocols Suitable for Edge Computing Applications: BMC Obtains Custom FPGA Board Information via I2C Bus

[0073]

[0074] The register data contains information about different types of boards, such as board temperature, power consumption, voltage, vendor ID (VID), device ID (DID), firmware version (FW), serial number (SN), etc. Therefore, only one S->P handshake interaction process is needed to obtain all the board information, eliminating the need for frequent data interaction between the BMC and the custom FPGA. Furthermore, the entire handshake interaction process handles and transmits a total of 10x8+15=95 bits of data, which is less than 33% of the data volume of the general board management protocol, greatly reducing the workload of the custom FPGA.

[0075] Step S2: Based on the communication protocol, read and write commands are sent to the FPGA through the information acquisition function. The raw data of all board information is obtained during a handshake interaction and stored in the buffer of the BMC.

[0076] It should be noted that the parameters of the information acquisition function include the I2C bus number, slave device address, read / write command, and a pointer to the buffer. Before sending read / write commands to the FPGA through the information acquisition function, it is necessary to first check whether the pointer to the buffer is null. If it is, it means that the BMC has not provided a valid buffer to store data, and the function will return error code -1; otherwise, the data acquisition function is called to send read / write commands to the FPGA and receive the board information returned by the FPGA.

[0077] Specifically, the parameters of the data acquisition function include the I2C bus number, slave device address, read / write command, pointer to the buffer, and the total length of all data. The data acquisition function sends read / write commands to the specified slave device address based on the I2C bus number to obtain the raw data of the board information and stores the function's return value in the variable `ret`. Therefore, it is necessary to check the return value. If the return value is negative, it indicates that data acquisition failed, and error code -1 is returned; otherwise, the function executes successfully, and the return value is the length of the acquired data, stored in the buffer.

[0078] like Figure 5 As shown, the specific steps for sending read / write commands to the FPGA by calling the data acquisition function include:

[0079] In step S21, the BMC sends the start bit S, the slave address, and the write flag W to the FPGA. Upon receiving these, the FPGA sends the response bit A to the BMC. The slave address is the FPGA address, which identifies the FPGA as a slave device on the I2C bus.

[0080] In step S22, the BMC sends the starting address of all registers to the FPGA, and the FPGA sends response bit A to the BMC after receiving it.

[0081] In step S23, the BMC sends the start bit S, the slave address, and the read flag R to the FPGA, indicating that it requests the FPGA to return all the data stored in the register address. After receiving the request, the board sends the response bit A to the BMC.

[0082] In step S24, the FPGA sends the corresponding register data to the BMC based on the starting addresses of all received registers. The register data includes board temperature, power consumption, voltage, vendor ID, device ID, firmware version, and serial number, with each type of register data consisting of one or more bytes.

[0083] Step S25: After the transmission is completed, the BMC sends the non-response bit NA and the stop bit P to the FPGA.

[0084] like Figure 4 As shown, the S->P handshake is a communication protocol between the BMC and the board. The BMC can obtain board information through this process. In this protocol, the BMC acts as the master device, sending a series of commands and requests to the board, while the board, acting as the slave device, responds to these commands and requests. After receiving the slave device address, the starting addresses of all registers, and the read / write commands, the FPGA returns all data in the registers to the BMC via the I2C bus.

[0085] It should be noted that in order to implement the new communication protocol between the BMC and the custom FPGA, the custom FPGA program needs to be able to send the required board information to the BMC during an S->P handshake interaction after receiving the command to acquire data from the BMC.

[0086] Preferably, depending on the actual situation of the computation and I / O resources of different FPGAs, the time interval for BMC to access the FPGA can be appropriately extended. For example, the access interval can be extended from the usual 1ms to 10ms to 200ms.

[0087] Step S3: Parse and output the original data in the buffer.

[0088] It should be noted that, in addition to sending read / write commands to the FPGA and receiving data from the FPGA, the BMC also needs to allocate a buffer in the memory area to store the raw data of the received board information. To enable the BMC to parse the raw data stored in the buffer, the custom FPGA program should organize its own register information and inform the BMC, such as the register's function, offset address, number of bytes, and endianness rules for multi-byte operations, so that the BMC can read and parse the data.

[0089] like Figure 6 As shown, the process of BMC parsing the raw FPGA data includes:

[0090] Step S31: Define and initialize the buffer that stores all the original data.

[0091] Step S32 defines the offsets of various data within the original data buffer. It should be noted that the data names and offsets may differ slightly depending on the custom FPGA. The FPGA data used in this embodiment is shown in Table 3.

[0092] Table 3 shows the offsets of each data point in the original data buffer.

[0093]

[0094]

[0095] Step S33: Based on the number of bytes occupied by the obtained original data and the endianness rule, parse the original data in the buffer and extract it into the corresponding memory variable. Specifically, if the obtained original data is a single byte, it is directly extracted into the memory variable; if the obtained original data is multi-byte, the original data is subjected to corresponding left shift, right shift, or merging operations according to the endianness rule, and then stored in the memory variable after parsing.

[0096] It should be noted that big-endian and little-endian are methods of storing data. Big-endian means that objects are stored in memory in order from the most significant byte to the least significant byte. This storage method is consistent with the computer's internal representation. Therefore, it is more efficient for the CPU to read and write data, and big-endian is usually chosen. Little-endian means that objects are stored in memory in order from the least significant byte to the most significant byte.

[0097] For example, FPGA core temperature, board temperature, and memory temperature data are all single-byte, so they can be directly extracted into the corresponding memory variables based on their starting index in the buffer. Board power consumption data, starting from index 3, consists of 4 bytes and requires bitwise operations to extract. First, the second byte is left-shifted by 16 bits, then ORed with the first byte, and then ORed with the third byte, expanding from 16 bits to 32 bits. Finally, the result is divided by 1000.0 to obtain a floating-point number. Board voltage data requires merging the last two bytes of the index into a 16-bit integer. Manufacturer ID and device ID data require merging the last two bytes of the index into a single value. Firmware version data requires formatting the last two bytes of the index into a three-digit version number string. Serial number data is directly copied into the corresponding string.

[0098] Step S34: Based on the different user needs and application scenarios, process the data in the memory variables accordingly to obtain the final readable data. For example, it can be directly displayed on a web page for the user, or the data can be further processed to meet different user needs and application scenarios.

[0099] This application utilizes the board information of a customized FPGA. The BMC can monitor the FPGA board's status in real time, including parameters such as temperature, power consumption, and voltage. Based on the real-time status information of the FPGA board, the data center can better manage and optimize resources. For example, by monitoring the power consumption status of the FPGA board in real time, the BMC can formulate corresponding power management strategies based on the relationship between different workload requirements and power consumption. For compute-intensive workloads, Dynamic Voltage and Frequency Scaling (DVFS) technology can be used to reduce hardware power consumption by dynamically adjusting the CPU voltage and frequency according to task requirements to achieve more efficient power management. For storage-intensive workloads, more efficient storage devices can be used or storage access patterns can be optimized. For example, SSDs can be used instead of HDDs, or data access patterns can be optimized to reduce disk I / O operations, thereby reducing the power consumption of storage devices.

[0100] Furthermore, based on the temperature and power consumption information of the boards, tasks can be rationally scheduled and cooling resources allocated. Tasks can be assigned to hardware devices or nodes with lower power consumption to reduce the overall power consumption of the data center, improve its energy efficiency, and help ensure its stable operation. For example, if the temperature or power consumption of a certain board is too high, some computing tasks can be transferred to other boards with lower temperatures to balance the load and reduce the energy consumption of the data center.

[0101] Furthermore, since FPGAs typically exist as slave devices within the chassis, starting up with the system power-on without independent power and power consumption control, a dedicated management system can be added to manage the FPGAs. For example, a power control module can be added to sense the system power status (including whether it is powered on, voltage, current, power consumption, etc.) and report it to the BMC and management software. At the same time, the power control module receives instructions from the management software and BMC to perform power-on, power-off, and reset operations on each FPGA. It can dynamically control the power switching status of each device in the system according to needs, thereby optimizing power consumption. A monitoring and alarm module can also be added to receive data from the board to determine whether the safe operating range has been exceeded and generate alarm information.

[0102] The communication method between the BMC and the custom FPGA described above can be implemented using the following code. It should be understood that the following code is for illustrative purposes only and is not the only implementation method.

[0103]

[0104]

[0105]

[0106] It should be understood that, although Figure 3 , Figure 5 , Figure 6 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 , Figure 5 , Figure 6 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0107] In one embodiment, such as Figure 7 As shown, a communication device between a BMC and a custom FPGA is provided, including: a communication protocol construction module, a data acquisition module, and a data analysis module, wherein:

[0108] The communication protocol building module is used to build an I2C communication protocol between the BMC and the custom FPGA based on edge computing.

[0109] The data acquisition module is used to send read and write commands to the FPGA through the information acquisition function based on the communication protocol, acquire the raw data of all board information in a handshake interaction process, and store it in the buffer of the BMC;

[0110] The data parsing module is used to parse and output the raw data in the buffer.

[0111] In one specific embodiment, the information acquisition function includes a data acquisition function and a pointer to the buffer. Before sending read / write commands to the FPGA through the information acquisition function, the pointer is checked to see if it is null. If it is, an error message is returned; otherwise, the data acquisition function is called to send read / write commands to the FPGA to obtain the original data of the board information.

[0112] In one specific embodiment, the parameters of the data acquisition function include the I2C bus number, slave device address, read / write command, pointer to the buffer, and the total length of all data. The data acquisition function sends read / write commands to the slave device address based on the I2C bus number to acquire the raw data of the board information, where the slave device address is the FPGA address. The return value of the data acquisition function is checked; if the return value is negative, data acquisition fails, and an error message is returned; otherwise, the data acquisition function executes successfully, and the return value is the length of the acquired data, which is stored in the buffer.

[0113] In one specific embodiment, sending a read / write command to the slave device address according to the I2C bus number includes: sending a start bit, the slave device address, and a write flag to the FPGA, and the FPGA generating a first response bit; after receiving the first response bit returned by the FPGA, sending the start address of all registers to the FPGA, and the FPGA generating a second response bit; after receiving the second response bit returned by the FPGA, sending a start bit, the slave device address, and a read flag to the FPGA, and the FPGA generating a third response bit.

[0114] In one specific embodiment, in response to the FPGA sending the corresponding register data according to the start address of all received registers, a non-response bit and a stop bit are sent to the FPGA; wherein, the register data includes board temperature, power consumption, voltage, manufacturer ID, device ID, firmware version and serial number, and each type of register data consists of one or more bytes.

[0115] In a specific embodiment, parsing and outputting the raw data in the buffer includes: defining and initializing the buffer; defining the offsets of various board information in the buffer; parsing the raw data in the buffer according to the number of bytes occupied by the obtained raw data and the big / little endian rule, and extracting it into the corresponding memory variables; and processing the data in the memory variables according to the usage requirements or application scenario to obtain the final readable data.

[0116] In a specific embodiment, if the obtained raw data is a single byte, it is directly extracted into a memory variable; if the obtained raw data is multi-byte, it is shifted left, shifted right, or merged according to the big / little endianness rule.

[0117] Specific limitations regarding the communication device between the BMC and the custom FPGA can be found in the above description of the communication method between the BMC and the custom FPGA, and will not be repeated here. Each module in the aforementioned communication device between the BMC and the custom FPGA can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0118] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 8As shown, the computer device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores board information data. The network interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements a communication method between a BMC and a custom FPGA.

[0119] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0120] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0121] Establish an I2C communication protocol between BMC and custom FPGA based on edge computing;

[0122] Based on the communication protocol, read and write commands are sent to the FPGA through the information acquisition function. The raw data of all board information is obtained in a handshake interaction process and stored in the buffer of the BMC.

[0123] The raw data in the buffer is parsed and output.

[0124] In one embodiment, when the processor executes the computer program, it also performs the following steps: checks if the pointer is null; if so, returns an error message; otherwise, it calls a data acquisition function to send read / write commands to the FPGA to obtain the raw data of the board information.

[0125] In one embodiment, when the processor executes the computer program, it further performs the following steps: using a data acquisition function, it sends a read / write command to the slave device address according to the I2C bus number to obtain the raw data of the board information; it checks the return value of the data acquisition function. If the return value is negative, the data acquisition fails and an error message is returned; otherwise, the data acquisition function is executed successfully, and the return value is the length of the acquired data, which is stored in a buffer.

[0126] In one embodiment, when the processor executes the computer program, it further performs the following steps: sending a start bit, a slave address, and a write flag to the FPGA; after receiving a response bit from the FPGA, sending the start address of all registers to the FPGA; and after receiving a response bit from the FPGA, sending a start bit, a slave address, and a read flag to the FPGA.

[0127] In one embodiment, when the processor executes the computer program, it also performs the following steps: In response to a read / write command, the FPGA sends the corresponding register data to the BMC based on the starting addresses of all received registers. The register data includes board temperature, power consumption, voltage, vendor ID, device ID, firmware version, and serial number, and each type of register data consists of one or more bytes. After receiving the register data, the BMC sends a non-response bit and a stop bit to the FPGA.

[0128] In one embodiment, when the processor executes the computer program, it also performs the following steps: defining and initializing a buffer; defining the offsets of various board information in the buffer; parsing the original data in the buffer according to the number of bytes occupied by the obtained original data and the big / little endian rule, and extracting it into the corresponding memory variable; and processing the data in the memory variable according to the usage requirements or application scenario to obtain the final readable data.

[0129] In one embodiment, when the processor executes the computer program, it further performs the following steps: if the obtained raw data is a single byte, it is directly extracted into a memory variable; if the obtained raw data is multi-byte, the raw data is shifted left, shifted right, or merged according to the big / little endian rule.

[0130] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0131] Establish an I2C communication protocol between BMC and custom FPGA based on edge computing;

[0132] Based on the communication protocol, read and write commands are sent to the FPGA through the information acquisition function. The raw data of all board information is obtained in a handshake interaction process and stored in the buffer of the BMC.

[0133] The raw data in the buffer is parsed and output.

[0134] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: before sending read / write commands to the FPGA through the information acquisition function, it checks whether the pointer is null; if so, it returns an error message; otherwise, it calls the data acquisition function to send read / write commands to the FPGA to obtain the raw data of the board information.

[0135] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: using a data acquisition function, it sends a read / write command to the slave device address according to the I2C bus number to obtain the raw data of the board information; it checks the return value of the data acquisition function. If the return value is negative, the data acquisition fails and an error message is returned; otherwise, the data acquisition function is executed successfully, and the return value is the length of the acquired data, which is stored in a buffer.

[0136] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: sending a start bit, a slave address, and a write flag to the FPGA, and the FPGA generates a first response bit; after receiving the first response bit returned by the FPGA, sending the start addresses of all registers to the FPGA, and the FPGA generates a second response bit; after receiving the second response bit returned by the FPGA, sending a start bit, a slave address, and a read flag to the FPGA, and the FPGA generates a third response bit.

[0137] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: in response to the FPGA sending corresponding register data according to the start address of all received registers, sending a non-response bit and a stop bit to the FPGA; wherein, the register data includes board temperature, power consumption, voltage, manufacturer ID, device ID, firmware version and serial number, and each type of register data consists of one or more bytes.

[0138] In one embodiment, when the computer program is executed by the processor, it also performs the following steps: defining and initializing a buffer; defining the offsets of various board information in the buffer; parsing the original data in the buffer according to the number of bytes occupied by the obtained original data and the big / little endian rule, and extracting it into the corresponding memory variables; processing the data in the memory variables according to usage requirements or application scenarios to obtain the final readable data.

[0139] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: if the obtained raw data is a single byte, it is directly extracted into a memory variable; if the obtained raw data is multi-byte, the raw data is shifted left, shifted right, or merged according to the big / little endian rule.

[0140] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A communication method between a BMC and a custom FPGA, characterized in that, include: Establish an I2C communication protocol between BMC and custom FPGA based on edge computing; Based on the communication protocol, read and write commands are sent to the FPGA through the information acquisition function. During a handshake interaction, the raw data of all board information is obtained and stored in the buffer of the BMC. The original data in the buffer is parsed and output; The information acquisition function includes a data acquisition function and a pointer to the buffer. Before sending read / write commands to the FPGA through the information acquisition function, the following steps are included: Check if the pointer is null; if so, return an error message. Otherwise, the data acquisition function is invoked to send read / write commands to the FPGA to obtain the raw data of the board information; The parameters of the data acquisition function include the I2C bus number, slave device address, read / write command, pointer to the buffer, and the total length of all data. Calling the data acquisition function to send read / write commands to the FPGA includes: The read / write command is sent to the slave device address according to the I2C bus number through the data acquisition function to obtain the original data of the board information, wherein the slave device address is the FPGA address. Check the return value of the data acquisition function. If the return value is negative, the data acquisition failed and an error message is returned. Otherwise, if the data acquisition function executes successfully, the return value is the length of the acquired data, which is stored in the buffer. The I2C communication protocol between the BMC and the custom FPGA based on edge computing includes: The communication protocol enables data exchange between the BMC and the custom FPGA. The communication protocol includes a start signal, FPGA address, read / write signal, register address, and end signal. The register address includes the start address of all registers in the custom FPGA that need to acquire data. The data exchange between the BMC and the custom FPGA is transmitted in a specific byte format. The data includes a start byte, an address byte, multiple data bytes, and an end byte. The address byte is used to indicate the register to be accessed, and the data bytes contain the raw data of the board information to be read or written. Based on the communication protocol, a start bit, slave device address, and write flag are sent to the FPGA, and the FPGA generates a first response bit. After receiving the first response bit returned by the FPGA, the starting address of all registers is sent to the FPGA, and the FPGA generates the second response bit; After receiving the second response bit returned by the FPGA, the start bit, slave address and read flag are sent to the FPGA, and the FPGA generates the third response bit.

2. The communication method between the BMC and the custom FPGA according to claim 1, characterized in that: The raw data for obtaining the board information includes: In response to the FPGA sending corresponding register data based on the start address of all received registers, a non-response bit and a stop bit are sent to the FPGA; wherein, the register data includes board temperature, power consumption, voltage, manufacturer ID, device ID, firmware version and serial number, and each type of register data consists of one or more bytes.

3. The communication method between the BMC and the custom FPGA according to claim 1, characterized in that: The step of parsing and outputting the raw data in the buffer includes: Define and initialize the buffer; Define the offset of various board information in the buffer; Based on the number of bytes occupied by the obtained raw data and the big / little endian rule, the raw data in the buffer is parsed and extracted into the corresponding memory variables; The data in the memory variables is processed according to usage requirements or application scenarios to obtain the final readable data.

4. The communication method between the BMC and the custom FPGA according to claim 3, characterized in that: The step of parsing the original data in the buffer based on the number of bytes occupied by the obtained original data and the big / little endian rule includes: If the obtained raw data is a single byte, it is directly extracted into a memory variable; If the obtained raw data is multi-byte, then the raw data is shifted left, shifted right, or merged according to the big / little endian rule.

5. A communication apparatus for implementing the communication method between a BMC and a custom FPGA as described in any one of claims 1-4, characterized in that, The device includes: The communication protocol building module is used to build an I2C communication protocol between the BMC and the custom FPGA based on edge computing. The data acquisition module is used to send read and write commands to the FPGA through the information acquisition function based on the communication protocol, acquire the raw data of all board information in a handshake interaction process, and store it in the buffer of the BMC; The data parsing module is used to parse and output the raw data in the buffer.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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