Protective circuit and safety chip for detecting a laser

Abstract

The application relates to the chip technical field and discloses a protection circuit for detecting laser light, which comprises an optical detection circuit configured to generate a mirror current of a reference current and generate a photoelectric current to discharge and lower the output terminal level of the optical detection circuit in the case of laser injection, so that the optical detection circuit outputs a low-level signal; wherein the photoelectric current is greater than the mirror current; and a logic control circuit connected with the optical detection circuit and configured to output an alarm signal in the case that the optical detection circuit outputs the low-level signal. Therefore, the application can output the alarm signal through the logic control circuit in the case that the optical detection circuit outputs the low-level signal. Therefore, the disclosed embodiment can timely and accurately perceive whether the security chip is subjected to the laser injection attack. The application further discloses a security chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, for example to a protective circuit and a security chip for detecting lasers. Background Technology

[0002] Security chips are widely used in mobile payments, identity verification, and IoT device identification. Their functions include secure storage, encryption, decryption, and identity verification of critical user data. Because of the importance of the data within security chips, attacks have become a significant means of acquiring it. Among these attacks, laser injection attacks have rapidly become a primary method of semi-intrusive attacks due to their inexpensive equipment, ease of implementation, and high controllability.

[0003] To protect the encrypted data inside the security chip from being stolen and to ensure the chip functions properly, there is an urgent need for a technical solution that can detect external laser injection attacks.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] This disclosure provides a protective circuit and a security chip for detecting lasers, which can detect in a timely and sensitive manner whether the security chip is subjected to laser injection attacks.

[0007] In some embodiments, the protection circuit for detecting lasers includes: a photodetector circuit configured to generate a mirror current of a reference current and to generate a photocurrent to discharge in the event of laser injection, thereby pulling down the output level of the photodetector circuit so that the photodetector circuit outputs a low-level signal; wherein the photocurrent is greater than the mirror current; and a logic control circuit connected to the photodetector circuit and configured to output an alarm signal when the photodetector circuit outputs a low-level signal.

[0008] Optionally, the photodetector circuit includes: a current generating subcircuit configured to generate a reference current; a current mirroring subcircuit connected to the output of the current generating subcircuit and configured to mirror the reference current into a mirror current; and a photocurrent subcircuit, with a first terminal connected to the output of the current mirroring subcircuit and forming the output of the photodetector circuit at the connection point, and a second terminal grounded, configured to generate a photocurrent to discharge the logic control circuit in the event of laser injection, thereby pulling down the output level of the photodetector circuit.

[0009] Optionally, the current generating sub-circuit includes: a first NMOS transistor, the drain of which is connected to the power supply voltage; a second NMOS transistor, the gate of which is connected to the gate and source of the first NMOS transistor, and the drain of which is connected to the source of the first NMOS transistor and the gate of the second NMOS transistor, and the source of which is grounded; a third NMOS transistor, the source of which is connected to the source of the second NMOS transistor, and the gate of which is connected to the drain of the second NMOS transistor; and a first PMOS transistor, the source of which is connected to the power supply voltage, the gate of which is connected to the input terminal of the current mirroring sub-circuit and the drain of the first PMOS transistor, and the drain of which is connected to the drain of the second NMOS transistor.

[0010] Optionally, the current mirror sub-circuit includes: a second PMOS transistor, the source of which is connected to the power supply voltage, the gate of which is connected to the output terminal of the current generation sub-circuit, the drain of which is connected to the output terminal of the photocurrent sub-circuit, and the connection point forms the output terminal of the photodetector circuit.

[0011] Optionally, the logic control circuit includes: an enable signal terminal configured to output an enable signal; a switch sub-circuit with its input terminal connected to the enable signal terminal and configured to receive the enable signal; and an inverting sub-circuit with its first input terminal connected to the output terminal of the light detection circuit and its second input terminal connected to the output terminal of the switch sub-circuit, configured to output a high-level alarm signal when the light detection circuit outputs a low-level signal and the enable signal is a low-level signal.

[0012] Optionally, the inverting sub-circuit includes: a latching unit, with a first input terminal connected to the output terminal of the photodetector circuit and a second input terminal connected to the output terminal of the switching sub-circuit, configured to output and latch a high-level signal when the photodetector circuit outputs a low-level signal and the enable signal is a low-level signal; and an alarm unit, with an input terminal connected to the output terminal of the latching unit, configured to output a high-level alarm signal when the latching unit outputs a high-level signal.

[0013] Optionally, the latching unit includes: a third PMOS transistor, whose gate is connected to the output terminal of the photodetector circuit and whose source is connected to the power supply voltage; a fourth NMOS transistor, whose gate is connected to the output terminal of the photodetector circuit, whose drain is connected to the drain of the third PMOS transistor and the output terminal of the switching sub-circuit respectively, and whose output terminal of the latching unit is formed at the connection with the output terminal of the switching sub-circuit, and whose source is grounded.

[0014] Optionally, the alarm unit includes: a first conversion subunit, the input of which is connected to the output of the latch unit, configured to convert the high-level signal output by the latch unit into a low-level signal for output; and a second conversion subunit, the input of which is connected to the first conversion subunit, configured to convert the low-level signal output by the first conversion subunit into a high-level alarm signal for output.

[0015] Optionally, the inverting sub-circuit further includes: a signal broadening unit, the first terminal of which is connected to the power supply voltage, the second terminal of which is connected to the second input terminal of the latch unit and the output terminal of the switching sub-circuit respectively, and the third terminal of which is connected to the output terminal of the first conversion sub-unit and the input terminal of the second conversion sub-unit respectively, and is configured to be turned on when the latch unit outputs a high-level signal and the enable signal is a low-level signal so that the output terminal of the latch unit continuously outputs a high-level signal.

[0016] In some embodiments, the security chip includes: a chip body; and a protection circuit for detecting lasers, as described above, mounted on the chip body.

[0017] The protective circuit and safety chip for detecting lasers provided in this disclosure can achieve the following technical effects:

[0018] In this embodiment, the circuit for detecting laser attacks includes a light detection circuit and a logic control circuit. When a laser injection attack occurs, the potential output by the light detection circuit is pulled low. Since the logic control circuit is connected to the light detection circuit, an alarm signal can be output through the logic control circuit when the light detection circuit outputs a low-level signal. Therefore, this embodiment can detect whether the security chip is under laser injection attack in a timely and accurate manner.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0021] Figure 1 This is a schematic diagram of a protection circuit for detecting laser provided in an embodiment of this disclosure;

[0022] Figure 2 This is a schematic diagram of another protection circuit for detecting laser provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of a light detection circuit provided in an embodiment of this disclosure;

[0024] Figure 4 This is a schematic diagram of a logic control circuit provided in an embodiment of this disclosure;

[0025] Figure 5 This is a timing example diagram illustrating the working principle of a protection circuit for detecting lasers provided in an embodiment of this disclosure;

[0026] Figure 6 This is a schematic diagram of a security chip provided in an embodiment of this disclosure.

[0027] Figure label:

[0028] 200. Protective circuit for laser detection; 1. Safety chip; 100. Chip body;

[0029] 10. Photodetector circuit; 101. Current generation sub-circuit; 1011. First NMOS transistor; 1012. Second NMOS transistor; 1013. Third NMOS transistor; 1014. First PMOS transistor; 102. Current mirror sub-circuit; 1021. Second PMOS transistor; 103. Photocurrent sub-circuit;

[0030] 20. Logic control circuit; 201. Enable signal terminal; 202. Switch sub-circuit; 203. Inverting sub-circuit; 2031. Latch unit; 2311. Third PMOS transistor; 2312. Fourth NMOS transistor; 2032. Alarm unit; 2321. First conversion sub-unit; 2322. Fourth PMOS transistor; 2323. Fifth NMOS transistor; 2324. Second conversion sub-unit; 2325. Fifth PMOS transistor; 2326. Sixth NMOS transistor; 2033. Signal widening unit;

[0031] 30. Power input terminal. Detailed Implementation

[0032] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0033] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0034] Unless otherwise stated, the term "multiple" means two or more.

[0035] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0036] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0038] Combination Figure 6 As shown, this embodiment of the disclosure provides a protection circuit 200 for detecting lasers, which is disposed on a security chip 1. The security chip 1 is a chip used for identity authentication or as a payment tool. Since such chips typically store important data, it is necessary to provide a circuit capable of detecting whether they are under laser attack. Upon detecting a laser attack, the laser detection protection circuit 200 outputs an alarm signal to a connected alarm device (e.g., a buzzer) to trigger an alarm.

[0039] Combination Figure 1 and Figure 2 As shown, this disclosure provides a protection circuit 200 for detecting lasers. The protection circuit 200 for detecting lasers includes a photodetector circuit 10 and a logic control circuit 20. The photodetector circuit 10 is configured to generate a mirror current of a reference current and, in the event of laser injection, generate a photocurrent to discharge and pull down the output level of the photodetector circuit 10, causing the photodetector circuit 10 to output a low-level signal; wherein the photocurrent is greater than the mirror current. The logic control circuit 20 is connected to the photodetector circuit 10 and is configured to output an alarm signal when the photodetector circuit 10 outputs a low-level signal.

[0040] Specifically, the photocurrent is much larger than the mirror current.

[0041] In this embodiment, the circuit for detecting laser attacks includes a light detection circuit 10 and a logic control circuit 20. When a laser injection attack occurs, the potential output by the light detection circuit 10 is pulled low. Since the logic control circuit 20 is connected to the light detection circuit 10, an alarm signal can be output through the logic control circuit 20 when the light detection circuit 10 outputs a low-level signal. Therefore, this embodiment can detect whether the security chip 1 has been subjected to a laser injection attack in a timely and accurate manner.

[0042] Optionally, such as Figure 3As shown, the photodetector circuit 10 includes a current generation sub-circuit 101, a current mirroring sub-circuit 102, and a photocurrent sub-circuit 103. The current generation sub-circuit 101 is configured to generate a reference current. The current mirroring sub-circuit 102 is connected to the output of the current generation sub-circuit 101 and is configured to mirror the reference current into a mirrored current. The first terminal of the photocurrent sub-circuit 103 is connected to the output of the current mirroring sub-circuit 102, forming the output of the photodetector circuit 10 at the connection point. The second terminal is grounded and configured to generate a photocurrent to discharge the logic control circuit 20 in the event of laser injection, thereby pulling down the output level of the photodetector circuit 10. The output of the photodetector circuit 10 is point A.

[0043] For example, the current mirroring sub-circuit 102 replicates the reference current generated by the current generation sub-circuit 101 at a 1:1 ratio to mirror the reference current. That is, the mirrored current has the same magnitude as the reference current.

[0044] In this disclosed embodiment, the current generating sub-circuit 101 generates a reference current with a relatively small temperature coefficient and much smaller than the photocurrent. The current mirroring sub-circuit 102 mirrors the reference current into a mirror current, so that the photocurrent generated by the photocurrent sub-circuit 103 is much larger than the mirror current in the case of laser injection, thereby causing the photocurrent to discharge the logic control circuit 20. In this way, the output level of the photodetector circuit 10 can be lowered, so that the photodetector circuit 10 outputs a low-level signal, thereby enabling timely and sensitive detection of whether laser injection has occurred.

[0045] Optionally, such as Figure 3 As shown, the current generating sub-circuit 101 includes a first NMOS transistor 1011, a second NMOS transistor 1012, a third NMOS transistor 1013, and a first PMOS transistor 1014. The drain of the first NMOS transistor 1011 is connected to the power supply voltage. The gate of the second NMOS transistor 1012 is connected to both the gate and source of the first NMOS transistor 1011, and its drain is connected to both the source and gate of the first NMOS transistor 1011 and the second NMOS transistor 1012, with its source grounded. The source of the third NMOS transistor 1013 is connected to the source of the second NMOS transistor 1012, and its gate is connected to the drain of the second NMOS transistor 1012. The source of the first PMOS transistor 1014 is connected to the power supply voltage, its gate is connected to both the input terminal of the current mirroring sub-circuit 102 and the drain of the first PMOS transistor 1014, and its drain is connected to the drain of the second NMOS transistor 1012.

[0046] Among them, such as Figure 3 As shown, the power supply voltage is provided by the power input terminal 30.

[0047] For example, the first NMOS transistor 1011 is a native MOS transistor. Thus, the V1011 of the first NMOS transistor 1011... gs =0, then V gs Less than V TH Among them, V gs V is the gate-source voltage. TH This is the threshold voltage. When V gs Less than V TH At this time, the channel between the source and drain of the first NMOS transistor 1011 has not been formed, and it is in the off state. At this time, even if V... gs The current is zero, and no large current flows through the channel between the source and drain. Since adjusting the transistor's dimensions (e.g., increasing or decreasing the channel length or width) can alter its operating characteristics, adjusting the dimensions of the first NMOS transistor 1011 allows it to operate in the subthreshold region, thus generating a small reference current.

[0048] In this disclosed embodiment, a reference current with a relatively small temperature coefficient and much smaller than the photocurrent is generated by the first NMOS transistor 1011, the second NMOS transistor 1012, the third NMOS transistor 1013 and the first PMOS transistor 1014, thereby making the mirror current much smaller than the photocurrent, and thus making the photocurrent discharge the logic control circuit 20 to realize the output of a low-level signal by the photodetector circuit 10.

[0049] Optionally, such as Figure 3 As shown, the current mirror sub-circuit 102 includes a second PMOS transistor 1021. The source of the second PMOS transistor 1021 is connected to the power supply voltage, the gate is connected to the output terminal of the current generation sub-circuit 101, and the drain is connected to the output terminal of the photocurrent sub-circuit 103, forming the output terminal of the photodetector circuit 10 at the connection point.

[0050] For example, the W / L of the second PMOS transistor 1021 is proportional to the W / L of the first PMOS transistor 1014, and the μ of the two transistors... p c ox V gs V TH They are equal, according to the formula:

[0051]

[0052] It can be seen that the I of the second PMOS transistor 1021 and the first PMOS transistor 1014 are... D Proportional. Where W / L is the ratio of width to length, I... D For current. μ p It is conductivity, which measures the conductivity of a PMOS transistor. oxIt is the oxide layer capacitance, which represents the capacitance between the oxide layer and the semiconductor layer in a PMOS transistor.

[0053] In this disclosed embodiment, by setting the second PMOS transistor 1021 to replicate the current of the first PMOS transistor 1014, the structure of the current generation sub-circuit 101 is avoided by directly connecting its output terminal to the photocurrent sub-circuit 103, thus preventing disruption of the current generation sub-circuit 101's structure. In this way, the current generation sub-circuit 101 is less susceptible to external circuitry, thereby ensuring the stable generation of the reference current.

[0054] Optionally, the photocurrent quantum circuit 103 includes a photodiode. This improves the photosensitivity of the photocurrent quantum circuit 103, enabling more sensitive detection of laser injection.

[0055] For example, the photodiode is a photodiode composed of NWELL and PSUB. Since the photodiode composed of NWELL and PSUB can effectively suppress reflected light and improve photosensitivity, it can further improve the photosensitivity performance of the photocurrent circuit.

[0056] Specifically, when the optical detection circuit 10 detects a laser injection attack, the potential at its output terminal is pulled low. That is, when the optical detection circuit 10 detects a laser injection attack, it outputs a low-level signal to enable the protection circuit 200 for laser detection to detect the laser attack in a timely manner.

[0057] Optionally, such as Figure 4 As shown, the logic control circuit 20 includes an enable signal terminal 201, a switching sub-circuit 202, and an inverter sub-circuit 203. The enable signal terminal 201 is configured to output an enable signal. The input terminal of the switching sub-circuit 202 is connected to the enable signal terminal 201 and is configured to receive the enable signal. The first input terminal of the inverter sub-circuit 203 is connected to the output terminal of the light detection circuit 10, and the second input terminal is connected to the output terminal of the switching sub-circuit 202. It is configured to output a high-level alarm signal when the light detection circuit 10 outputs a low-level signal and the enable signal is low.

[0058] In this circuit, the second input terminal of the inverting sub-circuit 203 and the output terminal of the switching sub-circuit 202 form point B at the connection point.

[0059] It should be noted that the switching sub-circuit 202 receives an enable signal and turns the detection function of the optical detection circuit 10 on or off according to the enable signal. Furthermore, when the enable signal is low (i.e., the enable signal is zero), the switching sub-circuit 202 turns on the detection function of the optical detection circuit 10 to detect whether laser injection has occurred. When the enable signal is high (i.e., the enable signal is high), the switching sub-circuit 202 turns off the detection function of the optical detection circuit 10 to stop detecting whether laser injection has occurred. That is, regardless of whether a laser attack occurs, since the detection function of the optical detection circuit 10 is turned off, the inverting sub-circuit 203 will not output a high-level alarm signal. In this way, by controlling whether the protection circuit 200 used for laser detection turns on or off via the enable signal, the protection circuit 200 only performs laser detection when necessary, reducing the power consumption of the protection circuit.

[0060] In this disclosed embodiment, when the enable signal is a low-level signal, it indicates that the switch sub-circuit 202 controls the photodetector circuit 10 to activate the detection function. When the photodetector circuit 10 activates the detection function and outputs a low-level signal, it indicates that the photodetector circuit 10 has detected laser injection. Then, the inverting sub-circuit 203 converts the low-level signal into a high-level signal and outputs a high-level alarm signal.

[0061] Optionally, such as Figure 4 As shown, the inverting sub-circuit 203 includes a latch unit 2031 and an alarm unit 2032. The first input terminal of the latch unit 2031 is connected to the output terminal of the light detection circuit 10, and the second input terminal is connected to the output terminal of the switching sub-circuit 202. It is configured to output and latch a high-level signal when the light detection circuit 10 outputs a low-level signal and the enable signal is low. The input terminal of the alarm unit 2032 is connected to the output terminal of the latch unit 2031, and it is configured to output a high-level alarm signal when the latch unit 2031 outputs a high-level signal.

[0062] Understandably, when the latch unit 2031 receives a low-level signal output from the optical detection circuit 10, it converts the low-level signal to a high-level signal and latches the high-level signal as a long-term high-level signal until the enable signal becomes a high-level signal (i.e., the enable signal is set high). At this point, the latch unit 2031 is unlocked or reset. This allows the inverter sub-circuit 203 to output a long-term alarm signal until the detection function of the optical detection circuit 10 is turned off due to the enable signal being set high.

[0063] In this disclosed embodiment, because the latching unit 2031 can maintain a high-level signal, the alarm signal of the alarm unit 2032 can continue for a period of time until the latching unit 2031 is unlocked or reset. This helps to ensure that the protection circuit can issue an alarm signal in a timely and accurate manner when laser injection is detected, and that the alarm signal can continue for a period of time so that appropriate responses and processing can be carried out subsequently.

[0064] Optionally, the latch unit 2031 can be configured as an inverter, which can shape irregular waveforms into rectangular waves for easy digital capture.

[0065] Optionally, such as Figure 4 As shown, the latch unit 2031 includes a third PMOS transistor 2311 and a fourth NMOS transistor 2312. The gate of the third PMOS transistor 2311 is connected to the output terminal of the photodetector circuit 10, and its source is connected to the power supply voltage. The gate of the fourth NMOS transistor 2312 is connected to the output terminal of the photodetector circuit 10, and its drain is connected to both the drain of the third PMOS transistor 2311 and the output terminal of the switching sub-circuit 202. The connection point with the output terminal of the switching sub-circuit 202 forms the output terminal of the latch unit 2031, and its source is grounded.

[0066] The third PMOS transistor, 2311, is used as a latch.

[0067] Understandably, when the enable signal is low, the switch sub-circuit 202 activates the detection function of the photodetector circuit 10 based on the enable signal. When the photodetector circuit 10 detects laser injection, it outputs a low-level signal. Since the latch unit 2031 is connected to the output of the photodetector circuit 10, and the PMOS transistor conducts when its gate input is low, and the NMOS transistor conducts when its gate input is high, when the photodetector circuit 10 outputs a low-level signal, the gate input of the third PMOS transistor 2311 is low, so the third PMOS transistor 2311 conducts; the gate input of the fourth NMOS transistor 2312 is low, so the fourth NMOS transistor 2312 is off. In this case, since the third PMOS transistor 2311 is in the conducting state, and its source is connected to the power supply voltage, the third PMOS transistor 2311 outputs and latches a high-level signal.

[0068] In this disclosed embodiment, the cooperation of the third PMOS transistor 2311 and the fourth NMOS transistor 2312 enables the conversion of the low-level signal into a high-level signal and latching it when the photodetector circuit 10 outputs a low-level signal.

[0069] Specifically, when the photocurrent is greater than the mirror current, it discharges the latch unit 2031 in the logic control circuit 20. More specifically, when the photocurrent is greater than the mirror current, it discharges the third PMOS transistor 2311 and the fourth NMOS transistor 2312.

[0070] Optionally, such as Figure 4 As shown, the alarm unit 2032 includes a first conversion subunit 2321 and a second conversion subunit 2324. The input terminal of the first conversion subunit 2321 is connected to the output terminal of the latch unit 2031 and is configured to convert the high-level signal output by the latch unit 2031 into a low-level signal for output. The input terminal of the second conversion subunit 2324 is connected to the first conversion subunit 2321 and is configured to convert the low-level signal output by the first conversion subunit 2321 into a high-level alarm signal for output.

[0071] For example, the first conversion subunit 2321 and / or the second conversion subunit 2324 can be configured as inverters to convert the input signal and output it. At the same time, the inverter can shape irregular waveforms into rectangular waves, which is convenient for digital capture.

[0072] In this disclosed embodiment, the alarm unit 2032 can further process and convert the high-level signal output by the latching unit 2031. Specifically, the first conversion subunit 2321 converts the input high-level signal into a low-level signal for output, and the second conversion subunit 2324 converts the input low-level signal into a high-level signal for output. Finally, a high-level alarm signal is output to remind people to pay attention to safety or take appropriate measures.

[0073] Optionally, such as Figure 4 As shown, the first conversion sub-unit 2321 includes a fourth PMOS transistor 2322 and a fifth NMOS transistor 2323. The gate of the fourth PMOS transistor 2322 is connected to the output terminal of the latch unit 2031, and its source is connected to the power supply voltage. The gate of the fifth NMOS transistor 2323 is connected to the output terminal of the latch unit 2031, its drain is connected to the drain of the fourth PMOS transistor 2322 and the second conversion sub-unit 2324, and its source is grounded.

[0074] Understandably, when the latch unit 2031 outputs a high-level signal, the gate of the fourth PMOS transistor 2322 receives a high-level signal, and the fourth PMOS transistor 2322 is turned off; when the gate of the fifth NMOS transistor 2323 receives a high-level signal, the fifth NMOS transistor 2323 is turned on and outputs a low-level signal.

[0075] In this disclosed embodiment, since the first conversion subunit 2321 includes a fourth PMOS transistor 2322 and a fifth NMOS transistor 2323, the first conversion subunit 2321 converts the high-level signal output by the latch unit 2031 into a low-level signal and outputs it to the second conversion subunit 2324.

[0076] Optionally, such as Figure 4 As shown, the second conversion sub-unit 2324 includes a fifth PMOS transistor 2325 and a sixth NMOS transistor 2326. The gate of the fifth PMOS transistor 2325 is connected to the output terminal of the first conversion sub-unit 2321, and its source is connected to the power supply voltage. The gate of the sixth NMOS transistor 2326 is connected to the output terminal of the first conversion sub-unit 2321, its drain is connected to the drain of the fifth PMOS transistor 2325, and its source is grounded.

[0077] For example, the drains of the fifth PMOS transistor 2325 and the sixth NMOS transistor 2326 are also connected to an alarm device to trigger an alarm.

[0078] It is understandable that when the first conversion subunit 2321 outputs a low-level signal, the gate of the fifth PMOS transistor 2325 receives a low-level signal, so the fifth PMOS transistor 2325 is turned on and outputs a high-level signal; when the gate of the sixth NMOS transistor 2326 receives a low-level signal, the sixth NMOS transistor 2326 is turned on.

[0079] In this disclosed embodiment, since the second conversion subunit 2324 includes a fifth PMOS transistor 2325 and a sixth NMOS transistor 2326, the second conversion subunit 2324 converts the low-level signal output by the first conversion subunit 2321 into a high-level signal, so as to realize the output of a high-level alarm signal by the second conversion subunit 2324.

[0080] Optionally, such as Figure 4 As shown, the inverting sub-circuit 203 also includes a signal broadening unit 2033. The first terminal of the signal broadening unit 2033 is connected to the power supply voltage, the second terminal is connected to the second input terminal of the latch unit 2031 and the output terminal of the switching sub-circuit 202, and the third terminal is connected to the output terminal of the first conversion sub-unit 2321 and the input terminal of the second conversion sub-unit 2324, respectively. It is configured to be turned on when the latch unit 2031 outputs a high-level signal and the enable signal is a low-level signal, so that the output terminal of the latch unit 2031 continuously outputs a high-level signal.

[0081] Specifically, the second end of the widened signal unit 2033 is connected to the circuit between the output end of the latch unit 2031 and point B.

[0082] For example, the signal broadening unit 2033 includes a sixth PMOS transistor. The source of the sixth PMOS transistor is connected to the power supply voltage, the drain is connected to the second input terminal of the latch unit 2031 and the output terminal of the switching sub-circuit 202, and the gate is connected to the output terminal of the first conversion sub-unit 2321 and the input terminal of the second conversion sub-unit 2324.

[0083] It is understandable that, since the gate of the sixth PMOS transistor is connected to the output terminal of the first conversion sub-unit 2321, when the first conversion sub-unit 2321 outputs a low-level signal, the sixth PMOS transistor is turned on and outputs a high-level signal, causing point B to output a continuous high-level signal, thereby causing the second conversion sub-unit 2324 to continuously output a high-level alarm signal.

[0084] In this disclosed embodiment, by setting the broadened signal unit 2033, when laser injection occurs, the voltage at point A is pulled low and the output at point B is high. Since the gate voltage of the sixth PMOS transistor is high, the sixth PMOS transistor is turned on, so point B is always pulled high, and the output of the logic control circuit 20 is always in an alarm state.

[0085] Optionally, the switching sub-circuit 202 includes a seventh NMOS transistor. The gate of the seventh NMOS transistor is connected to the enable signal terminal 201, the source is grounded, and the drain is connected to the output terminal of the latch unit 2031, the output terminal of the broadened signal unit 2033, and the output terminal of the first conversion sub-unit 2321, respectively.

[0086] It is understandable that when the enable signal terminal 201 outputs a low-level signal, the seventh NMOS transistor is turned off, and point B is the high-level signal output by the latch unit 2031 and the continuous high-level signal output by the broadening signal unit 2033.

[0087] In this embodiment, by setting a seventh NMOS transistor, it is easier to control the detection function of the photodetector circuit 10 and the control function of the logic control circuit 20.

[0088] Specifically, when the enable signal terminal 201 outputs a high-level signal, the seventh NMOS transistor is turned on. In this case, regardless of whether the photodetector circuit 10 detects laser injection, point B is a low-level signal. The first conversion subunit 2321 converts the input low-level signal to a high-level signal for output, and the second conversion subunit 2324 converts the input high-level signal to a low-level signal for output. Therefore, when the enable signal terminal 201 outputs a high-level signal, the logic control circuit 20 outputs a low-level signal regardless of whether the photodetector circuit 10 detects laser injection. This situation can be considered as the seventh NMOS transistor controlling the photodetector circuit 10 to disable its detection function when the enable signal terminal 201 outputs a high-level signal.

[0089] When the enable signal terminal 201 outputs a low-level signal, the seventh NMOS transistor is turned off. In this case, if the photodetector circuit 10 detects laser injection, it outputs a low-level signal. The latch unit 2031 then converts the input low-level signal into a high-level signal for input and latching. The first conversion subunit 2321 converts the input high-level signal into a low-level signal for output, and the second conversion subunit 2324 converts the input low-level signal into a high-level signal to output a high-level alarm signal. Furthermore, by setting the broadening signal unit 2033, since the gate of the broadening signal unit 2033 receives the high-level signal output from the first conversion subunit 2321, the broadening signal unit 2033 is turned on and continuously outputs a high-level signal at point B, thereby causing the second conversion subunit 2324 to continuously output a high-level alarm signal. Similarly, when the photodetector circuit 10 does not detect laser injection, the logic control circuit 20 outputs a low-level signal.

[0090] This reduces the risk of missed detections during laser injection and improves the accuracy of laser injection detection of security chip 1.

[0091] More specifically, such as Figure 5 As shown, ENN represents the enable signal, Light_pluse is the laser signal (a low level laser signal indicates no laser injection is detected, a high level laser signal indicates laser injection is detected), VOUT represents the alarm signal, T1 is the first time period, T2 is the second time period, and T3 is the third time period. When the enable signal is low (i.e., the enable signal is set to zero), the laser signal is valid. In the case of the laser signal, if the laser signal is low, the alarm signal is low (i.e., no alarm signal is output); if the laser signal is high, the alarm signal is high (i.e., a high-level alarm signal is output). Figure 5In the T1 time period, when the enable signal is high (i.e., the enable signal is set to zero), since the laser signal is invalid at this time, the alarm signal is low regardless of whether the laser signal is high or low, meaning no alarm is triggered. In the T2 time period, when the enable signal is low (i.e., the enable signal is set to zero), if the laser signal is low, it indicates that no laser injection has been detected, and the alarm signal is also low, meaning no alarm is triggered. In the T2 time period, when the enable signal is low (i.e., the enable signal is set to zero), since the laser signal is high, it indicates that laser injection has been detected, and the alarm signal is high. Because the latch unit 2031 latches the high-level alarm signal until the enable signal is high, the latch unit 2031 resets or unlatches the current high-level alarm signal. Therefore, in the T2 time period, the alarm signal remains high. During the T3 time period, because the enable signal is set high, the latch unit 2031 is reset, and the laser signal is invalid. Therefore, regardless of whether the laser signal is high or low, the alarm signal is low, that is, no alarm is triggered.

[0092] Combination Figure 6 As shown, this embodiment of the disclosure provides a security chip 1. The security chip 1 includes a chip body 100 and a protection circuit 200 for detecting lasers as described above, which is mounted on the chip body 100.

[0093] In this embodiment of the disclosure, by installing the protection circuit 200 for detecting lasers on the chip body 100, the detection of whether the security chip 1 is subjected to laser injection attack is realized, thereby improving the reliability of the security chip 1.

[0094] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0095] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0096] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A protective circuit for detecting lasers, characterized in that, include: The photodetector circuit is configured to generate a mirror current of a reference current and, in the event of laser injection, generate a photocurrent to discharge and pull down the output level of the photodetector circuit, so that the photodetector circuit outputs a low-level signal; wherein, the photocurrent is greater than the mirror current. The photodetector circuit includes: a current generation subcircuit configured to generate a reference current; a current mirroring subcircuit connected to the output of the current generation subcircuit and configured to mirror the reference current into a mirror current; and a photocurrent subcircuit, the first terminal of which is connected to the output of the current mirroring subcircuit and forms the output of the photodetector circuit at the connection point, and the second terminal is grounded, configured to generate a photocurrent to discharge the logic control circuit in the event of laser injection, thereby pulling down the output level of the photodetector circuit. The current generating sub-circuit includes: a first NMOS transistor, the drain of which is connected to the power supply voltage; a second NMOS transistor, the gate of which is connected to both the gate and source of the first NMOS transistor, and the drain of which is connected to both the source and gate of the first and second NMOS transistors, with the source grounded; a third NMOS transistor, the source of which is connected to the source of the second NMOS transistor, and the gate of which is connected to the drain of the second NMOS transistor; and a first PMOS transistor, the source of which is connected to the power supply voltage, the gate of which is connected to both the input terminal of the current mirroring sub-circuit and the drain of the first PMOS transistor, and the drain of which is connected to the drain of the second NMOS transistor. The logic control circuit, connected to the light detection circuit, is configured to output an alarm signal when the light detection circuit outputs a low-level signal.

2. The protection circuit according to claim 1, characterized in that, The current mirror circuit includes: The second PMOS transistor has its source connected to the power supply voltage, its gate connected to the output of the current generation sub-circuit, and its drain connected to the output of the photocurrent sub-circuit, forming the output of the photodetector circuit at the connection point.

3. The protection circuit according to claim 1, characterized in that, The logic control circuit includes: The enable signal terminal is configured to output an enable signal; The switching sub-circuit, with its input terminal connected to the enable signal terminal, is configured to receive the enable signal; The inverting sub-circuit has its first input terminal connected to the output terminal of the optical detection circuit and its second input terminal connected to the output terminal of the switching sub-circuit. It is configured to output a high-level alarm signal when the optical detection circuit outputs a low-level signal and the enable signal is a low-level signal.

4. The protection circuit according to claim 3, characterized in that, The inverting sub-circuit includes: The latching unit has a first input terminal connected to the output terminal of the optical detection circuit and a second input terminal connected to the output terminal of the switch sub-circuit. It is configured to output and latch a high-level signal when the optical detection circuit outputs a low-level signal and the enable signal is a low-level signal. The alarm unit, whose input is connected to the output of the latch unit, is configured to output a high-level alarm signal when the latch unit outputs a high-level signal.

5. The protection circuit according to claim 4, characterized in that, The latch unit includes: The third PMOS transistor has its gate connected to the output terminal of the photodetector circuit and its source connected to the power supply voltage. The fourth NMOS transistor has its gate connected to the output of the photodetector circuit, its drain connected to the drain of the third PMOS transistor and the output of the switching sub-circuit, and forms the output of the latch unit at the connection with the output of the switching sub-circuit. Its source is grounded.

6. The protection circuit according to claim 4, characterized in that, The alarm unit includes: The first conversion subunit, whose input terminal is connected to the output terminal of the latch unit, is configured to convert the high-level signal output by the latch unit into a low-level signal for output. The second conversion subunit, whose input is connected to the first conversion subunit, is configured to convert the low-level signal output by the first conversion subunit into a high-level alarm signal for output.

7. The protection circuit according to claim 6, characterized in that, The inverting sub-circuit also includes: The signal extension unit has a first terminal connected to the power supply voltage, a second terminal connected to the second input terminal of the latch unit and the output terminal of the switching sub-circuit, and a third terminal connected to the output terminal of the first conversion sub-unit and the input terminal of the second conversion sub-unit. It is configured to be turned on when the latch unit outputs a high-level signal and the enable signal is a low-level signal, so that the output terminal of the latch unit continuously outputs a high-level signal.

8. A security chip, characterized in that, include: Chip body; The protective circuit for detecting lasers as described in any one of claims 1 to 7 is mounted on the chip body.

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