Display panel and display device

Abstract

The application provides a display panel and a display device; the display panel comprises a pixel circuit and a gate drive circuit comprising a plurality of gate drive units; the pixel circuit comprises a switching transistor, a driving transistor, a first reset transistor and a second reset transistor; the gate drive unit comprises a first signal output end and a second signal output end; in the pixel circuit of the bth row of sub-pixel rows, the gate of the switching transistor is connected to the second signal output end of the ath gate drive unit, the gate of the first reset transistor is connected to the first signal output end of the bth gate drive unit, and the gate of the second reset transistor is connected to the first signal output end of the cth gate drive unit; by removing the gate drive unit connected to the gate of the second reset transistor and using gate drive units of different levels to provide corresponding control signals for the two reset transistors of the same pixel circuit, the structure of the gate drive circuit is simplified, and a narrow frame design is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the development of display technology, existing display devices have higher requirements for narrow bezels. Therefore, existing display devices will use GOA (Gate Driver On Array) technology to replace gate driver chips to reduce the bezel size.

[0003] Meanwhile, the pixel circuits in existing display panels typically need to receive three different control signals output by the gate drive circuit, and these three different control signals are usually output by at least two different gate drive units arranged in the same row. The increase in gate drive units occupies a larger bezel size of the display panel, which contradicts the narrow bezel design. Summary of the Invention

[0004] This application provides a display panel and a display device to solve the technical problem that existing gate drive circuits occupy a large bezel size of the display panel, which contradicts the narrow bezel design.

[0005] This application provides a display panel, which includes a display section and a gate driving circuit located on one side of the display section. The display section includes a plurality of sub-pixel rows, each sub-pixel row includes a plurality of sub-pixel units, and each sub-pixel unit is provided with a pixel circuit.

[0006] The pixel circuit includes a switching transistor, a driving transistor, a first reset transistor, and a second reset transistor. The switching transistor and the driving transistor are connected to a first reset node, the first reset transistor and the driving transistor are connected to the first reset node, and the second reset transistor and the driving transistor are connected to a second reset node.

[0007] The gate driving circuit includes a plurality of cascaded gate driving units. Each gate driving unit includes a first signal output terminal and a second signal output terminal. The gate of the switching transistor of the pixel circuit of the b-th sub-pixel row is connected to the second signal output terminal of the a-th stage. The gate of the first reset transistor of the pixel circuit of the b-th sub-pixel row is connected to the first signal output terminal of the b-th stage. The gate of the second reset transistor of the pixel circuit of the b-th sub-pixel row is connected to the first signal output terminal of the c-th stage.

[0008] Where a is greater than b, b is greater than c, and a, b, and c are positive integers.

[0009] In the display panel of this application, the first signal output terminal outputs a first control signal, and the second signal output terminal outputs a second control signal;

[0010] Within a scan frame of the gate drive circuit, the start time of the first control signal of stage b is located between the start time and the end time of the first control signal of stage c, and the start time of the second control signal of stage a is located after the end time of the first control signal of stage b.

[0011] In the display panel of this application, the pulse width of the first control signal is greater than the pulse width of the second control signal.

[0012] In the display panel of this application, the time interval between the start time of the first control signal of level b and the end time of the first control signal of level c is a first interval segment, and the duration of the first interval segment is greater than the pulse width of the second control signal.

[0013] In the display panel of this application, the plurality of gate driving units further include a first virtual driving unit and a second virtual driving unit located before the first-stage gate driving unit;

[0014] The first signal output terminal of the first virtual driving unit is connected to the gate of the second reset transistor of the pixel unit of the first sub-pixel row, and the first signal output terminal of the second virtual driving unit is connected to the gate of the second reset transistor of the pixel circuit of the second sub-pixel row.

[0015] In the display panel of this application, the time interval between the start time of the second control signal of level a and the end time of the first control signal of level b is a second interval segment, and the duration of the second interval segment is less than the pulse width of the second control signal.

[0016] In the display panel of this application, the gate driving unit includes:

[0017] The pull-up control unit, connected to the first node, is used to pull the potential of the first node high;

[0018] A pull-up unit, one end of which is connected to the first node, and the other end of which is connected to the first signal output terminal and the second signal output terminal. The pull-up unit is used to pull up the potential of the first signal output terminal and the second signal output terminal.

[0019] A pull-down unit, connected to the first node, is used to pull the potential of the first node low;

[0020] A pull-down sustaining unit is provided, one end of which is connected to the first node, and the other end of which is connected to the first signal output terminal and the second signal output terminal. The pull-down sustaining unit is used to maintain the low potential of the first node and pull down the potential of the first signal output terminal and the second signal output terminal.

[0021] In the display panel of this application, the first node is connected to the first low potential line through the pull-down unit, and the first signal output terminal and the second signal output terminal are connected to the second low potential line through the pull-down sustaining unit;

[0022] The potential of the first low-potential line is less than the potential of the second low-potential line.

[0023] In the display panel of this application, the pull-up unit includes a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor;

[0024] In this configuration, the first pull-up transistor, the second pull-up transistor, and the third pull-up transistor are all connected to the first node. The first electrode of the first pull-up transistor is connected to the first clock signal line, the second electrode of the first pull-up transistor is connected to the stage signal terminal, the first electrode of the second pull-up transistor is connected to the second clock signal line, the second electrode of the second pull-up transistor is connected to the first signal output terminal, the first electrode of the third pull-up transistor is connected to the third clock signal line, and the second electrode of the third pull-up transistor is connected to the third signal output terminal.

[0025] The pulse width of the clock signal output from the first clock signal line is less than the pulse width of the clock signal output from the second clock signal line, and the pulse width of the clock signal output from the third clock signal line is less than the pulse width of the clock signal output from the first clock signal line.

[0026] This application also proposes a display device that includes the aforementioned display panel.

[0027] Beneficial Effects: This application provides a display panel and a display device. The display panel includes a display section and a gate driving circuit located on one side of the display section. The display section includes multiple sub-pixel rows, each sub-pixel row includes multiple sub-pixel units, and each sub-pixel unit is provided with a pixel circuit. The pixel circuit includes a switching transistor, a driving transistor, a first reset transistor, and a second reset transistor. The switching transistor and the first reset transistor are connected to a first reset node along with the driving transistor. The second reset transistor and the driving transistor are connected to a second reset node. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes a first signal output terminal and a second signal output terminal. The gate of the switching transistor of the pixel circuit in the b-th sub-pixel row is connected to the second signal output terminal of the a-th stage. The gate of the first reset transistor of the pixel circuit in the b-th sub-pixel row is connected to the first signal output terminal of the b-th stage. The gate of the second reset transistor of the pixel circuit in the b-th sub-pixel row is connected to the first signal output terminal of the c-th stage. a is greater than b, b is greater than c, and a, b, and c are positive integers. This application simplifies the structure of the gate driving circuit and achieves a narrow bezel design by removing the gate driving unit connected to the gate of the second reset transistor and using gate driving units of different stages to provide corresponding control signals to the two reset transistors of the same pixel circuit. Attached Figure Description

[0028] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0029] Figure 1 This is a simplified structural diagram of the display panel of this application;

[0030] Figure 2 This is a structural diagram of the pixel circuit of this application;

[0031] Figure 3 This is a first connection diagram of the gate driving circuit and the pixel circuit of this application;

[0032] Figure 4 This is a circuit diagram of the gate driving unit in the gate driving circuit of this application;

[0033] Figure 5 for Figure 4 Timing diagram of the first clock signal line, the second clock signal line and the third clock signal line;

[0034] Figure 6 for Figure 2 Timing diagram of the switch signal terminal, the first reset terminal, and the second reset terminal;

[0035] Figure 7 This is a second connection diagram of the gate drive circuit and pixel circuit in this application. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0037] Please see Figure 1 This application proposes a display panel 200 including a gate driving circuit 100 and a display section 300. The display panel 200 can be an organic light-emitting diode display panel or a micro light-emitting diode display panel, etc.

[0038] Please see Figure 1 and Figure 2 The display unit 300 includes a plurality of sub-pixel rows 310, each sub-pixel row 310 includes a plurality of sub-pixel units 301, and each sub-pixel unit 301 is provided with a pixel circuit 20. The pixel circuit 20 may include a first storage capacitor C1, a switching transistor T2, a driving transistor T1, a first reset transistor T3 and a second reset transistor T4. The switching transistor T2 and the driving transistor T1 are connected to the first reset node M1, the first reset transistor T3 and the driving transistor T1 are connected to the first reset node M1, and the second reset transistor T4 and the driving transistor T1 are connected to the second reset node M2.

[0039] In this embodiment, the gate of switching transistor T2 is connected to the switching signal terminal Gn, the first electrode of switching transistor T2 is connected to the data signal line Vdata, and the second electrode of switching transistor T2 is connected to the first reset node M1; the gate of the first reset transistor T3 is connected to the first reset terminal Ref, the first electrode of the first reset transistor T3 is connected to the first reference potential Vref, and the second electrode of the first reset transistor T3 is connected to the first reset node M1; the gate of driving transistor T1 is connected to the first reset node M1, the first electrode of driving transistor T1 is connected to the constant voltage high-level source VDD, and the second electrode of driving transistor T1 is connected to the second reset node M2; the gate of the second reset transistor T4 is connected to the second reset terminal Ini, the first electrode of the second reset transistor T4 is connected to the second reference potential Vini, and the second electrode of the second reset transistor T4 is connected to the second reset node M2; the first plate of the first storage capacitor C1 is connected to the first reset node M1, and the second plate of the first storage capacitor C1 is connected to the second reset node M2.

[0040] Meanwhile, the pixel circuit 20 also includes a light-emitting device. The anode of the light-emitting device is connected to the second reset node M2, and the cathode of the light-emitting device is connected to a constant voltage low-level source VSS. The light-emitting device can be an organic light-emitting diode or an LED device, etc.

[0041] Since the operating current in pixel circuit 20 is positively correlated with the difference between the gate potential and the source potential in driving transistor T1, that is... Figure 2 The voltage difference between the first reset node M1 and the second reset node M2; therefore, in order to ensure the accuracy of the operating current in the sub-pixel unit 301, the potentials of the gate and source in the driving transistor T1 need to be reset to the corresponding reference potentials before operation to ensure the accuracy of the operating current. That is, the setting of the first reset transistor T3 and the second reset transistor T4 can solve the above-mentioned technical problem; however Figure 2 The four transistors in the display panel 200 require three different control signals to turn them on. However, the gate drive circuit 100 in the prior art outputs three control signals, which usually requires at least two different gate drive units to be set in the same row. The increase in gate drive units occupies the size of the bezel of the display panel 200, which contradicts the narrow bezel design of the display panel 200.

[0042] Please see Figure 1 and Figure 3 The gate driving circuit 100 may include a plurality of cascaded gate driving units 10. Each gate driving unit 10 includes a first signal output terminal REF(n) and a second signal output terminal WR(n). The gate of the switching transistor T2 of the pixel circuit 20 of the b-th sub-pixel row 310 is connected to the second signal output terminal WR(n) of the a-th stage. The gate of the first reset transistor T3 of the pixel circuit 20 of the b-th sub-pixel row 310 is connected to the first signal output terminal REF(n) of the b-th stage. The gate of the second reset transistor T4 of the pixel circuit 20 of the b-th sub-pixel row 310 is connected to the first signal output terminal REF(n) of the c-th stage. a is greater than b, b is greater than c, and a, b and c are positive integers.

[0043] For example, taking pixel circuit 20 in sub-pixel row 310 of the nth row as an example, the gate of switching transistor T2 is connected to the second signal output terminal WR(n+1) of the (n+1)th stage, the gate of the first reset transistor T3 is connected to the first signal output terminal REF(n) of the nth stage, and the gate of the second reset transistor T4 is connected to the first signal output terminal REF(n-2) of the (n-2)th stage, where n is an integer greater than or equal to 3.

[0044] That is, in Figure 3In the structure, the (n-2)th stage first signal output terminal REF(n-2) provides a control signal to the gate of the second reset transistor T4 of the nth row sub-pixel unit 301, the nth stage first signal output terminal REF(n) provides a control signal to the gate of the first reset transistor T3 of the nth row sub-pixel unit 301, and the (n+1)th stage second signal output terminal WR(n+1) provides a control signal to the gate of the first reset transistor T3 of the nth row sub-pixel unit 301; simultaneously, Figure 3 In the structure, the (n-1)th stage first signal output terminal REF(n-1) provides a control signal to the gate of the second reset transistor T4 of the (n+1)th row sub-pixel unit 301, the (n+1)th stage first signal output terminal REF(n+1) provides a control signal to the gate of the first reset transistor T3 of the (n+1)th row sub-pixel unit 301, and the (n+2)th stage second signal output terminal WR(n+2) provides a control signal to the gate of the first reset transistor T3 of the (n+1)th row sub-pixel unit 301; simultaneously, Figure 3 In the structure, the first signal output terminal REF(n) of the nth stage provides a control signal to the gate of the second reset transistor T4 of the (n+2)th row sub-pixel unit 301, the first signal output terminal REF(n+2) of the (n+2)th stage provides a control signal to the gate of the first reset transistor T3 of the (n+2)th row sub-pixel unit 301, and the second signal output terminal WR(n+3) of the (n+2)th stage provides a control signal to the gate of the first reset transistor T3 of the (n+2)th row sub-pixel unit 301.

[0045] Right now Figure 3 The first signal output terminal REF(n) of the nth stage in the structure provides a control signal for the gate of the first reset transistor T3 of the nth row sub-pixel unit 301, and also provides a control signal for the gate of the second reset transistor T4 of the (n+2)th row sub-pixel unit 301. This enables one signal output terminal of the gate driving circuit 100 to provide two different control signals to the pixel circuit 20, simplifying the structure of the gate driving circuit 100.

[0046] This application simplifies the structure of the gate drive circuit 100 and achieves a narrow bezel design by removing a gate drive unit connected to the gate of the second reset transistor, and by using the first signal output terminal REF(n) of the b-th stage of the gate drive circuit 100 to provide the control signal required by the first reset transistor T3, and the first signal output terminal REF(n) of the c-th stage to provide the control signal required by the second reset transistor T4.

[0047] Please see Figure 4The gate drive unit 10 of the nth stage may include a pull-up control unit 110, a pull-up unit 120, a pull-down unit 130, a pull-down sustaining unit 140 and a compensation unit 170, all connected to the first node Q. The pull-up control unit 110 is used to pull up the potential of the first node Q. The pull-up unit 120 is used to pull up the potential of the first signal output terminal REF(n) and the second signal output terminal WR(n). The pull-down unit 130 is used to pull down the potential of the first node Q. The pull-down sustaining unit 140 is used to maintain the low potential of the first node Q.

[0048] Please see Figure 4 The pull-up control unit 110 includes a first pull-up control transistor T11 and a second pull-up control transistor T12. The first electrode of the first pull-up control transistor T11 is connected to the second high-potential line Vgh2. The second electrode of the first pull-up control transistor T11 and the first electrode of the second pull-up control transistor T12 are connected. The second electrode of the second pull-up control transistor T12 is connected to the first node Q. The gate of the first pull-up control transistor T11 and the gate of the second pull-up control transistor T12 are connected to the third-level signal transmission line Cout-PU3.

[0049] Meanwhile, the pull-up control unit 110 may also include a third pull-up control transistor T13 and a fourth pull-up control transistor T14. The gates of the third pull-up control transistor T13 and the fourth pull-up control transistor T14 are connected to the second high-potential line Vgh2. The first electrode of the third pull-up control transistor T13 is connected to the first electrode of the second pull-up control transistor T12. The second electrode of the third pull-up control transistor T13 is connected to the first electrode of the fourth pull-up control transistor T14. The second electrode of the fourth pull-up control transistor T14 is connected to the third-stage signal transmission line Cout-PU3.

[0050] It should be noted that the first pull-up control transistor T11 and the second pull-up control transistor T12 are configured to reduce the leakage current in the pull-up control unit 110. The gate of the third pull-up control transistor T13 and the fourth pull-up control transistor T14 are configured so that when the third stage signal line Cout-PU3 outputs a low level, the second electrode of the first pull-up control transistor T11 and the first electrode of the second pull-up control transistor T12 are kept at a high potential, preventing the first pull-up control transistor T11 from turning on and thus pulling the potential of the first node Q high.

[0051] In this embodiment, the stage transmission signal output by the third stage transmission signal line Cout-PU3 turns on the first pull-up control transistor T11, the second pull-up control transistor T12, the third pull-up control transistor T13 and the fourth pull-up control transistor T14, and the high level output by the second high potential line Vgh2 pulls up the potential of the first node Q, while charging the second storage capacitor C2 in the pull-up unit 120.

[0052] Please see Figure 4 The pull-up unit 120 includes a first pull-up transistor T21, a second pull-up transistor T22, a third pull-up transistor T23, and a second storage capacitor C2. The first electrode of the first pull-up transistor T21 is connected to the first clock signal line CKa, and the second electrode of the first pull-up transistor T21 is connected to the stage transmission signal terminal Cout(n). The first electrode of the second pull-up transistor T22 is connected to the second clock signal line CKb, and the second electrode of the second pull-up transistor T22 is connected to the first signal output terminal REF(n). The first electrode of the third pull-up transistor T23 is connected to the third clock signal line CKc, and the second electrode of the third pull-up transistor T23 is connected to the second signal output terminal WR(n). The gates of the first pull-up transistor T21, the second pull-up transistor T22, and the third pull-up transistor T23 are connected to the first node Q. The first plate of the second storage capacitor C2 is connected to the first node Q, and the second plate of the second storage capacitor C2 is connected to the stage transmission signal terminal Cout(n).

[0053] In this embodiment, the cascading signal terminal Cout(n) transmits the cascading signal to the cascading signal line of this application, and the signal output terminal is used to output the control signal.

[0054] In this embodiment, the high potential of the first node Q turns on the first pull-up transistor T21, the second pull-up transistor T22, and the third pull-up transistor T23, and the second storage capacitor C2 discharges to maintain the high potential of the first node Q. The first clock signal line CKa outputs a stage transmission signal to the stage transmission signal terminal Cout(n) through the first pull-up transistor T21. The second clock signal line CKb outputs a first control signal to the first signal output terminal REF(n) through the second pull-up transistor T22. The third clock signal line CKc outputs a second control signal to the second signal output terminal WR(n) through the third pull-up transistor T23.

[0055] Please see Figure 4 The gate drive unit 10 also includes a leakage protection unit 150 connected to the first node Q. The output terminal N(n) of the leakage protection unit 150 is connected to the pull-down unit 130 and the pull-down sustaining unit 140.

[0056] The leakage protection unit 150 includes a first leakage protection transistor T71 and a second leakage protection transistor T72. The first electrode of the first leakage protection transistor T71 is connected to the first high potential line Vgh1, the second electrode of the first leakage protection transistor T71 is connected to the first electrode of the second leakage protection transistor T72, the second electrode of the second leakage protection transistor T72 is connected to the output terminal N(n) of the leakage protection unit 150, and the gate of the first leakage protection transistor T71 and the gate of the second leakage protection transistor T72 are connected to the first node Q.

[0057] In this embodiment, the high potential of the first node Q turns on the first leakage protection transistor T71 and the second leakage protection transistor T72, and the first high potential line Vgh1 outputs a high level to the output terminal N(n) of the leakage protection unit 150 through the first leakage protection transistor T71 and the second leakage protection transistor T72.

[0058] Please see Figure 4 The pull-down unit 130 includes a first pull-down transistor T41 and a second pull-down transistor T42. The gate of the first pull-down transistor T41 and the gate of the second pull-down transistor T42 are connected to the first stage signal transmission line Cout-PU1. The first electrode of the first pull-down transistor T41 is connected to the first node Q. The second electrode of the first pull-down transistor T41 and the first electrode of the second pull-down transistor T42 are connected to the output terminal N(n) of the leakage protection unit 150. The second electrode of the second pull-down transistor T42 is connected to the first low potential line Vgl1.

[0059] In this embodiment, the first-stage signal line Cout-PU1 outputs a high potential to the gate of the first pull-down transistor T41 and the gate of the second pull-down transistor T42 to turn on the first pull-down transistor T41 and the second pull-down transistor T42. The first node Q is connected to the first low potential line Vgl1 through the first pull-down transistor T41 and the second pull-down transistor T42. The first low potential line Vgl1 pulls the potential of the first node Q down, and the first pull-up transistor T21 and the second pull-up transistor T22 are turned off.

[0060] Please see Figure 4 The pull-down sustaining unit 140 includes a first pull-down sustaining transistor T31, a second pull-down sustaining transistor T32, a third pull-down sustaining transistor T43, a fourth pull-down sustaining transistor T44, and a fifth pull-down sustaining transistor T33.

[0061] In this embodiment, the first electrode of the first pull-down sustaining transistor T31 is connected to the stage signal terminal Cout(n), the second electrode of the first pull-down sustaining transistor T31 is connected to the first low potential line Vgl1, the first electrode of the second pull-down sustaining transistor T32 is connected to the first signal output terminal REF(n), and the second electrode of the second pull-down sustaining transistor T32 is connected to the second low potential line Vgl2; the first electrode of the fifth pull-down sustaining transistor T33 is connected to the second signal output terminal WR(n), and the second electrode of the fifth pull-down sustaining transistor T33 is connected to the second low potential line Vgl2. The first electrode of the third pull-down sustaining transistor T43 is connected to the first node Q. The second electrode of the third pull-down sustaining transistor T43 and the first electrode of the fourth pull-down sustaining transistor T44 are connected to the output terminal N(n) of the leakage protection unit 150. The second electrode of the fourth pull-down sustaining transistor T44 is connected to the first low potential line Vgl1. The gates of the first pull-down sustaining transistor T31, the second pull-down sustaining transistor T32, the third pull-down sustaining transistor T43, the fourth pull-down sustaining transistor T44, and the fifth pull-down sustaining transistor T33 are all connected to the third node G.

[0062] Please see Figure 4 The gate drive unit 10 also includes an inverter 160 connected to the pull-down sustaining unit 140 at the third node G. The inverter 160 is used to invert the potentials of the first node Q and the third node G. The inverter 160 includes a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53, a fourth inverting transistor T54, a fifth inverting transistor T55, and a sixth inverting transistor T56.

[0063] In this embodiment, the first electrode of the first inverter transistor T51, the gate of the first inverter transistor T51, the gate of the second inverter transistor T52, and the first electrode of the fourth inverter transistor T54 are connected to the low-frequency clock signal line LC. The second electrode of the first inverter transistor T51 is connected to the first electrode of the second inverter transistor T52. The second electrode of the second inverter transistor T52 is connected to the first electrode of the third inverter transistor T53 and the gate of the fourth inverter transistor T54. The second electrode of the third inverter transistor T53 is connected to the first low-potential line Vgl1. The second electrode of the fourth inverter transistor T54, the first electrode of the fifth inverter transistor T55, and the first electrode of the sixth inverter transistor T56 are connected to the second node P. The second electrodes of the fifth inverter transistor T55 and the sixth inverter transistor T56 are connected to the first low-potential line Vgl1. The gates of the third inverter transistor T53 and the fifth inverter transistor T55 are connected to the first node Q. The gate of the sixth inverter transistor T56 is connected to the second-stage transmission signal line Cout-PU2.

[0064] In this embodiment, the low-frequency clock signal line LC outputs a high level to the first electrode of the first inverting transistor T51, the gate of the first inverting transistor T51, and the gate of the second inverting transistor T52, so as to turn on the first inverting transistor T51 and the second inverting transistor T52. At the same time, the high level transmitted by the low-frequency clock signal line LC is transmitted to the first electrode and the gate of the fourth inverting transistor T54, and the fourth inverting transistor T54 is turned on. The high level transmitted by the low-frequency clock signal line LC is transmitted to the third node G, and the potential of the third node G is pulled up to a high level.

[0065] When the third node G is high, the first pull-down sustaining transistor T31, the second pull-down sustaining transistor T32, the third pull-down sustaining transistor T43, the fourth pull-down sustaining transistor T44, and the fifth pull-down sustaining transistor T33 are all turned on. The stage transmission signal terminal Cout(n) is connected to the first low potential line Vgl1 through the first pull-down sustaining transistor T31. The first signal output terminal REF(n) is connected to the second low potential line Vgl2 through the second pull-down sustaining transistor T32. The second signal output terminal WR(n) is connected to the second low potential line Vgl2 through the fifth pull-down sustaining transistor T33. The stage transmission signal terminal Cout(n), the first signal output terminal REF(n), and the second signal output terminal WR(n) output a low level. The first node Q is connected to the first low potential line Vgl1 through the third pull-down sustaining transistor T43 and the fourth pull-down sustaining transistor T44, maintaining the potential of the first node Q at a low potential.

[0066] It should be noted that only one of the first inverting transistor T51 and the second inverting transistor T52 can be provided. The provision of the first inverting transistor T51 and the second inverting transistor T52 can reduce leakage current. The sixth inverting transistor T56 mainly serves as feedback and does not need to be part of the inverter 160.

[0067] Please see Figure 4 The gate drive unit 10 also includes a global reset unit 170 connected to the first node Q, used to pull the potential of the first node Q low.

[0068] In this embodiment, the global reset unit 170 includes a first reference transistor T45 and a second reference transistor T46. The first electrode of the first reference transistor T45 is connected to the first node Q. The second electrode of the first reference transistor T45 and the first electrode of the second reference transistor T46 are connected to the output terminal N(n) of the leakage protection unit 150. The second electrode of the second reference transistor T46 is connected to the first low potential line Vgl1. The gates of the first reference transistor T45 and the second reference transistor T46 are connected to the control signal line VST.

[0069] In this embodiment, the control signal line VST outputs a high level to the gate of the first reference transistor T45 and the gate of the second reference transistor T46, the first reference transistor T45 and the second reference transistor T46 are turned on, the first node Q is connected to the first low potential line Vgl1 through the first reference transistor T45 and the second reference transistor T46, and the potential of the first node Q is pulled low.

[0070] It should be noted that the global reset unit 170 typically resets the potential of the first node Q when the gate drive unit 10 stops working or starts working.

[0071] It should be noted that the potential of the second low-potential line Vgl2 can be greater than the potential of the first low-potential line Vgl1; for example, the potential of the second low-potential line Vgl2 can be -8V, and the potential of the first low-potential line Vgl1 can be -10V. In this case, the potential of the first node Q is pulled down to -8V, and the potentials of the first signal output terminal REF(n) and the second signal output terminal WR(n) are pulled down to -10V. The first node Q is the gate of the second pull-up transistor T22 and the third pull-up transistor T23, and the first signal output terminal REF(n)... Since the source terminal of the second pull-up transistor T22 is the source terminal and the second signal output terminal WR(n) is the source terminal of the third pull-up transistor T23, the potential difference between the gate and source of the second pull-up transistor T22 is -2V, which is much smaller than the threshold voltage of the second pull-up transistor T22. Therefore, the second pull-up transistor T22 will be completely turned off to prevent it from being turned on and outputting a control signal when the row is not selected. Similarly, the third pull-up transistor T23 will be completely turned off to prevent it from being turned on and outputting a control signal when the row is not selected.

[0072] It should be noted that the voltages of the first low potential line Vgl1 and the second low potential line Vgl2 can also be the same, that is, the first low potential line Vgl1 and the second low potential line Vgl2 can be the same signal line to simplify the arrangement of signal lines.

[0073] It should be noted that the potentials of the first high potential line Vgh1 and the second high potential line Vgh2 in this application can be the same, that is, the first high potential line Vgh1 and the second high potential line Vgh2 can be the same signal line to simplify the arrangement of signal lines.

[0074] It should be noted that the second-stage signal transmission line Cout-PU2 and the third-stage signal transmission line Cout-PU3 can be the stage transmission signal output from the intermediate stage signal transmission terminal Cout(n) of a previous stage, such as the stage transmission signal output from the stage transmission signal terminal Cout(n) of the gate drive circuit 100 of the nx stage, where x can be 2; the first-stage signal transmission line Cout-PU1 can be the stage transmission signal output from the intermediate stage signal transmission terminal Cout(n) of a subsequent stage, such as the stage transmission signal output from the stage transmission signal terminal Cout(n) of the gate drive circuit 100 of the n+y stage, where y can be 5.

[0075] It should be noted that the second electrode of the first pull-down transistor T41 and the first electrode of the second pull-down transistor T42 in the pull-down unit 130, the second electrode of the first reference transistor T45 and the first electrode of the second reference transistor T46 in the global reset unit 170, and the second electrode of the third pull-down sustaining transistor T43 and the first electrode of the fourth pull-down sustaining transistor T44 in the pull-down sustaining unit 140 are all connected to the output terminal N(n) of the leakage protection unit 150. Since the output terminal N(n) of the leakage protection unit 150 outputs a high level, even if the threshold voltage is negatively biased, the voltage difference between the gate voltage and the source voltage can still be guaranteed to be less than the threshold voltage. Therefore, the potential of the first node Q can be prevented from leaking through the abnormal turn-on of the transistors in the pull-down unit 130, the pull-down sustaining unit 140 and the global reset unit 170, thus ensuring the stability of the potential of the first node Q.

[0076] It should be noted that, Figure 4 N(n) in the diagram includes multiple connection points, but in reality, the multiple connection points of N(n) are a single point. For ease of illustration and description, N(n) is divided into multiple connection points, and in reality, the multiple connection points are the same single point.

[0077] It should be noted that, Figure 4 The point marked with a black dot indicates that two intersecting lines are connected at that point, but... Figure 4 Not all connection points are marked; the actual connections are described in the following embodiments.

[0078] It should be noted that, Figure 4 The structure of the gate drive unit in this application is only one of the examples listed in this application. Any gate drive unit that outputs two different control signals at the same stage is applicable to this application.

[0079] Please see Figure 5 and Figure 6 , Figure 5 for Figure 4 Timing diagrams for the first clock signal line CKa, the second clock signal line CKb, and the third clock signal line CKc. Figure 6 for Figure 2Timing diagram of the switch signal terminal Gn, the first reset terminal Ref, and the second reset terminal Ini.

[0080] exist Figure 4 In the structure, the first clock signal line CKa is connected to the stage transmission signal terminal, the second clock signal line CKb is connected to the first signal output terminal REF(n), and the third clock signal line CKc is connected to the second signal output terminal WR(n). The first signal output terminal REF(n) in the pixel circuit 20 is connected to the second clock signal line CKb, which means that the first control signal output by the second clock signal line CKb is shared by the first reset transistor T3 and the second reset transistor T4, and the original wide pulse drive circuit is removed. Therefore, the second clock signal line CKb needs to output a wide pulse signal, that is, the pulse width of the clock signal output by the second clock signal line CKb needs to be greater than the pulse width of the clock signals output by the first clock signal line CKa and the second clock signal line CKb.

[0081] Secondly, the third clock signal line CKc is connected to the second signal output terminal WR(n), which means that the clock signal output by the third clock signal line CKc is received by the switching transistor T2. Since the clock signal only needs to turn on the switching transistor T2, the pulse width of the clock signal output by the third clock signal line CKc is the smallest. The pulse width of the clock signal output by the third clock signal line CKc is less than the pulse width of the clock signal output by the first clock signal line CKa, that is, the pulse width of the first control signal is greater than the pulse width of the second control signal.

[0082] Since the input of the first control signal is to reset the potential of the first reset node M1 and the second reset node M2 ​​in the pixel circuit 20, and since the first reset node M1 and the second reset node M2 ​​receive the first control signal with a certain phase difference, in order to ensure the accuracy of the potential reset in the first reset node M1 and the second reset node M2, the first reset node M1 and the second reset node M2 ​​usually need to be reset simultaneously.

[0083] In the display panel 200 of this application, within one scan frame of the gate driving circuit 100, the start time of the first control signal of the b-th stage is located between the start time and the end time of the first control signal of the c-th stage, and the start time of the second control signal of the a-th stage is located after the end time of the first control signal of the b-th stage.

[0084] For example, in Figure 6In the structure, the second control signal of the a-th stage received by the switch signal terminal Gn can be the second control signal of the (n+1)-th stage, the first control signal of the b-th stage received by the first reset terminal Ref can be the first control signal of the n-th stage, and the first control signal of the c-th stage received by the second reset terminal Ini can be the first control signal of the (n-2)-th stage. The start time of the first control signal of the second reset terminal Ini is t1 and the end time is t2, the start time of the first control signal of the first reset terminal Ref is t3 and the end time is t4, the start time of the second control signal of the switch signal terminal Gn is t5 and the end time is t6. The pulse width of the first control signal of the second reset terminal Ini and the first control signal of the first reset terminal Ref has a first interval segment t23, that is, the interval segment between time t3 and time t2. The first interval segment t23 is the time period during which the first reset node M1 and the second reset node M2 ​​are reset together.

[0085] In this embodiment, since the duration of the first interval t23 is positively correlated with the accuracy of the operating current in the pixel circuit 20, the duration of the first interval t23 should be as long as possible. At the same time, the duration of the first interval t23 needs to be greater than the pulse width of the second control signal. For example, the duration of the first interval t23 can be twice the pulse width of the second control signal, so that the potentials of the first reset node M1 and the second reset node M2 ​​can be reset to the reference potential.

[0086] In this embodiment, the time interval between the start time t5 of the second control signal of level a and the end time t4 of the first control signal of level b is the second interval t45, that is, the interval between time t4 and time t5. The duration of the second interval t45 is less than or equal to the pulse width of the second control signal.

[0087] In the pixel circuit 20 of this application, after the potential of the first reset node M1 is reset, the potentials of the first reset node M1 and the second reset node M2 ​​are both at the ideal reference potential. At this time, the optimal time is to input the second control signal to the switch signal terminal Gn. Since the pulse width of the second control signal is small, the duration of the second interval t45 of this application can be equal to the pulse width of the second control signal.

[0088] In this embodiment, the number of gate driving units 10 can be greater than the number of sub-pixel rows 310.

[0089] For example, in Figure 7In the structure, the gate driving circuit 100 includes a cascaded first virtual driving unit 101, a second virtual driving unit 102, a third virtual driving unit 103, and n gate driving units 10 disposed between the second virtual driving unit 102 and the third virtual driving unit 103. The first virtual driving unit 101, the second virtual driving unit 102, and the third virtual driving unit 103 all belong to the gate driving unit 10, but do not correspond to the sub-pixel row 310. For example, the first virtual driving unit 101 is the first stage of the gate driving circuit 100, the second virtual driving unit 102 is the second stage of the gate driving circuit 100, and the third virtual driving unit 103 is the last stage of the gate driving circuit 100. The n cascaded gate driving units 10 in the middle correspond to the n sub-pixel rows 310.

[0090] In this embodiment, the first signal output terminal REF(d1) of the first virtual driving unit 101 is connected to the gate of the second reset transistor T4 of the pixel unit 20 of the first sub-pixel row 310, the first signal output terminal REF(d2) of the second virtual driving unit 102 is connected to the gate of the second reset transistor T4 of the pixel circuit 20 of the second sub-pixel row 310, and the second signal output terminal WR(d3) of the third virtual driving unit 103 is connected to the gate of the first reset transistor T3 of the pixel circuit 20 of the nth sub-pixel row 310.

[0091] For example, the first signal output terminal REF(d1) of the first virtual driving unit 101 provides a control signal to the gate of the second reset transistor T4 of the first row sub-pixel unit 301; the first signal output terminal REF(1) of the first-stage gate driving unit 10 provides a control signal to the gate of the first reset transistor T3 of the first row sub-pixel unit 301; the second signal output terminal WR(2) of the second-stage gate driving unit 10 provides a control signal to the gate of the first reset transistor T3 of the first row sub-pixel unit 301; the first signal output terminal REF(d2) of the second virtual driving unit 102 provides a control signal to the gate of the second reset transistor T4 of the second row sub-pixel unit 301; the first signal output terminal REF(d2) of the second-stage gate driving unit 10 provides a control signal to the gate of the second reset transistor T4 of the second row sub-pixel unit 301; the second ... The gate of the first reset transistor T3 of the sub-pixel unit 301 provides a control signal, and the second signal output terminal WR(3) of the third-level gate driving unit 10 provides a control signal to the gate of the first reset transistor T3 of the third row sub-pixel unit 301; the first signal output terminal REF(n-2) of the (n-2)-level gate driving unit 10 provides a control signal to the gate of the second reset transistor T4 of the n-row sub-pixel unit 301, the first signal output terminal REF(n) of the n-level gate driving unit 10 provides a control signal to the gate of the first reset transistor T3 of the n-row sub-pixel unit 301, and the second signal output terminal WR(d3) of the third virtual driving unit 103 provides a control signal to the gate of the first reset transistor T3 of the n-row sub-pixel unit 301.

[0092] That is, the first virtual driving unit 101 provides a control signal only to the gate of the second reset transistor T4 of the first row sub-pixel unit 301, the second virtual driving unit 102 provides a control signal only to the gate of the second reset transistor T4 of the second row sub-pixel unit 301, and the third virtual driving unit 103 provides a control signal only to the gate of the first reset transistor T3 of the nth row sub-pixel unit 301.

[0093] It should be noted that, Figure 7 This is only one embodiment of the present application, as long as the timing received by the switch signal terminal Gn, the first reset terminal Ref, and the second reset terminal Ini in the pixel driving circuit meets the requirements... Figure 5 The timing diagram in the image is sufficient.

[0094] This application also proposes a display device, which includes a terminal body and the aforementioned display panel, wherein the terminal body and the display panel are integrated into one unit. The terminal body may be a circuit board or other components bonded to the display panel, or a cover plate or other components covering the display panel. The display device may include electronic devices such as mobile phones, televisions, and laptops.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0096] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The device includes a display unit and a gate driving circuit located on one side of the display unit. The display unit includes a plurality of sub-pixel rows, each sub-pixel row includes a plurality of sub-pixel units, and each sub-pixel unit is provided with a pixel circuit. The pixel circuit includes a switching transistor, a driving transistor, a first reset transistor, and a second reset transistor. The switching transistor and the driving transistor are connected to a first reset node. The first reset transistor and the driving transistor are connected to the first reset node. The second reset transistor and the driving transistor are connected to a second reset node. The gate driving circuit includes multiple cascaded gate driving units. Each gate driving unit includes a first signal output terminal and a second signal output terminal. The gate of the switching transistor of the pixel circuit of the b-th sub-pixel row is connected to the second signal output terminal of the a-th stage. The gate of the first reset transistor of the pixel circuit of the b-th sub-pixel row is connected to the first signal output terminal of the b-th stage. The gate of the second reset transistor of the pixel circuit of the b-th sub-pixel row is connected to the first signal output terminal of the c-th stage. a is greater than b, b is greater than c, and a, b, and c are positive integers. Wherein, the first signal output terminal outputs a first control signal, and the second signal output terminal outputs a second control signal; within one scan frame of the gate driving circuit, the start time of the first control signal of the b-th stage is located between the start time and the end time of the first control signal of the c-th stage, and the start time of the second control signal of the a-th stage is located after the end time of the first control signal of the b-th stage.

2. The display panel as described in claim 1, characterized in that, The pulse width of the first control signal is greater than the pulse width of the second control signal.

3. The display panel as described in claim 1, characterized in that, The time interval between the start time of the first control signal at level b and the end time of the first control signal at level c is a first interval segment, and the duration of the first interval segment is greater than the pulse width of the second control signal.

4. The display panel as described in claim 1, characterized in that, The plurality of gate driving units further include a first virtual driving unit and a second virtual driving unit located before the first-stage gate driving unit; The first signal output terminal of the first virtual driving unit is connected to the gate of the second reset transistor of the pixel unit of the first sub-pixel row, and the first signal output terminal of the second virtual driving unit is connected to the gate of the second reset transistor of the pixel circuit of the second sub-pixel row.

5. The display panel as described in claim 1, characterized in that, The time interval between the start time of the second control signal at level a and the end time of the first control signal at level b is the second interval segment, and the duration of the second interval segment is less than or equal to the pulse width of the second control signal.

6. The display panel as described in any one of claims 1 to 5, characterized in that, The gate driving unit includes: The pull-up control unit, connected to the first node, is used to pull the potential of the first node high; A pull-up unit, one end of which is connected to the first node, and the other end of which is connected to the first signal output terminal and the second signal output terminal. The pull-up unit is used to pull up the potential of the first signal output terminal and the second signal output terminal. A pull-down unit, connected to the first node, is used to pull the potential of the first node low; A pull-down sustaining unit is provided, one end of which is connected to the first node, and the other end of which is connected to the first signal output terminal and the second signal output terminal. The pull-down sustaining unit is used to maintain the low potential of the first node and pull down the potential of the first signal output terminal and the second signal output terminal.

7. The display panel as described in claim 6, characterized in that, The first node is connected to the first low potential line through the pull-down unit, and the first signal output terminal and the second signal output terminal are connected to the second low potential line through the pull-down sustaining unit; The potential of the first low-potential line is less than the potential of the second low-potential line.

8. The display panel as described in claim 6, characterized in that, The pull-up unit includes a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor; In this configuration, the first pull-up transistor, the second pull-up transistor, and the third pull-up transistor are all connected to the first node. The first electrode of the first pull-up transistor is connected to the first clock signal line, the second electrode of the first pull-up transistor is connected to the cascade signal terminal, the first electrode of the second pull-up transistor is connected to the second clock signal line, the second electrode of the second pull-up transistor is connected to the first signal output terminal, the first electrode of the third pull-up transistor is connected to the third clock signal line, and the second electrode of the third pull-up transistor is connected to the second signal output terminal. The pulse width of the clock signal output from the first clock signal line is less than the pulse width of the clock signal output from the second clock signal line, and the pulse width of the clock signal output from the third clock signal line is less than the pulse width of the clock signal output from the first clock signal line.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 8.

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