3D NAND storage devices and their control methods

Abstract

The present disclosure provides a method of controlling a 3D NAND memory using a read operation. The method can include increasing a voltage of a plurality of top select gates relative to a first reference voltage level during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage of a plurality of word lines relative to a second reference voltage level during the pre-pulse period. The method can also include decreasing a voltage of a bit line relative to the first reference voltage level during the pre-pulse period. The method can also include not applying a voltage change to a bottom select gate during the pre-pulse period.

Description

Technical Field

[0001] In general, this disclosure relates to the field of semiconductor technology, and more specifically, to methods for controlling 3D NAND memory. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] In 3D NAND flash memory, many layers of memory cells can be stacked vertically, significantly increasing the storage density per unit area. Vertically stacked cells form memory strings, with channels connecting the cells within each string. Each cell is addressed via word lines and bit lines. Data (i.e., logical state) in cells across an entire memory page sharing the same word line can be read or programmed simultaneously. However, due to this aggressive scaling, reliability can be a concern with 3D NAND flash memory. Summary of the Invention

[0004] This disclosure describes embodiments of methods and systems for data protection in storage devices.

[0005] In some embodiments, a method may include controlling a memory device using a read operation. The method may include: during a pre-pulse period of the read operation preceding a read phase of the read operation, increasing the voltage of a plurality of top select gates relative to a first reference voltage level. The method may further include: during the pre-pulse period, increasing the voltage of a plurality of word lines relative to a second reference voltage level. The method may further include: during the pre-pulse period, decreasing the voltage of bit lines relative to the first reference voltage level. The method may further include: during the pre-pulse period, not applying a voltage change to the bottom select gate.

[0006] In some embodiments, the read operation can be a first read operation. The prepulse period can be a first prepulse period. A second prepulse period can be defined for the second read operation. The second read operation can differ from the first read operation in that the second read operation does not perform a voltage reduction on the bit line. The method may further include setting the first prepulse period to be shorter than the second prepulse period.

[0007] In some embodiments, reducing the voltage of the bit line may include reducing the voltage of the bit line by more than 0.1 volts and less than about 4.0 volts, more than 0.5 volts and less than about 3.0 volts, or more than 1.0 volts and less than about 2.5 volts.

[0008] In some embodiments, the method may further include: increasing the voltage of the bit line to exceed the first reference voltage level during the read period. The method may further include: increasing the voltage of the bottom select gate relative to the first reference voltage level during the read period.

[0009] In some embodiments, the method may further include: during the read period, setting the voltage of a selected word line among the plurality of word lines to a read voltage relative to a second reference voltage level. The bit line is associated with the selected word line among the plurality of word lines. The method may further include: reading from a memory cell associated with the selected word line among the plurality of word lines.

[0010] In some embodiments, the method may further include: reducing the voltage of an unselected top select gate among the top select gates during the read period. The method may further include: increasing the voltage of a word line adjacent to a selected word line among the plurality of word lines during the read period.

[0011] In some embodiments, the storage device may be a 3D NAND storage device. After the storage cell is programmed, the read operation can be performed to verify the data stored in the storage cell of the 3D NAND storage device.

[0012] In some embodiments, a memory device may use a read operation method that reduces overall read time. The memory device may include memory cells capable of storing data. The memory device may also include a memory controller capable of controlling the memory device. The memory device may further include a non-transitory computer-readable medium storing instructions thereon, which, when executed by the memory controller, cause the memory controller to perform a read operation. The read operation may further include: increasing the voltage of a plurality of top select gates relative to a first reference voltage level during a pre-pulse period preceding the read period of the read operation. The read operation may further include: increasing the voltage of a plurality of word lines relative to a second reference voltage level during the pre-pulse period. The read operation may further include: decreasing the voltage of bit lines relative to the first reference voltage level during the pre-pulse period. The read operation may further include: not applying a voltage change to the bottom select gate during the pre-pulse period.

[0013] In some embodiments of the storage device, the read operation may be a first pre-pulse period. The pre-pulse period may be a first pre-pulse period. A second pre-pulse period may be defined for a second read operation. The second read operation may differ from the first read operation in that the second read operation does not perform a voltage reduction on the bit line. The first read operation may further include setting the first pre-pulse period to be shorter than the second pre-pulse period.

[0014] In some embodiments of the memory device, reducing the voltage of the bit line may include reducing the voltage of the bit line by more than 0.1 volts and less than about 4.0 volts, more than 0.5 volts and less than about 3.0 volts, or more than 1.0 volts and less than about 2.5 volts.

[0015] In some embodiments of the memory device, the read operation may further include: increasing the voltage of the bit line to exceed the first reference voltage level during the read period. The read operation may also include: increasing the voltage of the bottom select gate relative to the first reference voltage level during the read period.

[0016] In some embodiments of the storage device, the read operation may further include: during the read period, setting the voltage of a selected word line among the plurality of word lines to a read voltage relative to the second reference voltage level. The bit line is associated with the selected word line among the plurality of word lines. The read operation may further include: reading from a memory cell associated with the selected word line among the plurality of word lines.

[0017] In some embodiments of the memory device, the read operation may further include: reducing the voltage of the unselected top select gate in the top select gate during the read period. The read operation may further include: increasing the voltage of the word line adjacent to the selected word line among the plurality of word lines during the read period.

[0018] In some embodiments of the storage device, the storage device may be a 3D NAND storage device. After the storage cells are programmed, the read operation can be performed to verify the data stored in the storage cells of the 3D NAND storage device.

[0019] In some embodiments, a storage system may use a read operation method to reduce overall read time. The storage system may include a storage device. The storage device may include storage cells capable of storing data. The storage device may also include a memory controller capable of controlling the storage device. The storage device may further include a non-transitory computer-readable medium storing instructions thereon, which, when executed by the memory controller, cause the memory controller to perform a read operation. The read operation may include: increasing the voltage of a plurality of top select gates relative to a first reference voltage level during a pre-pulse period preceding a read period of the read operation. The read operation may also include: increasing the voltage of a plurality of word lines relative to a second reference voltage level during the pre-pulse period. The read operation may further include: decreasing the voltage of bit lines relative to the first reference voltage level during the pre-pulse period. The read operation may also include: not applying a voltage change to the bottom select gate during the pre-pulse period.

[0020] In some embodiments of the storage system, the read operation may be a first read operation. The pre-pulse period may be a first pre-pulse period. A second pre-pulse period may be defined for the second read operation. The second read operation may differ from the first read operation in that the second read operation does not perform a voltage reduction on the bit line. The first read operation may further include setting the first pre-pulse period to be shorter than the second pre-pulse period.

[0021] In some embodiments of the storage system, reducing the voltage of the bit line may include reducing the voltage of the bit line by more than 0.1 volts and less than about 4.0 volts, more than 0.5 volts and less than about 3.0 volts, or more than 1.0 volts and less than about 2.5 volts.

[0022] In some embodiments of the memory system, the read operation may further include: increasing the voltage of the bit line to exceed the first reference voltage level during the read period. The read operation may also include: increasing the voltage of the bottom select gate relative to the first reference voltage level during the read period.

[0023] In some embodiments of the storage system, the read operation may further include: during the read period, setting the voltage of a selected word line among the plurality of word lines to a read voltage relative to the second reference voltage level. The bit line is associated with the selected word line among the plurality of word lines. The read operation may further include: reading from a memory cell associated with the selected word line among the plurality of word lines.

[0024] In some embodiments of the storage system, the read operation may further include: reducing the voltage to the unselected top select gate among the top select gates during the read period. The read operation may further include: increasing the voltage of the word line adjacent to the selected word line among the plurality of word lines during the read period.

[0025] Other aspects of this disclosure can be understood by those skilled in the art based on the specification, claims, and drawings. Attached Figure Description

[0026] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate embodiments of the present disclosure and, together with the following description, are intended to further explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0027] Figure 1 A system having one or more memory chips is shown according to some embodiments.

[0028] Figure 2A A memory card according to some embodiments is shown.

[0029] Figure 2B A solid-state driver according to some embodiments is shown.

[0030] Figure 3 A schematic diagram of a memory die according to some embodiments is shown.

[0031] Figure 4 A schematic diagram of a three-dimensional (3D) memory die according to some embodiments is shown.

[0032] Figure 5 A perspective view of a portion of a 3D memory structure according to some embodiments is shown.

[0033] Figure 6 The threshold voltage V of NAND flash memory according to some embodiments is shown. th distributed.

[0034] Figure 7 and Figure 8 A read operation method according to some embodiments is shown.

[0035] The features and advantages of this disclosure will become more apparent when considered in conjunction with the accompanying drawings, in which the same reference numerals throughout identify corresponding elements. In the drawings, similar reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The first appearance of an element in the drawing is indicated by the leftmost numeral in the corresponding reference numeral.

[0036] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0037] While specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0038] It should be noted that references to "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing these features, structures, or characteristics in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0039] Generally, terms can be understood at least partly based on their use in context. For example, the term "one or more," as used herein, can be used, at least partly based on context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage, at least partly based on context. Additionally, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather, at least partly based on context, alternatively allowing for the presence of other factors that are not necessarily explicitly described.

[0040] It should be readily understood that the meanings of “on,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes the meaning of “on” something with an intermediate feature or layer between them. Furthermore, “above” or “above” means not only “above” or “on top of” something, but also includes the meaning of “above” or “on top of” something without an intermediate feature or layer between them (i.e., directly on) something.

[0041] Furthermore, for ease of description illustrating the relationship between one element or feature and another element(s) or feature as shown in the figures, spatial relative terms such as “below,” “under,” “below,” “above,” “over,” etc., are used herein. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or processing. The apparatus may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptors used herein may be interpreted accordingly.

[0042] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and thus the bottom surface of the substrate is opposite to the top surface of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can comprise a wide variety of semiconducting materials, such as silicon, germanium, gallium arsenide, indium phosphide, and so on. Alternatively, the substrate can be made of nonconducting materials such as glass, plastic, or sapphire wafers.

[0043] As used herein, the term "layer" refers to a portion of material comprising a region having a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or its extent may be less than the extent of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure, with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may contain multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

[0044] In this disclosure, for ease of description, the term "tier" is used to refer to components that are substantially the same height in the vertical direction. For example, a word line and the underlying gate dielectric layer can be called a "tier", a word line and the underlying insulating layer can be called a "tier" together, word lines of substantially the same height can be called a "layer word line" or similar names, and so on.

[0045] As used herein, the term “nominal” refers to the expected or target value of a feature or parameter for a component or process step, set during the design phase of a product or process, and a range of values ​​higher and / or lower than the expected value. This range may be due to minor variations in manufacturing processes or tolerances. As used herein, the terms “approximately” or “about” indicate a given number of values ​​that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the terms “approximately” or “about” may indicate a given number of values ​​that vary within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0046] In this disclosure, the terms “horizontal / horizontally / laterally” refer to a lateral surface that is nominally parallel to the substrate, and the terms “vertical” or “perpendicularly” refer to a lateral surface that is nominally perpendicular to the substrate.

[0047] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a “memory string”, such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a direction perpendicular to the substrate.

[0048] Figure 1 A block diagram of an electronic system S1 according to some embodiments is shown. In some embodiments, the electronic system S1 may include a storage system 10. The electronic system S1 may be a mobile phone, desktop computer, laptop computer, tablet device, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The storage system 10 (e.g., a NAND storage system) may include a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3, ..., 25- n Each semiconductor memory chip 25 (hereinafter referred to as a "memory chip") may be a NAND chip (e.g., "flash memory", "NAND flash memory", or "NAND"). The storage system 10 can communicate with the host computer 15 via a memory controller 20, wherein the memory controller 20 can communicate via one or more memory channels 30-1, 30-2, 30-3, ..., 30- n Connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25- n In some embodiments, each memory chip 25 may be managed by the memory controller 20 via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n.

[0049] In some embodiments, host computer 15 may include a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host computer 15 may send data to be stored in storage system 10, and / or retrieve data from data stored in storage system 10.

[0050] In some embodiments, memory controller 20 can process I / O requests received from host computer 15, ensure data integrity and efficient storage, and manage memory chips 25. To perform these tasks, memory controller 20 can run firmware 21, which can be executed by one or more processors 22 (e.g., microcontroller units, CPUs) of memory controller 20. For example, memory controller 20 can run firmware 21 to map logical addresses (e.g., addresses used by the host associated with host data) to physical addresses (e.g., the actual location where the data is stored) in memory chip 25. Controller 20 also runs firmware 21 to manage defective memory blocks in memory chip 25, where firmware 21 can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. Controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) that can be used to store various metadata used by firmware 21. In some embodiments, memory controller 20 can also perform error recovery via error correction code (ECC) engine 29. ECC is used to detect and correct raw bit errors occurring within each memory chip 25.

[0051] In some embodiments, the memory channel 30 can provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 can select one of the memory chips 25 based on a chip enable signal.

[0052] In some embodiments, Figure 1 Each memory chip 25 may include one or more memory dies 100, wherein each memory die may be a 3D NAND memory.

[0053] In some embodiments, the memory controller 20 and one or more memory chips 25 can be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 10 can be implemented and packaged into different types of end electronic products. In one example, such as... Figure 2AAs shown, the memory controller 20 and a single memory chip 25 can be integrated into the memory card 26. The memory card 26 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a connector for connecting the memory card 26 to a host computer (e.g., ...). Figure 1 The memory card connector 24 is coupled to the host computer 15. In such a way... Figure 2B In another example shown, the memory controller 20 and multiple memory chips 25 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may also include a connection between the SSD 27 and a host computer (e.g., Figure 1 The host computer 15) is coupled with the SSD connector 28.

[0054] Figure 3 A top view of a memory die 100 according to some embodiments is shown. Figure 3 The example configuration shown is given as a non-limiting example, and it should be understood that the memory is scalable. In some embodiments, the memory die 100 may include one or more memory surfaces 101, each memory surface 101 may include multiple memory blocks 103. The same and concurrent operations may occur on each memory surface 101. The memory block 103 may be megabytes (MB) in size, which is the minimum size to perform an erase operation. The memory die 100 may include, for example, four memory surfaces 101. Each memory surface 101 may include, for example, six memory blocks 103. Each memory block 103 may include multiple memory cells, wherein each memory cell may be addressed by interconnects such as bit lines and word lines. Bit lines and word lines may be arranged vertically (e.g., arranged in rows and columns, respectively), forming a metal wire array. Figure 3 The directions of the bit lines and word lines are marked as "BL" and "WL". In this disclosure, memory block 103 is also referred to as a "memory array" or "array". A memory array is the core region of a memory device that performs storage functions.

[0055] In some embodiments, the memory die 100 may further include a peripheral region 105, a region surrounding the memory surface 101. The peripheral region 105 may include a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0056] In some embodiments, the arrangement of the storage surfaces 101 in the memory die 100 and Figure 3 The arrangement of memory blocks 103 in each storage surface 101 shown is merely an example and does not limit the scope of protection of this disclosure.

[0057] Figure 4 A schematic diagram of a memory die 100 according to some embodiments is shown. In some embodiments, the memory die 100 may include one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 may include a plurality of memory strings 212. Each memory string 212 includes a plurality of memory cells 340. Memory cells 340 sharing the same word line form memory pages 432. The memory string 212 may also include at least one field-effect transistor (e.g., MOSFET) at each end, which is controlled by a lower select gate (“LSG”) 332 and an upper select gate (“TSG”) 334, respectively. The lower select gate (“LSG”) may also be referred to as the bottom select gate (“BSG”). The drain terminal of the top select transistor 334-T may be connected to a bit line 341, while the source terminal of the lower select transistor 332-T may be connected to an array common source (“ACS”) 430. The ACS 430 may be shared by the memory strings 212 throughout the memory block, and the ACS 430 is also referred to as the common source line.

[0058] In some embodiments, the memory die 100 may further include peripheral circuitry, which may include a variety of digital, analog, and / or mixed-signal circuits to support the functionality of the memory block 103, such as a page buffer / sensor amplifier 50, a row decoder / word line driver 40, a column decoder / bit line driver 52, control circuitry 70, a voltage generator 65, and an input / output buffer 55. These circuits may include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0059] In some embodiments, memory block 103 may be coupled to row decoder / word line driver 40 via word line (“WL”) 333, lower select gate (“LSG”) 332, and upper select gate (“TSG”) 334. Memory block 103 may be coupled to page buffer / sensor amplifier 50 via bit line (“BL”) 341. Row decoder / word line driver 40 may select one of memory blocks 103 on memory die 100 in response to an X-path control signal provided by control circuitry 70. Row decoder / word line driver 40 may deliver a voltage from voltage generator 65 to word line according to the X-path control signal. During read and programming operations, row decoder / word line driver 40 may deliver read voltage V according to the X-path control signal received from control circuitry 70. read and programming voltage V pgm Transmitted to the selected word line and will be transmitted through voltage V pass Transmit to an unselected word line.

[0060] In some embodiments, the column decoder / bit line driver 52 can, based on the Y-path control signal received from the control circuit 70, disable the voltage V. inhibit The data is transmitted to the unselected location line, and the selected location line is connected to ground. In other words, the column decoder / bit line driver 52 can be configured to select or deselect one or more memory strings 212 according to the Y-path control signal from the control circuitry 70. The page buffer / sensor amplifier 50 can be configured to read and program (write) data from and to memory block 103 according to the Y-path control signal from the control circuitry 70. For example, the page buffer / sensor amplifier 50 can store a page of data to be programmed into a memory page 432. In another example, the page buffer / sensor amplifier 50 can perform a verification operation to ensure that data has been correctly programmed into each memory cell 340. In another example, during a read operation, the page buffer / sensor amplifier 50 can sense the current flowing through the bit line 341 (which reflects the logic state (i.e., data) of the memory cell 340) and amplify the small signal to a measurable amplification.

[0061] In some embodiments, the input / output buffer 55 can transmit I / O data from / to the page buffer / sensor amplifier 50, and transmit address ADDR or command CMD to the control circuitry 70. In some embodiments, the input / output buffer 55 can be used as a memory controller 20 (in... Figure 1 The interface between the memory die 100 on the memory chip 25 and the memory die 100 on the memory chip 25.

[0062] In some embodiments, control circuitry 70 can control page buffer / sensor amplifier 50 and row decoder / word line driver 40 in response to command CMD transmitted by input / output buffer 55. During programming operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to program selected memory cells. During read operations, control circuitry 70 can control row decoder / word line driver 40 and page buffer / sensor amplifier 50 to read selected memory cells. X-path control signals and Y-path control signals include row address X-ADDR and column address Y-ADDR, which can be used to locate selected memory cells in memory block 103. Row address X-ADDR can include page index PD, block index BD, and face index PL to identify memory page 432, memory block 103, and memory face 101, respectively. Figure 3 (In the middle). The column address Y-ADDR can identify a byte or a word of data in memory page 432.

[0063] In some embodiments, voltage generator 65, under the control of control circuitry 70, generates voltages to be supplied to word lines and bit lines. The voltage generated by voltage generator 65 includes the read voltage V. read Programming voltage V pgm Through voltage V pass Prohibited voltage V inhibit etc.

[0064] It should be noted that, in Figure 1 , 2A -2B and Figure 3-4 The arrangement of electronic components in the storage system 10 and memory die 100 is shown as a non-limiting example. In some embodiments, the storage system 10 and memory die 100 may have other layouts and may include other components. Figure 4 Components shown on the memory die 100 (e.g., control circuitry 70, I / O buffer 55) can be removed from the memory die 100 and used as independent electrical components in the storage system 10. Alternatively, they can be... Figure 4 Components on the memory die 100 shown (e.g., control circuitry 70, I / O buffer 55) can be moved to other components in the memory system 10. For example, a portion of the control circuitry 70 can be combined with the memory controller 20, or vice versa.

[0065] Figure 5 A perspective view of a 3D memory structure 500 according to some embodiments is shown. In some embodiments, the memory die 100 may be a 3D NAND memory, and the 3D memory structure 500 may be a portion of the memory die 100 (e.g., in...). Figure 3 (In region 108). The 3D memory structure 500 may include a stepped region 210 and a channel structure region 211. The channel structure region 211 may include multiple memory strings 212, each memory string including multiple stacked memory cells 340. The stepped region 210 may include a stepped structure.

[0066] In some embodiments, the 3D memory structure 500 may include a substrate 330, an insulating film 331 above the substrate 330, a lower select gate (LSG) layer 332 above the insulating film 331, and a plurality of control gate (also referred to as "word lines (WL)") layers 333 stacked on top of the LSG 332 to form a film stack 335 of alternating conductive and dielectric layers. For clarity, [the remaining text is incomplete and likely refers to a different topic]. Figure 5 The dielectric layer adjacent to the control gate layer is shown in the figure.

[0067] In some embodiments, the control gate of each layer is separated by slot structures 216-1 and 216-2 through the film stack 335. The 3D memory structure 500 may also include a top selected gate (TSG) layer 334 above the control gate stack 333. The stack of TSG 334, control gate 333, and LSG 332 may also be referred to as a “gate electrode”. The 3D memory structure 500 may further include a doped source electrode region 344 in the portion of the substrate 330 between adjacent LSGs 332. Each memory string 212 of the 3D memory structure 500 may include a channel via 336 extending through an insulating film 331 and the film stack 335 of alternating conductive and dielectric layers. The memory string 212 may also include a memory film 337 on the sidewall of the channel via 336, a channel layer 338 above the memory film 337, and a core-filling film 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) can be formed at the intersection of the control gate 333 (e.g., 333-1, 333-2, 333-3) and the memory string 212. A portion of the channel layer 338 can be responsive to the corresponding control gate and is also referred to as the channel 338 of the memory cell. The 3D memory structure 500 also includes multiple bit lines (BLs) 341 connected to the memory string 212 above the TSG 334. The 3D memory structure 500 may also include multiple metal interconnects 343 connected to the gate electrode via multiple contact structures 214. The edges of the film stack 335 are configured in a stepped shape to allow electrical connection to the gate electrode of each layer.

[0068] exist Figure 5For illustrative purposes, the three control gates 333-1, 333-2, and 333-3 are shown together with a TSG 334 and an LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3, corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be more than three to increase storage capacity. The 3D memory structure 500 may also include other structures, such as TSG notches, common source contacts (i.e., arrayed common sources), and dummy memory strings. For simplicity, these are not shown in the text. Figure 5 These structures are shown in the diagram. It is worth noting that... Figure 5 The 3D memory structure 500 shown is merely an example and does not limit the scope of protection of this disclosure. Any other suitable 3D memory structure may also be used.

[0069] Return to reference Figure 4 In some embodiments, memory blocks 103 may be formed based on floating gate technology. In some embodiments, memory blocks 103 may be formed based on charge trapping technology. Charge trapping-based NAND flash memory can provide high storage density and high inherent reliability. Logic states (“states”, such as the threshold voltage V of memory cell 340) th The stored data in the form of () depends on the number of charge carriers trapped in the memory membrane 337 of the storage cell 340.

[0070] In some embodiments, in a NAND flash memory, read and write operations (also known as programming operations) can be performed on memory page 432, and erase operations can be performed on memory block 103.

[0071] In some embodiments, in the NAND memory, memory cell 340 can be in an erase state ER or a programmable state P1. Initially, memory cell 340 in memory block 103 can be reset to the erase state ER, which is logic "1," by implementing a negative voltage difference between control gate 333 and channel 338, so that trapped charge carriers in the memory film of memory cell 340 can be removed. For example, this can be achieved by setting the control gate 333 of memory cell 340 to ground and applying a high positive voltage (erase voltage V) to ACS 430. erase This causes a negative voltage difference. In the erase state ER (“state ER”), the threshold voltage V of memory cell 340 can be reduced. th Reset to the lowest value.

[0072] In some embodiments, during programming (i.e., writing), a positive voltage difference between the control gate 333 and the channel 338 can be established, for example, by applying a programming voltage V to the control gate 333. pgm (For example, a positive voltage pulse between 10V and 20V), and ground the corresponding bit line 341. As a result, charge carriers (e.g., electrons) can be injected into the memory film of memory cell 340, thereby increasing the threshold voltage V of memory cell 340. th Therefore, storage unit 340 can be programmed to programming state P1 ("state P1" or logic "0").

[0073] In some embodiments, the threshold voltage V of the memory cell can be measured or sensed. th To determine the state of the memory cell (e.g., state ER or state P1). During a read operation, a read voltage V can be applied to the control gate 333 of the memory cell. read Furthermore, the current flowing through the memory cell can be measured at bit line 341. The voltage V can be used to measure this current. pass Apply to an unselected word line to enable the unselected memory cell.

[0074] In some embodiments, NAND flash memory can be configured to operate in single-level cell (SLC) mode. To increase storage capacity, NAND flash memory can also be configured to operate in multi-level cell (MLC) mode, three-level cell (TLC) mode, four-level cell (QLC) mode, or any combination of these modes. In SLC mode, a memory cell stores 1 bit and has two logical states (“states”), logic {1 and 0}, i.e., states ER and P1. In MLC mode, a memory cell stores 2 bits and has four logical states, logic {11, 10, 01, and 00}, i.e., states ER, P1, P2, and P3. In TLC mode, a memory cell stores 3 bits and has 8 logical states, logic {111, 110, 101, 100, 011, 010, 001, 000}, i.e., states ER and states P1-P7. In QLC mode, a memory cell stores 4 bits and has 16 logical states. Storage system 10 (see...) Figure 1 The memory controller 20 can convert data received from the host computer 15 into the corresponding logical state of the memory cell on the memory die 100, and vice versa.

[0075] Figure 6 The threshold voltage V of a NAND flash memory programmed in three-level cell (TLC) mode according to some embodiments is shown. th Distribution. In some embodiments, each state of a storage cell may correspond to a threshold voltage V. thA specific range, where the threshold voltage V for each state th The distribution can be represented by a probability density. In some embodiments, the eight TLC states can be programmed using an incremental step pulse programming (ISPP) scheme, where step pulses V can be added. step To incrementally increase the programming voltage V pgm Therefore, the eight TLC states can be programmed from state P1 with the lower threshold voltage to state P7 with the highest threshold voltage.

[0076] In some embodiments, after programming, during the verification process, one or more read reference voltages V can be used. R1 -V R7 To verify the eight TLC states ER and P1-P7, the reference voltage V is read. R1 -V R7 One or more of the control gates applied to the target memory cell can determine the threshold voltage V of the memory cell. th The range. For example, to verify whether a memory cell is in state ER, a read reference voltage V can be used. R1 If the target memory cell is in state ER, then the threshold voltage V of the target memory cell... th Below the reading reference voltage V R1 The target memory cell can be turned on, and a conductive path can be formed in the channel. If the target memory cell is in any of the states P1-P7, the threshold voltage V of the target memory cell is... th Higher than the reference voltage V R1 The target memory cell is thus turned off. The state of the target memory cell or the threshold voltage V can be verified by measuring or sensing the current through the target memory cell on the corresponding bit line via the page buffer / sensing amplifier 50. th .

[0077] In some embodiments, as described above, determining the two states ER and Pl stored in the SLC mode depends solely on the read reference voltage V. R1 That's sufficient. To determine the four states ER and P1-P3 in MLC mode, the reference voltage V can be read. R1 V R2 and V R3 To determine the eight states ER and P1-P7 in TLC mode, the reference voltage V can be read. R1 -V R7 For example, in TLC mode, the threshold voltage of state ER is lower than V. R1 The threshold voltage of state P7 is higher than V. R7 The threshold voltage of state P1 is between V R1 and VR2 Between these points, states P2-P6 can be similarly determined.

[0078] The above has described embodiments of the structure and function of 3D NAND memory (e.g., 3D memory structure 500 (Figure 5)). In some embodiments, it is desirable to provide reliable and convenient read operations to retrieve stored data from one or more memory cells. While some of the methods described above (e.g., ECC) can be used to address errors in programming, not all sources of error originate from the programming data. In some embodiments, programming data can be correctly stored in one or more memory cells, but read operations may fail for other reasons. Other sources of instability may affect read operations, such as temperature variations.

[0079] Refer again Figure 6 In some embodiments, conditions of the 3D NAND (e.g., temperature variations) can disrupt the distribution of the threshold voltage. For example, as shown in distribution 602, the threshold voltage distribution of state ER may be perturbed. Higher states may also be similarly perturbed. Figure 6 Non-limiting examples of variations of threshold voltage distributions 604, 606, and 608 corresponding to the distributions of states P1, P2, and P3 are shown (which can similarly affect higher states). This effect may be referred to herein as a “read disturbance.” If the effect of the read disturbance is significant enough, the read operation may fail (e.g., reading an incorrect value, different from the value programmed in the memory cell). Similarly, the term “verification disturbance” may refer to the effect of interfering with a verification operation. Verification operations are used to verify whether a programming operation has been successfully completed. Verification operations may be similar to read operations, but may also have some differences, such as using similar voltage schemes. These individual voltage schemes are described in more detail below. The term “read operation” may be used to describe verification operations with differences. It should be understood that the effector of a read operation can also be applied to a verification operation. Therefore, the term “effector of a read operation” can also refer to the effector of a verification operation. Furthermore, a verification operation can be viewed as a read operation with different applied voltages as described herein.

[0080] In some embodiments, storage system 10 ( Figure 1The 3D NAND flash memory, or its sub-components, can undergo power cycles (e.g., power outages, hibernation, wake-ups, etc.). When powered down or operating at limited power, one or more cells of the 3D NAND flash memory may experience significant temperature variations (e.g., from well above room temperature to near room temperature). In a non-limiting example, the operating temperature could be approximately 70-100°C, and the room temperature could be approximately 20-30°C (this can vary depending on environmental conditions). When the 3D NAND flash memory is powered back on, the temperature difference can exacerbate read / verify interference. Even if the temperature difference is not so significant, read / verify interference can still be exacerbated by power cycles.

[0081] In some embodiments, hot carrier injection is an example phenomenon that may lead to read disturbances represented by distributions 602, 604, 606, and 608. When a read operation is performed on an adjacent selected WL (e.g., WLn), the structure of unselected WLs (e.g., WLn-1, WLn+1, WLn+) may be boosted (e.g., voltage boosted). Unless otherwise stated, the notation used herein will imply that the nth WL (WLn) is a selected WL. The notation n+ / - can denote a WL separated from WLn. For example, unselected WLn-1 and WLn+1 can be adjacent to WLn. Then, unselected WLn-2 and WLn+2 can be located further away from WLn, and so on. Hot carrier injection may occur when the increased bias at an unselected WL causes electrons to be injected into the charge trap layer of the unselected WL. The description of scenarios involving hot carrier injection is heuristic (e.g., references...). Figure 7 ).

[0082] Figure 7 A read operation method 700 for reading from 3D NAND memory is illustrated according to some embodiments. For the context, Figure 7 Some descriptions will also rely on at least Figure 5 References to components in the document. In some embodiments, voltage can be applied to various structures of the 3D memory structure 500 and said voltage can be adjusted in a timely manner. Various timelines corresponding to the structures of the 3D memory structure 500 are illustrated. Figure 7 The vertical axis of the timeline represents the applied voltage. The horizontal axis of the timeline represents time. Furthermore, in some embodiments, the read operation method 700 can also describe a verification operation method with minor differences in the applied voltage, as described below.

[0083] In some embodiments, the read operation method 700 may have different time periods. For example, the read operation method may include sending a pre-pulse voltage signal (or simply "pre-pulse") to various structures of the 3D memory structure 500. The time period for the pre-pulse may be referred to as pre-pulse period 702. Similarly, the read operation method may include adjusting the voltage of various structures of the 3D memory structure 500 to read from one or more memory cells of the 3D memory structure 500. The time period for reading from the memory cells may be referred to as read period 704. The pre-pulse period 702 and read period 704 may be adjusted (e.g., using memory controller 20). Figure 1 )).

[0084] In some embodiments, timeline 706 shows how voltage can be applied to a selected TSG 334. Timeline 708 shows how voltage can be applied to an unselected TSG 334. Timeline 710 shows how voltage can be applied to an unselected WL 333. Timeline 712 shows how voltage can be applied to WLn+1 and WLn-1 (i.e., WL 333 of WL 333 immediately adjacent to the selected WL 333). As previously described, the selected WL 333 is denoted as WLn. Timeline 714 shows how voltage can be applied to WLn (i.e., the selected WL 333). Timeline 716 shows how voltage can be applied to LSG 332. Timeline 718 shows how voltage can be applied to BL 341. It should be understood that while some timelines refer to applying voltage to a single structure (e.g., a selected TSG 334 within a TSG 334), the methods described herein are not limited to this. For example, memory structures can be fabricated using multiple memory pages and blocks. Multiple structures spanning pages / blocks can be selected and / or deselected for voltage application. In another example, while bias voltage can be applied to channels, it should be understood that bias voltage can also be applied to other channels within the same memory page. In yet another example, it is envisioned that the memory structure design can have a single common LSG 332 or multiple LSG 332s within a single page, and depending on the architecture, applying voltage to the LSG 332 does not need to be limited to a single LSG.

[0085] In some embodiments, the read operation method 700 may include setting a start voltage for the structure of the 3D memory structure 500 before a pre-pulse period 702. For example, TSG, WL, LSG, and BL may be set to voltages Vss (e.g., a first reference voltage level) or Vdd (e.g., a second reference voltage level), such as... Figure 7As shown in the figures. It should be understood that in some embodiments, enumeration adjectives (e.g., "first," "second," "third," etc.) may be used as naming conventions and are not intended to indicate quantity or order of introduction (unless otherwise stated). For example, the terms "first reference voltage level" and "second reference voltage level" may distinguish between two reference voltage levels, but it is not necessary to specify whether the first level is higher or lower than the second level. Furthermore, the elements in the figures are not limited to any particular enumeration adjective. For example, if one or more other voltage levels use one or more appropriately distinguishing enumeration adjectives, Vss may be referred to as the second reference voltage level.

[0086] In some embodiments, the read operation method 700 may include increasing the voltage of a plurality of TSG 334s during a pre-pulse period 702 (see timelines 706 and 708). The voltage increase of the plurality of TSG 334s may be relative to Vss (e.g., a first reference voltage level). The voltage increase of the plurality of TSG 334s may reach a given voltage, in Figure 7 It is marked as Vbias_hv3.

[0087] In some embodiments, the read operation method 700 may further include increasing the voltage of multiple WL 333s during a pre-pulse period 702 (see timelines 710, 712, and 714). The voltage increase of the multiple WL 333s may be relative to Vdd (e.g., a second reference voltage level). The voltage increase of the multiple WL 333s may reach one or more different voltages. For example, an unselected WL 333 may be increased to Vpass1, which may be different from Vbias_hv3. A selected WL 333 may be increased to Vbias_hv3. As mentioned above, the read operation and the verification operation may have subtle differences in the voltage applied. For example, the selected WL 333 may be increased to Vrd_p instead during the read period 704. This changes read operation method 700 to a verification operation (in this case, it should be understood that read time period 704 can also be a verification time period). Vrd_p It can be used to read the reference voltage V R1 -V R7 ( Figure 6 Any one of the following, which can be positive or negative.

[0088] In some embodiments, the read operation method 700 may further include: increasing the voltage of LSG 332 during the pre-pulse period 702 (see timeline 716). The voltage increase of LSG 332 may be relative to Vss. For example, the voltage increase of LSG 332 may reach Vbias_hv3. The read operation method 700 may further include: not applying a voltage change to BL 341 during the pre-pulse period 702 (see timeline 718).

[0089] In some embodiments, read period 704 can be defined as a period during which a voltage signal is applied to the structure of a NAND memory device (e.g., 3D memory structure 500) to allow sensing of stored data in the memory cells of the NAND memory device. Pre-pulse period 702 can be defined as a period preceding read period 704. For example, even when a voltage signal is applied during pre-pulse period 702, the applied voltage signal is not at a level that would allow sensing of data stored in the memory cells of the NAND memory device. Pre-pulse period 702 is characterized in that the pre-pulse signal is used to regulate the electronic state of the 3D memory structure 500 to avoid undesirable effects when an actual read is performed during read period 704. Non-limiting examples of undesirable effects include voltage fluctuations and hot carrier injection typically caused by the voltage signal applied during read period 704. Therefore, it should be understood that... Figure 7 The limitations of the pre-pulse period 702 and read period 704 shown are not restrictive, but are provided as examples consistent with the pre-pulse period 702 and read period 704 described above.

[0090] In some embodiments, the read operation method 700 may further include setting the voltage of a selected TSG 334 among a plurality of TSGs 334 during a read period 704 (see timeline 706). For example, the voltage level (Vbias_hv3) set in the pre-pulse period 702 may be maintained by transitioning from the pre-pulse period 702 to the read period 704. In other words, the read operation method 700 may further include not applying a voltage change to the selected TSG 334 among the plurality of TSGs 334 during the read period 704. The read operation method 700 may further include reducing the voltage of an unselected TSG among the plurality of TSGs 334 (see timeline 708). For example, the voltage may be reduced back to Vss at the beginning of the read period 704.

[0091] In some embodiments, the read operation method 700 may further include setting the voltage of an unselected WL among a plurality of WL 333 during a read period 704 (see timeline 710). For example, the voltage level (Vpass1) set in the pre-pulse period 702 can be maintained by transitioning from the pre-pulse period 702 to the read period 704. In other words, the read operation method 700 may further include not applying a voltage change to the unselected WL 333 among the plurality of WL 333 during the read period 704. The read operation method 700 may further include increasing the voltage of WL 333 immediately adjacent to WLn among the plurality of WL 333 (that is, WLn+1 and WLn-1) during the read period 704 (see timeline 712). The voltage increase of WLn+1 and WLn-1 during the read period 704 may be a voltage higher than Vpass1 (e.g., up to Vpass3, such as...). Figure 7 (as shown in the image).

[0092] In some embodiments, the read operation method 700 may further include: during the read period 704, applying the read voltage Vrd_p Set to a selected WL 333 (i.e., WLn) among multiple WL 333s (see timeline 714). Vrd_p It can be used to read the reference voltage V R1 -V R7 ( Figure 6 Any of the following, which can be positive or negative. The read operation method 700 may further include: reading from a memory cell associated with a selected WL 333 among a plurality of WL 333s.

[0093] In some embodiments, the read operation method 700 may further include: not applying a voltage change to the LSG 332 during the read period 704 (see timeline 716).

[0094] In some embodiments, the read operation method 700 may further include increasing the voltage of BL 341 during a read period 704 (see timeline 718). The increase in the voltage of BL 341 may be performed after a short delay during the read period 704. For example, the voltage Vrd_p may be set in timeline 714. Then, the voltage increase of BL 341 is executed. The voltage increase of BL 341 can reach, for example, Vbl_rve, which can be different from Vbias_hv3, Vpass1, Vpass3 and / or Vrd_p. Configure Vbl_rve so that Vrd_p With the appropriate settings, a measurable current exists in the channel. This is how data can be sensed from the storage cells of the 3D memory structure 500.

[0095] In some embodiments, after reading data from the 3D memory structure 500, the voltages of TSG, WL, LSG, and BL can return to the initial level Vss or Vdd.

[0096] In some embodiments, the pre-pulse operation described above can mitigate some undesirable effects, such as voltage rise and hot carrier injection. However, even with pre-pulse, certain conditions can lead to hot carrier injection, for example, when a NAND memory device is powered off for an extended period (e.g., 5 minutes or more), causing hole carriers to accumulate in the charge trap layer, further increasing the potential at WLn+1 and above. In such cases, pre-pulse may still be insufficient to reduce hot carrier injection to a tolerable level. One approach to address this issue could be, for example, increasing the duration of the pre-pulse period 702. However, increasing the duration of the pre-pulse period 702 for multiple read operations results in significant read latency. Accurate and rapid storage and retrieval of data by memory devices is critical. In some embodiments, it is envisioned that read operation methods can further mitigate read interference without relying on increasing the duration of the pre-pulse period (or at least reducing the amount by which the duration of the pre-pulse period should be increased to achieve the target reliability metric).

[0097] Figure 8 This illustrates a read operation method 800 for reading from 3D NAND memory according to some embodiments. For the context, Figure 8 Some descriptions will also rely on at least Figure 5 References to components are included. In some embodiments, voltage can be applied to various structures of the 3D memory structure 500 and said voltage can be adjusted in a timely manner. Various timelines corresponding to the structures of the 3D memory structure 500 are used for illustration. Figure 8 The vertical axis of the time line represents the applied voltage. The horizontal axis of the time line represents time.

[0098] In some embodiments, Figure 8 The read operation method 800 shown may include similar methods to the reference method. Figure 7 The description refers to the function of read operation method 700. Therefore, unless otherwise stated, [the following is unclear and likely incomplete: "for"] Figure 7 The description of the element can also be applied to Figure 8 The corresponding elements (e.g., the reference numerals sharing the rightmost two numbers) will not reintroduce redundant features.

[0099] In some embodiments, the read operation method 800 may have a pre-pulse period 802 and a read period 804 (e.g., using a memory controller 20). Figure 1(Adjustable). Timelines 806, 808, 810, 812, and 814 can be referenced to their corresponding timelines 706, 708, 710, 712, and 714. Figure 7 As described in ( ).

[0100] In some embodiments, the read operation method 800 may include: not applying a voltage change to the LSG 332 during the pre-pulse period 802 (see timeline 816). The read operation method 800 may also include: increasing the voltage of the LSG 332 during the read period 804. The voltage increase of the LSG 332 may be relative to Vss. The voltage increase of the LSG 332 may reach, for example, Vbias_hv3.

[0101] In some embodiments, the read operation method 800 may further include: reducing the voltage of BL 341 during a pre-pulse period 802 (see timeline 818). The voltage reduction of BL 341 may be relative to Vss. The voltage reduction of BL 341 may be reduced to, for example... Figure 8 The amplitude of Vblpre is shown in the figure. In some embodiments, the amplitude of Vblpre can be greater than about 0.1 volts and less than about 4.0 volts. In some embodiments, the amplitude of Vblpre can be greater than about 0.5 volts and less than about 3.0 volts. In some embodiments, the amplitude of Vblpre can be greater than about 1.0 volt and less than about 2.5 volts. The voltage reduction of BL 341 can reduce the effect of hot carrier injection by neutralizing the artificially raised potential in the channel of the unselected word line (e.g., WLn+1, etc.). Using this effect, the read operation 800 may further include setting the pre-pulse period 802 to be shorter than another pre-pulse period associated with not performing the voltage reduction of BL 341.

[0102] In some embodiments, the read operation method 800 may further include: increasing the voltage of BL 341 during the read period 804 (e.g., returning to Vss). The read operation method 800 may further include: further increasing the voltage of BL 341 during the read period 804 (e.g., increasing it up to Vbl_rve), as previously referenced. Figure 7 As described.

[0103] In some embodiments, after reading data from the 3D memory structure 500, the voltages of TSG, WL, LSG, and BL can return to the initial level Vss or Vdd.

[0104] In some embodiments, the activity term "setting" may include: checking whether a parameter is at a target value. If it is not at the target value, then "setting" may also include: adjusting the parameter to the target value by increasing or decreasing the parameter value. "Setting" may also include actions that do not perform a check. For example, setting a voltage may include: sending a command to set a target voltage at a structure, regardless of whether the structure is affected by the command (e.g., if the structure is already at the target voltage, then no change is made).

[0105] In some embodiments, firmware 21 can be used ( Figure 1 Read operations 700 and 800 can be performed on the host computer 15 in some embodiments. Figure 1 Data is read upon request. In some embodiments, read operations 700 and 800 may verify the data stored in the memory cell using different voltages (as described above) after the memory cell has been programmed.

[0106] The method steps in the embodiments disclosed herein can be performed in any conceivable order, and it is not necessary to perform all the steps.

[0107] In summary, this disclosure provides a method for controlling a 3D NAND memory using a read operation. The read operation may have a pre-pulse period prior to the read period. The method includes: during the pre-pulse period, increasing the voltage of a plurality of top select gates relative to a first reference voltage level. The method also includes: during the pre-pulse period, increasing the voltage of a plurality of word lines relative to a second reference voltage level. The method further includes: during the pre-pulse period, decreasing the voltage of the bit lines relative to the first reference voltage level. The method also includes: during the pre-pulse period, not applying a voltage change to the bottom select gate. This reduces the potential rise of the channels associated with unselected word lines among the plurality of word lines.

[0108] This disclosure also provides a non-transitory computer-readable medium for controlling a 3D NAND memory. The non-transitory computer-readable medium may include instructions stored thereon that, when executed by one or more computing devices communicating with the 3D NAND memory, cause the one or more computing devices to perform a read operation having a pre-pulse period prior to a read period. The method includes: during the pre-pulse period, increasing the voltage of a plurality of top-select gates relative to a first reference voltage level. The method further includes: during the pre-pulse period, increasing the voltage of a plurality of word lines relative to a second reference voltage level. The method further includes: during the pre-pulse period, decreasing the voltage of bit lines relative to the first reference voltage level. The method further includes: during the pre-pulse period, not applying a voltage change to the bottom-select gate. This reduces the potential rise of the channel associated with an unselected word line among the plurality of word lines.

[0109] This disclosure also provides a system for controlling a 3D NAND memory. The system may include one or more computing devices and a non-transitory computer-readable medium. The non-transitory computer-readable medium may include instructions stored thereon that, when executed by one or more computing devices communicating with the 3D NAND memory, cause the one or more computing devices to perform a read operation having a pre-pulse period prior to a read period. The method includes: during the pre-pulse period, increasing the voltage of a plurality of top-select gates relative to a first reference voltage level. The method further includes: during the pre-pulse period, increasing the voltage of a plurality of word lines relative to a second reference voltage level. The method further includes: during the pre-pulse period, decreasing the voltage of the bit lines relative to the first reference voltage level. The method further includes: during the pre-pulse period, not applying a voltage change to the bottom-select gate. This reduces the potential rise of the channel associated with an unselected word line among the plurality of word lines.

[0110] The foregoing description of specific embodiments will fully reveal the general nature of this disclosure, enabling others to easily modify and / or adjust various applications of these particular embodiments by applying knowledge within the scope of the art, without requiring extensive experimentation and without departing from the general concept of this disclosure. Therefore, based on this disclosure and the guidance provided herein, such modifications and adjustments are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive purposes only and not for limitation, and that the terminology or terminology in this specification should be interpreted by those skilled in the art based on this disclosure and guidance.

[0111] The embodiments of this disclosure have been described above using functional building blocks that illustrate the implementation of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries may be defined, provided that the specified functions and their relationships are performed appropriately.

[0112] The summary and abstract may set forth one or more, but not all, exemplary embodiments of this disclosure as contemplated by the inventors(s), and therefore are not intended to limit this disclosure and the appended claims in any way.

[0113] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A computer-implemented method for controlling a storage device using read operations, the method comprising: During the pre-pulse period of the read operation preceding the read period of the read operation, the voltage of multiple top-select gates is increased relative to the first reference voltage level; During the pre-pulse period, the voltage of multiple word lines is increased relative to the second reference voltage level; During the pre-pulse period, the voltage of the bit line is reduced relative to the first reference voltage level; as well as During the pre-pulse period, no voltage change is applied to the bottom select gate.

2. The computer-implemented method according to claim 1, wherein: The read operation is the first read operation; The prepulse period is the first prepulse period; Define a second pre-pulse period for the second read operation; The second read operation differs from the first read operation in that the second read operation does not reduce the voltage of the bit line; and The computer-implemented method further includes setting the first prepulse period to be shorter than the second prepulse period.

3. The computer-implemented method according to claim 1, wherein, Reducing the voltage of the bit line includes reducing the voltage of the bit line by more than 0.1 volts and less than about 4.0 volts, more than 0.5 volts and less than about 3.0 volts, or more than 1.0 volts and less than about 2.5 volts.

4. The computer-implemented method according to claim 1 further includes: During the read period, the voltage of the bit line is increased to exceed the first reference voltage level; as well as During the read period, the voltage of the bottom select gate is increased relative to the first reference voltage level.

5. The computer-implemented method according to claim 1, further comprising: During the read period, the voltage of a selected word line among the plurality of word lines is set as the read voltage relative to the second reference voltage level, wherein the bit line is associated with the selected word line among the plurality of word lines; and Read from the storage unit associated with the selected word line among the plurality of word lines.

6. The computer-implemented method according to claim 5, further comprising: During the read period, the voltage of the unselected top select gate in the top select gate is reduced; as well as During the read period, the voltage of the word line adjacent to the selected word line is increased.

7. The computer-implemented method according to claim 1, wherein: The storage device is a 3D NAND storage device; and After the storage cells of the 3D NAND storage device are programmed, the read operation is used to verify the data stored in the storage cells.

8. A storage device comprising: Storage unit, which is configured to store data; A memory controller configured to control the memory device; as well as A non-transitory computer-readable medium having instructions stored thereon, which, when executed by the memory controller, cause the memory controller to perform read operations including the following: During the pre-pulse period of the read operation preceding the read period of the read operation, the voltage of multiple top-select gates is increased relative to the first reference voltage level; During the pre-pulse period, the voltage of multiple word lines is increased relative to the second reference voltage level; During the pre-pulse period, the voltage of the bit line is reduced relative to the first reference voltage level; as well as During the pre-pulse period, no voltage change is applied to the bottom select gate.

9. The storage device according to claim 8, wherein: The read operation is the first read operation; The prepulse period is the first prepulse period; Define a second pre-pulse period for the second read operation; The second read operation differs from the first read operation in that the second read operation does not reduce the voltage of the bit line; as well as The first read operation further includes setting the first prepulse period to be shorter than the second prepulse period.

10. The storage device according to claim 8, wherein, Reducing the voltage of the bit line includes reducing the voltage of the bit line by more than 0.1 volts and less than about 4.0 volts, more than 0.5 volts and less than about 3.0 volts, or more than 1.0 volts and less than about 2.5 volts.

11. The storage device according to claim 8, wherein, The read operation also includes: During the read period, the voltage of the bit line is increased to exceed the first reference voltage level; and During the read period, the voltage of the bottom select gate is increased relative to the first reference voltage level.

12. The storage device according to claim 8, wherein, The read operation also includes: During the read period, the voltage of a selected word line among the plurality of word lines is set as the read voltage relative to the second reference voltage level, wherein the bit line is associated with the selected word line among the plurality of word lines; and Read from the storage unit associated with the selected word line among the plurality of word lines.

13. The storage device according to claim 12, wherein, The read operation also includes: During the read period, the voltage of the unselected top select gate in the top select gate is reduced; and During the read period, the voltage of the word line adjacent to the selected word line among the plurality of word lines is increased.

14. The storage device according to claim 8, wherein: The storage device is a 3D NAND storage device; and After the storage cells of the 3D NAND storage device are programmed, the read operation is used to verify the data stored in the storage cells.

15. A storage system, comprising: Storage devices, including: Storage unit, which is configured to store data; A memory controller configured to control the memory device; and A non-transitory computer-readable medium having instructions stored thereon, which, when executed by the memory controller, cause the memory controller to perform read operations including the following: During the pre-pulse period of the read operation preceding the read period of the read operation, the voltage of multiple top-select gates is increased relative to the first reference voltage level; During the pre-pulse period, the voltage of multiple word lines is increased relative to the second reference voltage level; During the pre-pulse period, the voltage of the bit line is reduced relative to the first reference voltage level; and During the pre-pulse period, no voltage change is applied to the bottom select gate.

16. The storage system according to claim 15, wherein: The read operation is the first read operation; The prepulse period is the first prepulse period; Define a second pre-pulse period for the second read operation; The second read operation differs from the first read operation in that the second read operation does not reduce the voltage of the bit line; and The first read operation further includes setting the first prepulse period to be shorter than the second prepulse period.

17. The storage system according to claim 15, wherein, Reducing the voltage of the bit line includes reducing the voltage of the bit line by more than 0.1 volts and less than about 4.0 volts, more than 0.5 volts and less than about 3.0 volts, or more than 1.0 volts and less than about 2.5 volts.

18. The storage system according to claim 15, wherein, The read operation also includes: During the read period, the voltage of the bit line is increased to exceed the first reference voltage level; and During the read period, the voltage of the bottom select gate is increased relative to the first reference voltage level.

19. The storage system according to claim 15, wherein, The read operation also includes: During the read period, the voltage of a selected word line among the plurality of word lines is set as the read voltage relative to the second reference voltage level, wherein the bit line is associated with the selected word line among the plurality of word lines; and Read from the storage unit associated with the selected word line among the plurality of word lines.

20. The storage system according to claim 19, wherein, The read operation also includes: During the read period, the voltage of the unselected top select gate in the top select gate is reduced; and During the read period, the voltage of the word line adjacent to the selected word line among the plurality of word lines is increased.

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