Memory and its operation methods, memory system

Abstract

This disclosure provides a memory including a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple memory surfaces. The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface. The selected voltage selection circuits are used to select a voltage from the multiple selected voltages and output it to the global word line voltage selection circuits. The global word line voltage selection circuits are used to select a voltage from the unselected voltage and the voltage output from the selected voltage selection circuits and output it to the local word line voltage selection circuits. During programming operations, the multiple memory surfaces share the multiple selected voltage selection circuits. During reading operations, each memory surface uses a portion of the selected voltage selection circuits from the multiple selected voltage selection circuits to perform voltage selection.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, and a memory system. Background Technology

[0002] Memory is a storage device used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] With the increasing demands on memory, reducing memory area has become one of the most pressing technical problems to be solved in this field. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory is provided, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array;

[0005] The storage cell array includes multiple storage surfaces;

[0006] The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface.

[0007] The selected voltage selection circuit is used to select one voltage from a plurality of selected voltages and output it to the global word line voltage selection circuit; the global word line voltage selection circuit is used to select one voltage from the unselected voltage and the voltage output from the selected voltage selection circuit and output it to the local word line voltage selection circuit;

[0008] During programming operations, the multiple storage surfaces share the multiple selected voltage selection circuits; during reading operations, each storage surface uses a portion of the selected voltage selection circuits among the multiple selected voltage selection circuits to select the voltage.

[0009] In the above scheme, during programming operations, the number of selected voltages corresponding to multiple storage surfaces is 'a', and the number of selected voltage selection circuits corresponding to multiple storage surfaces is at least 'a'; during reading operations, the number of selected voltages corresponding to each storage surface is 'b', and the number of selected voltage selection circuits corresponding to each storage surface is at least 'b'.

[0010] The number of storage surfaces is c, and the relationship between a, b, and c is: a ≥ b * c; where a and b are both positive integers greater than 0, and c is a positive integer greater than 1.

[0011] In the above scheme, the peripheral circuit also includes: multiple global word lines that correspond one-to-one with the global word line voltage selection circuit;

[0012] During programming operations, the number of selected voltage selection circuits corresponding to multiple memory surfaces is 'a', and each of the 'a' adjacent global word lines on each memory surface corresponds to a different selected voltage selection circuit.

[0013] During a read operation, different global word lines on different memory planes correspond to different selected voltage selection circuits. The number of selected voltage selection circuits corresponding to each memory plane is b, and each of the b adjacent global word lines on each memory plane corresponds to a different selected voltage selection circuit.

[0014] In the above scheme, the peripheral circuit further includes: a plurality of unselected voltage selection circuits corresponding to the plurality of storage surfaces; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on a storage surface, and each local word line voltage selection circuit corresponds to an unselected voltage selection circuit;

[0015] Each of the unselected voltage selection circuits is used to select a voltage from at least one unselected voltage and output it to the local word line voltage selection circuit;

[0016] During programming operations, the multiple storage surfaces share the multiple unselected voltage selection circuits; during reading operations, each storage surface uses a portion of the multiple unselected voltage selection circuits for voltage selection.

[0017] In the above scheme, during programming operations, the number of unselected voltages corresponding to multiple storage surfaces is d, and the number of unselected voltage selection circuits corresponding to multiple storage surfaces is at least d; during reading operations, the number of unselected voltages corresponding to each storage surface is e, and the number of unselected voltage selection circuits corresponding to each storage surface is at least e.

[0018] The number of storage surfaces is c, and the relationship between c, d, and e is: d ≥ e * c; where d and e are both positive integers greater than 0, and c is a positive integer greater than 1.

[0019] In the above scheme, each of the storage surfaces includes multiple word lines;

[0020] The peripheral circuit also includes: multiple global word lines corresponding to the global word line voltage selection circuit and multiple local word lines corresponding to the local word line voltage selection circuit; wherein, each global word line corresponds to multiple local word lines; each local word line corresponds to one global word line and each local word line corresponds to one word line.

[0021] The global word line voltage selection circuit outputs voltage to the local word line voltage selection circuit through the global word line; the local word line voltage selection circuit outputs voltage to the corresponding word line through the local word line.

[0022] In the above scheme, the selected voltage selection circuit, the global word line voltage selection circuit, the local word line voltage selection circuit, and the unselected voltage selection circuit all include multiplexers.

[0023] According to a second aspect of the present disclosure, a memory system is provided, comprising:

[0024] One or more memories as described in any of the above schemes; and

[0025] A memory controller, which is coupled to the memory and controls the memory.

[0026] In the above scheme, the memory system includes a memory card or a solid-state drive.

[0027] According to a third aspect of the present disclosure, a method for operating a memory is provided, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array;

[0028] The storage cell array includes multiple storage surfaces;

[0029] The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface.

[0030] The selected voltage selection circuit is used to select one voltage from a plurality of selected voltages and output it to the global word line voltage selection circuit; the global word line voltage selection circuit is used to select one voltage from the unselected voltage and the voltage output from the selected voltage selection circuit and output it to the local word line voltage selection circuit;

[0031] The method includes:

[0032] Receive a first instruction, which instructs to perform programming operations on the plurality of storage surfaces simultaneously;

[0033] In response to the first instruction, multiple different voltages output by the multiple selected voltage selection circuits are applied to each storage surface;

[0034] Receive a second instruction, which instructs to perform a read operation on the plurality of storage surfaces;

[0035] In response to the second instruction, a portion of the multiple different voltages output by the multiple selected voltage selection circuits are applied to different storage surfaces.

[0036] In the above scheme, during the simultaneous programming operation on the multiple storage surfaces, the number of selected voltages corresponding to the multiple storage surfaces is 'a', and the number of selected voltage selection circuits corresponding to the multiple storage surfaces is at least 'a'; during the read operation on the multiple storage surfaces, the number of selected voltages corresponding to each storage surface is 'b', and the number of selected voltage selection circuits corresponding to each storage surface is at least 'b'.

[0037] The number of storage surfaces is c, and the relationship between a, b, and c is: a ≥ b * c; where a and b are both positive integers greater than 0, and c is a positive integer greater than 1.

[0038] In the above scheme, the peripheral circuit also includes: multiple global word lines that correspond one-to-one with the global word line voltage selection circuit;

[0039] During the simultaneous programming operation on the multiple memory surfaces, the number of selected voltage selection circuits corresponding to the multiple memory surfaces is 'a', and each of the 'a' adjacent global word lines on each memory surface corresponds to a different selected voltage selection circuit.

[0040] During the read operation on the multiple storage surfaces, the global word lines on different storage surfaces correspond to different selected voltage selection circuits. The number of selected voltage selection circuits corresponding to each storage surface is b, and the b adjacent global word lines on each storage surface correspond to different selected voltage selection circuits.

[0041] In the above scheme, the peripheral circuit further includes: a plurality of unselected voltage selection circuits corresponding to the plurality of storage surfaces; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on a storage surface, and each local word line voltage selection circuit corresponds to an unselected voltage selection circuit;

[0042] Each of the unselected voltage selection circuits is used to select a voltage from at least one unselected voltage and output it to the local word line voltage selection circuit;

[0043] The method further includes:

[0044] In response to the first instruction, multiple different unselected voltages output by the multiple unselected voltage selection circuits are applied to each storage surface;

[0045] In response to the second instruction, a portion of the multiple different voltages output by the multiple unselected voltage selection circuits are applied to different storage surfaces.

[0046] In the above scheme, during programming operations, the number of unselected voltages corresponding to multiple storage surfaces is d, and the number of unselected voltage selection circuits corresponding to multiple storage surfaces is at least d; during reading operations, the number of unselected voltages corresponding to each storage surface is e, and the number of unselected voltage selection circuits corresponding to each storage surface is at least e.

[0047] The number of storage surfaces is c, and the relationship between c, d, and e is: d ≥ e * c; where d and e are both positive integers greater than 0, and c is a positive integer greater than 1.

[0048] In the above scheme, each of the storage surfaces includes multiple word lines;

[0049] The peripheral circuit also includes: multiple global word lines corresponding to the global word line voltage selection circuit and multiple local word lines corresponding to the local word line voltage selection circuit; wherein, each global word line corresponds to multiple local word lines; each local word line corresponds to one global word line and each local word line corresponds to one word line.

[0050] The global word line voltage selection circuit outputs voltage to the local word line voltage selection circuit through the global word line; the local word line voltage selection circuit outputs voltage to the corresponding word line through the local word line.

[0051] In the above scheme, during the reading operation on the multiple storage planes, the Asynchronous Multi Plane Independent (AMPI) method is used to perform reading operations on the multiple storage planes.

[0052] This disclosure provides a memory and its operation method, a memory system, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array including multiple memory surfaces; the peripheral circuitry including: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface; the selected voltage selection circuits are used to select a voltage from the multiple selected voltages and output it to the global word line voltage selection circuits; the global word line voltage selection circuits are used to select a voltage from the unselected voltages and the voltages output from the selected voltage selection circuits and output it to the local word line voltage selection circuits; during programming operations, the multiple memory surfaces share the multiple selected voltage selection circuits; during reading operations, each memory surface uses a portion of the selected voltage selection circuits among the multiple selected voltage selection circuits for voltage selection. In this embodiment of the present disclosure, during programming operations, multiple storage surfaces share multiple selected voltage selection circuits. During reading operations, each storage surface uses a portion of the selected voltage selection circuits used during programming operations for voltage selection. In other words, in this embodiment of the present disclosure, programming operations and reading operations share the selected voltage selection circuits. This eliminates the need to add additional selected voltage selection circuits required for reading operations, resulting in a smaller total number of selected voltage selection circuits. Consequently, the area of ​​the memory can be reduced, which is beneficial for memory miniaturization. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0054] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0055] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0056] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0057] Figure 3b This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of the present disclosure;

[0058] Figure 4 This is a schematic cross-sectional view of a memory array including NAND memory strings according to an embodiment of the present disclosure.

[0059] Figure 5This is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of the present disclosure;

[0060] Figure 6a This is a schematic diagram of the word line voltage during programming operations according to an embodiment of this disclosure;

[0061] Figure 6b This is a schematic diagram of the word line voltage during a read operation according to an embodiment of this disclosure;

[0062] Figure 7 This is a schematic diagram of the structure of a peripheral circuit according to an embodiment of the present disclosure. Figure 1 ;

[0063] Figure 8 This is a schematic diagram of the peripheral circuit structure according to an embodiment of the present disclosure;

[0064] Figure 9a This is a schematic diagram showing the correspondence between multiple memory surfaces and the selected voltage selection circuit during programming operations according to an embodiment of this disclosure;

[0065] Figure 9b This diagram illustrates the correspondence between multiple storage surfaces and the selected voltage selection circuit during a read operation according to an embodiment of this disclosure. Figure 1 ;

[0066] Figure 10 This is a schematic diagram showing the correspondence between multiple storage surfaces and the selected voltage selection circuit during a read operation according to an embodiment of this disclosure;

[0067] Figure 11 This is a schematic diagram of a simulated waveform of an asynchronous multi-faceted independent read operation according to an embodiment of the present disclosure;

[0068] Figure 12 This is a schematic diagram of the peripheral circuit structure according to an embodiment of the present disclosure;

[0069] Figure 13a This is a schematic diagram showing the correspondence between multiple memory surfaces and unselected voltage selection circuits during programming operations according to an embodiment of this disclosure;

[0070] Figure 13b This is a schematic diagram showing the correspondence between multiple storage surfaces and the unselected voltage selection circuit during a read operation according to an embodiment of this disclosure;

[0071] Figure 14 This is a schematic diagram illustrating the implementation flow of a memory operation method according to an embodiment of the present disclosure. Detailed Implementation

[0072] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0073] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0074] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0075] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0076] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0077] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0078] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0079] The memory in the embodiments of this disclosure includes, but is not limited to, a three-dimensional NAND type memory. For ease of understanding, a three-dimensional NAND type memory will be used as an example for explanation.

[0080] Three-dimensional NAND flash memory stacks memory cells in a direction perpendicular to the substrate, enabling the formation of more memory cells in a smaller area. Compared to traditional two-dimensional memory, it has a larger storage capacity and represents a major development direction in the current memory field. With the increasing demands on three-dimensional NAND flash memory, how to reduce the memory area has attracted widespread attention.

[0081] To address one or more of the above-mentioned problems, embodiments of this disclosure introduce a solution that reduces the area of ​​the peripheral circuitry, thereby reducing the area of ​​the memory.

[0082] Figure 1A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory 104.

[0083] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0084] The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0085] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2a In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0086] Figure 3aAn exemplary schematic diagram of a three-dimensional NAND flash memory array is provided, such as... Figure 3a As shown, the memory array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Each two rows of memory cells are separated by a gate isolation structure and an up-select gate isolation structure. Each row of memory cells includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple blocks. Multiple second gate isolation structures can divide the blocks into multiple finger regions. An up-select gate isolation structure located in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two strings. Figure 3a The storage block shown contains 6 storage chips. In actual applications, the number of storage chips in a storage block is not limited to this.

[0087] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0088] Figure 3b A schematic circuit diagram of an exemplary memory 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is provided. Memory 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0089] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0090] like Figure 3b As shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0091] like Figure 3bAs shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a memory page 320 of memory cell 306, where the memory page 320 is the basic data unit for programming operations. The size of a memory page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A memory page 320 contains multiple memory cells 306, which are separated by an upselect gate isolation structure and a gate isolation structure. The multiple memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the upselect gate isolation structure. The memory cells in the memory chip sharing the same word line form a programmable (read / write) page.

[0092] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory array 301.

[0093] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0094] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0095] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0096] Return to reference Figure 3bThe peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0097] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0098] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0099] In some specific embodiments, the programming operation may include multiple steps. For example, the programming operation may include a bit line setting step, a programming execution step, and a programming recovery step. After the programming operation, a programming verification operation is also required; after the programming verification operation, a programming verification recovery operation is also required. During the bit line setting step of the programming operation, the voltage of unselected word lines can be maintained at ground (GND). During the programming execution step of the programming operation, a pass voltage Vpass can be applied to the unselected word lines, and a programming voltage Vgm can be applied to the selected word lines. Therefore, the memory cells connected to the selected word lines can be programmed. During the programming recovery step of the programming operation, the voltage applied to all word lines can be reduced to ground (GND). During the programming verification operation, a verification voltage Vvrf can be applied to the selected word lines, and a read voltage Vrd can be applied to the unselected word lines. During the programming verification recovery operation, a recovery operation can be performed on both the unselected and selected word lines to reduce their voltages to ground (GND).

[0100] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0101] In a three-dimensional NAND flash memory, a single chip may include multiple dies capable of independently performing NAND operations (e.g., read, write, and erase). Each die may include multiple memory planes, and each memory plane may include multiple vertically stacked memory cells to increase the storage capacity per unit area. In multi-plane read operations, all selected memory planes are required to have the same word line address, and read operations on multiple planes must be synchronized. This causes read operations between multiple memory planes to be mutually restrictive, resulting in slow read speeds. To support fast read operations, in some embodiments, the peripheral circuitry can be configured to support asynchronous multi-plane independent read operations. This means that the word line address, page type, and memory cell type of each memory plane can be selected independently, and the read operation of each memory plane can be performed in one step. In other words, multiple memory planes can perform asynchronous independent read operations. In asynchronous multi-plane independent read operations, if the selected word line address and page type are different, each memory plane requires different word line bias conditions, thus each memory plane should have circuitry for selecting different voltages, which significantly increases the area of ​​the peripheral circuitry.

[0102] This disclosure provides a memory, which includes a memory cell array and peripheral circuitry coupled to the memory cell array;

[0103] The storage cell array includes multiple storage surfaces;

[0104] The peripheral circuitry includes: a plurality of first selected voltage selection circuits corresponding to the plurality of memory surfaces, a plurality of second selected voltage selection circuits corresponding to each memory surface, a plurality of global word line voltage selection circuits corresponding to each memory surface, and a plurality of local word line voltage selection circuits corresponding to each memory surface.

[0105] The first selected voltage selection circuit and the second selected voltage selection circuit are used to select one voltage from a plurality of selected voltages and output it to the global word line voltage selection circuit; the global word line voltage selection circuit is used to select one voltage from the unselected voltage and the voltage output from the first selected voltage selection circuit or the second selected voltage selection circuit and output it to the local word line voltage selection circuit.

[0106] During programming operations, the plurality of storage surfaces share the plurality of first selected voltage selection circuits; during reading operations, each storage surface uses a portion of the plurality of second selected voltage selection circuits for voltage selection.

[0107] In some specific examples, Figure 5 The line decoder / WL driver shown includes the first selected voltage selection circuit, the second selected voltage selection circuit, the global word line voltage selection circuit, the local word line voltage selection circuit, and the unselected voltage selection circuit and the selected voltage selection circuit mentioned later.

[0108] In some specific examples, such as Figure 6a As shown, during programming, different voltages need to be applied to the target word line and several word lines adjacent to it to reduce the high electric field stress effect. However, for read operations, since the voltage applied to the target word line during read operations is much smaller than that applied during programming operations, the electric field effect is weaker, and it is not necessary to apply special voltages to too many word lines adjacent to the target word line. For example, during programming operations, different voltages are applied to the target word line (WLn) and the four word lines above it (WLn-4 to WLn-1) and the five word lines below it (WLn+1 to WLn+5). That is, a total of 10 special word lines need to be individually biased with different voltages. The selection voltage here can be understood as the bias voltage that needs to be applied to the special word lines individually. Therefore, there are a total of 10 selection voltages, requiring 10 selection voltage selection circuits. Figure 6b As shown, during a read operation, the target word line (WLm), the word line above it (WLm-1), and the word line below it (WLm+1) all require independent voltages. However, the voltages of the word line above and below the target word line can be the same. This means there are two different selection voltages, thus requiring two selection voltage selection circuits to provide these two different selection voltages. For more information, please refer to [link / reference]. Figure 3bThe word lines above and below the target word line are understood as follows: the word line above the target word line can be understood as the word line between the target word line and bit line 316, and the word line below the target word line can be understood as the word line between the target word line and source line 314.

[0109] Figure 7 An exemplary schematic diagram of the peripheral circuitry during programming and reading operations is shown. Figure 7 As can be seen, the peripheral circuit has 10 first-selection voltage selection circuits for voltage selection during programming operations. These 10 first-selection voltage selection circuits are shared by the four memory surfaces during programming operations. During read operations, two voltages are selected, and each memory surface is equipped with two second-selection voltage selection circuits for voltage selection.

[0110] It is understandable that in the solution provided in the above embodiments, during the programming operation, a first selection voltage selection circuit is used to provide 10 different selection voltages for 10 special word lines. Ten first selection voltage selection circuits are required, and multiple memory surfaces share these 10 circuits. During the read operation, to achieve asynchronous multi-surface independent read operations, a second selection voltage selection circuit is used to provide voltages for special word lines on different memory surfaces. Here, two selection voltages are used, so each memory surface requires two second selection voltage selection circuits. For example, when there are four memory surfaces, eight second selection voltage selection circuits are needed. In other words, the read operation and the programming operation use different selection voltage selection circuits. At least 18 first and second selection voltage selection circuits need to be set in the peripheral circuitry, resulting in a large number of selection voltage selection circuits, a large peripheral circuit area, and a large memory area.

[0111] Based on the above problems, this disclosure provides another memory, which includes a memory cell array and peripheral circuitry coupled to the memory cell array;

[0112] The storage cell array includes multiple storage surfaces;

[0113] The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface.

[0114] The selected voltage selection circuit is used to select one voltage from a plurality of selected voltages and output it to the global word line voltage selection circuit; the global word line voltage selection circuit is used to select one voltage from the unselected voltage and the voltage output from the selected voltage selection circuit and output it to the local word line voltage selection circuit;

[0115] During programming operations, the multiple storage surfaces share the multiple selected voltage selection circuits; during reading operations, each storage surface uses a portion of the selected voltage selection circuits among the multiple selected voltage selection circuits to select the voltage.

[0116] The multiple selected voltage selection circuits corresponding to the multiple storage surfaces mentioned here can be understood as having multiple correspondences between the storage surfaces and the selected voltage selection circuits. In the programming operation, the multiple selected voltage selection circuits correspond to each of the multiple storage surfaces, while in the reading operation, different parts of the multiple selected voltage selection circuits correspond to each of the multiple storage surfaces respectively.

[0117] In some specific examples, the memory cell array and the peripheral circuitry are disposed on the same chip. In other specific examples, the memory cell array is disposed on an array chip, while the peripheral circuitry is disposed on a different chip, specifically a chip implemented using Complementary Metal Oxide Semiconductor (CMOS) technology and referred to as a CMOS chip, the array chip and the CMOS chip being electrically coupled together using a bonding process. In some examples, the CMOS chip may be coupled to multiple array chips.

[0118] It is understandable that the selected voltage and the unselected voltage here can both be determined by... Figure 5 The voltage generator shown in the diagram generates multiple different voltages. The selected voltage selection circuit, the global word line voltage selection circuit, the local word line voltage selection circuit, and the unselected voltage selection circuit mentioned later are all used to select the voltage. Finally, the different voltages generated by the voltage generator are applied to different word lines in the memory plane, thereby realizing the programming and reading operations of multiple memory planes.

[0119] It is understood that in the above embodiments of this disclosure, the selected voltage selection circuit is shared during programming and reading operations. That is, during the reading operation, the selected voltage selection circuit used during the programming operation is reused, and a separate selected voltage selection circuit is not set up for the reading operation. This reduces the number of selected voltage selection circuits, thereby reducing the area of ​​the peripheral circuit and the area of ​​the memory.

[0120] The following example illustrates the scenario where, during programming operations, different voltages need to be applied to 10 special word lines, resulting in 10 selected voltages. This requires 10 selected voltage selection circuits across 4 memory surfaces. During read operations, two different voltages need to be applied to 3 special word lines, resulting in 2 unselected voltages. This requires 2 selected voltage selection circuits per memory surface, resulting in 8 selected voltage selection circuits across 4 memory surfaces.

[0121] Figure 8 An exemplary schematic diagram of the peripheral circuitry during programming and reading operations is shown. Figure 8 As can be seen, the peripheral circuit has 10 selected voltage selection circuits for voltage selection during programming operations. These 10 selected voltage selection circuits are shared by the four memory surfaces during programming operations. During read operations, there are 2 selected voltages, with 2 selected voltage selection circuits configured on each memory surface for voltage selection.

[0122] During programming operations, since the four storage surfaces share 10 select voltage selection circuits, a total of 10 select voltage selection circuits are required. However, during read operations, if an asynchronous multi-surface independent read method is used, each storage surface requires a separate select voltage selection circuit for voltage selection. Since each storage surface needs to provide 2 select voltages, a total of 8 select voltage selection circuits are required. However, the select voltage selection circuits used in programming operations are reused during read operations, eliminating the need for 8 separate select voltage selection circuits dedicated to read operations. Therefore, 8 fewer select voltage selection circuits can be used, thereby reducing the area of ​​the external circuitry.

[0123] Figure 9a The correspondence between multiple memory surfaces and the selected voltage selection circuit is shown during programming operations; Figure 9b The diagram illustrates the correspondence between multiple memory surfaces and the selected voltage selection circuit during a read operation. It should be noted that... Figure 9a as well as Figure 9b The examples shown are merely exemplary and are not intended to limit the correspondence between the storage surface and the selected voltage selection circuit in the embodiments of this disclosure. Figure 9a as well as Figure 9bAs can be seen, during the programming operation, the four storage surfaces share 10 selected voltage selection circuits (configurable voltage domains 0-9). During the read operation, each storage surface corresponds to a different selected voltage selection circuit. The selected voltage selection circuits used during the read operation are the same as those used in the programming operation. Specifically, storage surface 0 corresponds to configurable voltage domains 0-1, storage surface 1 corresponds to configurable voltage domains 2-3, storage surface 2 corresponds to configurable voltage domains 4-5, and storage surface 3 corresponds to configurable voltage domains 6-7. The remaining two selected voltage selection circuits can be used as backups.

[0124] In some embodiments, during programming operations, the number of selected voltages corresponding to multiple storage surfaces is 'a', and the number of selected voltage selection circuits corresponding to multiple storage surfaces is at least 'a'; during reading operations, the number of selected voltages corresponding to each storage surface is 'b', and the number of selected voltage selection circuits corresponding to each storage surface is at least 'b'.

[0125] The number of storage surfaces is c, and the relationship between a, b, and c is: a ≥ b * c; where a and b are both positive integers greater than 0, and c is a positive integer greater than 1.

[0126] Here, during programming operations, the selected voltage corresponding to multiple memory planes refers to the different voltages applied to the target word line and the word lines adjacent to it. The requirement that the number of selected voltage selection circuits is at least *a* can be understood as meaning that the number of selected voltage selection circuits can be equal to or greater than the number of selected voltages. When the number of selected voltage selection circuits is the same as the number of selected voltages, each selected voltage selection circuit selects one selected voltage. When the number of selected voltage selection circuits is greater than the number of selected voltages, any *a* selected voltage selection circuits are used for voltage selection, and the remaining selected voltage selection circuits can be used as backups. During read operations, the selected voltage corresponding to each memory plane is different. For an understanding of selected voltages and selected voltage selection circuits, please refer to the previous explanation of selected voltages and selected voltage selection circuits during programming operations; it will not be repeated here.

[0127] Here, a≥b*c can be understood as follows: since the selected voltage selection circuit is shared during programming and reading operations, and a total of b*c selected voltage selection circuits are needed during reading operations, in order to allocate b selected voltage selection circuits for voltage selection to each storage surface during reading operations, the number of selected voltage selection circuits during programming operations is greater than or equal to the total number of selected voltage selection circuits needed during reading operations.

[0128] In some specific examples, such as Figure 10As shown, to achieve asynchronous multi-faceted independent read functionality, each memory face is provided with independent, non-shared voltages related to asynchronous multi-faceted independent reads, while the shared voltages supporting any operation (e.g., common logic voltages, common power supply voltages) are shared across the four memory faces. This reduces the analog circuit area while implementing asynchronous multi-faceted independent read operations. During asynchronous multi-faceted independent read operations, logic control signals are provided independently for different configurable voltage domain groups. Therefore, voltage sources can be asynchronously connected to the configurable voltage domains.

[0129] Figure 11 This diagram illustrates a simulated waveform of an asynchronous multi-faceted independent read operation. Figure 11 As can be seen, during asynchronous multi-face independent read operations, the selected voltage selection circuits allocated to different memory faces can perform voltage selection operations asynchronously.

[0130] In some specific examples, local word lines can be divided into multiple groups, each containing 20 local word lines (for a memory with 232 local word lines per memory surface, some groups may contain fewer than 20 local word lines). Only the group containing the target local word line and the special local word line adjacent to the target local word line is supplied with voltage using the global word line voltage selection circuit, while the local word lines of other groups are supplied with voltage using the unselected voltage selection circuit. Figure 7 as well as Figure 8 In the proposed scheme, each storage plane corresponds to a set of unselected voltage selection circuits, and each set of unselected voltage selection circuits contains 12 unselected voltage selection circuits for selecting unselected voltages. In some specific examples, for read operations, except for the target word line and the two word lines adjacent to the target word line, the voltage to be applied to other word lines is the same, Vbais1. Therefore, in asynchronous multi-plane independent read operations, not many unselected voltage selection circuits are needed to implement asynchronous multi-plane independent read operations.

[0131] To further reduce the area of ​​the peripheral circuit, the following solutions are proposed for the unselected voltage selection circuit.

[0132] In some embodiments, the peripheral circuitry further includes: a plurality of unselected voltage selection circuits corresponding to the plurality of memory surfaces; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on a memory surface, and each local word line voltage selection circuit corresponds to an unselected voltage selection circuit.

[0133] Each of the unselected voltage selection circuits is used to select a voltage from at least one unselected voltage and output it to the local word line voltage selection circuit;

[0134] During programming operations, the multiple storage surfaces share the multiple unselected voltage selection circuits; during reading operations, each storage surface uses a portion of the multiple unselected voltage selection circuits for voltage selection.

[0135] The multiple unselected voltage selection circuits corresponding to the multiple storage surfaces can be understood to mean that there are multiple correspondences between the storage surfaces and the unselected voltage selection circuits. In the programming operation, the multiple unselected voltage selection circuits correspond to each of the multiple storage surfaces, while in the reading operation, different parts of the multiple unselected voltage selection circuits correspond to each of the multiple storage surfaces respectively.

[0136] In some embodiments, during programming operations, the number of unselected voltages corresponding to multiple storage surfaces is d, and the number of unselected voltage selection circuits corresponding to multiple storage surfaces is at least d; during reading operations, the number of unselected voltages corresponding to each storage surface is e, and the number of unselected voltage selection circuits corresponding to each storage surface is at least e.

[0137] The number of storage surfaces is c, and the relationship between c, d, and e is: d ≥ e * c; where d and e are both positive integers greater than 0, and c is a positive integer greater than 1.

[0138] Here, during programming operations, the unselected voltages corresponding to multiple memory planes are the voltages applied to word lines other than special word lines (including the target word line and multiple word lines adjacent to the target word line). The requirement that the number of unselected voltage selection circuits is at least *d* can be understood as the number of unselected voltage selection circuits being equal to or greater than the number of unselected voltages. When the number of unselected voltage selection circuits is the same as the number of unselected voltages, each unselected voltage selection circuit selects one unselected voltage. When the number of unselected voltage selection circuits is greater than the number of unselected voltages, any *d* unselected voltage selection circuits are used for voltage selection, and the remaining unselected voltage selection circuits can be used as backups. During read operations, the unselected voltages corresponding to each memory plane are different. For an understanding of unselected voltages and unselected voltage selection circuits, please refer to the previous explanation of selected voltages and selected voltage selection circuits during programming operations; it will not be repeated here.

[0139] Here, d≥e*c can be understood as follows: since the unselected voltage selection circuit is shared during programming and reading operations, and a total of e*c unselected voltage selection circuits are needed during reading operations, in order to allocate e unselected voltage selection circuits for voltage selection to each storage surface during reading operations, the number of unselected voltage selection circuits during programming operations is greater than or equal to the total number of unselected voltage selection circuits required during reading operations.

[0140] Figure 7 as well as Figure 8 In the corresponding embodiment, different unselected voltage selection circuits may need to select different unselected voltages for programming and erasing operations. However, for asynchronous multi-faceted independent read operations, the corresponding unselected voltage selection circuits in a memory face select the same unselected voltage, and only one unselected voltage selection circuit is needed for each memory face. Therefore, only one set of unselected voltage selection circuits needs to be retained, instead of four sets of unselected voltage selection circuits for four memory faces. During programming operations, the local word lines of the four memory faces share the same set of unselected voltage selection circuits. During read operations, if the number of unselected voltage selection circuits is greater than the number of memory faces, the multiple unselected voltage selection circuits can be divided into multiple parts, and the number of unselected voltage selection circuits can be the same as the number of memory faces. Then, each part of the unselected voltage selection circuits is assigned to a memory face.

[0141] Figure 12 This shows a schematic diagram of another type of peripheral circuit. Figure 12 As can be seen, multiple storage surfaces share a common set of unselected voltage selection circuits. Each set contains 12 unselected voltage selection circuits. During programming operations, multiple storage surfaces share these 12 unselected voltage selection circuits. During read operations, the unselected voltage selection circuits used for programming are reused in the read operations. Each storage surface can correspond to one unselected voltage selection circuit, meaning that each memory only needs to be configured with 12 unselected voltage selection circuits. Figure 7 as well as Figure 8 The proposed scheme configures one set of unselected voltage selection circuits for each storage surface. With four storage surfaces, a total of four sets of unselected voltage selection circuits are needed, resulting in a total of 48 unselected voltage selection circuits required. Therefore... Figure 12 The proposed solution is compared to Figure 7 as well as Figure 8 The proposed scheme significantly reduces the number of unselected voltage selection circuits, thereby saving the area of ​​peripheral circuits.

[0142] Figure 13a An exemplary schematic diagram illustrates the correspondence between multiple unselected voltage selection circuits and the memory surface during programming operations; Figure 13b An exemplary diagram illustrates the correspondence between multiple unselected voltage selection circuits and memory surfaces during a read operation. From Figure 13a As can be seen, during programming and erasing operations, the four memory surfaces share 12 unselected voltage selection circuits (gwlu0-gwlu11); from Figure 13bAs can be seen, during the read operation, each of the four memory surfaces corresponds to three unselected voltage selection circuits, and the unselected voltage selection circuits are different for different memory surfaces. Here, allocating three unselected voltage selection circuits to each memory surface during the read operation is to make full use of the existing circuitry and reduce the area of ​​each unselected voltage selection circuit.

[0143] In some embodiments, the peripheral circuit further includes: a plurality of global word lines corresponding one-to-one with the global word line voltage selection circuit;

[0144] During programming operations, the number of selected voltage selection circuits corresponding to multiple memory surfaces is 'a', and each of the 'a' adjacent global word lines on each memory surface corresponds to a different selected voltage selection circuit.

[0145] During a read operation, different global word lines on different memory planes correspond to different selected voltage selection circuits. The number of selected voltage selection circuits corresponding to each memory plane is b, and each of the b adjacent global word lines on each memory plane corresponds to a different selected voltage selection circuit.

[0146] In some embodiments, each of the storage surfaces includes a plurality of word lines;

[0147] The peripheral circuit also includes: multiple global word lines corresponding to the global word line voltage selection circuit and multiple local word lines corresponding to the local word line voltage selection circuit; wherein, each global word line corresponds to multiple local word lines; each local word line corresponds to one global word line and each local word line corresponds to one word line.

[0148] The global word line voltage selection circuit outputs voltage to the local word line voltage selection circuit through the global word line; the local word line voltage selection circuit outputs voltage to the corresponding word line through the local word line.

[0149] In some specific examples, the global word line voltage selection circuit is used to select a voltage from the unselected voltage and the voltage output from the selected voltage selection circuit and output it to the local word line voltage selection circuit through a global word line; the local word line voltage selection circuit is used to select a voltage from the voltage output from the corresponding global word line voltage selection circuit and the voltage output from the unselected voltage selection circuit and output it to the corresponding word line through a local word line.

[0150] In some specific examples, for a 3D NAND flash memory with four memory planes (Plane0-Plane3), each memory plane in the peripheral circuitry corresponding to 232 local word lines, each memory plane corresponding to 20 global word lines, four memory planes corresponding to 10 selected voltages during programming operations, four memory planes corresponding to 12 unselected voltages during programming operations, each memory plane corresponding to 2 selected voltages during read operations, and each memory plane corresponding to 1 unselected voltage during read operations, Table 1 specifically illustrates the correspondence of the selected voltage selection circuit (configurable voltage domain 0-configurable voltage domain 7), the global word line voltage selection circuit (gwl0-gwl19), the unselected voltage selection circuit (gwlu0-gwlu11), and the local word lines (LWL0-LWL231) corresponding to one memory plane in a peripheral circuitry provided in an embodiment of this disclosure. It should be noted that the correspondence in Table 1 is merely an example and is not intended to limit the correspondence between different parts of the memory in the embodiments of this disclosure.

[0151] Table 1

[0152]

[0153]

[0154]

[0155]

[0156]

[0157] In some embodiments, the selected voltage selection circuit, the global word line voltage selection circuit, the local word line voltage selection circuit, and the unselected voltage selection circuit all include a multiplexer.

[0158] In some specific examples, the memory includes a three-dimensional NAND-type memory.

[0159] However, the memory in this disclosure is not limited to three-dimensional NAND memory. In this disclosure, the memory can be a semiconductor memory, including but not limited to three-dimensional NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), or nano random access memory (NRAM), etc.

[0160] This disclosure provides a memory comprising a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple memory surfaces. The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface. The selected voltage selection circuits are used to select a voltage from the multiple selected voltages and output it to the global word line voltage selection circuits. The global word line voltage selection circuits are used to select a voltage from the unselected voltage and the voltage output from the selected voltage selection circuits and output it to the local word line voltage selection circuits. During programming operations, the multiple memory surfaces share the multiple selected voltage selection circuits. During reading operations, each memory surface uses a portion of the selected voltage selection circuits among the multiple selected voltage selection circuits for voltage selection. In this embodiment of the present disclosure, during programming operations, multiple storage surfaces share multiple selected voltage selection circuits. During reading operations, each storage surface uses a portion of the selected voltage selection circuits used during programming operations for voltage selection. In other words, in this embodiment of the present disclosure, programming operations and reading operations share the selected voltage selection circuits. This eliminates the need to add additional selected voltage selection circuits required for reading operations, resulting in a smaller total number of selected voltage selection circuits. Consequently, the area of ​​the memory can be reduced, which is beneficial for memory miniaturization.

[0161] This disclosure also provides a memory system, the memory system comprising:

[0162] One or more memories as described in any of the above embodiments; and

[0163] A memory controller, which is coupled to the memory and controls the memory.

[0164] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 , Figure 2a The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here.

[0165] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0166] Based on the above-described memory, this disclosure also provides a method for operating the memory, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array;

[0167] The storage cell array includes multiple storage surfaces;

[0168] The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface.

[0169] The selected voltage selection circuit is used to select one voltage from a plurality of selected voltages and output it to the global word line voltage selection circuit; the global word line voltage selection circuit is used to select one voltage from the unselected voltage and the voltage output from the selected voltage selection circuit and output it to the local word line voltage selection circuit;

[0170] like Figure 14 As shown, the method includes:

[0171] Step S1001: Receive a first instruction, which instructs to perform programming operations on the plurality of storage surfaces simultaneously;

[0172] Step S1002: In response to the first instruction, apply the multiple different voltages output by the multiple selected voltage selection circuits to each storage surface;

[0173] Step S1003: Receive a second instruction, which instructs to perform a read operation on the plurality of storage surfaces;

[0174] Step S1004: In response to the second instruction, a portion of the multiple different voltages output by the multiple selected voltage selection circuits are applied to different storage surfaces.

[0175] In some embodiments, during the simultaneous programming operation on the plurality of storage surfaces, the number of selected voltages corresponding to the plurality of storage surfaces is 'a', and the number of selected voltage selection circuits corresponding to the plurality of storage surfaces is at least 'a'; during the read operation on the plurality of storage surfaces, the number of selected voltages corresponding to each storage surface is 'b', and the number of selected voltage selection circuits corresponding to each storage surface is at least 'b'.

[0176] The number of storage surfaces is c, and the relationship between a, b, and c is: a ≥ b * c; where a and b are both positive integers greater than 0, and c is a positive integer greater than 1.

[0177] In some embodiments, the peripheral circuit further includes: a plurality of global word lines corresponding one-to-one with the global word line voltage selection circuit;

[0178] During the simultaneous programming operation on the multiple memory surfaces, the number of selected voltage selection circuits corresponding to the multiple memory surfaces is 'a', and each of the 'a' adjacent global word lines on each memory surface corresponds to a different selected voltage selection circuit.

[0179] During the read operation on the multiple storage surfaces, the global word lines on different storage surfaces correspond to different selected voltage selection circuits. The number of selected voltage selection circuits corresponding to each storage surface is b, and the b adjacent global word lines on each storage surface correspond to different selected voltage selection circuits.

[0180] In some embodiments, the peripheral circuitry further includes: a plurality of unselected voltage selection circuits corresponding to the plurality of memory surfaces; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on a memory surface, and each local word line voltage selection circuit corresponds to an unselected voltage selection circuit.

[0181] Each of the unselected voltage selection circuits is used to select a voltage from at least one unselected voltage and output it to the local word line voltage selection circuit;

[0182] The method further includes:

[0183] In response to the first instruction, multiple different voltages output by the multiple unselected voltage selection circuits are applied to each storage surface;

[0184] In response to the second instruction, a portion of the multiple different voltages output by the multiple unselected voltage selection circuits are applied to different storage surfaces.

[0185] In some embodiments, during programming operations, the number of unselected voltages corresponding to multiple storage surfaces is d, and the number of unselected voltage selection circuits corresponding to multiple storage surfaces is at least d; during reading operations, the number of unselected voltages corresponding to each storage surface is e, and the number of unselected voltage selection circuits corresponding to each storage surface is at least e.

[0186] The number of storage surfaces is c, and the relationship between c, d, and e is: d ≥ e * c; where d and e are both positive integers greater than 0, and c is a positive integer greater than 1.

[0187] In some embodiments, each of the storage surfaces includes a plurality of word lines;

[0188] The peripheral circuit also includes: multiple global word lines corresponding to the global word line voltage selection circuit and multiple local word lines corresponding to the local word line voltage selection circuit; wherein, each global word line corresponds to multiple local word lines; each local word line corresponds to one global word line and each local word line corresponds to one word line.

[0189] The global word line voltage selection circuit outputs voltage to the local word line voltage selection circuit through the global word line; the local word line voltage selection circuit outputs voltage to the corresponding word line through the local word line.

[0190] In some embodiments, during the reading operation on the plurality of storage surfaces, an asynchronous multi-surface independent reading method is used to perform reading operations on the plurality of storage surfaces.

[0191] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0192] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0193] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array; The storage cell array includes multiple storage surfaces; The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface. The selected voltage selection circuit is used to select one voltage from a plurality of selected voltages and output it to the global word line voltage selection circuit; the global word line voltage selection circuit is used to select one voltage from the unselected voltage and the voltage output from the selected voltage selection circuit and output it to the local word line voltage selection circuit; During programming operations, the multiple storage surfaces share the multiple selected voltage selection circuits; during reading operations, each storage surface uses a portion of the selected voltage selection circuits among the multiple selected voltage selection circuits to select the voltage.

2. The memory according to claim 1, characterized in that, During programming operations, the number of selected voltages corresponding to multiple storage surfaces is 'a', and the number of selected voltage selection circuits corresponding to multiple storage surfaces is at least 'a'; during reading operations, the number of selected voltages corresponding to each storage surface is 'b', and the number of selected voltage selection circuits corresponding to each storage surface is at least 'b'. The number of storage surfaces is c, and the relationship between a, b, and c is: a ≥ b * c; where a and b are both positive integers greater than 0, and c is a positive integer greater than 1.

3. The memory according to claim 2, characterized in that, The peripheral circuit also includes: multiple global word lines corresponding one-to-one with the global word line voltage selection circuit; During programming operations, the number of selected voltage selection circuits corresponding to multiple memory surfaces is 'a', and each of the 'a' adjacent global word lines on each memory surface corresponds to a different selected voltage selection circuit. During a read operation, different global word lines on different memory planes correspond to different selected voltage selection circuits. The number of selected voltage selection circuits corresponding to each memory plane is b, and each of the b adjacent global word lines on each memory plane corresponds to a different selected voltage selection circuit.

4. The memory according to claim 1, characterized in that, The peripheral circuit also includes: a plurality of unselected voltage selection circuits corresponding to the plurality of storage surfaces; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on a storage surface, and each local word line voltage selection circuit corresponds to an unselected voltage selection circuit; Each of the unselected voltage selection circuits is used to select a voltage from at least one unselected voltage and output it to the local word line voltage selection circuit; During programming operations, the multiple storage surfaces share the multiple unselected voltage selection circuits; during reading operations, each storage surface uses a portion of the multiple unselected voltage selection circuits for voltage selection.

5. The memory according to claim 4, characterized in that, During programming operations, the number of unselected voltages corresponding to multiple storage surfaces is d, and the number of unselected voltage selection circuits corresponding to multiple storage surfaces is at least d; during reading operations, the number of unselected voltages corresponding to each storage surface is e, and the number of unselected voltage selection circuits corresponding to each storage surface is at least e. The number of storage surfaces is c, and the relationship between c, d, and e is: d ≥ e * c; where d and e are both positive integers greater than 0, and c is a positive integer greater than 1.

6. The memory according to claim 4, characterized in that, Each of the aforementioned storage surfaces includes multiple word lines; The peripheral circuit also includes: multiple global word lines corresponding to the global word line voltage selection circuit and multiple local word lines corresponding to the local word line voltage selection circuit; wherein, each global word line corresponds to multiple local word lines; each local word line corresponds to one global word line and each local word line corresponds to one word line. The global word line voltage selection circuit outputs voltage to the local word line voltage selection circuit through the global word line; the local word line voltage selection circuit outputs voltage to the corresponding word line through the local word line.

7. The memory according to claim 4, characterized in that, The selected voltage selection circuit, the global word line voltage selection circuit, the local word line voltage selection circuit, and the unselected voltage selection circuit all include multiplexers.

8. A memory system, characterized in that, The memory system includes one or more memories as described in any one of claims 1-7; and A memory controller, which is coupled to the memory and controls the memory.

9. The memory system according to claim 8, characterized in that, The memory system includes a memory card or a solid-state drive.

10. A method for operating a memory, characterized in that, The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array; The storage cell array includes multiple storage surfaces; The peripheral circuitry includes: multiple selected voltage selection circuits corresponding to the multiple memory surfaces, multiple global word line voltage selection circuits corresponding to each memory surface, and multiple local word line voltage selection circuits corresponding to each memory surface. The selected voltage selection circuit is used to select one voltage from a plurality of selected voltages and output it to the global word line voltage selection circuit; the global word line voltage selection circuit is used to select one voltage from the unselected voltage and the voltage output from the selected voltage selection circuit and output it to the local word line voltage selection circuit; The method includes: Receive a first instruction, which instructs to perform programming operations on the plurality of storage surfaces simultaneously; In response to the first instruction, multiple different voltages output by the multiple selected voltage selection circuits are applied to each storage surface; Receive a second instruction, which instructs to perform a read operation on the plurality of storage surfaces; In response to the second instruction, a portion of the multiple different voltages output by the multiple selected voltage selection circuits are applied to different storage surfaces.

11. The method according to claim 10, characterized in that, During the simultaneous programming operation on the multiple storage surfaces, the number of selected voltages corresponding to the multiple storage surfaces is a, and the number of selected voltage selection circuits corresponding to the multiple storage surfaces is at least a. During the read operation on the plurality of storage surfaces, the number of selected voltages corresponding to each storage surface is b, and the number of selected voltage selection circuits corresponding to each storage surface is at least b. The number of storage surfaces is c, and the relationship between a, b, and c is: a ≥ b * c; where a and b are both positive integers greater than 0, and c is a positive integer greater than 1.

12. The method according to claim 11, characterized in that, The peripheral circuit also includes: multiple global word lines corresponding one-to-one with the global word line voltage selection circuit; During the simultaneous programming operation on the multiple memory surfaces, the number of selected voltage selection circuits corresponding to the multiple memory surfaces is 'a', and each of the 'a' adjacent global word lines on each memory surface corresponds to a different selected voltage selection circuit. During the read operation on the multiple storage surfaces, the global word lines on different storage surfaces correspond to different selected voltage selection circuits. The number of selected voltage selection circuits corresponding to each storage surface is b, and the b adjacent global word lines on each storage surface correspond to different selected voltage selection circuits.

13. The method according to claim 10, characterized in that, The peripheral circuit also includes: a plurality of unselected voltage selection circuits corresponding to the plurality of storage surfaces; each unselected voltage selection circuit corresponds to a plurality of local word line voltage selection circuits on a storage surface, and each local word line voltage selection circuit corresponds to an unselected voltage selection circuit; Each of the unselected voltage selection circuits is used to select a voltage from at least one unselected voltage and output it to the local word line voltage selection circuit; The method further includes: In response to the first instruction, multiple different voltages output by the multiple unselected voltage selection circuits are applied to each storage surface; In response to the second instruction, a portion of the multiple different voltages output by the multiple unselected voltage selection circuits are applied to different storage surfaces.

14. The method according to claim 13, characterized in that, During programming operations, the number of unselected voltages corresponding to multiple storage surfaces is d, and the number of unselected voltage selection circuits corresponding to multiple storage surfaces is at least d; during reading operations, the number of unselected voltages corresponding to each storage surface is e, and the number of unselected voltage selection circuits corresponding to each storage surface is at least e. The number of storage surfaces is c, and the relationship between c, d, and e is: d ≥ e * c; where d and e are both positive integers greater than 0, and c is a positive integer greater than 1.

15. The method according to claim 13, characterized in that, Each of the aforementioned storage surfaces includes multiple word lines; The peripheral circuit also includes: multiple global word lines corresponding one-to-one with the global word line voltage selection circuit, and multiple local word lines corresponding one-to-one with the local word line voltage selection circuit; wherein, each global word line corresponds to multiple local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line; the global word line voltage selection circuit outputs voltage to the local word line voltage selection circuit through the global word lines; The local word line voltage selection circuit outputs voltage to the corresponding word line through the local word line.

16. The method according to claim 10, characterized in that, During the read operation on the multiple storage surfaces, an asynchronous multi-surface independent read method is used to perform read operations on the multiple storage surfaces.

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