Matchless plasma source for semiconductor wafer manufacturing

Abstract

A matcherless plasma source is described. The matcherless plasma source includes a controller coupled to a agile DC rail to control a shape of an amplified square wave form generated at an output of a half bridge transistor circuit. The matcherless plasma source also includes the half bridge transistor circuit to generate the amplified square wave form to power an electrode (e.g., an antenna) of a plasma chamber. The matcherless plasma source also includes a reactance circuit between the half bridge transistor circuit and the electrode. The reactance circuit has a high quality factor that cancels out a reactance of the electrode. There is no radio frequency (RF) matcher and no RF cable coupling the matcherless plasma source to the electrode.

Description

[0001] This application is a divisional application of application number 201880067919.9, filed on October 16, 2018, entitled "Matcherless Plasma Source for Semiconductor Wafer Manufacturing". Technical Field

[0002] This invention relates to a matchless plasma source for coupling to electrodes. Background Technology

[0003] Plasma systems are used to perform various operations on wafers. A plasma system includes a radio frequency (RF) generator, an RF matcher, and a plasma chamber. The RF generator is coupled to the RF matcher via an RF cable, and the RF matcher is coupled to the plasma chamber. RF power is supplied to the plasma chamber via the RF cable and the RF matcher, where the wafer is processed. Additionally, one or more gases are supplied to the plasma chamber, and plasma is generated within the plasma chamber upon receiving RF power.

[0004] The embodiments described in this invention arose in this context. Summary of the Invention

[0005] Embodiments of the present invention provide systems, apparatus, methods, and computer programs for providing a matchless plasma source to be coupled to an electrode. It should be understood that these embodiments can be implemented in many ways, such as as a process, apparatus, system, piece of hardware, method, or computer-readable medium. Several embodiments are described below.

[0006] In some implementations, an RF power delivery system (e.g., a matcher-free plasma source) is coupled to an excitation electrode that can be used to generate or modify plasma in any wafer fabrication chamber where RF power is used. For example, the RF power delivery system supplies RF power to the excitation electrode, such as one or more coils, nozzles, wafer platforms, or chucks. The RF power is coupled to the electrode using power transistors (e.g., field-effect transistors (FETs) or insulated-gate bipolar transistors (IGBTs)) that act as low-impedance voltage sources to couple power to the electrode. This approach offers several advantages over systems that use RF generators, RF cables, and RF matchers. These advantages include reduced cost of RF matchers and RF cables, increased speed of plasma ignition and impedance tuning, increased ability to generate different types of advanced pulses, and coil power multiplexing.

[0007] An RF generator with a 50 Ohm output section supplies power to the load using an RF cable (which is a 50 Ohm transmission line). Power is then supplied from the RF cable to an RF matching unit (a mechanical or electronic RF impedance matching box) to convert the load impedance to 50 Ohms. When all impedances are matched to 50 Ohms, maximum power is delivered to the load, with zero reflected power. This is how power is delivered in wafer fabrication using plasma processing (e.g., etching, deposition, and physical vapor deposition (PVD)). Therefore, this operation has limitations that restrict future processing capabilities. These limitations include a limited speed of plasma ignition and impedance tuning, high cost of RF matching units and RF cables, limited ability to generate different types of pulses, and limited plasma uniformity control.

[0008] In some embodiments described in this invention, the 50-Ohm RF power generator, 50-Ohm RF cable, and RF matching device used to convert the load impedance to near 50 Ohms are replaced by connecting a low-impedance voltage source to the connection of the excitation electrode to be powered. The low-impedance voltage source includes power transistors (e.g., FETs or IGBTs) organized in a half-bridge configuration and operated in a push-pull or full-bridge (H) configuration to avoid shoot-through. The power transistors are controlled by a controller board, and signals related to the RF frequency and pulse are sent to a gate driver, such as a FET gate driver. The power output from the low-impedance voltage source is determined by an agile DC rail. The agile DC rail is used to increase, decrease, or pulse the power output from the low-impedance voltage source. The agile DC rail is used for power regulation and modulation, while allowing pulses of arbitrary shapes to be constructed. The pulse capability is enhanced compared to plasma tools with RF generators, RF cables, and RF matching devices.

[0009] Furthermore, in many implementations, multiple transistors (e.g., FETs or IGBTs) are combined in a full-bridge or half-bridge configuration to provide a predetermined power output, depending on the power requirements. Typically, the output impedance of each transistor ranges from approximately 0.01 Ohms to approximately 10 Ohms. The predetermined power output is achieved by varying the number of transistors.

[0010] In some implementations, to power the excitation electrode, a reactance circuit is connected in series with the power transistor to eliminate the reactance of the excitation electrode. In the absence of plasma, the power transistor experiences a substantially low-resistivity load. The reactance circuit located between the output of the power transistor in a full-bridge or half-bridge configuration and the excitation electrode provides series resonance and generates a quality factor (Q) to eliminate the electrode's reactance. The reactance of the reactance circuit is designed to provide a high Q value at the operating frequency of the power generator. For example, in the absence of plasma ignition in the wafer fabrication chamber, this Q value is approximately between about 50 and about 500. The advantage of a high Q value is that the excitation electrode experiences a high voltage and electromagnetic field, which makes the plasma ignition in the chamber substantially instantaneous. Plasma in the wafer fabrication chamber is sustained after this substantially instantaneous ignition.

[0011] In many implementations, once the plasma is ignited, the operating frequency and agile DC rail voltage are adjusted to maintain a constant output power from the power transistor by measuring the phase difference between the complex voltage and complex current at the power transistor's output and maintaining a zero-degree phase difference. For example, a fast digital converter is used to measure the current input to the excitation electrode and to change the operating frequency to achieve a zero-degree phase difference.

[0012] In several implementations, the systems and methods described herein cover all plasma processing impedance ranges.

[0013] Other aspects will become clearer based on the subsequent implementation plan and accompanying drawings. Attached Figure Description

[0014] The implementation scheme can be understood by referring to the following description in conjunction with the accompanying drawings.

[0015] Figure 1 A pattern for an embodiment of a system for supplying power from a matchless plasma source to an electrode, wherein there is no coupled radio frequency (RF) matcher and RF cable between the matchless plasma source and the electrode.

[0016] Figure 2 This is a diagram illustrating the implementation scheme of the system, used to explain the details of the matchless plasma source.

[0017] Figure 3A This is a diagram illustrating the implementation scheme of the system, used to explain... Figure 2 Further details of the input, output, and reactance circuits of the matchless plasma source.

[0018] Figure 3B This is a diagram illustrating the implementation of a system, used to show the use of voltage and current probes, rather than the use of... Figure 3A Voltage and current (VI) probes in the system.

[0019] Figure 3C This is a diagram illustrating an implementation scheme of the system, used to explain the use of diodes for limiting. Figure 3A and 3B The voltage across the transistor in the half-bridge field-effect transistor (FET) circuit of the system.

[0020] Figure 3D The diagram illustrates an implementation scheme of the system, which is used to illustrate the use of a reactive circuit with an inductor coupled to a capacitively coupled plasma (CCP) chamber.

[0021] Figure 4A This is a graphical embodiment illustrating the shape of the envelope of an enlarged square waveform. Figure 3A and 3B It is generated at the output of the half-bridge FET circuit of the system.

[0022] Figure 4B This is a graphical implementation scheme used to illustrate the removal of higher harmonics from an amplified square waveform.

[0023] Figure 5A A graphical implementation scheme, used to illustrate from Figure 3A and 3B The system's reactive circuit outputs a pulse-shaped sine wave.

[0024] Figure 5B This is a graphical implementation scheme used to illustrate the triangular and sinusoidal waveforms output from the reactance circuit.

[0025] Figure 5C This is a graphical implementation scheme used to illustrate the multi-state pulse sinusoidal waveform output from the reactance circuit.

[0026] Figure 5D This is a graphical implementation scheme used to illustrate another multi-state pulse sine waveform output from the reactance circuit.

[0027] Figure 5E This is a graphical implementation scheme used to illustrate another multi-state pulse sinusoidal waveform output from the reactance circuit.

[0028] Figure 5F This is a graphical implementation scheme used to illustrate a sinusoidal waveform of arbitrary shape output from a reactive circuit.

[0029] Figure 5G This is a graphical implementation scheme used to illustrate a sinusoidal waveform of a continuous waveform output from a reactance circuit.

[0030] Figure 5HThis is a graphical implementation scheme used to illustrate the envelope of a pulse-shaped sinusoidal waveform output from a reactance circuit.

[0031] Figure 5I This is a graphical implementation scheme used to illustrate the envelope of a triangular sine wave output from a reactance circuit.

[0032] Figure 6A This is an embodiment of a resonance diagram, used to illustrate: in the absence of plasma, as the operating frequency of the signal generator changes, Figure 1 The change in the ratio of current to voltage at the electrodes in the plasma chamber of the system.

[0033] Figure 6B This is an embodiment of a resonance diagram used to illustrate the changes in voltage, current, and power at the electrodes as the operating frequency of the signal generator changes in the presence of plasma.

[0034] Figure 7A A graphical embodiment is provided to illustrate the use of... Figure 1 The system is the ion saturation current across the entire wafer surface.

[0035] Figure 7B This is a graphical implementation illustrating the ion saturation current when using a 50 Ohm RF generator, RF matcher, and RF cable.

[0036] Figure 8 This is a graphical implementation scheme used to illustrate: using Figure 1 The system helps achieve multiple tuning ranges of plasma impedance in the plasma chamber, and these tuning ranges are similar to those achieved using a 50 Ohm RF generator, RF matching unit, and RF cable.

[0037] Figure 9A This is a graphical embodiment illustrating the power supplied at the output of the reactor circuit to provide power to the electrodes.

[0038] Figure 9B This is a graphical embodiment used to illustrate the relationship between the voltage and time of a pulsed sinusoidal waveform supplied to the electrodes.

[0039] Figure 9C A graphical implementation scheme, used to illustrate from Figure 3A and 3B The output voltage of the system's power FET.

[0040] Figure 9D This is a graphical implementation of the scheme, used to illustrate the output current from the power FET.

[0041] Figure 10A This is a graphical implementation that illustrates the relationship between the operating frequency and time t during a pulse.

[0042] Figure 10B This is a graphical embodiment illustrating that the voltage and current supplied to the electrodes are in phase for a period of time to achieve the power level supplied to the electrodes.

[0043] Figure 10C This is a graphical embodiment illustrating that the voltage and current supplied to the electrodes are in phase during another time period to achieve the aforementioned power level.

[0044] Figure 10D This is a graphical embodiment illustrating that the voltage and current supplied to the electrodes are in phase during another time period to achieve the aforementioned power level.

[0045] Figure 11A This is a diagram illustrating a system implementation scheme, used to explain a tree with FETs and transformers for supplying power to the electrodes.

[0046] Figure 11B This is a diagram illustrating an implementation scheme of a system, which serves as another tree for illustrating a transistor circuit used to power the electrodes.

[0047] Figure 11C This is a diagram illustrating an implementation scheme of an H-bridge circuit used to supply power to the electrodes.

[0048] Figure 12A This is a diagram illustrating an implementation scheme of a system, used to explain a cooling plate for cooling a transistor circuit board.

[0049] Figure 12B-1 This is a side view of an implementation of a system used to illustrate the cooling of multiple integrated circuit wafers.

[0050] Figure 12B-2 for Figure 12B-1 The system shown is shown in top view from above.

[0051] Figure 12C This is a top isometric view of a system implementation, illustrating the cooling of an integrated circuit chip when it is mounted vertically on a printed circuit board.

[0052] Figure 12D This is a top isometric view of an implementation scheme for illustrating the cooling of an integrated circuit chip when a cooling plate is arranged adjacent to a vertically mounted plate.

[0053] Figure 12E This is a side view of an implementation scheme for cooling an integrated circuit chip.

[0054] Figure 12F This is a side view of one implementation scheme, which illustrates another implementation scheme for cooling an integrated circuit chip.

[0055] Figure 12G This is a side view of an implementation scheme for a system, illustrating yet another implementation scheme for cooling an integrated circuit chip.

[0056] Figure 12H This is a side view of an implementation of a system, illustrating a cooling plate and a container in which channels are milled.

[0057] Figure 13 An isometric view of the implementation scheme for the cooling plate.

[0058] Figure 14A This is a diagram illustrating an implementation scheme of an inductively coupled (ICP) / transformer-coupled (TCP) chamber and the use of a matchless plasma source.

[0059] Figure 14B The diagram illustrates an implementation of a system for use in an ICP chamber, wherein a matchless plasma source is coupled to a substrate support, and a TCP coil is coupled to an RF generator via an RF matcher.

[0060] Figure 14C The diagram illustrates an implementation of a system that demonstrates another use of an ICP chamber, in which a matchless plasma source is coupled to a substrate support and another matchless plasma source is coupled to a TCP coil.

[0061] Figure 14D This is a diagram illustrating a system implementation scheme, used to explain the coupling between a matchless plasma source and a Faraday shield.

[0062] Figure 14E This is a diagram illustrating a system implementation scheme, used to explain multiplexing operation, in which different TCP coils of the TCP plasma chamber operate in a multiplexed manner.

[0063] Figure 15A This is a diagram illustrating a system implementation scheme, used to explain the use of a matchless plasma source and a CCP chamber.

[0064] Figure 15B This is a diagram illustrating an implementation of a system that demonstrates the use of a matchless plasma source and a CCP chamber, wherein the matchless plasma source is coupled to a substrate support.

[0065] Figure 15CThe diagram illustrates an implementation of a system for using a matchless plasma source and a CCP chamber, wherein a matchless plasma source is coupled to a substrate support and another matchless plasma source is coupled to the upper electrode of the CCP chamber.

[0066] Figure 15D This is a diagram illustrating an implementation scheme of a system used to illustrate the coupling between a matchless power source and an RF power supply to a substrate support of a CCP chamber.

[0067] Figure 15E This is a diagram illustrating an implementation scheme of a system used to illustrate the coupling between a matchless power source and an RF power supply to the upper electrode of the CCP chamber.

[0068] Figure 15F This is a diagram illustrating an implementation of a system, used to illustrate the coupling of a matchless power source and an RF power supply to the upper electrode of the CCP chamber, and the coupling of another matchless power source and another set of RF power supplies to the substrate support of the CCP chamber.

[0069] Figure 16A The diagram illustrates an implementation of a system for a plasma chamber with a nozzle coupled to a matchless plasma source.

[0070] Figure 16B This is a diagram illustrating a system implementation scheme. Figure 16A The plasma chamber in which a matchless plasma source is coupled to a substrate support instead of a nozzle.

[0071] Figure 16C This is a diagram illustrating a system implementation scheme. Figure 16A The plasma chamber has a matchless plasma source coupled to a substrate support and another matchless plasma source coupled to a nozzle.

[0072] Figure 17A This is a diagram illustrating a system implementation scheme, used to explain the coupling of multiple matchless plasma sources with multiple micro-sources.

[0073] Figure 17B This is a diagram illustrating an implementation of a system, used to explain the coupling of a substrate support with a 50 Ohm RF generator and a matchless plasma source.

[0074] Figure 17C The diagram illustrates an implementation of a system that provides RF power from a matchless plasma source to a grid within a chuck and from a 50 Ohm RF generator to the cathode of the chuck.

[0075] Figure 18This is a diagram illustrating an implementation scheme for a system used to explain a housing for accommodating a power supply without a matcher.

[0076] Figure 19 This is a block diagram illustrating an implementation scheme for an RF cable and an RF matching device. Detailed Implementation Plan

[0077] The following embodiments describe a matchless plasma source for coupling to electrodes. It should be understood that electrodes can take many forms and can be integrated into many types of systems to provide radio frequency (RF) power. More broadly, electrodes can also be referred to as antennas, receiving RF power via an electrical connection. In the context of the several embodiments described herein, RF power is supplied to the electrodes of the chamber to ignite the plasma to perform one or more processing operations. For example, the delivered RF power can be used to ignite the plasma to perform etching operations, deposition operations, chamber cleaning operations, and other operations described in this application. Examples of matchless plasma sources (MPS) will be described, illustrating useful constructive embodiments and usage methods for efficient RF power delivery and precise, controlled ignition of the plasma. It is apparent that the invention can be practiced without some or all of these specific details. In other examples, well-known processing operations will not be described in detail to avoid unnecessarily obscuring the invention.

[0078] Matchless plasma sources offer several technological advantages, including a high quality factor that results in high current and voltage for plasma pre-excitation. These advantages also include an optimal quality factor for plasma sustainability, ensuring stable processing operations. Furthermore, they offer lower costs for higher-performance plasma tools. Matchless plasma sources also feature low output impedance. Additionally, the use of matchless plasma sources eliminates the need for radio frequency (RF) matchers and RF cables.

[0079] A matchless plasma source is configured to increase impedance tuning speed, provide enhanced pulse capability, and offer multiplexing of coil power. The matchless plasma source is configured to connect to electrodes such as nozzles, coils, antennas, or wafer platforms. No RF cable or RF matcher is required between the matchless plasma source and the plasma chamber. The absence of an RF matcher and RF cable reduces (e.g., eliminates) the chance of any power being reflected from the plasma chamber toward the matchless plasma source. Impedance tuning speed is increased due to the absence of an RF matcher. RF matchers have numerous circuit components, some of which are adjusted to tune the impedance associated with the plasma chamber. These adjustments reduce impedance tuning speed. The system and method described herein lack an RF matcher to increase impedance tuning speed. Furthermore, the cost of an RF matcher and RF cable is saved.

[0080] The matchless plasma source has an input section and an output section. The input section has a signal generator that operates at a driving frequency. The reactive circuit associated with the output section generates a high quality factor (Q) in the absence of plasma. The high Q value generated by the reactive circuit at the driving frequency helps to provide a high voltage to the electrodes. The high voltage provided to the electrode surfaces is highly advantageous for plasma ignition within the plasma chamber.

[0081] Furthermore, the output section includes a half-bridge field-effect transistor (FET) circuit. Once the plasma is ignited in the plasma chamber, the drive frequency is adjusted to maintain a constant output power from the half-bridge FET circuit. For example, a fast digital converter is coupled to the output of the half-bridge FET circuit to measure the input current and input voltage waveforms. The input current and voltage waveforms are measured as the drive frequency is changed until the phase difference between the input current and input voltage waveforms is zero. Therefore, by controlling the phase difference to zero, the desired constant power is provided to the electrodes.

[0082] Furthermore, the electrodes are driven by different types of waveforms to support different types of processes, such as etching, cleaning, sputtering, and deposition. For example, pulses of arbitrary shapes or multi-state pulses are generated at the output of the half-bridge FET circuit. Therefore, pulses of different shapes and power levels are used to drive the electrodes. Different waveforms are generated by controlling the amount of direct current (DC) voltage provided at the output of the agile DC rail within the half-bridge FET circuit. The DC voltage is controlled by a controller board that provides the voltage value to the DC source of the agile DC rail. In addition, the drive frequency is tuned at a high rate (e.g., less than 10 microseconds) to tune the impedance associated with the plasma chamber.

[0083] Figure 1This diagram illustrates an embodiment of a system 100 for supplying power from a matchless plasma source 102 to an electrode 106. The system 100 includes a matchless plasma source 102 and a plasma chamber 104. An example of the matchless plasma source 102 is a low-impedance voltage source. Examples of the plasma chamber 104 include a capacitively coupled plasma (CCP) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, a transformer-coupled plasma (TCP) reactor, a plasma-assisted chemical vapor deposition (PECVD) chamber, a plasma etching chamber, a plasma deposition chamber, or a plasma-assisted atomic layer deposition (PEALD) chamber. Furthermore, examples of the electrode 106 include a nozzle, a chuck, a substrate support, a capacitive upper electrode, a transformer-coupled plasma (TCP) coil, and a wafer platform. The matchless plasma source 102 is coupled to the electrode 106 via a connection 110 (e.g., a wire, an RF strip, a pillar, a bridging conductor, or a combination thereof).

[0084] It should be noted that there is no RF matching device between the unmatched plasma source 102 and the plasma chamber 104. Furthermore, there is no RF cable coupling the unmatched plasma source to the antenna. An RF matching device comprises multiple circuit components (e.g., inductors and capacitors) to match the impedance of a load (e.g., the plasma chamber) to the impedance of a source (e.g., the RF generator and the RF cable), wherein the load is coupled to the output of the RF matching device, and the source is coupled to the input of the RF matching device. Most of the power generated by the unmatched plasma source 102 is applied to the electrode 106. For example, since there is no RF matching device and RF cable between the unmatched plasma source 102 and the electrode 106, power is effectively applied from the unmatched plasma source 102 to the electrode 106.

[0085] A substrate 108 (e.g., a wafer) on which an integrated circuit is fabricated is placed on the top surface of or below the electrodes 106 within the plasma chamber 104. A matchless plasma source 102 operates at an operating frequency ranging from 50 kHz to 100 MHz to generate a shaped sine wave, which is an RF signal. The shaped sine wave is supplied from the matchless plasma source 102 to the electrodes 106 via a connection 110 to process the substrate 108. Examples of processing the substrate 108 include depositing material on the substrate 108, etching the substrate 108, cleaning the substrate 108, and sputtering the substrate 108.

[0086] Figure 2This diagram illustrates an embodiment of system 200, detailing the matchless plasma source 102. System 200 includes the matchless plasma source 102, a connection 110, and a plasma chamber 104. The matchless plasma source 102 includes an input 202, an output 204, and a reactor circuit 206. The input 202 is coupled to the output 204, and the output 204 is further coupled to the reactor circuit 206. The reactor circuit 206 is coupled to an electrode 106 via the connection 110.

[0087] Input section 202 includes a portion of a signal generator and a gate driver. Output section 204 includes the remainder of the gate driver and a half-bridge transistor circuit. An example of reactance circuit 206 includes a variable capacitor. Another example of reactance circuit 206 includes a fixed capacitor. Yet another example of reactance circuit 206 includes multiple capacitors and / or inductors coupled to each other in series, parallel, or a combination thereof. Some capacitors are variable, while the remaining capacitors are fixed. In another example, all capacitors are either variable or fixed. Similarly, some inductors are variable, while the remaining inductors are fixed. In another example, all inductors are either variable or fixed.

[0088] Input unit 202 generates multiple square wave signals and provides these square wave signals to output unit 204. Output unit 204 generates an amplified square wave waveform based on the multiple square wave signals received from input unit 202. Furthermore, output unit 204 shapes the envelope (e.g., peak-to-peak amplitude) of the amplified square wave waveform. For example, a shaping control signal 203 is supplied from input unit 202 to output unit 204 to generate the envelope. The shaping control signal 203 has multiple voltage values ​​to shape the amplified square wave waveform.

[0089] The shaped, amplified square waveform is transmitted from the output unit 204 to the reactor circuit 206. The reactor circuit 206 removes (e.g., filters) the higher harmonics of the amplified square waveform to generate a shaped sine wave with a fundamental frequency. The shaped sine wave has a shaped envelope.

[0090] A shaped sinusoidal waveform is transmitted from the reactance circuit 206 to the electrode 106 via the connection portion 110 to process the substrate 108. For example, one or more processing materials (such as fluorine-containing gas, oxygen-containing gas, nitrogen-containing gas, liquid, etc. used for metal and dielectric deposition) are supplied to the plasma chamber 104. After receiving the shaped sinusoidal waveform and the processing material, the plasma is ignited in the plasma chamber 104 to process the substrate 108.

[0091] Furthermore, the reactance of the reactance circuit 206 is modified by transmitting the quality factor control signal 207 from the input unit 202 to the reactance circuit 206, thereby changing the reactance of the reactance circuit 206. In some embodiments, a feedback signal 205 is transmitted from the output O1 of the output unit 204 to the input unit 202. A phase difference is identified or determined based on the feedback signal 205 to control the output unit 204 to reduce (e.g., eliminate) the phase difference.

[0092] In many embodiments, in addition to or in place of feedback signal 205, an optional feedback signal 209 is provided from the output of reactor circuit 206 to input section 202.

[0093] In some implementations, the input section 202 includes a controller board with a signal generator and further includes a gate driver, while the output section includes a half-bridge transistor circuit.

[0094] Figure 3A This diagram illustrates an embodiment of system 300, providing further details regarding input section 202, output section 204, and reactance circuit 206. Input section 202 includes a portion of controller board 302 and gate driver 311. Gate driver 311 is coupled to controller board 302. Output section 204 includes the remainder of gate driver 311 and a half-bridge field-effect transistor (FET) circuit 318. The half-bridge FET circuit 318, sometimes referred to herein as an amplifier circuit, is coupled to gate driver 311.

[0095] Reactor circuit 206 includes capacitor 322A, which is a variable capacitor. Controller board 302 includes controller 304, signal generator 306, and frequency input 308. Examples of controllers used herein include processors and memory devices. Other examples of controllers include microprocessors, application-specific integrated circuits (ASICs), central processing units, processors, programmable logic devices (PLDs), or ideally, a field-programmable gate array (FPGA). Signal generator 306 is a square wave oscillator that generates square wave signals, such as digital waveforms or pulse trains. The square wave pulses between a first logic level (e.g., one or high) and a second logic level (e.g., zero or low). Signal generator 306 generates square wave signals at operating frequencies (e.g., 400 kHz, or 2 MHz, or 13.56 MHz, or 27 MHz, or 60 MHz).

[0096] Gate driver 311 includes a portion of a primary winding 316A having a gate driver sub-section 310, a capacitor 312, a resistor 314, and a transformer 316. Furthermore, gate driver 311 includes the remaining portion containing secondary windings 316B and 316C of the transformer 316. Gate driver sub-section 310 includes a plurality of gate drivers 310A and 310B. Each of gate drivers 310A and 310B is coupled to a positive voltage source at one end and to a negative voltage source at the opposite end.

[0097] The half-bridge FET circuit 318 includes FETs 318A and FET 318B, which are coupled to each other in a push-pull configuration. Examples of FETs include metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, each FET in the half-bridge FET circuit 318 is made of silicon carbide, silicon, or gallium nitride. Each FET 318A and FET 318B has an output impedance falling within a predetermined range (e.g., from 0.01 ohms to 10 ohms). Furthermore, the half-bridge FET circuit 318 includes a DC rail 313 (shown in the dashed area) containing a voltage source Vdc and a conductive component 319 (such as a wire) coupled to the drain terminal D and source terminal S of FET 318A. Additionally, the conductive component 319 is coupled to the drain terminal D and source terminal S of FET 318B. The source terminal S of FET 318A is coupled to the drain terminal D of FET 318B, and the source terminal S of FET 318 is coupled to ground potential. Within plasma chamber 104, electrode 106 is illustrated as a TCP coil, but could be an electrode in a CCP configuration.

[0098] System 300 also includes a voltage and current (VI) probe 324 coupled to the output O1 of a half-bridge FET circuit 318. This VI probe 324 is a sensor that measures the complex current at output O1, the complex voltage at output O1, and the phase difference between the complex voltage and the complex current. The complex current has both amplitude and phase. Similarly, the complex voltage has both amplitude and phase. Output O1 is located between the source terminal S of FET 318A and the drain terminal D of FET 318B. The VI probe 324 is coupled to a controller 304.

[0099] Controller 304 is coupled to signal generator 306 to provide frequency input 308 (such as the operating frequency) to signal generator 306. Controller 304 is further coupled via wire to voltage source Vdc of DC rail 313. Additionally, signal generator 306 is coupled at its output to gate drivers 310A and 310B. Gate driver 310A is coupled to capacitor 312, while gate driver 310B is coupled to resistor 314. Capacitor 312 and resistor 314 are coupled to primary winding 316A of transformer 316.

[0100] Furthermore, the secondary winding 316B of transformer 316 is coupled to the gate terminal of FET 318A, while the secondary winding 316C of transformer 316 is coupled to the gate terminal of FET 318B. The output O1 of the half-bridge FET circuit 318 is coupled to capacitor 322A, and capacitor 322A is coupled to the TCP coil of electrode 106 via connection portion 110.

[0101] Controller 304 generates a setting (such as frequency input 308) and provides frequency input 308 to signal generator 306. Frequency input 308 is a numerical value of the operating frequency, such as 2MHz or 13.56MHz. After receiving the setting from controller 304, signal generator 306 generates an input RF signal with the operating frequency. This input RF signal is a square wave signal. Gate drivers 310A and 310B amplify this input RF signal to generate an amplified RF signal, and provide this amplified RF signal to the primary winding 316A of transformer 316.

[0102] Based on the directionality of the current flow in the amplified RF signal, the secondary winding 316B or the secondary winding 316C generates a gate drive signal with a threshold voltage. For example, when the current in the amplified RF signal flows from the positive terminal (represented by a point) of the primary winding 316A to the negative terminal (not a point) of the primary winding 316A, the secondary winding 316B generates a gate drive signal 315A with a threshold voltage to turn on the FET 318A, while the secondary winding 316C does not generate a threshold voltage and the FET 318B is not turned on. On the other hand, when the current in the amplified RF signal flows from the negative terminal to the positive terminal of the primary winding 316A, the secondary winding 316C generates a gate drive signal 315B with a threshold voltage to turn on the FET 318B, while the secondary winding 316B does not generate a threshold voltage and the FET 318A is not turned on.

[0103] Each gate drive signal 315A and 315B is a square wave, for example, a digital signal or pulse signal with an operating frequency. For example, each gate drive signal 315A and 315B transitions between a low level and a high level. The gate drive signals 315A and 315B have operating frequencies and are anti-synchronized relative to each other. For example, gate drive signal 315A transitions from a low level (e.g., a low power level) to a high level (e.g., a high power level). During the period or time that gate drive signal 315A transitions from a low level to a high level, gate drive signal 315B transitions from a high level to a low level. Similarly, during the period or time that gate drive signal 315A transitions from a high level to a low level, gate drive signal 315B transitions from a low level to a high level. This anti-synchronization allows FETs 318A and 318B to be continuously turned on and continuously turned off.

[0104] FETs 318A and 318B are operated sequentially. For example, when FET 318A is turned on, FET 318B is turned off, and when FET 318B is turned on, FET 318A is turned off. For instance, during the period when FET 318A is turned on, FET 318B is turned off. Furthermore, during the period when FET 318B is turned on, FET 318A is turned off. FETs 318A and 318B are not turned on at the same time or during the same period.

[0105] When FET 318A is turned on, current flows from the voltage source Vdc to the output O1 to generate a voltage at output O1, and FET 318B is not turned on. The voltage at the output is generated based on the voltage value received from the controller 304 or an arbitrary waveform generator (described further below). When FET 318B is not turned on, no current flows from output O1 to the ground potential coupled to FET 318B. Current flows from output O1 to capacitor 322A. When FET 318A is turned on, current is pushed from the voltage source Vdc to capacitor 322A. Furthermore, when FET 318B is turned on, the voltage generated at output O1 generates current that flows from output O1 to the ground potential coupled to FET 318B, and FET 318A is not turned on. Current is pulled from output O1 to ground potential. During the period when FET 318A is not conducting, no current flows from the voltage source Vdc to the output O1.

[0106] Furthermore, controller 304 generates a control signal (such as shaping control signal 203) with a voltage value and provides this control signal to voltage source Vdc via a wire coupling voltage source Vdc to controller 304. The voltage value is in, for example, a range of zero to eighty volts, causing agile DC rail 313 to operate within this range. The voltage value is the amplitude of the voltage signal generated by voltage source Vdc, used to define the shaping envelope of the voltage signal to further define the shaping envelope of the amplified square waveform at output O1. For example, to generate a continuous waveform at output O1, the voltage value provides the peak-to-peak amplitude of the continuous waveform. The peak-to-peak amplitude defines the shaping envelope of the continuous waveform. In another example, to generate an amplified square waveform with a pulse-shaped shaping envelope at output O1, the voltage value is changed substantially instantaneously (e.g., during a time period or a predetermined time interval) to cause the peak-to-peak amplitude of the amplified square waveform to change from a first parameter level (e.g., high level) to a second parameter level (e.g., low level), or from a second parameter level to a first parameter level. In yet another example, to generate an amplified square waveform with an arbitrarily shaped envelope at output O1, the voltage value is arbitrarily changed by controller 304 to change the peak-to-peak amplitude of the amplified square waveform in a desired manner. When generating an amplified square waveform of arbitrary shape, controller 304 acts as an arbitrary waveform generator. In yet another example, to generate an amplified square waveform with a shaped envelope of multi-state pulse shapes at output O1, the voltage value is changed substantially instantaneously (e.g., at one moment) to change the peak-to-peak amplitude of the amplified square waveform from a high parameter level to one or more intermediate levels, and then from one or more intermediate levels to another level (such as a low parameter level or a high parameter level). It should be noted that the amplified square waveform with a shaped envelope of multi-state pulse shapes has any number of states, for example, in the range of two to one thousand.

[0107] The parameter levels used in this document include one or more parameter values, but do not include one or more parameter values ​​from another parameter level. For example, the power at one parameter level may be greater or less than the power at different parameter levels. Examples of parameters include current, voltage, and power.

[0108] An amplified square waveform is generated at output O1 by continuously operating FETs 318A and 318B based on gate drive signals 315A and 315B, and by controlling the agile DC voltage rail voltage Vdc to change the voltage value. The amplification of the amplified square waveform is based on the output impedance of the FETs in the half-bridge FET circuit 318, the voltage value supplied to the voltage source Vdc by the controller 304, and the maximum achievable voltage value of the voltage source Vdc. The amplified square waveform has a shaped envelope. Capacitor 322A, combined with the inductance of the TCP coil, receives the amplified square waveform and reduces (e.g., removes or filters) the higher harmonics of the amplified square waveform to generate a shaped sine wave with a fundamental frequency. The shaped sine wave also has a shaped envelope. The shaped sine wave is supplied from the output of capacitor 322A to the TCP coil of electrode 106 via connection 110 to ignite or sustain the plasma within plasma chamber 104. The plasma is used to process substrate 108 ( Figure 1 ).

[0109] The VI probe 324 measures the complex voltage and complex current of the amplified square waveform at output O1 and provides a feedback signal 205 (containing the complex voltage and complex current) to the controller 304. The controller 304 identifies the phase difference between the complex voltage and complex current of the amplified square waveform based on the complex voltage and complex current received from the VI probe 324 and determines whether the phase difference is within a predetermined limit. For example, the controller 304 determines whether the phase difference is zero or within a predetermined percentage of zero. Once it is determined that the phase difference is not within the predetermined limit, the controller 304 changes the frequency value of the operating frequency to change the frequency input 308. The changed frequency value is provided from the controller 304 to the signal generator 306 to change the operating frequency of the signal generator 306. The operating frequency is changed, for example, within 10 microseconds. The operating frequency of the signal generator 306 is changed until the controller 304 determines that the phase difference between the complex voltage and complex current measured by the VI probe 324 is within the predetermined limit. Once it is determined that the phase difference between the complex voltage and the complex current is within a predetermined limit, the controller 304 will no longer change the frequency input 308. When the phase difference is within the predetermined limit, a predetermined amount of power is provided from the output O1 to the electrode 106 via the reactor circuit 206.

[0110] In addition to changing the frequency input 308, or instead of changing the frequency input 308, the controller 304 is modified by altering the voltage value supplied to the agile DC rail voltage Vdc, thereby changing the voltage signal generated by the voltage source Vdc. Upon receiving the modified voltage value, the voltage source Vdc modifies the voltage signal to have the modified voltage value. The controller 304 continues to change the voltage value until a predetermined power setpoint is reached. The predetermined power setpoint is stored in the memory device of the controller 304.

[0111] In many embodiments, the current of the amplified waveform is changed, rather than the voltage of the amplified waveform at output O1. For example, a voltage change controls the change in current of the amplified waveform generated at output O1 of the half-bridge FET circuit 318. For instance, the voltage value is changed to achieve a predetermined current value of the amplified waveform at output O1. The predetermined current value is stored in the memory device of controller 304. Furthermore, in some embodiments, the power of the amplified waveform is changed, rather than the voltage of the amplified waveform at output O1. For instance, a voltage change controls the change in power of the amplified waveform generated at output O1. For instance, the voltage value is changed to achieve a predetermined power value of the amplified waveform at output O1. The predetermined power value is stored in the memory device of controller 304. It should be noted that any change in the voltage, current, or power of the amplified waveform generated at output O1 causes the same change in the voltage, current, or power of the shaped sinusoidal waveform generated at the output of reactance circuit 206.

[0112] In some embodiments, controller 304 is coupled to reactance circuit 206 via a motor driver and a motor. An example of a motor driver includes one or more transistors. Controller 304 transmits a signal (such as a quality factor control signal 207) to the motor driver to generate a current signal, which is transmitted from the motor driver to the motor. Upon receiving the current signal, the motor operates to change the reactance of reactance circuit 206. For example, the motor is operated to change the area between the plates of capacitor 322A, thereby changing the capacitance of reactance circuit 206. In another example, the motor is operated to change the inductance of the inductor in reactance circuit 206. For example, the reactance of reactance circuit 206 is changed to maintain a predetermined quality factor (such as a high quality factor) for reactance circuit 206. In yet another example, the reactance of reactance circuit 206 is changed based on the type of plasma chamber to which reactance circuit 206 is coupled (such as CCP or ICP).

[0113] Capacitor 312 and Resistor 314

[0114] Capacitor 312 has a capacitance that reduces (e.g., eliminates or removes) the inductance of the primary winding 316A. Reducing the inductance of the primary winding 316A helps in the generation of the square wave signals 315A and 315B. Furthermore, resistor 314 reduces the oscillation of the square wave signal generated by signal generator 306.

[0115] Agile DC Rail 313

[0116] The DC rail 313 is agile because the controller 304 can quickly control the voltage source Vdc. Both the controller 304 and the voltage source Vdc are electronic circuits, allowing the controller 304 to control the voltage source Vdc substantially instantaneously. For example, when the controller 304 transmits a voltage value to the voltage source Vdc, the voltage source Vdc causes a voltage change in the voltage signal generated by the voltage source.

[0117] 320 resistors

[0118] Resistor 320 is sensed by the output O1 of the half-bridge FET circuit 318. Resistor 320 is the stray resistance in electrode 106, in the plasma ignited in plasma chamber 104, and in connection 110.

[0119] 322A capacitor

[0120] The capacitor 322A, combined with the inductance of the TCP coil, has a high quality factor (Q). For example, the amount of power lost in the amplified square waveform within the capacitor 322A is low compared to the amount of power transmitted to the electrode 106 via the capacitor 322A. The power of the amplified square waveform is transmitted via a shaped sine wave, which is output from the capacitor 322A to the electrode 106. This high quality factor of the circuit contributes to the rapid ignition of the plasma within the plasma chamber 104. Furthermore, the capacitance of the capacitor 322A eliminates the inductive reactance resonance of the TCP coil and the plasma (when ignited) within the plasma chamber 104. For example, the reactance circuit 206 has reactance that reduces (e.g., removes or eliminates) the reactance of the electrode 106, the reactance of the connection 110, the reactance of the plasma (when ignited), or a combination thereof within the plasma chamber 104. The reactance of the reactance circuit 206 is achieved by adjusting the capacitance of the capacitor 322A. In the CCP chamber example, the reactance circuit 206 includes one or more inductors, and the reactance of the inductors is achieved by adjusting the inductance of one or more inductors. Due to the reduced reactance, output O1 senses resistance 320 without sensing any reactance.

[0121] FET 318A and 318B

[0122] In some implementation schemes, the following are... Figure 11A and 11BThe individual FETs in the half-bridge FET circuit 318 or tree described herein are made of silicon carbide. Silicon carbide FETs have low internal resistance and fast switching times. The low internal resistance provides high efficiency, which causes the FETs to turn on nearly instantaneously (e.g., in less than 10 microseconds) and turn off quickly. For example, the individual FETs described herein turn on or off in less than a predetermined period of time (e.g., less than 10 microseconds). For instance, the individual FETs turn on or off in a period of time between about 1 microsecond and about 5 microseconds. In another example, the individual FETs turn on or off in a period of time between about 3 microseconds and about 7 microseconds. In yet another example, the individual FETs turn on or off in a period of time between about 0.5 microseconds and about 10 microseconds. Due to the fast turn-on and turn-off, the delays in the transition from turn-on to turn-off and from turn-off to turn-on are minimal (e.g., zero). For example, FET 318A may be turned on simultaneously with or during a period when FET 318B is turned off, and FET 318A may be turned off simultaneously with or during a period when FET 318B is turned on. When the on-times of FETs 318A and 318B overlap, a shoot-through effect occurs, which can damage the FET. Near-instantaneous on and off of the FET reduces the chance of a shoot-through effect, thus reducing the chance of damage. Furthermore, silicon carbide FETs are easier to cool. For example, the low internal resistance of silicon carbide FETs reduces the heat generated by them. Therefore, it is easier to use cooling plates or heat sinks to cool silicon carbide FETs.

[0123] The components (e.g., transistors) of the matchless plasma source 102 are electronic devices. Furthermore, there is no RF matcher or RF cable between the matchless plasma source 102 and the electrode 106. These electronic components, and the absence of the RF matcher and RF cable, promote reproducibility and consistency, thereby facilitating rapid plasma ignition and plasma sustainability.

[0124] In some implementations, multiple controllers are used in addition to or in place of controller 304. For example, one of the multiple controllers is coupled to a voltage source Vdc, while another of the multiple controllers is coupled to a signal generator 306 to provide a frequency input 308. For instance, controller 304 is coupled to an arbitrary waveform generator (e.g., a digital signal processor) and to a frequency controller. The frequency controller is coupled to signal generator 306. Controller 304 sends a signal to the arbitrary waveform generator and another signal to the frequency controller. Upon receiving this signal from controller 304, the arbitrary waveform generator generates a voltage value for a shaping control signal 203 to shape the amplified square waveform at output O1. Furthermore, upon receiving this other signal from controller 304, the frequency controller generates a frequency value for a square wave signal, which is generated by signal generator 306, to reduce the phase difference between the complex voltage and complex current received in feedback signal 205.

[0125] In many implementations, the controller 304 and the signal generator 306 are fabricated on different circuit boards.

[0126] In some embodiments, instead of using a transformer 316 as part of the gate driver 311, transistors (such as FETs or insulated gate bipolar transistors (IGBTs)) are coupled to each other to form part of the gate driver 311.

[0127] In some embodiments, instead of FETs, another type of transistor is used, such as IGBTs or metal-semiconductor field-effect transistors (MESFETs) or junction field-effect transistors (JFETs).

[0128] In some implementations, instead of the half-bridge FET circuit 318, a tree-like circuit containing transistors is used as the other half-bridge. For example, the first column of the tree contains 32 transistors coupled to a first voltage source. Half of the 32 transistors are coupled to the secondary winding of the transformer in the same manner as FET 318A is coupled to the secondary winding 316B, while the other half of the 32 transistors are coupled to the secondary winding of the transformer in the same manner as FET 318B is coupled to the secondary winding 316C. The second column of the tree, located next to the first column, contains 16 transistors coupled to a second voltage source. Furthermore, the third column of the tree is located next to the second column and contains 8 transistors. The fourth column of the tree is located next to the third column and contains four transistors. The fifth column of the tree is located next to the fourth column and contains two transistors coupled to output O1.

[0129] In many implementations, instead of the VI probe 324, voltage and current sensors are coupled to the output O1.

[0130] In some embodiments, in addition to the series capacitor 322A, a parallel capacitor is also used. This parallel capacitor is coupled at one end to the connection 110 and at the other end to ground potential. In many embodiments, multiple parallel capacitors are used instead of a single parallel capacitor. These multiple parallel capacitors are coupled in series or in parallel with each other.

[0131] In many embodiments, in addition to or in place of capacitor 322A, inductors are coupled in series or in parallel with capacitor 322A to eliminate the reactance of electrode 106. In some embodiments, any number of inductors are coupled in series or in parallel with capacitor 322A to eliminate the reactance of electrode 106.

[0132] The FET described herein is n-type. In some embodiments, a p-type FET is used instead of an n-type FET. For example, in a half-bridge circuit, a voltage source Vdc is coupled to the source terminal of a p-type FET via conductive component 319. Furthermore, the drain terminal of the p-type FET is coupled to the source terminal of another p-type FET. The drain terminal of this other p-type FET is coupled to ground potential.

[0133] Figure 3B This diagram illustrates an implementation of system 348, showing the use of voltage probe 350 and current probe 352 instead of VI probe 324. Figure 3A System 348 is the same as system 300, except that in system 348, voltage probe 350 and current probe 352 are used instead of VI probe 324. Voltage probe 350 is a sensor coupled to the output O1 of the half-bridge FET circuit 318, used to measure the voltage of the amplified square waveform at output O1. Furthermore, current probe 352 is coupled to a point on connection 110, for example, to the output of reactance circuit 206. This point is located between reactance circuit 206 and electrode 106. Voltage probe 350 is coupled to controller 304 via a wire, and current probe 352 is coupled to controller 304 via a wire.

[0134] Voltage probe 350 measures the complex voltage of the amplified square waveform at output O1 and provides the complex voltage to controller 304. Furthermore, current probe 352 measures the complex current of the shaped sinusoidal waveform output by reactance circuit 206 and provides the complex current to controller 304. The complex voltage is provided to controller 304 in feedback signal 205, and the complex current is provided to controller 304 in optional feedback signal 209. Controller 304 identifies the phase of the complex voltage and the phase of the complex current, and determines the phase difference between the phases of the complex voltage and the complex current. Controller 304 controls the operating frequency of signal generator 306, or the amplitude of the parameter at output O1, or a combination thereof, to reduce the phase difference to within a predetermined limit.

[0135] Figure 3C A diagram illustrating an implementation of system 370, used to illustrate the use of diodes to limit the half-bridge FET circuit 318. Figure 3A , 3B And the voltage across FETs 318A and 318B (3D). System 370 and Figure 3A System 300 or Figure 3B The system is the same as system 348, but in system 370, multiple diodes D1 and D2 are used. Additionally, capacitor 372 is used in system 370. Diode D1 is coupled between the drain and source terminals of FET 318A, while diode D2 is coupled between the drain and source terminals of FET 318B. Furthermore, capacitor 372 is coupled to the drain terminal D of FET 318A and to the source terminal S of FET 318B.

[0136] When FET 318A is turned on and FET 318B is turned off, the voltage across FET 318A increases and continues to increase in the positive direction until the voltage is limited by diode D1. Similarly, when FET 318A is turned off and FET 318B is turned on, the voltage across FET 318B increases and continues to increase in the negative direction until the voltage is limited by diode D2. Therefore, diode D1 reduces (e.g., avoids) the chance of breakdown effect across FET 318A, and diode D2 reduces (e.g., avoids) the chance of breakdown effect across FET 318B.

[0137] If there is a delay between the turn-off and turn-on of FETs 318A and 318B, the current in DC rail 313 flows through capacitor 372, reducing the chance that current will flow from output O1 to electrode 106 via capacitor 322A. For example, during the period when both FETs 318A and FET 318B are either on or both are off, current flows from DC rail 313 to capacitor 372. This reduces the chance that current will flow to electrode 106.

[0138] It should be noted that Figure 3C The diode shown in the implementation scheme can be coupled to Figure 3A , 3B And the corresponding FET in any of the 3D implementation schemes.

[0139] Figure 3D This diagram illustrates an embodiment of system 380, showing a reactive circuit 206 with an inductor 382 coupled to plasma chamber 104 when plasma chamber 104 is a CCP plasma chamber. System 380 and Figure 3AThe system is the same as system 300, but in system 380, plasma chamber 104 is a CCP plasma chamber. When plasma chamber 104 is a CCP plasma chamber, reactance circuit 206 includes inductor 382 instead of capacitor 322A. Inductor 382 is coupled to output O1 and to electrode 106, such as the upper or lower electrode of the chuck of the CCP chamber.

[0140] In some embodiments, a variable inductor is used instead of inductor 382. The inductance of the variable inductor is controlled by controller 304 in the same way that controller 304 controls the capacitance of capacitor 322A. In many embodiments, reactance circuit 206 includes multiple inductors coupled in series, parallel, or a combination thereof. Some of these inductors are variable, while the rest are fixed. In another example, all the inductors in reactance circuit 206 are either variable or fixed.

[0141] Figure 4A As shown in the embodiment of figure 402, this illustrates the shaping of the envelope 408 of the amplified square waveform 406, which is formed in the half-bridge FET circuit 318. Figure 3A and 3B An example of the amplified square waveform produced at output O1 is shown. Figure 402 depicts the relationship between the parameters of the amplified square waveform 406 and time t. As shown, the amplified square waveform 406 transitions between multiple parameter levels (e.g., low level P1 and high level P2). Low level P1 has a lower peak-to-peak amplitude than high level P2.

[0142] It should be noted that in some implementations, instead of generating an amplified square waveform 406 with a shaped envelope 408, another amplified square waveform with a shaped envelope of a different shape (e.g., arbitrary shape, multi-level pulse shape, continuous waveform, or triangle) is generated.

[0143] Figure 4B The embodiment of figure 404 illustrates the removal of higher harmonics in the amplified square waveform 406, which is in the half-bridge FET circuit 318. Figure 3A and 3B The output O1 is generated. Figure 404 depicts the relationship between the parameters of the amplified square waveform 406 and time t. The amplified square waveform 406 consists of a waveform 408A with a fundamental frequency and numerous waveforms (e.g., waveforms 408B and 408C) with higher harmonic frequencies. Waveform 408B has a second harmonic frequency, and waveform 408C has a third harmonic frequency. Reactor circuit 206 ( Figure 3A and 3BThe high-quality factor helps remove high-order harmonics from the amplified waveform 406 to provide waveform 408A at the output of reactor circuit 206. Waveform 408A is supplied from reactor circuit 206 to electrode 106. Waveform 408A is an example of a shaped sine wave output from reactor circuit 206.

[0144] Figure 5A The illustration for diagram 502 illustrates a shaped sinusoidal waveform 504 with an envelope 506, which is an example of a shaped envelope. The shaped sinusoidal waveform 504 is derived from the reactance circuit 206 ( Figure 2 Example of a shaped sine wave output. Graph 502 depicts the relationship between the parameters of the shaped sine wave 504 and time t. The envelope 506 is a peak-to-peak parameter (e.g., peak-to-peak voltage) and has a square shape (e.g., pulse shape).

[0145] Figure 5B The embodiment of figure 508 is used to illustrate the triangular sine wave 510. The triangular sine wave 510 is derived from the reactance circuit 206 ( Figure 2 Example of a shaped sine wave output. Figure 508 depicts the relationship between the parameters of a triangular sine wave 510 and time t. The triangular sine wave 510 has a triangular envelope 512, which is an example of a shaped envelope.

[0146] In some implementations, from reactor circuit 206 ( Figure 2 The output shaped sine wave has a sawtooth waveform envelope.

[0147] Figure 5C Figure 514 illustrates an embodiment of a multi-state sinusoidal waveform 516. Figure 514 depicts the relationship between the parameters of the multi-state sinusoidal waveform 516 and time t. The multi-state sinusoidal waveform 516 originates from the reactance circuit 206 ( Figure 2 Example of a shaped sine wave output. The multi-state sine wave 516 has an envelope 518 having multiple states S1, S2, and S3. Envelope 518 is an example of a shaped envelope. The peak-to-peak parameter of the multi-state sine wave 516 during state S1 is greater than the peak-to-peak parameter of the multi-state sine wave 516 during state S2. Furthermore, the peak-to-peak parameter of the multi-state sine wave 516 during state S2 is greater than the peak-to-peak parameter of the multi-state sine wave 516 during state S3. States S1, S2, and S3 are below the signal generator 306 ( Figure 3A and 3B The operating frequency is repeated at the specified frequency. The shaped sine wave 516 has this operating frequency.

[0148] In some implementations, the peak-to-peak parameter of the multi-state sine waveform 516 during state S1 is different from (e.g., less than or greater than) the peak-to-peak parameter of the multi-state sine waveform 516 during state S2. Furthermore, the peak-to-peak parameter of the multi-state sine waveform 516 during state S2 is different from (e.g., greater than or less than) the peak-to-peak parameter of the multi-state sine waveform 516 during state S3. And, the peak-to-peak parameter of the multi-state sine waveform 516 during state S3 is different from (e.g., greater than or less than) the peak-to-peak parameter of the multi-state sine waveform 516 during state S1.

[0149] Figure 5D This is an embodiment of figure 520, used to illustrate a multi-state sinusoidal waveform 522. Figure 520 depicts the relationship between the parameters of the multi-state sinusoidal waveform 522 and time t. The multi-state sinusoidal waveform 522 is derived from the reactance circuit 206 ( Figure 2 Example of an output shaped sine wave. The multi-state sine wave 522 has an envelope 524 having multiple states S1, S2, S3, and S4. Envelope 524 is an example of a shaped envelope. The peak-to-peak parameter of the multi-state sine wave 522 during state S1 is greater than that during state S2. Furthermore, the peak-to-peak parameter of the multi-state sine wave 522 during state S2 is greater than that during state S3. Moreover, the peak-to-peak parameter of the multi-state sine wave 522 during state S3 is greater than that during state S4. For example... Figure 5D As shown, states S1, S2, S3, and S4 are below the signal generator 306 ( Figure 3A and 3B The operating frequency is repeated at the frequency of the 522-shaped sine wave.

[0150] In some implementations, the peak-to-peak parameter of the multi-state sine wave 522 during state S1 is different from (e.g., less than or greater than) the peak-to-peak parameter of the multi-state sine wave 522 during state S2. Furthermore, the peak-to-peak parameter of the multi-state sine wave 522 during state S2 is different from (e.g., greater than or less than) the peak-to-peak parameter of the multi-state sine wave 522 during state S3. And, the peak-to-peak parameter of the multi-state sine wave 522 during state S3 is different from (e.g., greater than or less than) the peak-to-peak parameter of the multi-state sine wave 522 during state S4. The peak-to-peak parameter of the multi-state sine wave 522 during state S4 is different from (e.g., greater than or less than) the peak-to-peak parameter of the multi-state sine wave 522 during state S1.

[0151] Figure 5EThis is an embodiment of Figure 524, used to illustrate the multi-state pulse of the shaped sinusoidal waveform 526. Figure 524 depicts the relationship between the parameters of the multi-state sinusoidal waveform 526 and time t. The shaped sinusoidal waveform 526 is derived from the reactance circuit 206 ( Figure 2 Example of an output shaped sine wave. The shaped sine wave 526 has a multi-state envelope 528 that alternates between states S1 to Sn, where n is an integer greater than one. For example, the multi-state envelope 528 transitions from state S1 to state S2. The multi-state envelope 528 further transitions from state S2 to state S3, and so on, until it reaches state Sn. In one example, the value of n is in the range of 4 to 1000. For example, the shaped sine wave 526 has 100 states. States S1 to Sn repeat periodically. Envelope 528 is an example of a shaped envelope.

[0152] It should be noted that the parameter levels (e.g., peak-to-peak parameter values) during one of the states S1 to Sn differ from the parameter levels during the other of the states S1 to Sn. For example, the peak-to-peak parameter values ​​during states S1 to S5 are different from each other. Figure 5E As shown, states S1 to Sn are below signal generator 306 ( Figure 3A and 3B The operating frequency is repeated at the same frequency. The shaped sine wave 526 has this operating frequency.

[0153] Figure 5F The diagram 530 illustrates an embodiment of the shaped sine wave 532, specifically its envelope 534. Envelope 534 is an example of a shaped envelope. The shaped sine wave 532 is derived from the reactance circuit 206 (…). Figure 2 Example of the output shaped sine wave. Graph 530 depicts the relationship between the parameters of the shaped sine wave 532 and time t.

[0154] The shaped sine wave 532 has an envelope 534, which has an arbitrary shape. For example, the envelope 534 has multiple states S1 to S8 that repeat periodically. During each state S1 and S2, the envelope 534 has a zero slope. Furthermore, during state S3, the envelope 534 has a positive slope, while during state S4, the envelope 534 has a negative slope. Moreover, during state S5, the envelope 534 has a positive slope. During state S6, the envelope 534 has a negative slope, while during state S7, the envelope 534 has a positive slope. During state S8, the envelope 534 has a negative slope. Figure 5F As shown, states S1 to S8 are below signal generator 306 ( Figure 3A and 3B The operating frequency is repeated at the specified frequency. The shaped sine wave 532 has this operating frequency.

[0155] It should be noted that in some implementations, during one or more of states S1 to S8, the envelope 534 has a relationship with... Figure 5F The slopes shown are different. For example, during state S4, the shaped sine wave 532 has a positive slope or a zero slope, but not a negative slope. In another example, during state S5, the shaped sine wave 532 has a negative slope or a zero slope, but not a positive slope.

[0156] Figure 5G Figure 536 illustrates a shaped sine wave 538 having a continuous waveform. For example, the shaped sine wave 538 has an envelope 540 that is continuous and not pulses from one parameter level to another. Further, the peak-to-peak parameters of the shaped sine wave 538 are constant or fall between that constant and a predetermined variable thereof. Envelope 540 is an example of a shaped envelope. Figure 536 depicts the relationship between the parameters of the shaped sine wave 538 and time t. The shaped sine wave 538 is derived from the reactance circuit 206 (… Figure 2 Example of the output shaped sine wave.

[0157] Figure 5H As shown in the embodiment of figure 540, which is used to illustrate the envelope 542 of the pulse-shaped sine wave, the pulse-shaped sine wave originating from the reactance circuit 206 ( Figure 2 Output. Graph 540 depicts the relationship between the power of the pulsed sinusoidal waveform and time t (measured in milliseconds). The pulsed sinusoidal waveform with envelope 542 and... Figure 5A The sine wave 504 is similar. Envelope 542 has a pulse shape and transitions between low and high states. The low state has a lower power level (e.g., one or more power amounts) than the high state. For example, all power amounts in the high state are in the range of 350 to 400 watts, while all power amounts in the low state are in the range of 80 to 120 watts.

[0158] Figure 5I The embodiment of figure 544 illustrates the envelope 546 of the shaped sine wave, which originates from reactance circuit 206 ( Figure 2 Output. Graph 544 depicts the relationship between the power of the shaped sine wave and time t (measured in milliseconds). The shaped sine wave with envelope 546 and... Figure 5B The sine wave 510 is similar. The envelope 546 is triangular. For example, the envelope 546 has a positive slope followed by a negative slope. After the negative slope, there is another positive slope, followed by another negative slope.

[0159] Figure 6A As shown in the embodiment of pattern 600, which is a resonance diagram, it is used to illustrate: with the signal generator 306 ( Figure 3Aand 3B The change in the operating frequency of electrode 106 ( Figure 1 The change in the ratio of current to voltage related to this. Graph 600 is shown in plasma chamber 104 ( Figure 1 The signal generator 306 is generated when no plasma is ignited. Current and voltage are measured at electrode 106. Graph 600 depicts the relationship between the magnitude of the current-to-voltage ratio and the operating frequency of the signal generator 306. Graph 600 shows that the quality factor Q of electrode 106 is high when the plasma is not ignited in plasma chamber 104.

[0160] Figure 6B As shown in the embodiment of pattern 602, which is a resonance diagram, it is used to illustrate: with the signal generator 306 ( Figure 3A and 3B The change in the operating frequency of electrode 106 ( Figure 1 The graph shows the changes in voltage, current, and power at electrode 106. Figure 602 depicts the relationship between the power, voltage, and current measured at electrode 106 and the operating frequency of signal generator 306. The graph also depicts the changes in voltage, current, and power at electrode 106 when the plasma is in plasma chamber 104. Figure 1 The power, voltage, and current during ignition in the signal generator 306 are measured. The operating frequency of the signal generator 306 is controlled by the controller 304. Figure 3A and 3B The system controls the power, voltage, and current measured at electrode 106. As can be seen from Figure 602, the quality factor Q at electrode 106 is lower than that shown in Figure 600 because the plasma in plasma chamber 104 consumes energy.

[0161] Figure 7A This is an embodiment of figure 702, used to illustrate the ion saturation current Isat (measured in milliamperes (mA)) across the entire wafer surface. Figure 702 depicts the plasma chamber 104 ( Figure 1 The relationship between the ion saturation current of different wafers processed in the plasma chamber 104 and the distance from the wafer center, and the plasma chamber 104 coupled to the unmatched plasma source 102. Figure 1 There is no RF matching device or RF cable between the unmatched plasma source 102 and the plasma chamber 104. The distance from the wafer center is measured in millimeters (mm). The effect of different power ratios on the radial ion saturation current is shown in... Figure 7A middle.

[0162] Figure 7B The embodiment of Figure 704 is used to illustrate when the RF matching unit and RF cable are used in system 1902 (as shown below). Figure 19The ion saturation current (in the middle). System 1902 includes RF cable 1908 and RF matching unit 1906 (in the middle). Figure 19 Figure 704 depicts the relationship between the ion saturation current and the distance from the wafer center. The effect of different power ratios on the radial ion saturation current is shown in Figure 704. It should be noted that when using System 100 (… Figure 1 When using system 1302 or system 1302, the ion saturation currents on the entire wafer surface are similar.

[0163] Figure 8 The following is an implementation scheme for Graphic 800, used to illustrate: Compared to implementations using an RF matcher, using... Figure 1 System 100 helps to realize plasma chamber 104 ( Figure 1 The similar tuning range of plasma impedance in plasma chamber 104. Figure 800 depicts the relationship between the reactance X and resistance R of the plasma in plasma chamber 104. Figure 800 includes multiple tuning ranges T1, T2, and T3 with plasma resistance and reactance values, and tuning ranges T1, T2, and T3 are when the unmatched plasma source 102 is coupled to plasma chamber 104 (e.g., ...). Figure 1 This is achieved as shown. All tuning ranges T1, T2, and T3 of the plasma's resistance and reactance are achieved by using... Figure 1 The system is implemented by 100.

[0164] Figure 9A The embodiment of figure 902 is used to illustrate the reactor circuit 206 ( Figure 2 Power is supplied at the output of ) to provide power to electrode 106 ( Figure 2 The power is shaped according to envelope 904. Graph 902 depicts the relationship between power and time t.

[0165] Figure 9B The embodiment of figure 906 is used to illustrate: supply to plasma chamber 104 ( Figure 1 The voltage of the shaped sinusoidal waveform is related to time t. The voltage has a pulse-shaped envelope 908, which further has an upper boundary 908A and a lower boundary 908B. Boundaries 908A and 908B define the peak-to-peak voltage.

[0166] Figure 9C The embodiment of Figure 910 is used to illustrate the use of a power FET (e.g., FET 318A or FET 318B). Figure 3A , 3B And 3D), at output O1 ( Figure 3A and 3BThe voltage provided. The voltage at output O1 has an envelope 912, which further has an upper boundary 912A and a lower boundary 912B. Boundaries 912A and 912B define the peak-to-peak voltage.

[0167] Figure 9D The embodiment of Figure 914 is used to illustrate the power FET ( Figure 3A , 3B And 3D), the current supplied at output O1. The voltage at output O1 has an envelope 916, which further has an upper boundary 916A and a lower boundary 916B. Boundaries 916A and 916B define the peak-to-peak current.

[0168] Figure 10A The embodiment of graphic 1000 is used to illustrate: signal generator 306 ( Figure 3A and 3B 1002 shows a graph illustrating the relationship between the operating frequency of the controller 304 and time t (measured in milliseconds (ms)). Figure 3A , 3B And 3D) tunes the operating frequency for less than a predetermined period of time (e.g., less than or equal to 50 microseconds (ms)). For example, any changes in the operating frequency of the signal generator 306 caused by the controller 304 are transmitted via the gate driver 311, the half-bridge FET circuit 318, and the reactance circuit 206 ( Figure 3A , 3B (And 3D) and transmitted to electrode 106 within 50 microseconds or less. This predetermined time period helps to achieve plasma impedance of the plasma in plasma chamber 104. Another example of a predetermined time period includes 100 microseconds. For example, the operating frequency is tuned within a time period between 10 microseconds and 100 microseconds. Yet another example of a predetermined time period includes 70 microseconds. For example, the operating frequency is tuned within a time period between 20 microseconds and 70 microseconds. When the operating frequency is tuned, there is self-adjustment of signal generator 306.

[0169] Figure 10B The embodiment of figure 1004 is used to illustrate: in the half-bridge FET circuit 318 ( Figure 3A , 3B The voltage signal 1006B and current signal 1006A measured at the output O1 of the 3D converter are in phase during the first time period to achieve the power level supplied to the electrode 106. Graph 1004 depicts the relationship between the current signal 1006A and the voltage signal 1006B and time t. As can be seen from Graph 1004, at time 0.95 milliseconds, both the current signal 1006A and the voltage signal 1006B are in phase.

[0170] Figure 10CAs illustrated in Figure 1008, voltage signal 1006B and current signal 1006A are in phase during a second time period to achieve the power level supplied to electrode 106. Figure 1008 depicts the relationship between current signal 1006A and voltage signal 1006B and time t. It can be seen from Figure 1008 that at approximately 1 millisecond, both current signal 1006A and voltage signal 1006B are in phase.

[0171] Figure 10D As illustrated in Figure 1010, voltage signal 1006B and current signal 1006A are in phase during the third time period to achieve the power level supplied to electrode 106. Figure 1010 depicts the relationship between current signal 1006A and voltage signal 1006B and time t. It can be seen from Figure 1010 that at a time of 1.05 milliseconds, both current signal 1006A and voltage signal 1006B are in phase. Therefore, it should be noted that during the first, second, and third time periods, current signal 1006A and voltage signal 1006B are in phase to achieve the required power level during these periods.

[0172] Figure 11A The diagram is for an embodiment of system 1100, which is used to illustrate the following trees 1101: FETs 1102A, 1102B, 1102C, 1102D, 1102E, 1102F, 1102G, 1102H, 1102I, 1102J, 1102K, 1102L, 1102M, 1102N, 1102O, and 1102P, and transformers 1106A, 1106B, 1106C, 1106D, 1106E, 1106F, and 1106G.

[0173] System 1100 includes a tree 1101, a capacitor 322A, and a plasma load. The plasma load, upon ignition, includes electrodes 106 and plasma. Tree 1101 includes multiple half-bridge circuits 1104A, 1104B, 1104C, 1104D, 1104E, 1104F, 1104G, and 1104H. Half-bridge circuit 1104A includes FETs 1102A and 1102B. Similarly, half-bridge circuit 1104B includes FETs 1102C and 1102D, half-bridge circuit 1104C includes FETs 1102E and 1102F, half-bridge circuit 1104D includes FETs 1102G and 1102H, and half-bridge circuit 1104E includes FETs 1102I and 1102J. In addition, the half-bridge circuit 1104F includes FETs 1102K and 1102L, the half-bridge circuit 1104G includes FETs 1102M and 1102N, and the half-bridge circuit 1104H includes FETs 1102O and 1102P.

[0174] The gate terminals of FETs 1102A, 1102C, 1102E, 1102G, 1102I, 1102K, 1102M, and 1102O are coupled to gate driver 1152A. Figure 11B ), and the gate terminals of FETs 1102B, 1102D, 1102F, 1102H, 1102J, 1102L, 1102N, and 1102P are coupled to another gate driver 1152B. Figure 11B ).

[0175] The output OUT1 of half-bridge circuit 1104A is coupled to the primary winding 1108A of transformer 1106A. Similarly, the output OUT2 of half-bridge circuit 1104B is coupled to the primary winding 1108B of transformer 1106A. Furthermore, the output OUT3 of half-bridge circuit 1104C is coupled to the primary winding 1108C of transformer 1106B, and the output OUT4 of half-bridge circuit 1104D is coupled to the primary winding 1108D of transformer 1106B. Additionally, the output OUT5 of half-bridge circuit 1104E is coupled to the primary winding 1108E of transformer 1106C, and the output OUT6 of half-bridge circuit 1104F is coupled to the primary winding 1108F of transformer 1106C. The output OUT7 of the half-bridge circuit 1104G is coupled to the primary winding 1108G of the transformer 1106D, and the output OUT8 of the half-bridge circuit 1104H is coupled to the primary winding 1108H of the transformer 1106D.

[0176] Furthermore, the secondary winding 1108H of transformer 1106A is coupled to the primary winding 1108L of transformer 1106E. Similarly, the secondary winding 1108I of transformer 1106B is coupled to the primary winding 1108M of transformer 1106E. Likewise, the secondary winding 1108J of transformer 1106C is coupled to the primary winding 1108N of transformer 1106F. And the secondary winding 1108K of transformer 1106D is coupled to the primary winding 1108O of transformer 1106F.

[0177] The secondary winding 1108P of transformer 1106E is coupled to the primary winding 1108R of transformer 1106G. Similarly, the secondary winding 1108Q of transformer 1106F is coupled to the primary winding 1108S of transformer 1106G. The secondary winding 1108T of transformer 1106G is coupled to capacitor 322A via output O1.

[0178] It should be noted that when FETs 1102A, 1102C, 1102E, 1102G, 1102I, 1102K, 1102M, and 1102O are turned on, FETs 1102B, 1102D, 1102F, 1102H, 1102J, 1102L, 1102N, and 1102P are not turned on. For example, during the time or period when FETs 1102A, 1102C, 1102E, 1102G, 1102I, 1102K, 1102M, and 1102O are turned on by a signal from gate driver 1152A, FETs 1102B, 1102D, 1102F, 1102H, 1102J, 1102L, 1102N, and 1102P are turned off by a signal from gate driver 1152B. Similarly, during the time or period when FETs 1102B, 1102D, 1102F, 1102H, 1102J, 1102L, 1102N, and 1102P are turned on by a signal from gate driver 1152B, FETs 1102A, 1102C, 1102E, 1102G, 1102I, 1102K, 1102M, and 1102O are turned off by a signal from gate driver 1152A.

[0179] When FETs 1102A, 1102C, 1102E, 1102G, 1102I, 1102K, 1102M, and 1102O are turned on, the positive voltages generated at outputs OUT1 and OUT2 are transformed by transformers 1106A, 1106E, and 1106G; the positive voltages generated at outputs OUT3 and OUT4 are transformed by transformers 1106B, 1106E, and 1106G; the positive voltages generated at outputs OUT5 and OUT6 are transformed by transformers 1106C, 1106F, and 1106G; and the positive voltages generated at outputs OUT7 and OUT8 are transformed by transformers 1106D, 1106F, and 1106G into the positive voltage at output O1.

[0180] Similarly, when FETs 1102B, 1102D, 1102F, 1102H, 1102J, 1102L, 1102N, and 1102P are turned on, the negative voltages generated at outputs OUT1 and OUT2 are transformed by transformers 1106A, 1106E, and 1106G; the negative voltages generated at outputs OUT3 and OUT4 are transformed by transformers 1106B, 1106E, and 1106G; the negative voltages generated at outputs OUT5 and OUT6 are transformed by transformers 1106C, 1106F, and 1106G; and the negative voltages generated at outputs OUT7 and OUT8 are transformed by transformers 1106D, 1106F, and 1106G into a negative voltage at output O1.

[0181] It should be noted that the voltage signal generated by the DC voltage source Vdc of tree 1101 is controlled by controller 304. Figure 3A , 3B And 3D), which is controlled by the same voltage signal generated by the voltage source Vdc (and 3D). Figure 3A , 3B Control can be achieved in a manner that includes 3D control. For example, controller 304 is coupled to the DC voltage source Vdc of tree 1101 to control the voltage signal generated by the DC voltage source.

[0182] It should be noted that the predetermined power level is achieved based on the following: the number of DC voltage sources in tree 1101, the number of FETs used in tree 1101, and the maximum achievable voltage of each voltage source in tree 1101. For example, the predetermined power level at output O1 varies with the number of half-bridge circuits used in tree 1101. For instance, as the number of half-bridge circuits increases, the number of FETs increases. As the number of FETs increases, the output impedance of the FETs increases. Furthermore, as the number of half-bridge circuits in tree 1101 increases, the number of DC voltage sources increases. Therefore, the predetermined power level achieved at output O1 changes.

[0183] In many embodiments, the maximum realizable voltage of a DC voltage source coupled to the half-bridge circuit of tree 1101 is different from the maximum realizable voltage of another DC voltage source coupled to another half-bridge circuit of tree 1101. For example, a voltage source with a maximum realizable voltage Vdc1 is coupled to half-bridge circuit 1104A, while another voltage source with a maximum realizable voltage Vdc2 is coupled to half-bridge circuit 1104B.

[0184] In some implementations, a predetermined number of FETs are integrated onto a single chip. For example, two FETs of a half-bridge circuit are integrated onto one chip, while two FETs of another half-bridge circuit are integrated onto another chip. In another implementation, four FET branches are integrated onto one chip, while another set of four FET branches are integrated onto another chip.

[0185] Figure 11B This diagram illustrates an implementation of system 1150, using a tree 1156 of FETs 318A, 318B, 318C, 318D, 318E, and 318F to generate an amplified square waveform at the O1 output. System 1150 and... Figure 3A System 300 or Figure 3B The system is the same as system 348, but system 1150 uses a larger number of FETs compared to systems 300 or 348. Furthermore, system 1150 uses gate drive circuitry 1158 instead of gate driver 311. Figure 3A , 3B And 3D). In the matchless plasma source 102 ( Figure 1 Within it, a gate drive circuit 1158 is used instead of a gate driver 311. Figure 3A , 3B And 3D). Furthermore, a tree 1156 is used within the matchless plasma source 102 instead of the half-bridge FET circuit 318 (and 3D). Figure 3A , 3B And 3D).

[0186] System 1150 includes gate drive circuitry 1158, a tree 1156, capacitor 322A, and electrode 106. Gate drive circuitry 1158 includes gate driver 1152A and gate driver 1152B. Gate driver 1152B serves as a NOT gate. The inputs of gate drivers 1152A and 1152B are coupled to signal generator 306. Figure 3A , 3B (And 3D). Furthermore, the output of gate driver 1152A is coupled to the gate terminals of FETs 318A to 318C. Also, the supply voltage terminal of gate driver 1152A is coupled to output O1. Similarly, the output of gate driver 1152B is coupled to the gate terminals of FETs 318D to 318F, and the supply voltage terminal of gate driver 1152B is coupled to ground.

[0187] The drain terminal D of FET 318A is coupled to DC voltage source 1154A, the drain terminal D of FET 318B is coupled to another DC voltage source 1154B, and the drain terminal D of FET 318C is coupled to yet another DC voltage source 1154C. The source terminal of each of FETs 318A, 318B, and 318C is coupled to output O1. Furthermore, the source terminal of each of FETs 318D, 318E, and 318F is coupled to ground. The drain terminal of each of FETs 318D, 318E, and 318F is coupled to output O1.

[0188] It should be noted that FETs 318A and 318F form a half-bridge circuit. Similarly, FETs 318B and 318E form another half-bridge circuit. Furthermore, FETs 318C and 318D form yet another half-bridge circuit.

[0189] The square wave signal generated by signal generator 306 is received by gate driver 1152A and amplified to generate gate drive signal 1160A. Similarly, the square wave signal generated by signal generator 306 is received by gate driver 1152B and amplified to generate gate drive signal 1160B, which is an inverse pulse relative to gate drive signal 1160A. For example, when or during a period when gate drive signal 1160A is at a high level (e.g., a high power level), gate drive signal 1160B is at a low level (e.g., a low power level). Furthermore, when or during a period when gate drive signal 1160A is at a low level (e.g., a low power level), gate drive signal 1160B is at a high level (e.g., a high power level). In another example, when or during a period when gate drive signal 1160A transitions from a low level to a high level, gate drive signal 1160B transitions from a high level to a low level. Similarly, when or during the period when the gate drive signal 1160A transitions from a high level to a low level, the gate drive signal 1160B transitions from a low level to a high level.

[0190] Gate drive signal 1160A is supplied from the output of gate driver 1152A to the gate terminals of FETs 318A to 318C. Furthermore, gate drive signal 1160B is supplied from the output of gate driver 1152B to the gate terminals of FETs 318D to 318F. Since gate drive signal 1160B is an inverse pulse relative to gate drive signal 1160A, FETs 318D, 318E, and 318F are not turned on when or during the period when FETs 318A, 318B, and 318C are turned on. Conversely, FETs 318D, 318E, and 318F are turned on when or during the period when FETs 318A, 318B, and 318C are not turned on.

[0191] In addition, controller 304 ( Figure 3A , 3BThe voltage source 1154A is coupled to voltage source 1154B via wires, and to voltage source 1154C via wires. Controller 304 provides a voltage value to voltage sources 1154A to 1154C. During push mode, upon receiving a voltage value, voltage source 1154A generates a voltage signal, which is transmitted to output O1 via FET 318A (when on). Similarly, during push mode, upon receiving a voltage value, voltage source 1154B generates a voltage signal, which is transmitted to output O1 via FET 318B (when on). Furthermore, during push mode, in response to receiving a voltage value, voltage source 1154C generates a voltage signal, which is transmitted to output O1 via FET 318C (when on). When FETs 318A to 318C are in push mode, a positive voltage is generated at output O1.

[0192] By changing the voltage values ​​supplied to voltage sources 1154A to 1154C, controller 304 shapes the envelope of the amplified square waveform. For example, based on the rate of change of the voltage values ​​supplied to voltage sources 1154A to 1154C, an amplified square waveform with an envelope of arbitrary shape, a multi-state pulse shape, or a continuous waveform shape is generated at output O1. For example, to generate a multi-state pulse shape envelope, the voltage value is changed instantaneously by controller 304. In another example, to generate a triangular pulse envelope, the voltage value is changed periodically in a common direction (e.g., increasing or decreasing) for a set time period by controller 304. In yet another example, to generate an envelope of arbitrary waveform, the voltage value is changed instantaneously and periodically in a common direction in a random manner.

[0193] Furthermore, during push-pull mode, FETs 318A to 318C are turned off by gate drive signal 1160A, and FETs 318D to 318F are turned on by gate drive signal 1160B. During the period when FETs 318A to 318C are turned off and FETs 318D to 318F are turned on, a negative voltage is generated at output O1. By operating FETs 318A to 318F in push-pull mode, an amplified square waveform is generated at output O1. The amplified square waveform is transmitted to capacitor 322A via output O1.

[0194] It should be noted that in some embodiments, diodes are optionally coupled in parallel between the drain and source terminals of the FETs in tree 1156. For example, diode D1 is coupled between the drain and source terminals of FET 318A. Similarly, diode D2 is coupled between the drain and source terminals of FET 318B, diode D3 is coupled between the drain and source terminals of FET 318C, and diode D4 is coupled between the drain and source terminals of FET 318D. Furthermore, diode D5 is coupled between the drain and source terminals of FET 318E, and diode D6 is coupled between the drain and source terminals of FET 318F. Diodes D1 to D3 limit the positive voltage at output O1, and diodes D4 to D6 limit the negative voltage at output O1.

[0195] It should be further noted that although tree 1156 shows six FETs, in some implementations, any other number of FETs in the half-bridge circuit is used. For example, four, five, six, or ten half-bridge circuits are used instead of three.

[0196] Figure 11C This diagram illustrates an embodiment of system 1170, demonstrating the use of an H-bridge circuit 1172 to power electrode 106. An H-bridge circuit 1172 is used instead of a half-bridge circuit. System 1170 includes a voltage source Vdc, a capacitor 1174, FETs 318A to 318D, gate drivers 1152A and 1152B, gate driver 1152C, and gate driver 1152D. Gate driver 1152C is identical to gate driver 1152B (e.g., having the same structure and function), and gate driver 1152D is identical to gate driver 1152A.

[0197] System 1170 also includes multiple diodes D5, D6, D7, and D8. Diode D5 is coupled between the drain and gate terminals of FET 318A. Similarly, diode D6 is coupled between the drain and gate terminals of FET 318B. Furthermore, diode D7 is coupled between the drain and gate terminals of FET 318C, and diode D8 is coupled between the drain and gate terminals of FET 318D.

[0198] Furthermore, the output of gate driver 1152A is coupled to the gate terminal of FET 318A, and the output of gate driver 1152B is coupled to the gate terminal of FET 318B. Similarly, the output of gate driver 1152C is coupled to the gate terminal of FET 318C, and the output of gate driver 1152D is coupled to the gate terminal of FET 318D. The inputs of gate drivers 1152A to 1152D are coupled to the output of signal generator 306. Capacitor 322A and electrode 106 are coupled between the source terminals of FETs 318A and 318C, and between the drain terminals of FETs 318B and 318D.

[0199] When FETs 318A and 318D are turned on, FETs 318B and 318C are turned off. For example, FETs 318A and 318D receive gate drive signal 1160A and are turned on. Meanwhile, FETs 318B and 318C receive gate drive signal 1160B and are turned off. In another example, FETs 318B and 318C are turned off during or for a period of time when FETs 318A and 318D are turned on.

[0200] Similarly, when FETs 318B and 318C are turned on, FETs 318A and 318D are turned off. For example, FETs 318B and 318C receive gate drive signal 1160B and are turned on. Conversely, FETs 318A and 318D receive gate drive signal 1160B and are turned off. In another example, FETs 318A and 318D are turned off during or for a period of time when FETs 318B and 318C are turned on.

[0201] When FETs 318A and 318D are turned on, current flows from the voltage source Vdc through FET 318A, capacitor 322A, electrode 106, and FET 318D to ground. Similarly, when FETs 318B and 318C are turned on, current flows from the voltage source Vdc through FET 318C, electrode 106, capacitor 322A, and FET 318B to ground. Therefore, current flows through electrode 106 in two opposite directions to generate positive and negative voltages between the terminals of electrode 106 during a frequency period.

[0202] Figure 12A This diagram illustrates an embodiment of system 1200, showing a cooling plate 1204 for cooling the FET circuit board 1202 (such as a half-bridge or H-bridge circuit board). Half-bridge FET circuit 318 ( Figure 3A , 3B and 3D), or H-bridge circuit 1172 ( Figure 11C ), or tree 1101 ( Figure 11A ), or tree 1156 ( Figure 11B The FETs (FETs) of the FET circuit board 1202 are connected to the FET circuit board 1202. The cooling plate 1204 contains a cooling liquid that passes through cooling pipes within the cooling plate 1204 to cool the FETs of the FET circuit board 1202, such as FETs 318A-318F. Figure 3A , 3B and 11B), or Figure 11A FETs, or Figure 11C FETs.

[0203] In some implementations, the cooling plate 1204 is positioned above the FET circuit board 1202, rather than below it.

[0204] Figure 12B-1 This is a side view of an embodiment of system 1210, illustrating the cooling of multiple integrated circuit chips 1214A, 1214B, and 1214C. System 1210 includes a cooling plate 1212, a printed circuit board (PCB) 1216, and chips 1214A, 1214B, and 1214C. Each chip 1214A, 1214B, and 1214C includes circuitry such as a half-bridge FET circuit 318. Figure 3A , 3B and 3D), or H-bridge circuit 1172 ( Figure 11C ), or tree 1101 ( Figure 11A ), or tree 1156 ( Figure 11B In some implementations, each of the chips 1214A, 1214B, and 1214C contains any number of transistors, or any number of half-bridge circuits, H-bridge circuits, or trees.

[0205] Cooling plate 1212 is coupled to printed circuit board 1216 and chips 1214A, 1214B, and 1214C via thermal adhesive 1218 (such as thermal paste or heat-conducting paste). Chips 1214A, 1214B, and 1214C are bonded to printed circuit board 1216 via cutouts in the printed circuit board 1216 to bring them into contact with cooling plate 1212. Furthermore, chips 1214A, 1214B, and 1214C are electrically coupled to printed circuit board 1216 via multiple connectors at the chip edges. For example, chips 1214A, 1214B, and 1214C are soldered to printed circuit board 1216.

[0206] When a coolant (e.g., water) is delivered through one or more cooling channels (e.g., cooling pipes) within the cooling plate 1212, the cooling plate 1212 is cooled to transfer heat generated by the transistors of chips 1214A, 1214B, and 1214C away from the chips. Each cooling channel serves as an inlet for the coolant and an outlet for the coolant. Furthermore, thermal adhesive 1218 facilitates the conduction of heat generated by the transistors of chips 1214A, 1214B, and 1214C away from the chips.

[0207] Figure 12B-2 This is a top isometric view of an embodiment of system 1211, illustrating the cooling of integrated circuit chips 1214A, 1214B, and 1214C. System 1211 includes gate driver circuitry 1158, system 1210, and reactor circuitry 206. Gate driver 1158 is coupled to printed circuit board 1216 via multiple input connectors on printed circuit board 1216. Additionally, output O1 on printed circuit board 1216 is coupled to reactor circuitry 206. Cooling plate 1212 is positioned below printed circuit board 1216 and is connected via hot glue 1218 (…). Figure 12B-1 It is coupled to the printed circuit board 1216. It should be noted that the cooling plate 1212 and the chips 1214A, 1214B and 1214C are horizontally placed. For example, the cooling plate 1212 is located in one horizontal plane, while the chips 1214A, 1214B and 1214C are located in another horizontal plane.

[0208] Figure 12C This is a top isometric view of an embodiment of system 1220, illustrating the cooling of integrated circuit chips 1214A, 1214B, and 1214C when the chips are vertically mounted on a printed circuit board 1222. System 1220 includes a printed circuit board 1222, a cooling plate 1226, and a mounting plate 1224. Chips 1214A, 1214B, and 1214C are electrically coupled to mounting plate 1224, which is coupled to the printed circuit board 1222. Furthermore, cooling plate 1226 is vertically mounted relative to the printed circuit board 1222. A space exists between mounting plate 1224 and cooling plate 1226. Coolant flows through one or more cooling channels within cooling plate 1226 to cool it. When cooling plate 1226 is cold, heat generated by chips 1214A, 1214B, and 1214C is transferred to areas away from the chips via conduction and convection.

[0209] Figure 12DThis is a top isometric view of an embodiment of system 1230, illustrating the cooling of integrated circuit chips 1214A, 1214B, and 1214C when the cooling plate 1226 is disposed adjacent to the board 1224. The cooling plate 1226 is vertically mounted to the printed circuit board 1222 and coupled to the board 1224 to be disposed next to the board 1224. There is no space between the cooling plate 1226 and the board 1224. This lack of space reduces any stray capacitance between the cooling plate 1226 and the board 1224. The cooling plate 1226 is disposed to the left of the board 1224, as shown below. Figure 12D As shown.

[0210] In many implementations, hot glue 1218 ( Figure 12B-1 The material is applied between the cooling plate 1226 and the plate 1224 to promote the conduction between the cooling plate 1226 and the plate 1224, thereby further promoting the cooling of chips 1214A, 1214B and 1214C.

[0211] In some embodiments, the cooling plate 1226 is disposed on the right side of the plate 1224 and adjacent to the plate 1224, rather than on the left side of the plate 1224.

[0212] Figure 12E This is a side view of an embodiment of system 1240, illustrating an embodiment for cooling chips 1214A, 1214B, and 1214C. System 1240 includes a printed circuit board 1219, an integrated circuit package 1242, a heat sink 1244, and a cooling fan 1246. The heat sink 1244 has multiple fins and is made of metal (e.g., aluminum). The package 1242 is coupled to and disposed on the top surface of the printed circuit board 1219. Furthermore, the heat sink 1244 is coupled to and disposed on the top surface of the package 1242. The cooling fan 1246 is coupled to and disposed above the heat sink 1244. Chips 1214A, 1214B, and 1214C are embedded in the package 1242.

[0213] The heat generated by chips 1214A, 1214B, and 1214C is transferred away from the chips via heat sink 1244. In addition, cooling fan 1246 is operated to transfer heat away from chips 1214A, 1214B, and 1214C.

[0214] In many implementations, multiple cooling fans are used instead of cooling fan 1246. In some implementations, multiple heat sinks are used instead of heat sink 1244.

[0215] Figure 12FThis is a side view of an embodiment of system 1250, illustrating another embodiment of cooling chips 1214A, 1214B, and 1214C. System 1250 includes a printed circuit board 1219, a package 1242, a heat sink 1244, and a cooling plate 1252. System 1250 and system 1240 (… Figure 12E Same as, but replaces cooling fan 1246 ( Figure 12E The cooling plate 1252 is disposed on the top surface of the heat sink 1244 and coupled to the top surface of the heat sink 1244.

[0216] Coolant is delivered through one or more channels of cooling plate 1252 to cool cooling plate 1252. When cooling plate 1252 is cooled, heat generated by chips 1214A, 1214B and 1214C is transferred away from the chips via heat sink 1244 and cooling plate 1252 to cool the chips.

[0217] Figure 12G This is a side view of an embodiment of system 1260, illustrating another embodiment of cooling chips 1214A, 1214B, and 1214C. System 1260 includes a printed circuit board 1219, a package 1242, and a heat sink 1244. Heat generated by chips 1214A, 1214B, and 1214C is transferred to the heat sink 1244 by conduction.

[0218] Figure 12H This is a side view of an embodiment of system 1270, illustrating cooling plate 1274 and container 1272, in which channels CH1 and CH2 are milled. Container 1272 houses a matchless plasma source 102. Figure 1 For example, a matchless plasma source 102 is positioned on a printed circuit board within a container 1272. A portion of channel CH1 is milled in the bottom surface of container 1272, while the remaining portion of channel CH1 is milled in the top surface of cooling plate 1274. Similarly, a portion of channel CH2 is milled in the bottom surface of container 1272, while the remaining portion of channel CH2 is milled in the top surface of cooling plate 1274. Each channel CH1 and CH2 is U-shaped.

[0219] Furthermore, an O-ring 1276A is attached to the bottom surface of the container 1272, while another O-ring 1276B is attached to the top surface of the cooling plate 1274. The container 1272 and the cooling plate 1274 are in contact with each other, such that O-rings 1276A and 1276B form a seal, thereby sealing the cooling fluid within channels CH1 and CH2. The cooling fluid is used to cool the powered components, such as the half-bridge FET circuit 318. Figure 3A , 3B and 3D), or H-bridge circuit 1172 ( Figure 11C), or tree 1101 ( Figure 11A ), or tree 1156 ( Figure 11B ).

[0220] In some embodiments, channels CH1 and CH2 have a shape different from the U-shape. In many embodiments, any number of channels are milled within the container 1272 and the cooling plate 1274. For example, four linear channels are formed within the container 1272 and the cooling plate 1274, rather than U-shaped channels CH1 and CH2.

[0221] Figure 13 An isometric view of an embodiment of cooling plate 1300. Cooling plate 1300 is cooling plate 1204 ( Figure 12A ), 1212 ( Figure 12B-1 and 12B-2 ), 1226 Figure 12C and 12D ) and 1252 ( Figure 12F Examples of any of the following: Cooling plate 1300 includes a cooling channel 1304A (such as a pipe) and another cooling channel 1304B. Each cooling channel 1304A and 1304B has an inlet for receiving coolant and an outlet for leaving coolant. Cooling channels 1304A and 1304B are embedded in the body 1302 (such as a metal plate) of cooling plate 1300.

[0222] In some embodiments, instead of pipes, holes are drilled in the body 1302 to form one or more channels within the cooling plate 1300 for the passage of cooling liquid.

[0223] In many implementations, a smart cold plate is used. For example, the cold plate described herein is coupled to a thermocouple. The thermocouple is further coupled to a controller 304. Figure 3A , 3B (And 3D). Signals from the thermocouples are transmitted to controller 304. Controller 304 determines the temperature of the cold plate based on the signals received from the thermocouples. Furthermore, controller 304 is coupled to a driver, which is coupled to the smart cold plate, to control the inflow and outflow of cooling liquid through one or more channels to further control the temperature of the smart cold plate. The temperature control of the smart cold plate is used to control the temperature of a half-bridge circuit located near the smart cold plate (e.g., adjacent to or at a short distance from it). This temperature control of the smart cold plate reduces the chance of condensation, further reducing the chance of corrosion between the smart cold plate and the half-bridge circuit described herein.

[0224] Figure 14AThis diagram illustrates an embodiment of system 1400, demonstrating the use of an ICP chamber 1402 with a matchless plasma source 102. Chamber 1402 includes a TCP coil 1404, a dielectric window 1410, and a vacuum housing of chamber 1402. The dielectric window 1410 is positioned above the vacuum housing. The TCP coil 1404 is positioned above the dielectric window 1410.

[0225] TCP coil 1404 is coupled at one end to a matchless plasma source 102, and at the opposite end to ground or a capacitor. The capacitor at the opposite end is coupled to ground. The vacuum housing also includes a substrate support 1412, such as an electrostatic chuck or lower electrode. The substrate support 1412 is coupled to the RF generator 1408 via an RF matcher 1406. The RF matcher used herein refers to... Figure 19 This will be further explained below. The RF generator used in this paper includes an RF power supply, which is an oscillator that generates a sinusoidal signal. This is different from the signal generator 306 that generates a square wave signal. Figure 3A , 3B In comparison with 3D, the RF matcher 1406 is coupled to the RF generator 1408 via the RF cable 1409.

[0226] A matched plasma source 102 supplies a shaped sine wave to the TCP coil 1404. Additionally, an RF generator 1408 generates an RF signal (such as a sine wave signal), which is supplied to an RF matched unit 1406. The RF matched unit 1406 matches the impedance of a load (e.g., the substrate support 1412 and the plasma within the plasma chamber 1402) to the impedance of a source (e.g., the RF generator 1408 and the RF cable 1409) to generate a modified RF signal, wherein the load is coupled to the output of the RF matched unit 1406 and the source is coupled to the input of the RF matched unit 1406. When a shaped sine wave is supplied to the TCP coil 1404 and a modified RF signal is supplied to the substrate support 1412, in addition to supplying one or more processing gases to the gap between the substrate support 1412 and the dielectric window 1410, the plasma is ignited or maintained in a vacuum chamber to process the substrate 108 disposed within the plasma chamber 1402. Examples of gases that can be processed include oxygen-containing gases, nitrogen-containing gases, and fluorine-containing gases.

[0227] Figure 14BThis diagram illustrates an embodiment of system 1403, used to explain the use of ICP chamber 1402, in which a matchless plasma source 102 is coupled to a substrate support 1412, and a TCP coil 1404 is coupled to an RF generator 1408 via an RF matcher 1406. The matchless plasma source 102 is coupled to the substrate support 1412 via a connection 110, and a substrate 108 is disposed on the substrate support 1412 for processing. Furthermore, the RF generator 1408 is coupled to the TCP coil 1404 via an RF cable 1409 and the RF matcher 1406. In addition to supplying one or more processing gases to the gap between the substrate support 1412 and the dielectric window 1410, a modified RF signal is supplied from the RF matcher 1406 to the TCP coil 1404, and a shaped sine wave is supplied from the matchless plasma source 102 to the substrate support 1412 to ignite or sustain the plasma within the plasma chamber 1402.

[0228] Figure 14C The diagram illustrates an embodiment of system 1405, specifically another use of the ICP chamber 1402, wherein a matchless plasma source 102 is coupled to a substrate support 1412, and another matchless plasma source 102 is coupled to a TCP coil 1404. Matchless plasma sources 102 supply a shaped sinusoidal waveform to the TCP coil 1404 and to the substrate support 1412. Plasma is generated or maintained within the plasma chamber 1402 when one or more process gases are supplied to the gap between the substrate support 1412 and the dielectric window 1410, in addition to supplying the shaped sinusoidal waveform to the TCP coil 1404 and the substrate support 1412.

[0229] It should be noted that in some embodiments, the number of transistors in the unmatched plasma source 102 coupled to the TCP coil 1404 is different from the number of transistors in the unmatched plasma source 102 coupled to the substrate support 1412. For example, the number of half-bridge circuits in the unmatched plasma source 102 coupled to the TCP coil 1404 is different from the number of half-bridge circuits in the unmatched plasma source 102 coupled to the substrate support 1412.

[0230] In many embodiments, the operating frequency of the matchless plasma source 102 coupled to the TCP coil 1404 is different from the operating frequency of the matchless plasma source 102 coupled to the substrate support 1412.

[0231] In some implementations, the operating frequency of the matchless plasma source 102 coupled to the TCP coil 1404 is the same as the operating frequency of the matchless plasma source 102 coupled to the substrate support 1412.

[0232] Further attention should be paid to system 1400 ( Figure 14A ), 1403 Figure 14B ), or any of 1405, is used to process substrate 108 (e.g., to perform conductor etching thereon).

[0233] Figure 14D The diagram illustrates an embodiment of system 1420, showing the coupling of a matchless plasma source 102 to a Faraday shield 1422. System 1420 includes an ICP plasma chamber 1424. The plasma chamber 1424 includes a TCP coil 1404, a dielectric window 1410, a Faraday shield 1422, and a vacuum chamber. The Faraday shield 1422 is positioned below the dielectric window 1410. The matchless plasma source 102 is coupled to the Faraday shield 1422 to supply a shaped sinusoidal waveform to the Faraday shield 1422, thereby reducing the chance of residual material from the processes performed within the plasma chamber 1424 depositing on the dielectric window 1410. Therefore, the walls of the plasma chamber 1424 are protected from erosion.

[0234] In some implementations, the Faraday shield 1422 is positioned between the TCP coil 1404 and the dielectric window 1410.

[0235] Figure 14E This is a diagram illustrating an embodiment of system 1430, used to illustrate the multiplexing of TCP coil 1432A and another TCP coil 1432B. System 1430 includes an ICP plasma chamber 1434. The ICP plasma chamber 1434 includes a substrate support 1412, a dielectric window 1410, and TCP coils 1432A and 1432B.

[0236] TCP coil 1432A is coupled to a non-matched power source 102, and TCP coil 1432B is coupled to another non-matched power source 102. System 1430 also includes a controller 1436, which is coupled to the non-matched power source 102 and the other non-matched power source 102.

[0237] Unmatched power source 102 and another unmatched power source 102 are multiplexed relative to each other. For example, when or during a period when controller 1436 sends a signal to turn on unmatched power source 102 coupled to TCP coil 1432A, controller 1436 sends a signal to turn off unmatched power source 102 coupled to TCP coil 1432B. Similarly, when or during a period when controller 1436 sends a signal to turn on unmatched power source 102 coupled to TCP coil 1432B, controller 1436 sends a signal to turn off unmatched power source 102 coupled to TCP coil 1432A.

[0238] Therefore, when the unmatched power source 102 coupled to TCP coil 1432A provides power to TCP coil 1432A, the unmatched power source 102 coupled to TCP coil 1432B does not provide power to TCP coil 1432B. Similarly, when the unmatched power source 102 coupled to TCP coil 1432B provides power to TCP coil 1432B, the unmatched power source 102 coupled to TCP coil 1432A does not provide power to TCP coil 1432A. For example, during the period when power is provided from unmatched power source 102 to TCP coil 1432A, another unmatched power source 102 does not provide power to TCP coil 1432B. Similarly, during the period when power is provided from unmatched power source 102 to TCP coil 1432B, another unmatched power source 102 does not provide power to TCP coil 1432A.

[0239] In some implementations, instead of performing multiplexing, both unmatched power sources are operated simultaneously, in which the unmatched power source 102 coupled to TCP coil 1432A and another unmatched power source 102 coupled to TCP coil 1432B are multiplexed. For example, while the unmatched power source 102 coupled to TCP coil 1432A provides power to TCP coil 1432A, the unmatched power source 102 coupled to TCP coil 1432B also provides power to TCP coil 1432B. For instance, during the period when power is provided from unmatched power source 102 to TCP coil 1432A, the other unmatched power source 102 also provides power to TCP coil 1432B.

[0240] Figure 15A This diagram illustrates an embodiment of system 1500, showing the use of the matchless plasma source 102 and CCP chamber 1502. System 1500 includes CCP chamber 1502 and matchless plasma source 102. CCP chamber 1502 includes a substrate support 1412 (such as an electrostatic chuck) and an upper electrode 1504 facing the substrate support 1412. The substrate support 1412 is coupled to an RF generator 1408 via an RF matcher 1406. Matchless plasma source 102 supplies a shaped sine wave to upper electrode 1504 via connection 110 to generate or sustain plasma in plasma chamber 1502. Furthermore, a modified RF signal is supplied from RF matcher 1406 to substrate support 1412. In addition, when one or more processing gases are supplied to the gap between the substrate support 1412 and the upper electrode 1504 in addition to the supply of a shaped sine wave, plasma is generated or maintained in the CCP chamber 1502 to process the substrate 108, which is disposed above the substrate support 1412.

[0241] In some embodiments, the substrate support 1412 is coupled to the RF generator via an RF matching device, rather than being coupled to ground. The RF generator produces an RF signal, which is provided to the RF matching device. The RF matching device modifies the RF signal to produce a modified RF signal. The modified RF signal is supplied to the substrate support 1412 to generate or sustain plasma in the plasma chamber 1502.

[0242] In many implementations, the substrate support 1412 is coupled to ground potential rather than to the RF generator.

[0243] Figure 15B This diagram illustrates an embodiment of system 1510, showing the use of a matchless plasma source 102 and a CCP chamber 1502, wherein the matchless plasma source 102 is coupled to a substrate support 1412. Furthermore, an upper electrode 1504 is coupled to ground potential. The matchless plasma source 102 supplies a shaped sinusoidal waveform to the substrate support 1412 via a connection 110. Additionally, when one or more processing gases are supplied to the gap between the substrate support 1412 and the upper electrode 1504 in addition to supplying the shaped sinusoidal waveform to the substrate support 1412, plasma is generated or maintained in the CCP chamber 1502. The plasma is generated or maintained to process a substrate 108 disposed above the substrate support 1412.

[0244] In some embodiments, the upper electrode 1504 is coupled to the RF generator via an RF matching unit, rather than being coupled to ground potential. The RF generator produces an RF signal, which is provided to the RF matching unit. The RF matching unit modifies the RF signal to produce a modified RF signal. The modified RF signal is supplied to the upper electrode 1504 to generate or sustain plasma in the plasma chamber 1502.

[0245] Figure 15CThe diagram illustrates an embodiment of system 1520, showing the use of a matchless plasma source 102 and a CCP chamber 1502. One matchless plasma source 102 is coupled to a substrate support 1412, and another matchless plasma source 102 is coupled to an upper electrode 1504. Matchless plasma sources 102 supply a shaped sinusoidal waveform to the substrate support 1412 via a connection 110, and also supply a shaped sinusoidal waveform to the upper electrode 1504 via the connection 110. Furthermore, when one or more processing gases are supplied to the gap between the substrate support 1412 and the upper electrode 1504 in addition to supplying a shaped sinusoidal waveform to the substrate support 1412 and the upper electrode 1504, plasma is generated or maintained in the CCP chamber 1502. The plasma is generated or maintained to process a substrate 108, which is disposed above the substrate support 1412.

[0246] It should be noted that system 1500 ( Figure 15A ), 1510 Figure 15B ), or any of 1520, are used to process substrate 108 (e.g., to perform dielectric etching operations thereon).

[0247] Figure 15D This diagram illustrates an embodiment of system 1530, showing a matchless power source 102 and RF generators 1408 and 1534 coupled to a substrate support 1412 of CCP chamber 1502. For example, the operating frequency of the matchless power source 102 differs from the operating frequency of the RF power generator 1408, and the operating frequency of the RF power generator 1408 differs from the operating frequency of the RF power generator 1534. For example, the operating frequency of the matchless power source 102 is 400 kHz, the operating frequency of the RF power generator 1408 is 2 MHz, 13.56 MHz, or 27 MHz, and the operating frequency of the RF power generator 1534 is 60 MHz. Each of the RF power generators 1408 and 1534 includes an oscillator that generates a sinusoidal waveform to supply RF power to the substrate support 1412. Neither the RF power generators 1408 nor 1534 has a signal generator 306. Figure 3A , 3B And 3D).

[0248] The unmatched power source 102 provides a shaped sine wave to the substrate support 1412. In addition, RF power generators 1408 and 1534 provide RF power to the substrate support 1412 to process the substrate 108.

[0249] Figure 15EThe diagram illustrates an embodiment of system 1540, showing a matchless power source 102 and RF power generators 1408 and 1534 coupled to the upper electrode 1504 of the CCP chamber 1502. The matchless power source 102 provides a shaped sine wave to the upper electrode 1504. Furthermore, the RF power generators 1408 and 1534 provide RF power to the upper electrode 1504 to process the substrate 108.

[0250] Figure 15F The diagram illustrates an embodiment of system 1550, showing a matchless power source 102 and RF power generators 1408 and 1534 coupled to a substrate support 1412 of a CCP chamber 1502, and further illustrating the matchless power source 102 and RF power generators 1408 and 1534 coupled to an upper electrode 1504 of the CCP chamber 1502. The matchless power source 102 provides a shaped sine wave to the upper electrode 1504. Additionally, another matchless power source 102 provides a shaped sine wave to the substrate support 1412. Furthermore, RF power generators 1408 and 1534 provide RF power to the upper electrode 1504, and another set of RF power generators 1408 and 1534 provides RF power to the substrate support 1412 to process the substrate 108.

[0251] In some embodiments, the substrate support 1412 is coupled to a plurality of matchless plasma sources, each of which is a matchless plasma source 102. Each of the matchless plasma sources has a different operating frequency. For example, a first matchless plasma source has an operating frequency of 400 kHz or 2 MHz. A second matchless plasma source has an operating frequency of 27 MHz, and a third matchless plasma source has an operating frequency of 60 MHz.

[0252] In many embodiments, the upper electrode 1504 is coupled to a plurality of matchless plasma sources, each of which is a matchless plasma source 102. As described above, each of the matchless plasma sources has a different operating frequency.

[0253] In some embodiments, the upper electrode 1504 is coupled to a plurality of matchless plasma sources, each of which is a matchless plasma source 102. Furthermore, the substrate support 1412 is coupled to a plurality of matchless plasma sources, each of which is a matchless plasma source 102. As described above, each of the matchless plasma sources coupled to the substrate support 1412 has a different operating frequency. Similarly, as described above, each of the matchless plasma sources coupled to the upper electrode 1504 has a different operating frequency.

[0254] Figure 16A This diagram illustrates an embodiment of system 1600, showing a plasma chamber 1602 with a nozzle 1604 coupled to a matchless plasma source 102. System 1600 includes a plasma chamber 1602 and a matchless plasma source 102. The plasma chamber 1602 has a nozzle 1604 and a substrate support 1412 coupled to ground potential. The nozzle 1604 has multiple openings to allow process material (such as a process gas or liquid material, such as a metallic material) to pass through the gap between the nozzle 1604 and the substrate support 1412 to process a substrate 108. For example, the nozzle 1604 is used to perform atomic layer deposition or chemical vapor deposition on the substrate 108. Plasma is generated or maintained in the plasma chamber 1602 when one or more process materials are supplied to the gap between the substrate support 1412 and the nozzle 1604, in addition to supplying a shaped sine wave to the upper electrode within the nozzle 1604. A plasma is generated or maintained to process a substrate 108 disposed on top of a substrate support 1412.

[0255] In some embodiments, the substrate support 1412 of the plasma chamber 1602 is coupled to the RF generator via an RF matching device, rather than being coupled to ground. The RF generator produces an RF signal, which is provided to the RF matching device. The RF matching device modifies the RF signal to produce a modified RF signal. The modified RF signal is supplied to the substrate support 1412 within the plasma chamber 1602 to generate or sustain plasma within the plasma chamber 1602.

[0256] Figure 16BThis diagram illustrates an embodiment of system 1610, showing the coupling of the matchless plasma source 102 to the substrate support 1412, rather than to the nozzle 1604. System 1610 includes a plasma chamber 1602. The matchless plasma source 102 is coupled to the substrate support 1412 via a connection 110, and the nozzle 1604 is coupled to ground potential. Plasma is generated or maintained in the plasma chamber 1602 when one or more processing materials are supplied to the gap between the substrate support 1412 and the nozzle 1604, in addition to supplying a shaped sine wave to the substrate support 1412. The plasma is generated or maintained to process a substrate 108 disposed on top of the substrate support 1412.

[0257] In some embodiments, the upper electrode in nozzle 1604 is coupled to the RF generator via an RF matching device, rather than being coupled to ground potential. The RF generator produces an RF signal, which is provided to the RF matching device. The RF matching device modifies the RF signal to produce a modified RF signal. The modified RF signal is supplied to the upper electrode in nozzle 1604 to generate or sustain plasma within plasma chamber 1602.

[0258] Figure 16C This diagram illustrates an embodiment of system 1620, showing the coupling of a matchless plasma source 102 to a substrate support 1412, and the coupling of another matchless plasma source 102 to a nozzle 1604. System 1620 includes multiple matchless plasma sources 102 and a plasma chamber 1602. Matchless plasma sources 102 supply shaped sinusoidal waveforms to the substrate support 1412 via a connection 110, and also supply shaped sinusoidal waveforms to the upper electrode of the nozzle 1604 via the connection 110. When one or more processing materials are supplied to the gap between the substrate support 1412 and the nozzle 1604, in addition to supplying shaped sinusoidal waveforms to the upper electrode of the nozzle 1604 and the substrate support 1412, plasma is generated or maintained in the plasma chamber 1602. The plasma is generated or maintained to process a substrate 108 disposed on top of the substrate support 1412.

[0259] Figure 17AThis diagram illustrates an embodiment of system 1700, showing the coupling of multiple matchless plasma sources (such as matchless plasma source 102) to multiple microsources 1704A, 1704B, 1704C, and 1704D. System 1700 includes multiple matchless plasma sources and a plasma chamber 1703. Plasma chamber 1703 includes multiple microsources 1704A to 1704D and a vacuum chamber 1702. Matchless plasma source 102 is coupled to the electrode of microsource 1704A, and another matchless plasma source 102 is coupled to the electrode of microsource 1704B. Similarly, another matchless plasma source 102 is coupled to the electrode of microsource 1704C, and another matchless plasma source 102 is coupled to the electrode of microsource 1704D. Each microsource 1704A to 1704D is a housing within which plasma is formed.

[0260] When one or more process gases and a shaped sinusoidal waveform are supplied to microsource 1704A, plasma is generated within microsource 1704A and supplied to vacuum chamber 1702 through the opening between microsource 1704A and vacuum chamber 1702. Similarly, when one or more process gases and a shaped sinusoidal waveform are supplied to microsource 1704B, plasma is generated within microsource 1704B and supplied to vacuum chamber 1702 through the opening between microsource 1704B and vacuum chamber 1702. Likewise, plasma generated within microsources 1704C and 1704D is supplied to vacuum chamber 1702.

[0261] Vacuum chamber 1702 includes substrate support 1412, on which substrate 108 is disposed. Plasma entering vacuum chamber 1702 from microsources 1704A to 1704D is used to process substrate 108.

[0262] Figure 17B The diagram illustrates an embodiment of system 1710, showing the coupling of substrate support 1412 with RF generator 1408 and matchless plasma source 102. System 1710 includes microsources 1704A, 1704B, 1704C, and 1704D and plasma chamber 1703.

[0263] Furthermore, in system 1710, RF generator 1408 is coupled to substrate support 1412, and matchless plasma source 102 is also coupled to substrate support 1412. The operating frequency of matchless plasma source 102 coupled to substrate support 1412 is different from the operating frequency of RF generator 1408. For example, when matchless plasma source 102 coupled to substrate support 1412 operates at a frequency of 400 kHz or 2 MHz, RF generator 1408 operates at a frequency of 13.56 MHz, 27 MHz, or 60 MHz. In another example, when matchless plasma source 102 coupled to substrate support 1412 operates at a frequency of 13.56 MHz, 27 MHz, or 60 MHz, RF generator 1408 operates at a frequency of 400 kHz or 2 MHz. The unmatched plasma source 102 supplies an amplified square waveform to the substrate support 1412, and the RF generator 1408 supplies RF power to the substrate support 1412 to process the substrate 108 within the plasma chamber 1703.

[0264] Figure 17C This diagram illustrates an embodiment of system 1720, showing the supply of RF power from a matchless plasma source 102 to gates 1726A and 1726B within chuck 1722, and the supply of RF power from an RF generator 1408 to the cathode of chuck 1722. System 1720 includes a plasma chamber 1730, an RF generator 1408, a matchless plasma source 102, another RF generator 1408, and another matchless plasma source 102. Plasma chamber 1730 includes an inner TCP coil 1724A and an outer TCP coil 1724B. Furthermore, plasma chamber 1730 includes chuck 1722, such as an electrostatic chuck.

[0265] RF generator 1408 is coupled to inner TCP coil 1724A, and a matchless plasma source is coupled to outer TCP coil 1724B. Additionally, a matchless plasma source 102 is coupled to gate 1726A of chuck 1722, and another matchless plasma source 102 is coupled to gate 1726B. Another RF generator 1408 is coupled to cathode of chuck 1722.

[0266] RF generator 1408 provides RF power to the inner TCP coil 1724A. Furthermore, a mismatched plasma source 102 coupled to the outer TCP coil 1724B supplies an amplified square waveform to the outer TCP coil 1724B. Additionally, a mismatched plasma source 102 coupled to the gate 1726A supplies an amplified square waveform to the gate 1726A. Furthermore, a mismatched plasma source 102 coupled to the gate 1726B supplies an amplified square waveform to the gate 1726B. Additionally, RF generator 1408 coupled to the cathode provides RF power to the cathode to process the substrate 108.

[0267] Figure 18 This is a diagram illustrating an embodiment of system 1800, showing a housing 1802 for accommodating a matchless plasma source 102. System 1800 includes housing 1802 and plasma chamber 1803. An example of plasma chamber 1803 includes plasma chamber 104 (…). Figure 1 ), ICP Room 1402 ( Figures 14A-14C ), ICP Room 1424 Figure 14B ), CCP Room 1502 ( Figures 15A-15C ) and plasma chamber 1602 ( Figures 16A-16C )as well as Figure 17A The plasma chamber 1703 is illustrated in the figure. For example, the housing 1802 has dimensions similar to those of a central processing unit (CPU) casing or a shoebox.

[0268] In addition, system 1800 includes network 1810, server 1812, and control terminal 1814. Housing 1802 is a container for surrounding printed circuit board 1808. Multiple chips 1804A, 1804B, and 1804C are coupled to printed circuit board 1808. Chip 1804A has a controller board 302 (…). Figure 3A , 3B And 3D). Additionally, chip 1804 has a gate driver, such as gate driver 311 ( Figure 3A , 3B and 3D) or gate drive circuit 1158 ( Figure 11B ), or gate drivers 1152A to 1152D ( Figure 11C In addition, the 1804C chip features a half-bridge FET circuit 318. Figure 3A , 3B And 3D), H-bridge circuit 1172 ( Figure 11C ), Tree 1101 ( Figure 11A ), or tree 1156 ( Figure 11B ).

[0269] Examples of network 1810 include computer networks, such as the Internet, intranets, or combinations thereof. Examples of control terminal 1814 include computers, such as laptops, desktop computers, tablets, or smartphones. Control terminal 1814 is connected to multiple housings (such as housing 1802) via server 1812 and network 1810 to control multiple plasma chambers via the multiple housings.

[0270] It should be noted that the housing 1802 is much smaller than the housings of the RF generator and the RF matching unit. In addition to saving space, the reduced size of the housing 1802 also saves costs.

[0271] Cooling plate 1806 provides cooling for chip 1804C. Cooling plate 1806 is positioned below or above chip 1804C. For example, cooling plate 1806 is coupled to chip 1804C via thermal adhesive.

[0272] In some embodiments, the controller board 302 and the gate driver are located on the same chip. Furthermore, in many embodiments, the gate driver, and any of the half-bridge FET circuits 318, tree 1101, and tree 1156, are located on the same chip. Moreover, in several embodiments, the controller board 302, and any of the half-bridge FET circuits 318, tree 1101, and tree 1156, are located on the same chip. And, in some embodiments, the controller board 302, the gate driver, and any of the half-bridge FET circuits 318, tree 1101, and tree 1156 are located on the same chip.

[0273] Figure 19 This is a block diagram illustrating an embodiment of system 1902, showing RF cable 1908 and RF matching device 1906. An example of RF cable 1908 is a coaxial cable. An example of RF matching device 1906 is an impedance matching device, or impedance matching circuit, or impedance matching network. RF matching device 1906 has multiple circuit components, such as inductors, capacitors, resistors, or combinations thereof. System 1902 also includes an RF generator 1904 and a plasma chamber 1910 with electrodes 1912.

[0274] RF generator 1904 includes an RF power supply that generates an RF signal with a sinusoidal waveform. The sinusoidal RF signal is supplied to RF matching unit 1906 via RF cable 1908. RF matching unit 1906 matches the impedance of a load (e.g., plasma chamber 1910) to the impedance of a source (e.g., RF generator 1904 and RF cable 1908) to generate a modified RF signal, wherein the load is coupled to the output of RF matching unit 1906 and the source is coupled to the input of RF matching unit 1906. The modified RF signal is supplied to electrode 1912. System 100 ( Figure 1 The lack of an RF cable 1908 and an RF matcher 1906 between the unmatched plasma source 102 and the plasma chamber 104, which are used to reflect power from the plasma chamber 104 back to the RF source 102 via the RF matcher 1906 and the RF cable 1908, is a significant deficiency. Figure 1 The chances of this happening decrease.

[0275] The implementation schemes described herein can be carried out through various computer system configurations including: handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The implementation schemes described herein can also be carried out in distributed computing environments, where operation is performed via remote processing hardware units linked through computer networks.

[0276] In some implementations, a controller (e.g., a host computer, etc.) is part of a system, which may be part of the examples described above. This system includes semiconductor processing equipment comprising one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). The system is integrated with electronic equipment to control the operation of semiconductor wafers or substrates before, during, and after processing. The electronic equipment, referred to as the controller, controls various components or sub-components of the system. Depending on the processing requirements and / or system type, the controller is programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of tools and other transfer tools and / or load locks connected to or engaged with the system.

[0277] In a broad sense, in many implementations, a controller is defined as an electronic device having numerous integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, initiate cleaning operations, initiate endpoint measurements, etc. Integrated circuits include: chips in hardware form that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), programmable logic devices (PLDs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller or system in the form of different individual settings (or program files) that define operating parameters for performing a process (on or on a semiconductor wafer). In some implementations, the operating parameters are part of a recipe defined by a process engineer to implement one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silica, surfaces, circuits, and / or the die of the wafer.

[0278] In some implementations, the controller is part of, or coupled to, a computer that is integrated with, coupled to, or networked to the system, or a combination thereof. For example, the controller may be located in, or in part of, a cloud-based or fab mainframe computer system that allows remote access to wafer processing. The controller enables remote access to the system to monitor the current progress of manufacturing operations, examine the history of past manufacturing operations, check trends or performance indicators from multiple manufacturing operations, adjust parameters for the current process, set the next processing step, or initiate a new process.

[0279] In some implementations, a remote computer (e.g., a server) provides processing recipes to the system via a computer network, including a local area network or the Internet. The remote computer includes a user interface that allows for the input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of settings for processing the chip. It should be understood that the settings are specific to the type of processing to be performed on the chip and the type of tool the controller engages or controls. Thus, as described above, the controller is distributed, for example by comprising one or more separate controllers networked together and operating toward a common purpose (e.g., the execution of the program as described herein). Examples of distributed controllers for this purpose include one or more integrated circuits located on-site and communicating with one or more integrated circuits located remotely (e.g., at the work platform level or as part of a remote computer), which together control processing in the room.

[0280] In many embodiments, the system includes, but is not limited to: plasma etching chamber, deposition chamber, rotary rinsing chamber, metal plating chamber, cleaning chamber, bevel edge etching chamber, physical vapor deposition (PVD) chamber, chemical vapor deposition (CVD) chamber, atomic layer deposition (ALD) chamber, atomic layer etching (ALE) chamber, ion implantation chamber, and any other semiconductor processing chamber associated with or used in the manufacture and / or processing of semiconductor wafers.

[0281] It should be further noted that although the above operations are described with reference to a pressure-coupled plasma (TCP) reactor, in some embodiments, the above operations are applied to other types of plasma chambers, such as conductor tools.

[0282] As described above, depending on the processing to be performed via the tool, the controller communicates with one or more of the following in the semiconductor manufacturing plant: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, nearby tools, adjacent tools, tools throughout the plant, a host computer, another controller, or tools used in material transport that deliver wafer containers to and from tool locations and / or loading ports.

[0283] In view of the above implementation schemes, it should be understood that some of these schemes employ numerous computer-implemented operations involving data stored in computer systems. These computer-implemented operations are operations that manipulate physical quantities.

[0284] Some of these implementations involve hardware units or devices that perform these operations. These devices are specifically designed for special-purpose computers. When defined as a special-purpose computer, it performs routines for other processing, program execution, or non-special-purpose purposes, while still retaining the ability to perform special-purpose operations.

[0285] In some implementations, the operations described herein are performed on a computer selectively enabled or configured by a computer program stored in computer memory or obtained via a computer network. When data is obtained via a computer network, it can be processed by other computers on the computer network (e.g., in the cloud, as computing resources).

[0286] One or more embodiments described herein can also be encoded into computer-readable code on a non-transitory computer-readable medium. A non-transitory computer-readable medium is any data storage hardware unit (e.g., a memory device) that stores data which is subsequently read by a computer system. Examples of non-transitory computer-readable media include hard disks, network attached storage (NAS), ROM, RAM, read-only optical discs (CD-ROMs), recordable optical discs (CD-Rs), rewritable optical discs (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, a non-transitory computer-readable medium comprises computer-readable tangible media distributed across a network-coupled computer system, such that the computer-readable code is stored and executed in a distributed manner.

[0287] Although some of the above-described method operations are presented in a specific order, it should be understood that in many implementations, other housekeeping operations are performed between the multiple method operations, or the method operations are arranged such that they occur at slightly different times, or they are distributed in a system that allows many method operations to occur at many intervals, or they are performed in a different order than those described above.

[0288] It should be further noted that, in one embodiment, one or more features from any of the above embodiments are combined with one or more features from any other embodiment without departing from the scope described in the various embodiments of the present invention.

[0289] While the foregoing embodiments have been described in considerable detail for purposes of clear understanding, it should be understood that certain changes and modifications may be made within the scope of the appended claims. Therefore, embodiments of the invention should be considered illustrative rather than restrictive, and these embodiments should not be limited to the details provided herein, but may be modified within the scope of the appended claims and their equivalents.

Claims

1. A matchless plasma source, comprising: A DC rail with an output; An arbitrary waveform generator coupled to the DC rail, wherein the arbitrary waveform generator is configured to provide multiple voltage values ​​to the DC rail, wherein the multiple voltage values ​​are provided to shape an amplified square waveform generated at the output of the DC rail, wherein the amplified square waveform is shaped to provide a shaped waveform at the output of the DC rail. as well as A reactor circuit coupled to the DC rail, wherein the reactor circuit is configured to receive the shaped waveform and remove multiple harmonics from the shaped waveform to provide a sinusoidal radio frequency waveform to the plasma chamber.

2. The matchless plasma source of claim 1, wherein the DC track comprises a DC voltage source, a first transistor, and a second transistor, wherein the DC voltage source is coupled to the first transistor, and the first transistor is coupled to the second transistor.

3. The matchless plasma source of claim 2, wherein the first transistor comprises a first drain terminal and a first source terminal, wherein the second transistor comprises a second drain terminal and a second source terminal, wherein the DC voltage source is coupled to the first drain terminal, wherein the first source terminal is coupled to the second drain terminal, and the second source terminal is coupled to ground potential, wherein the output is located between the first source terminal and the second drain terminal.

4. The matchless plasma source of claim 3, wherein the reactance circuit is a capacitor, wherein the capacitor is coupled to the output of the DC rail.

5. The matchless plasma source of claim 1, wherein the plurality of voltage values ​​are provided to shape the envelope of the amplified square waveform.

6. The matchless plasma source of claim 5, wherein the envelope is shaped to achieve multiple parameter states of the amplified square waveform, wherein each parameter state provides a corresponding parameter level.

7. The matchless plasma source of claim 1, wherein the reactance circuit is a capacitor or inductor coupled to the output of the DC rail.

8. A plasma system comprising: Unmatched plasma sources include: A DC rail with an output; An arbitrary waveform generator coupled to the DC rail, wherein the arbitrary waveform generator is configured to provide multiple voltage values ​​to the DC rail, wherein the multiple voltage values ​​are provided to shape an amplified square waveform generated at the output of the DC rail, wherein the amplified square waveform is shaped to provide a shaped waveform at the output of the DC rail; and A reactive circuit coupled to the DC rail, wherein the reactive circuit is configured to receive the shaped waveform and remove multiple harmonics from the shaped waveform to provide a sinusoidal radio frequency waveform; and A plasma chamber containing electrodes, wherein the electrodes are coupled to the unmatched plasma source to receive the sinusoidal radio frequency waveform.

9. The plasma system of claim 8, wherein the DC track comprises a DC voltage source, a first transistor, and a second transistor, wherein the DC voltage source is coupled to the first transistor, and the first transistor is coupled to the second transistor.

10. The plasma system of claim 9, wherein the first transistor comprises a first drain terminal and a first source terminal, wherein the second transistor comprises a second drain terminal and a second source terminal, wherein the DC voltage source is coupled to the first drain terminal, wherein the first source terminal is coupled to the second drain terminal, and the second source terminal is coupled to ground potential, wherein the output is located between the first source terminal and the second drain terminal.

11. The plasma system of claim 10, wherein the reactive circuit is a capacitor, wherein the capacitor is coupled to the output of the DC rail.

12. The plasma system of claim 8, wherein the plurality of voltage values ​​are provided to shape the envelope of the amplified square waveform.

13. The plasma system of claim 12, wherein the envelope is shaped to achieve a plurality of parameter states of the amplified square waveform, wherein each parameter state provides a corresponding parameter level.

14. The plasma system of claim 8, wherein the reactive circuit is a capacitor or inductor coupled to the output of the DC rail.

15. A method for operating a matchless plasma source, comprising: Provide multiple voltage values ​​from an arbitrary waveform generator to a DC rail with output; The amplified square waveform generated at the output of the DC track is shaped by the plurality of voltage values ​​to provide a shaped waveform at the output; as well as Multiple harmonics are removed from the shaped waveform to provide a sinusoidal radio frequency waveform to the plasma chamber.

16. The method of claim 15, wherein the DC rail comprises a DC voltage source, a first transistor, and a second transistor, wherein the DC voltage source is coupled to the first transistor, and the first transistor is coupled to the second transistor.

17. The method of claim 16, wherein the first transistor includes a first drain terminal and a first source terminal, wherein the second transistor includes a second drain terminal and a second source terminal, wherein the DC voltage source is coupled to the first drain terminal, wherein the first source terminal is coupled to the second drain terminal, and the second source terminal is coupled to ground, wherein the output is located between the first source terminal and the second drain terminal.

18. The method of claim 17, wherein the removal of the plurality of harmonics is performed by a reactance circuit, wherein the reactance circuit is a capacitor coupled to the output of the DC rail.

19. The method of claim 15, wherein the shaping of the amplified square waveform comprises shaping the envelope of the amplified square waveform.

20. The method of claim 19, wherein the shaping of the envelope of the amplified square waveform is performed to achieve a plurality of parameter states of the amplified square waveform, wherein each parameter state provides a corresponding parameter level.

Images