A multi-layer epitaxial super junction field effect transistor and a preparation method thereof

Abstract

The application provides a multilayer epitaxial super junction field effect transistor and a preparation method thereof, wherein a cell region super junction column is formed by diffusion connection of a first cell region super junction doping unit, a second cell region super junction doping unit, a third cell region super junction doping unit, a fourth cell region super junction doping unit and a fifth cell region super junction doping unit; the third cell region super junction doping unit deviates from the first cell region super junction doping unit by a preset distance in a width direction to a first side; and the fourth cell region super junction doping unit deviates from the first cell region super junction doping unit by a preset distance in a width direction to a second side opposite to the first side. The cell region super junction column can improve the short circuit resistance of the multilayer epitaxial super junction field effect transistor, and the improvement is specifically manifested as an increase in short circuit resistance time and a reduction in heat generation during short circuit. For example, when the super junction device works in a short circuit condition, the short circuit resistance time can be increased by 25%, and the device temperature before the start of short circuit protection can be reduced by 30-50 degrees Celsius.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a multilayer epitaxial superjunction field-effect transistor and its fabrication method. Background Technology

[0002] Multilayer epitaxial superjunction MOSFETs are widely used in electronic power systems as an advanced power MOSFET device technology. When superjunction devices are used as switching devices in circuits, they inevitably operate under some undesirable conditions, such as short-circuit conditions. In these conditions, the device is simultaneously subjected to large current and high voltage, which can cause the device to heat up rapidly. Furthermore, if the short-circuit protection mechanism does not activate in time, it may lead to device damage.

[0003] Therefore, how to improve the short-circuit withstand capability of superjunction devices has become an important technical problem that needs to be solved by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a multilayer epitaxial superjunction field-effect transistor and its fabrication method, so as to solve the problem that the short-circuit withstand capability of existing superjunction devices needs to be improved.

[0006] To achieve the above and other related objectives, the present invention provides a multilayer epitaxial superjunction field-effect transistor and its fabrication method, comprising the following steps:

[0007] A substrate is provided, and a first semiconductor layer is formed on the substrate. The first semiconductor layer includes a first epitaxial layer and a first cell region superjunction doped unit and a first terminal region superjunction doped unit located on the upper surface of the first epitaxial layer.

[0008] A second semiconductor layer is formed on the first semiconductor layer. The second semiconductor layer includes at least one second epitaxial layer. A second cell region superjunction doped unit and a second terminal region superjunction doped unit are formed on the upper surface of each second epitaxial layer. The second cell region superjunction doped unit is located directly above the first cell region superjunction doped unit.

[0009] A third semiconductor layer is formed on the second semiconductor layer. The third semiconductor layer includes at least one double-layer structure. Each double-layer structure includes a third epitaxial layer and a fourth epitaxial layer located on the third epitaxial layer. A third cell region superjunction doped unit and a third terminal region superjunction doped unit are formed on the upper surface of each third epitaxial layer. A fourth cell region superjunction doped unit and a fourth terminal region superjunction doped unit are formed on the upper surface of each fourth epitaxial layer. The third cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a predetermined distance in the width direction towards a first side. The fourth cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a predetermined distance in the width direction towards a second side opposite to the first side.

[0010] A fourth semiconductor layer is formed on the third semiconductor layer. The fourth semiconductor layer includes at least one fifth epitaxial layer. Each fifth epitaxial layer has a fifth cell region superjunction doped unit and a fifth terminal region superjunction doped unit formed on its upper surface. The fifth cell region superjunction doped unit is located directly above the first cell region superjunction doped unit.

[0011] Annealing is performed to diffusely connect the first, second, third, fourth, and fifth cell region superjunction doped units to form a cell region superjunction pillar, and to diffusely connect the first, second, third, fourth, and fifth terminal region superjunction doped units to form a terminal region superjunction pillar.

[0012] Optionally, the first terminal region superjunction doped unit, the second terminal region superjunction doped unit, the third terminal region superjunction doped unit, the fourth terminal region superjunction doped unit, and the fifth terminal region superjunction doped unit are located on a straight line in the thickness direction.

[0013] Optionally, the widths of the first, second, third, fourth, and fifth cell region superjunction doped units are the same, and the widths of the first, second, third, fourth, and fifth terminal region superjunction doped units are also the same.

[0014] Optionally, the third cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a distance of 10%-40% of the width of the first cell region superjunction doped unit in the width direction towards the first side, and the fourth cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a distance of 10%-40% of the width of the first cell region superjunction doped unit in the width direction towards the second side opposite to the first side.

[0015] Optionally, there are multiple super-pillars in the cell region, arranged sequentially and at intervals along the width direction of the super-pillars in the cell region; there are multiple super-pillars in the terminal region, arranged sequentially and at intervals along the width direction of the super-pillars in the terminal region; the width of the super-pillars in the terminal region is greater than the width of the super-pillars in the cell region, and the distance between two adjacent super-pillars in the terminal region is greater than the distance between two adjacent super-pillars in the cell region.

[0016] Optionally, the following steps are also included:

[0017] A field oxide layer is formed on the fourth semiconductor layer, and the field oxide layer covers the terminal region superjunction pillar;

[0018] A gate structure is formed on the fourth semiconductor layer. The gate structure is located on one side of the superjunction pillar in the cell region. The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer.

[0019] A body region is formed on the upper surface of the fourth semiconductor layer, the body region is directly opposite the fifth cell region superjunction doped unit, and the bottom surface of the body region is higher than the bottom surface of the topmost and diffused fifth cell region superjunction doped unit.

[0020] The source region is formed on the upper surface layer of the body region;

[0021] An interlayer dielectric layer covering the gate structure is formed on the fourth semiconductor layer;

[0022] Contact holes are formed in the interlayer dielectric layer;

[0023] A front-side metal interconnect layer is formed on the interlayer dielectric layer and in the contact hole;

[0024] Thinning the substrate from the back side;

[0025] A back metal layer is formed on the back side of the substrate.

[0026] Optionally, the first epitaxial layer, the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer, and the fifth epitaxial layer are all of the first conductivity type, and the cell region superjunction pillar and the terminal region superjunction pillar are both of the second conductivity type opposite to the first conductivity type, wherein the first conductivity type is N-type or P-type.

[0027] The present invention also provides a multilayer epitaxial superjunction field-effect transistor, comprising:

[0028] Substrate;

[0029] An epitaxial layer is located on the substrate;

[0030] A cellular superjunction pillar is located within the epitaxial layer, with its bottom surface higher than the bottom surface of the epitaxial layer. The cellular superjunction pillar comprises, from bottom to top, a first cellular superjunction diffusion region, a second cellular superjunction diffusion region, a third cellular superjunction diffusion region, and a fourth cellular superjunction diffusion region connected sequentially. The first cellular superjunction diffusion region includes a first cellular superjunction diffusion unit. The second cellular superjunction diffusion region includes one or more second cellular superjunction diffusion units stacked in the thickness direction, with the second cellular superjunction diffusion units located directly above the first cellular superjunction diffusion units. The third cellular superjunction diffusion region includes one or more second cellular superjunction diffusion units stacked in the thickness direction. A third-cell superjunction diffusion region, the third-cell superjunction diffusion region including a third-cell superjunction diffusion unit and a fourth-cell superjunction diffusion unit stacked in the thickness direction, the third-cell superjunction diffusion unit being offset from the first-cell superjunction diffusion unit by a predetermined distance in the width direction to a first side, the fourth-cell superjunction diffusion unit being offset from the first-cell superjunction diffusion unit by a predetermined distance in the width direction to a second side opposite to the first side, the fourth-cell superjunction diffusion region including one or a plurality of fifth-cell superjunction diffusion units stacked in the thickness direction, the fifth-cell superjunction diffusion units being located directly above the first-cell superjunction diffusion unit;

[0031] A terminal superstructure pillar is located in the epitaxial layer, and the bottom surface of the terminal superstructure pillar is higher than the bottom surface of the epitaxial layer.

[0032] Optionally, the third cell region superjunction diffusion unit deviates from the first cell region superjunction diffusion unit in the width direction by a distance of 10%-40% of the width of the first cell region superjunction diffusion unit, and the fourth cell region superjunction diffusion unit deviates from the first cell region superjunction diffusion unit in the width direction by a distance of 10%-40% of the width of the first cell region superjunction diffusion unit in the width direction to a second side opposite to the first side.

[0033] Optionally, it also includes:

[0034] A field oxygen layer is located on the epitaxial layer, and the field oxygen layer covers the terminal region superjunction pillar;

[0035] A gate structure is located on the epitaxial layer and disposed on one side of the cell region superjunction pillar. The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer.

[0036] The body region is located on the upper surface of the epitaxial layer and directly opposite the fifth cell region superjunction diffusion unit. The bottom surface of the body region is higher than the bottom surface of the fifth cell region superjunction diffusion unit located at the top layer.

[0037] The source region is located on the upper surface layer of the body region;

[0038] An interlayer dielectric layer is located on the epitaxial layer and covers the gate structure;

[0039] Contact holes are located in the interlayer dielectric layer;

[0040] A front-side metal interconnect layer is located on the interlayer dielectric layer and in the contact hole;

[0041] A back metal layer is located on the back side of the substrate.

[0042] As described above, in the multilayer epitaxial superjunction field-effect transistor and its fabrication method of the present invention, the cellular superjunction pillar is formed by diffusion connection of a first cellular superjunction doped unit, a second cellular superjunction doped unit, a third cellular superjunction doped unit, a fourth cellular superjunction doped unit, and a fifth cellular superjunction doped unit. The third cellular superjunction doped unit is offset from the first cellular superjunction doped unit by a predetermined distance in the width direction towards a first side, and the fourth cellular superjunction doped unit is offset from the first cellular superjunction doped unit by a predetermined distance in the width direction towards a second side opposite to the first side. Using this cellular superjunction pillar can improve the short-circuit withstand capability of the multilayer epitaxial superjunction field-effect transistor device, specifically by increasing the short-circuit withstand time and reducing heat generation during short circuits. For example, when the superjunction device operates under short-circuit conditions, it can increase the short-circuit withstand time by 25% and reduce the device temperature by 30-50 degrees Celsius before short-circuit protection is activated. Attached Figure Description

[0043] Figure 1 This diagram shows a cross-sectional view of the cell region and terminal region of a multilayer epitaxial superjunction field-effect transistor device.

[0044] Figure 2 The diagram shows a process flow chart of the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0045] Figure 3 The diagram shows a schematic of the structure obtained after forming a first semiconductor layer on a substrate according to the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0046] Figure 4The diagram shown is a schematic of the structure obtained after forming the first layer of the second semiconductor layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0047] Figure 5 The diagram shown is a schematic of the structure obtained after forming the second layer of the second semiconductor layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0048] Figure 6 The diagram shown is a schematic of the structure obtained after forming the first layer of the third semiconductor layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0049] Figure 7 The diagram shown is a schematic of the structure obtained after forming the second layer of the third semiconductor layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0050] Figure 8 The diagram shown is a schematic of the structure obtained after forming the third semiconductor layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0051] Figure 9 The diagram shown is a schematic of the structure obtained after forming the fourth layer of the third semiconductor layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0052] Figure 10 The diagram shows the structure obtained after forming a fourth semiconductor layer on a third semiconductor layer according to the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0053] Figure 11 The diagram shows the structure obtained after annealing the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention to obtain a cell region superjunction pillar and a terminal region superjunction pillar.

[0054] Figure 12 The diagram shows a schematic of the structure obtained after forming a field oxide layer on the fourth semiconductor layer according to the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0055] Figure 13 The diagram shows the structure obtained after forming a gate structure on the fourth semiconductor layer according to the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0056] Figure 14 The diagram shows a schematic of the structure obtained after the body region is formed on the upper surface of the fourth semiconductor layer according to the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0057] Figure 15 The diagram shows the structure obtained after forming the interlayer dielectric layer and contact holes according to the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0058] Figure 16 The diagram shown is a schematic of the structure obtained after forming the front metal interconnect layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0059] Figure 17 The diagram shown is a schematic of the structure obtained after forming the back metal layer in the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention.

[0060] Explanation of icon numbers

[0061] S1~S5 Step 101 Substrate

[0062] 102 N-type epitaxial layer

[0063] 103 cell region P-column

[0064] 104 Terminal Area P Column

[0065] 105 P-well

[0066] 106 N-type heavily doped source region

[0067] 107 Gate oxide

[0068] 108 oxygen fields

[0069] 109 Polycrystalline Silicon

[0070] 110 Interlayer Dielectric Layer

[0071] 111 Front metal layer

[0072] 112 Backside Metal Layer

[0073] 201 substrate

[0074] 202 First Semiconductor Layer

[0075] 2021 First Epitaxial Layer

[0076] 2022 First-cell region superjunction doped unit

[0077] 2023 First terminal region superjunction doped unit

[0078] 203 Photoresist layer

[0079] 204 Second Semiconductor Layer

[0080] 2041 Second Epitaxial Layer

[0081] 2042 Second-cell region superjunction doped unit

[0082] 2043 Second terminal region superjunction doped unit

[0083] 205 photoresist layer

[0084] 206 Third Semiconductor Layer

[0085] 2061 Third epitaxial layer

[0086] 2062 Fourth epitaxial layer

[0087] 2063 Third-cell superjunction doped unit

[0088] 2064 Third terminal region superjunction doped unit

[0089] 2065 Fourth-cell region superjunction doped unit

[0090] 2066 Fourth terminal region superjunction doped unit

[0091] 207 photoresist layer

[0092] 208 Fourth Semiconductor Layer

[0093] 2081 Fifth epitaxial layer

[0094] 2082 Fifth-cell region superjunction doped unit

[0095] 2083 Fifth terminal region superjunction doped unit

[0096] 209 Photoresist layer

[0097] 210-cell superstructure column

[0098] 2101 First-cell region superjunction diffusion unit

[0099] 2102 Second-cell region superjunction diffusion unit

[0100] 2103 Third-cell region superjunction diffusion unit

[0101] 2104 Fourth-cell region superjunction diffusion unit

[0102] 2105 Fifth-cell superjunction diffusion unit

[0103] 211 Terminal Area Superstructure Column

[0104] 2111 First terminal region superjunction diffusion unit

[0105] 2112 Second terminal region superjunction diffusion unit

[0106] 2113 Third terminal region superjunction diffusion unit

[0107] 2114 Fourth terminal region superjunction diffusion unit

[0108] 2115 Fifth terminal region superjunction diffusion unit

[0109] 212 field oxygen layer

[0110] 213 Photoresist layer

[0111] 214 gate structure

[0112] 2141 Gate dielectric layer

[0113] 2142 Gate conductive layer

[0114] 215 Body Area

[0115] 216 source region

[0116] 217 Interlayer Dielectric Layer

[0117] 218 Contact Hole

[0118] 219 Front-side metal interconnect layer

[0119] 220 Backside Metal Layer

[0120] A First-cell region superjunction diffusion region

[0121] B. Second-cell region superjunction diffusion zone

[0122] C. Third cell region superjunction diffusion region

[0123] D. Fourth cell region superjunction diffusion region

[0124] E Third cell region superjunction diffusion region Detailed Implementation

[0125] Please see Figure 1This diagram shows a cross-sectional structure of a multilayer epitaxial superjunction field-effect transistor (SFET), including a substrate 101, an N-type epitaxial layer 102, P-pillars in the cell region 103, P-pillars in the terminal region 104, a P-well 105, a heavily doped N-type source region 106, gate oxide 107, field oxide 108, polysilicon 109, an interlayer dielectric layer 110, a front metal layer 111, and a back metal layer 112. The P-pillars are formed through repeated epitaxial growth, photolithography, and boron implantation processes. Since a superjunction SFET requires charge balance between the P-pillars and the N-type epitaxial layer to ensure complete depletion of the space charge region after expansion, the product of the doping concentration and volume of the P-pillars must be comparable to the product of the doping concentration and volume of the N-type epitaxial layer. When the P-pillars and N-type epitaxial layer are perfectly balanced, the breakdown voltage reaches its peak, and the on-resistance is lowest. However, the short-circuit withstand capability is poor at this point, and the device is easily damaged under short-circuit conditions. Through extensive analysis and research, the inventors of this application have improved the formation method and structure of P-pillars, which can improve the short-circuit withstand capability of multilayer epitaxial superjunction field-effect transistor devices, specifically by increasing the short-circuit withstand time and reducing heat generation during short circuits.

[0126] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0127] Please see Figures 2 to 17 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0128] Example 1

[0129] This invention provides a method for fabricating a multilayer epitaxial superjunction field-effect transistor. Please refer to [link to relevant documentation]. Figure 2 The diagram shows the process flow of this method, which includes the following steps:

[0130] S1: A substrate is provided, and a first semiconductor layer is formed on the substrate. The first semiconductor layer includes a first epitaxial layer and a first cell region superjunction doped unit and a first terminal region superjunction doped unit located on the upper surface of the first epitaxial layer.

[0131] S2: A second semiconductor layer is formed on the first semiconductor layer. The second semiconductor layer includes at least one second epitaxial layer. A second cell region superjunction doped unit and a second terminal region superjunction doped unit are formed on the upper surface of each second epitaxial layer. The second cell region superjunction doped unit is located directly above the first cell region superjunction doped unit.

[0132] S3: A third semiconductor layer is formed on the second semiconductor layer. The third semiconductor layer includes at least one double-layer structure. Each double-layer structure includes a third epitaxial layer and a fourth epitaxial layer located on the third epitaxial layer. A third cell region superjunction doped unit and a third terminal region superjunction doped unit are formed on the upper surface of each third epitaxial layer. A fourth cell region superjunction doped unit and a fourth terminal region superjunction doped unit are formed on the upper surface of each fourth epitaxial layer. The third cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a predetermined distance in the width direction towards a first side. The fourth cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a predetermined distance in the width direction towards a second side opposite to the first side.

[0133] S4: A fourth semiconductor layer is formed on the third semiconductor layer. The fourth semiconductor layer includes at least one fifth epitaxial layer. Each fifth epitaxial layer has a fifth cell region superjunction doped unit and a fifth terminal region superjunction doped unit formed on its upper surface. The fifth cell region superjunction doped unit is located directly above the first cell region superjunction doped unit.

[0134] S5: Perform annealing to diffuse and connect the first cell region superjunction doped unit, the second cell region superjunction doped unit, the third cell region superjunction doped unit, the fourth cell region superjunction doped unit, and the fifth cell region superjunction doped unit to form a cell region superjunction pillar, and diffuse and connect the first terminal region superjunction doped unit, the second terminal region superjunction doped unit, the third terminal region superjunction doped unit, the fourth terminal region superjunction doped unit, and the fifth terminal region superjunction doped unit to form a terminal region superjunction pillar.

[0135] The following section details each of the above steps in conjunction with the structural diagram.

[0136] Please refer to the following first. Figure 3 Perform step S1: Provide a substrate 201 and form a first semiconductor layer 202 on the substrate 201. The first semiconductor layer 202 includes a first epitaxial layer 2021 and a first cell region superjunction doped unit 2022 and a first terminal region superjunction doped unit 2023 located on the upper surface of the first epitaxial layer 2021.

[0137] Specifically, the first cell region superjunction doped unit 2022 is used to form a portion of the cell region superjunction pillar and has the same conductivity type as the cell region superjunction pillar. The first terminal region superjunction doped unit 2023 is used to form a portion of the terminal region superjunction pillar and has the same conductivity type as the terminal region superjunction pillar. When the first epitaxial layer 2021 is of the first conductivity type, both the cell region superjunction pillar and the terminal region superjunction pillar are of the second conductivity type, which is opposite to the first conductivity type. The first conductivity type is N-type or P-type. In a preferred embodiment, the first epitaxial layer 2021 is N-type, and both the cell region superjunction pillar and the terminal region superjunction pillar are P-type.

[0138] As an example, the substrate 201 may be a silicon substrate or other suitable semiconductor substrate.

[0139] As an example, forming the first semiconductor layer 202 includes the following steps:

[0140] (1) The first epitaxial layer 2021 is grown on the substrate 201. The thickness of the first epitaxial layer 2021 can be set according to the device performance requirements. This invention does not impose specific limitations.

[0141] (2) A photoresist layer 203 is formed on the first epitaxial layer 2021, and the photoresist layer 203 is patterned by photolithography processes such as exposure and development, thereby defining the cell region superpillar formation region and the terminal region superpillar formation region.

[0142] (3) A first cell region superjunction doped unit 2022 and a first terminal region superjunction doped unit 2023 are formed by ion implantation. For example, when both the cell region superjunction pillar and the terminal region superjunction pillar are P-type, boron ion implantation can be used.

[0143] As an example, there are multiple superjunction pillars in the cell region, arranged sequentially and at intervals along the width direction of the cell region superjunction pillars; there are also multiple superjunction pillars in the terminal region, arranged sequentially and at intervals along the width direction of the terminal region superjunction pillars; the width of the terminal region superjunction pillars is greater than the width of the cell region superjunction pillars, and the spacing between two adjacent terminal region superjunction pillars is greater than the spacing between two adjacent cell region superjunction pillars. In some embodiments, the spacing between two adjacent terminal region superjunction pillars is increased by 10%-20% compared to the spacing between two adjacent cell region superjunction pillars.

[0144] Please see again Figures 4 to 5Step S2 is performed: a second semiconductor layer 204 is formed on the first semiconductor layer 201. The second semiconductor layer 204 includes at least one second epitaxial layer 2041. Each second epitaxial layer 2041 has a second cell region superjunction doped unit 2042 and a second terminal region superjunction doped unit 2043 formed on its upper surface. The second cell region superjunction doped unit 2042 is located directly above the first cell region superjunction doped unit 2022.

[0145] Specifically, the second cell region superjunction doped unit 2042 is used to form a part of the cell region superjunction pillar and has the same conductivity type as the cell region superjunction pillar, and the second terminal region superjunction doped unit 2043 is used to form a part of the terminal region superjunction pillar and has the same conductivity type as the terminal region superjunction pillar.

[0146] As an example, the second cell region superjunction doped unit 2042 has the same width as the first cell region superjunction doped unit 2022, and the second terminal region superjunction doped unit 2043 has the same width as the first terminal region superjunction doped unit 2023.

[0147] As an example, the second terminal region superjunction doped unit 2043 is also located directly above the first terminal region superjunction doped unit 2023.

[0148] It should be noted that the second semiconductor layer 204 includes at least one second epitaxial layer 2041, and each second epitaxial layer 2041 has a second cell region superjunction doped unit 2042 and a second terminal region superjunction doped unit 2043 formed on its upper surface. In this embodiment, the formation process of the second semiconductor layer 204 is illustrated by taking two second epitaxial layers 2041 as an example, including the following steps:

[0149] (1) As Figure 4 As shown, a second epitaxial layer 2041 is grown on the first epitaxial layer 2021. The thickness of the second epitaxial layer 2041 can be set according to the device performance requirements, and the present invention does not impose specific limitations.

[0150] (2) Continue as follows Figure 4 As shown, a photoresist layer 205 is formed on the second epitaxial layer 2041, and the photoresist layer 205 is patterned through photolithography processes such as exposure and development to expose the cell region superpillar formation region and the terminal region superpillar formation region.

[0151] (3) Continue as follows Figure 4 As shown, a second cell region superjunction doped unit 2042 and a second terminal region superjunction doped unit 2043 are formed by ion implantation.

[0152] (4) Figure 5As shown, another second epitaxial layer 2041 is grown on the first second epitaxial layer 2041.

[0153] (5) Continue as follows Figure 5 As shown, another photoresist layer 205 is formed on the second epitaxial layer 2041 grown subsequently, and the other photoresist layer 205 is patterned through photolithography processes such as exposure and development to expose the cell region superpillar formation region and the terminal region superpillar formation region.

[0154] (6) Continue as follows Figure 5 As shown, the second cell region superjunction doped unit 2042 and the second terminal region superjunction doped unit 2043 are re-formed by ion implantation.

[0155] Please see again Figures 6 to 9 Step S3 is performed: a third semiconductor layer 206 is formed on the second semiconductor layer 204. The third semiconductor layer 206 includes at least one double-layer structure. Each double-layer structure includes a third epitaxial layer 2061 and a fourth epitaxial layer 2062 located on the third epitaxial layer 2061. A third cell region superjunction doped unit 2063 and a third terminal region superjunction doped unit 2064 are formed on the upper surface of each third epitaxial layer 2061. A fourth cell region superjunction doped unit 2065 and a fourth terminal region superjunction doped unit 2066 are formed on the upper surface of each fourth epitaxial layer 2062. The third cell region superjunction doped unit 2063 is offset from the first cell region superjunction doped unit 2022 by a predetermined distance in the width direction towards the first side. The fourth cell region superjunction doped unit 2065 is offset from the first cell region superjunction doped unit 2022 by a predetermined distance in the width direction towards the second side opposite to the first side.

[0156] Specifically, the third cell region superjunction doping unit 2063 and the fourth cell region superjunction doping unit 2065 are both used to form a part of the cell region superjunction pillar and have the same conductivity type as the cell region superjunction pillar. The third terminal region superjunction doping unit 2064 and the fourth terminal region superjunction doping unit 2066 are both used to form a part of the terminal region superjunction pillar and have the same conductivity type as the terminal region superjunction pillar.

[0157] As an example, the third cell region superjunction doped unit 2063 and the fourth cell region superjunction doped unit 2065 have the same width as the first cell region superjunction doped unit 2022, and the third terminal region superjunction doped unit 2064 and the fourth terminal region superjunction doped unit 2066 have the same width as the first terminal region superjunction doped unit 2023.

[0158] As an example, the third cell region superjunction doped unit 2063 is offset from the first cell region superjunction doped unit 2022 by a distance of 10%-40% (e.g., 30%) of the width of the first cell region superjunction doped unit 2022 in the width direction to a first side (e.g., the left side), and the fourth cell region superjunction doped unit 2065 is offset from the first cell region superjunction doped unit 2022 by a distance of 10%-40% (e.g., 30%) of the width of the first cell region superjunction doped unit 2022 in the width direction to a second side opposite to the first side (e.g., the right side).

[0159] As an example, the third terminal region superjunction doped unit 2064 and the fourth terminal region superjunction doped unit 2066 are both located directly above the first terminal region superjunction doped unit 2023.

[0160] It should be noted that the third semiconductor layer 206 includes at least one double-layer structure. In this embodiment, the formation process of the third semiconductor layer 206 is described using the example of the third semiconductor layer 206 including two double-layer structures, and includes the following steps:

[0161] (1) As Figure 6 As shown, the third epitaxial layer 2061 is grown on the second epitaxial layer 2041.

[0162] (2) Continue as follows Figure 6 As shown, a photoresist layer 207 is formed on the third epitaxial layer 2061, and the photoresist layer 207 is patterned through photolithography processes such as exposure and development to expose the cell region superpillar formation region and the terminal region superpillar formation region.

[0163] (3) Continue as follows Figure 6 As shown, the third cell region superjunction doped unit 2063 and the third terminal region superjunction doped unit 2064 are formed by ion implantation into the upper surface layer of the third epitaxial layer 2061.

[0164] (4) Figure 7 As shown, the fourth epitaxial layer 2062 is grown on the third epitaxial layer 2061.

[0165] (5) Continue as follows Figure 7 As shown, another photoresist layer 207 is formed on the fourth epitaxial layer 2062, and the photoresist layer 207 is patterned through photolithography processes such as exposure and development to expose the cell region superpillar formation region and the terminal region superpillar formation region.

[0166] (6) Continue as follows Figure 7As shown, the fourth cell region superjunction doped unit 2065 and the fourth terminal region superjunction doped unit 2066 are formed by ion implantation into the upper surface layer of the fourth epitaxial layer 2062.

[0167] (7) Figure 8 As shown, another third epitaxial layer 2061 is grown on the fourth epitaxial layer 2062.

[0168] (8) Continue as follows Figure 8 As shown, another photoresist layer 207 is formed on the third epitaxial layer 2061, and the other photoresist layer 207 is patterned by photolithography processes such as exposure and development, revealing the cell region superpillar formation region and the terminal region superpillar formation region.

[0169] (9) Continue as follows Figure 8 As shown, another third cell region superjunction doped unit 2063 and another third terminal region superjunction doped unit 2064 are formed by ion implantation into the upper surface layer of the other third epitaxial layer 2061.

[0170] (10) such as Figure 9 As shown, a fourth epitaxial layer 2062 is grown on the third epitaxial layer 2061.

[0171] (11) Continue as follows Figure 9 As shown, another photoresist layer 207 is formed on the other fourth epitaxial layer 2062, and the other photoresist layer 207 is patterned by photolithography processes such as exposure and development, revealing the cell region superpillar formation region and the terminal region superpillar formation region.

[0172] (12) Continue as follows Figure 9 As shown, another fourth cell region superjunction doped unit 2065 and another fourth terminal region superjunction doped unit 2066 are formed by ion implantation into the upper surface layer of the other fourth epitaxial layer 2062.

[0173] Please see again Figure 10 Step S4 is performed: a fourth semiconductor layer 208 is formed on the third semiconductor layer 206. The fourth semiconductor layer 208 includes at least one fifth epitaxial layer 2081. Each fifth epitaxial layer 2081 has a fifth cell region superjunction doped unit 2082 and a fifth terminal region superjunction doped unit 2083 formed on its upper surface. The fifth cell region superjunction doped unit 2082 is located directly above the first cell region superjunction doped unit 2022.

[0174] Specifically, the fifth cell region superjunction doped unit 2082 is used to form a part of the cell region superjunction pillar and has the same conductivity type as the cell region superjunction pillar; the fifth terminal region superjunction doped unit 2083 is used to form a part of the terminal region superjunction pillar and has the same conductivity type as the terminal region superjunction pillar.

[0175] As an example, the fifth cell region superjunction doped unit 2082 has the same width as the first cell region superjunction doped unit 2022, and the fifth terminal region superjunction doped unit 2083 has the same width as the first terminal region superjunction doped unit 2023. That is, up to this step, in one embodiment, the first cell region superjunction doped unit 2022, the second cell region superjunction doped unit 2042, the third cell region superjunction doped unit 2063, the fourth cell region superjunction doped unit 2065 and the fifth cell region superjunction doped unit 2802 have the same width, and the first terminal region superjunction doped unit 2023, the second terminal region superjunction doped unit 2043, the third terminal region superjunction doped unit 2064, the fourth terminal region superjunction doped unit 2066 and the fifth terminal region superjunction doped unit 2083 have the same width.

[0176] As an example, the fifth terminal region superjunction doped unit 2083 is also located directly above the first terminal region superjunction doped unit 2023. That is, up to this step, in one embodiment, the first terminal region superjunction doped unit 2023, the second terminal region superjunction doped unit 2043, the third terminal region superjunction doped unit 2064, the fourth terminal region superjunction doped unit 2066, and the fifth terminal region superjunction doped unit 2083 are located on a straight line in the thickness direction.

[0177] It should be noted that the fourth semiconductor layer 208 includes at least one fifth epitaxial layer 2081, and each fifth epitaxial layer 2081 has a fifth cell region superjunction doped unit 2082 and a fifth terminal region superjunction doped unit 2083 formed on its upper surface. In this embodiment, the formation process of the fourth semiconductor layer 208 is illustrated using the second semiconductor layer 204, which includes one second epitaxial layer 2041, as an example, and includes the following steps:

[0178] (1) As Figure 10 As shown, the fifth epitaxial layer 2081 is grown on the third semiconductor layer 206. The thickness of the fifth epitaxial layer 2081 can be set according to the device performance requirements, and the present invention does not impose specific limitations.

[0179] (2) Continue as follows Figure 10As shown, a photoresist layer 209 is formed on the fifth epitaxial layer 2081, and the photoresist layer 209 is patterned through photolithography processes such as exposure and development, revealing the cell region superpillar formation region and the terminal region superpillar formation region.

[0180] (3) Continue as follows Figure 10 As shown, the fifth cell region superjunction doped unit 2082 and the fifth terminal region superjunction doped unit 2083 are formed by ion implantation into the upper surface layer of the fifth epitaxial layer 2081.

[0181] Please see again Figure 11 Step S5 is executed: annealing is performed to diffusely connect the first cell region superjunction doped unit 2022, the second cell region superjunction doped unit 2042, the third cell region superjunction doped unit 2063, the fourth cell region superjunction doped unit 2065 and the fifth cell region superjunction doped unit 2802 to form a cell region superjunction pillar 210, and to diffusely connect the first terminal region superjunction doped unit 2023, the second terminal region superjunction doped unit 2043, the third terminal region superjunction doped unit 2064, the fourth terminal region superjunction doped unit 2066 and the fifth terminal region superjunction doped unit 2083 to form a terminal region superjunction pillar 211.

[0182] Specifically, the purpose of the annealing treatment is to diffuse the ions in each doped unit through high temperature to obtain a superjunction column that is connected in the shape of a candied hawthorn. The annealing treatment can be carried out in a furnace tube, and the specific annealing temperature can be adjusted according to the actual situation. No specific limitation is made in this invention.

[0183] Specifically, such as Figure 11As shown, the cellular superjunction pillar 210 includes a first cellular superjunction diffusion region A, a second cellular superjunction diffusion region B, a third cellular superjunction diffusion region C, and a fourth cellular superjunction diffusion region D, connected sequentially from bottom to top. The first cellular superjunction diffusion region A includes a first cellular superjunction diffusion unit 2101. The second cellular superjunction diffusion region B includes one or multiple second cellular superjunction diffusion units 2102 stacked in the thickness direction, with the second cellular superjunction diffusion units 2102 located directly above the first cellular superjunction diffusion units 2102. The third cellular superjunction diffusion region C includes one or multiple third cellular superjunction sub-diffusion regions E stacked in the thickness direction. The diffusion region E includes a third-cell superjunction diffusion unit 2103 and a fourth-cell superjunction diffusion unit 2104 stacked in the thickness direction. The third-cell superjunction diffusion unit 2103 is offset from the first-cell superjunction diffusion unit 2101 by a predetermined distance in the width direction. The fourth-cell superjunction diffusion unit 2104 is offset from the first-cell superjunction diffusion unit 2101 by a predetermined distance in the width direction to a second side opposite to the first side. The fourth-cell superjunction diffusion region D includes one or multiple fifth-cell superjunction diffusion units 2105 stacked in the thickness direction. The fifth-cell superjunction diffusion units 2105 are located directly above the first-cell superjunction diffusion unit 2101. That is, in a certain section (the third-cell superjunction diffusion region C), the positions of some diffusion units (the third-cell superjunction diffusion unit 2103 and the fourth-cell superjunction diffusion unit 2104) of the cell superjunction pillar 210 are staggered.

[0184] Specifically, in the process of forming the superjunction pillar, the present invention defines the device surface to be in a balance between P-type and N-type by means of a photomask, and at the same time makes the positions of some diffusion units of the superjunction pillar 210 in the cell region staggered from left to right. This can improve the distribution of charge carriers (e.g., holes) under short-circuit conditions, and distribute the charge carrier density that was originally concentrated in the center of the superjunction pillar evenly to the diffusion region C of the third cell region superjunction, thereby obtaining better short-circuit withstand capability. At the same time, the breakdown voltage of the device remains unchanged, so there is no loss of the process window for ion implantation of the superjunction pillar.

[0185] Specifically, such as Figure 11As shown, the terminal superjunction pillar 211 is composed of a first terminal superjunction diffusion unit 2111, at least one second terminal superjunction diffusion unit 2112, at least one third terminal superjunction diffusion unit 2113, at least one fourth terminal superjunction diffusion unit 2114, and at least one fifth terminal superjunction diffusion unit 2115. In some embodiments, the first terminal superjunction diffusion unit 2111, the second terminal superjunction diffusion unit 2112, the third terminal superjunction diffusion unit 2113, the fourth terminal superjunction diffusion unit 2114, and the fifth terminal superjunction diffusion unit 2115 constituting the terminal superjunction pillar 211 are located on a straight line in the thickness direction.

[0186] As an example, the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention further includes the following steps:

[0187] Please see Figure 12 A field oxide layer 212 is formed on the fourth semiconductor layer 208, and the field oxide layer 212 covers the terminal region superjunction pillar 211.

[0188] As an example, forming the field oxygen layer 212 includes the following steps:

[0189] (1) A silicon dioxide layer of a certain thickness is grown by the wet oxygen method in the furnace tube;

[0190] (2) Form a photoresist layer 213 to define the active region through the photoresist;

[0191] (3) The silicon dioxide layer in the active region is etched clean by wet etching, and the silicon dioxide layer that is not removed by photoresist is used as the field oxygen layer 212.

[0192] Please see Figure 13 A gate structure 214 is formed on the fourth semiconductor layer 208. The gate structure 214 is located on one side of the cell region superjunction pillar 210. The gate structure 214 includes a gate dielectric layer 2141 and a gate conductive layer 2142 located on the gate dielectric layer 2141.

[0193] As an example, forming the gate structure 214 includes the following steps:

[0194] (1) A silicon dioxide layer of a certain thickness is grown by furnace tube thermo-oxidation method;

[0195] (2) A layer of polycrystalline silicon of a certain thickness is grown on the surface of the silicon dioxide layer by means of furnace tube process;

[0196] (3) Define the gate region using photoresist;

[0197] (4) Remove polysilicon and silicon dioxide from other areas by dry etching.

[0198] As an example, a portion of the polysilicon remains on the field oxide layer 212.

[0199] Please see Figure 14 A body region 215 is formed on the upper surface of the fourth semiconductor layer 208, the body region 215 is directly opposite the fifth cell region superjunction doped unit 2082, and the bottom surface of the body region 215 is higher than the bottom surface of the topmost and diffused fifth cell region superjunction doped unit 2082 (i.e., the fifth cell region superjunction diffusion unit 2105), and then a source region 216 is formed on the upper surface of the body region 215.

[0200] As an example, when a P-pillar is selected as the superjunction pillar, the body region 215 is also P-type, while the source region 216 is N-type. In some embodiments, the body region 215 on the surface is formed by boron ion implantation, and the source region is defined by photoresist and then formed by phosphorus ion implantation to form the heavily doped N-type source region 216. Here, "heavily doped" is a relative concept, and the specific doping concentration can be set according to actual needs; this invention does not impose specific limitations.

[0201] Please see Figure 15 An interlayer dielectric layer 217 covering the gate structure 214 is formed on the fourth semiconductor layer 208, and a contact hole 218 is formed in the interlayer dielectric layer 217.

[0202] In some embodiments, a layer of silicon borophosphate glass and plasma-enhanced tetraethyl orthosilicate (PE-TEOS) of a certain thickness is first grown by chemical vapor deposition as the interlayer dielectric layer 217, and then the contact hole area is defined by photoresist and the contact hole 218 is dry etched.

[0203] Please see Figure 16 A front-side metal interconnect layer 219 is formed on the interlayer dielectric layer 217 and in the contact hole 218.

[0204] In some embodiments, a metal layer of a certain thickness is first deposited by physical vapor deposition, then the interconnect layer pattern is defined by photoresist, and then the front metal interconnect layer 219 is formed by dry etching.

[0205] As an example, the material of the front metal interconnect layer 219 may be an aluminum-copper alloy or other suitable materials.

[0206] Please see Figure 17 The substrate 101 is thinned from the back side, and a back metal layer 220 is formed on the back side of the substrate 101.

[0207] As an example, the back metal layer 220 may be a Ti / Ni / Au stack structure or other suitable metal stack.

[0208] Thus, a multilayer epitaxial superjunction field-effect transistor is fabricated. In the fabrication method of the multilayer epitaxial superjunction field-effect transistor of the present invention, the cellular superjunction pillar is formed by diffusion connection of a first cellular superjunction doped unit, a second cellular superjunction doped unit, a third cellular superjunction doped unit, a fourth cellular superjunction doped unit, and a fifth cellular superjunction doped unit. The third cellular superjunction doped unit is offset from the first cellular superjunction doped unit by a predetermined distance in the width direction towards the first side, and the fourth cellular superjunction doped unit is offset from the first cellular superjunction doped unit by a predetermined distance in the width direction towards the second side opposite to the first side. Using this cellular superjunction pillar can improve the short-circuit withstand capability of the multilayer epitaxial superjunction field-effect transistor device, specifically by increasing the short-circuit withstand time and reducing the heat generation during the short circuit. For example, when the superjunction device is working under short-circuit conditions, it can increase the short-circuit withstand time by 25% and reduce the device temperature by 30-50 degrees Celsius before the short-circuit protection is activated.

[0209] Example 2

[0210] The present invention also provides a multilayer epitaxial superjunction field-effect transistor, which can be prepared by the preparation method of the multilayer epitaxial superjunction field-effect transistor as described in Example 1, or by other suitable methods.

[0211] For details, please refer to Figure 17 The diagram shows a structural schematic of the multilayer epitaxial superjunction field-effect transistor, including a substrate 101, an epitaxial layer, a cell region superjunction pillar 210, and a terminal region superjunction pillar 211. The epitaxial layer is located on the substrate 101, and the cell region superjunction pillar 210 and the terminal region superjunction pillar 211 are both located in the epitaxial layer. The bottom surfaces of the cell region superjunction pillar 210 and the terminal region superjunction pillar 211 are both higher than the bottom surface of the epitaxial layer.

[0212] Specifically, the epitaxial layer can be composed of multiple sub-epitaxy layers stacked together, for example, as shown below. Figure 17 The structure presented includes a first epitaxial layer 2021, two second epitaxial layers 2041, two third epitaxial layers 2061 / fourth epitaxial layers 2062 in a double-layer structure, and a fifth epitaxial layer 2081. In other embodiments, the number of sub-epitaxy layers included in the epitaxial layer can be increased or decreased as needed, and this should not unduly limit the scope of protection of the present invention.

[0213] For specific details, please refer to... Figure 11The cell-region superjunction pillar 210 includes, from bottom to top, a first cell-region superjunction diffusion region A, a second cell-region superjunction diffusion region B, a third cell-region superjunction diffusion region C, and a fourth cell-region superjunction diffusion region D. The first cell-region superjunction diffusion region A includes a first cell-region superjunction diffusion unit 2101. The second cell-region superjunction diffusion region B includes one or multiple second cell-region superjunction diffusion units 2102 stacked in the thickness direction, with the second cell-region superjunction diffusion units 2102 located directly above the first cell-region superjunction diffusion units 2102. The third cell-region superjunction diffusion region C includes one or multiple third cell-region superjunction sub-diffusion regions E stacked in the thickness direction. The diffusion region E includes a third cell region superjunction diffusion unit 2103 and a fourth cell region superjunction diffusion unit 2104 stacked in the thickness direction. The third cell region superjunction diffusion unit 2103 is offset from the first cell region superjunction diffusion unit 2101 by a predetermined distance in the width direction towards a first side. The fourth cell region superjunction diffusion unit 2104 is offset from the first cell region superjunction diffusion unit 2101 by a predetermined distance in the width direction towards a second side opposite to the first side. The fourth cell region superjunction diffusion region D includes one or a plurality of fifth cell region superjunction diffusion units 2105 stacked in the thickness direction. The fifth cell region superjunction diffusion unit 2105 is located directly above the first cell region superjunction diffusion unit 2101. In other words, in a certain section (the third cell region superjunction diffusion region C), the positions of some diffusion units (the third cell region superjunction diffusion unit 2103 and the fourth cell region superjunction diffusion unit 2104) of the cell region superjunction pillar 210 are staggered. This cell region superjunction pillar structure can improve the distribution of carriers (e.g., holes) under short-circuit conditions, and distribute the carrier density that was originally concentrated in the center of the superjunction pillar evenly to the third cell region superjunction diffusion region C, thereby obtaining better short-circuit withstand capability, while the breakdown voltage of the device remains unchanged.

[0214] As an example, the third cell region superjunction diffusion unit 2103 is offset from the first cell region superjunction diffusion unit 2101 by a distance of 10%-40% of the width of the first cell region superjunction diffusion unit 2101 in the width direction towards the first side, and the fourth cell region superjunction diffusion unit 2104 is offset from the first cell region superjunction diffusion unit 2101 by a distance of 10%-40% of the width of the first cell region superjunction diffusion unit 2101 in the width direction towards the second side opposite to the first side.

[0215] Specifically, the terminal superjunction pillar 211 is composed of a first terminal superjunction diffusion unit 2111, at least one second terminal superjunction diffusion unit 2112, at least one third terminal superjunction diffusion unit 2113, at least one fourth terminal superjunction diffusion unit 2114, and at least one fifth terminal superjunction diffusion unit 2115. In some embodiments, the first terminal superjunction diffusion unit 2111, the second terminal superjunction diffusion unit 2112, the third terminal superjunction diffusion unit 2113, the fourth terminal superjunction diffusion unit 2114, and the fifth terminal superjunction diffusion unit 2115 constituting the terminal superjunction pillar 211 are located on a straight line in the thickness direction.

[0216] As an example, the multilayer epitaxial superjunction field-effect transistor further includes a field oxide layer 212, a gate structure 214, a body region 215, a source region 216, an interlayer dielectric layer 217, a contact hole 218, a front metal interconnect layer 219, and a back metal layer 220. The field oxide layer 212 is located on the epitaxial layer and covers the terminal region superjunction pillar 211. The gate structure 214 is located on the epitaxial layer and disposed on one side of the cell region superjunction pillar 210. The gate structure 214 includes a gate dielectric layer 2141 and a gate conductive layer 2142 located on the gate dielectric layer 2141. The body region 215 is located on the upper surface of the epitaxial layer and faces the fifth cell region superjunction diffusion unit 2105. The bottom surface of the body region 215 is higher than the bottom surface of the fifth cell region superjunction diffusion unit 2105 located on the top layer. The source region 216 is located on the upper surface of the body region 215. The interlayer dielectric layer 217 is located on the epitaxial layer and covers the gate structure 214. The contact hole 218 is located in the interlayer dielectric layer 217. The front metal interconnect layer 219 is located on the interlayer dielectric layer 217 and in the contact hole 218. The back metal layer 220 is located on the back side of the substrate 101.

[0217] In the multilayer epitaxial superjunction field-effect transistor of the present invention, the first cell region superjunction diffusion unit 2101, the second cell region superjunction diffusion unit 2102, the third cell region superjunction diffusion unit 2103, the fourth cell region superjunction diffusion unit 2104, and the fifth cell region superjunction diffusion unit 2105 constituting the cell region superjunction pillar 210 are not all on a straight line in the thickness direction. The unit positions of some sections of the cell region superjunction pillar are staggered, which improves the adjustment of the carrier distribution of the device under short-circuit conditions and makes the device obtain better short-circuit withstand capability.

[0218] In summary, in the multilayer epitaxial superjunction field-effect transistor and its fabrication method of the present invention, the cellular superjunction pillar is formed by diffusion connection of a first cellular superjunction doped unit, a second cellular superjunction doped unit, a third cellular superjunction doped unit, a fourth cellular superjunction doped unit, and a fifth cellular superjunction doped unit. The third cellular superjunction doped unit is offset from the first cellular superjunction doped unit by a predetermined distance in the width direction towards a first side, and the fourth cellular superjunction doped unit is offset from the first cellular superjunction doped unit by a predetermined distance in the width direction towards a second side opposite to the first side. Using this cellular superjunction pillar can improve the short-circuit withstand capability of the multilayer epitaxial superjunction field-effect transistor device, specifically by increasing the short-circuit withstand time and reducing heat generation during short circuits. For example, when the superjunction device operates under short-circuit conditions, it can increase the short-circuit withstand time by 25% and reduce the device temperature before short-circuit protection activation by 30-50 degrees Celsius. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0219] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a multilayer epitaxial superjunction field-effect transistor, characterized in that, Includes the following steps: A substrate is provided, and a first semiconductor layer is formed on the substrate. The first semiconductor layer includes a first epitaxial layer and a first cell region superjunction doped unit and a first terminal region superjunction doped unit located on the upper surface of the first epitaxial layer. A second semiconductor layer is formed on the first semiconductor layer. The second semiconductor layer includes at least one second epitaxial layer. A second cell region superjunction doped unit and a second terminal region superjunction doped unit are formed on the upper surface of each second epitaxial layer. The second cell region superjunction doped unit is located directly above the first cell region superjunction doped unit. A third semiconductor layer is formed on the second semiconductor layer. The third semiconductor layer includes at least one double-layer structure. Each double-layer structure includes a third epitaxial layer and a fourth epitaxial layer located on the third epitaxial layer. A third cell region superjunction doped unit and a third terminal region superjunction doped unit are formed on the upper surface of each third epitaxial layer. A fourth cell region superjunction doped unit and a fourth terminal region superjunction doped unit are formed on the upper surface of each fourth epitaxial layer. The third cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a predetermined distance in the width direction towards a first side. The fourth cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a predetermined distance in the width direction towards a second side opposite to the first side. A fourth semiconductor layer is formed on the third semiconductor layer. The fourth semiconductor layer includes at least one fifth epitaxial layer. Each fifth epitaxial layer has a fifth cell region superjunction doped unit and a fifth terminal region superjunction doped unit formed on its upper surface. The fifth cell region superjunction doped unit is located directly above the first cell region superjunction doped unit. Annealing is performed to diffusely connect the first cell region superjunction doped unit, the second cell region superjunction doped unit, the third cell region superjunction doped unit, the fourth cell region superjunction doped unit, and the fifth cell region superjunction doped unit to form a cell region superjunction pillar, and to diffusely connect the first terminal region superjunction doped unit, the second terminal region superjunction doped unit, the third terminal region superjunction doped unit, the fourth terminal region superjunction doped unit, and the fifth terminal region superjunction doped unit to form a terminal region superjunction pillar; The first, second, third, fourth, and fifth cell region superjunction doped units have the same width, as do the first, second, third, fourth, and fifth terminal region superjunction doped units.

2. The method for fabricating a multilayer epitaxial superjunction field-effect transistor according to claim 1, characterized in that: The first terminal region superjunction doped unit, the second terminal region superjunction doped unit, the third terminal region superjunction doped unit, the fourth terminal region superjunction doped unit, and the fifth terminal region superjunction doped unit are located on a straight line in the thickness direction.

3. The method for fabricating a multilayer epitaxial superjunction field-effect transistor according to claim 1, characterized in that: The third cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a distance of 10%-40% of the width of the first cell region superjunction doped unit in the width direction towards the first side, and the fourth cell region superjunction doped unit is offset from the first cell region superjunction doped unit by a distance of 10%-40% of the width of the first cell region superjunction doped unit in the width direction towards the second side opposite to the first side.

4. The method for fabricating a multilayer epitaxial superjunction field-effect transistor according to claim 1, characterized in that: The number of superjunction pillars in the cell region is multiple, arranged sequentially and at intervals along the width direction of the superjunction pillars in the cell region; the number of superjunction pillars in the terminal region is multiple, arranged sequentially and at intervals along the width direction of the superjunction pillars in the terminal region; the width of the superjunction pillars in the terminal region is greater than the width of the superjunction pillars in the cell region, and the distance between two adjacent superjunction pillars in the terminal region is greater than the distance between two adjacent superjunction pillars in the cell region.

5. The method for fabricating a multilayer epitaxial superjunction field-effect transistor according to claim 1, characterized in that, It also includes the following steps: A field oxide layer is formed on the fourth semiconductor layer, and the field oxide layer covers the terminal region superjunction pillar; A gate structure is formed on the fourth semiconductor layer. The gate structure is located on one side of the superjunction pillar in the cell region. The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer. A body region is formed on the upper surface of the fourth semiconductor layer, the body region is directly opposite the fifth cell region superjunction doped unit, and the bottom surface of the body region is higher than the bottom surface of the topmost and diffused fifth cell region superjunction doped unit. The source region is formed on the upper surface layer of the body region; An interlayer dielectric layer covering the gate structure is formed on the fourth semiconductor layer; Contact holes are formed in the interlayer dielectric layer; A front-side metal interconnect layer is formed on the interlayer dielectric layer and in the contact hole; Thinning the substrate from the back side; A back metal layer is formed on the back side of the substrate.

6. The method for fabricating a multilayer epitaxial superjunction field-effect transistor according to claim 1, characterized in that: The first epitaxial layer, the second epitaxial layer, the third epitaxial layer, the fourth epitaxial layer, and the fifth epitaxial layer are all of the first conductivity type, and the cell region superjunction pillar and the terminal region superjunction pillar are both of the second conductivity type, which is opposite to the first conductivity type. The first conductivity type is N-type or P-type.

7. A multilayer epitaxial superjunction field-effect transistor, characterized in that, include: Substrate; An epitaxial layer is located on the substrate; A cellular superjunction pillar is located within the epitaxial layer, with its bottom surface higher than the bottom surface of the epitaxial layer. The cellular superjunction pillar comprises, from bottom to top, a first cellular superjunction diffusion region, a second cellular superjunction diffusion region, a third cellular superjunction diffusion region, and a fourth cellular superjunction diffusion region connected sequentially. The first cellular superjunction diffusion region includes a first cellular superjunction diffusion unit. The second cellular superjunction diffusion region includes one or more second cellular superjunction diffusion units stacked in the thickness direction, with the second cellular superjunction diffusion units located directly above the first cellular superjunction diffusion units. The third cellular superjunction diffusion region includes one or more second cellular superjunction diffusion units stacked in the thickness direction. A third-cell superjunction diffusion region, the third-cell superjunction diffusion region including a third-cell superjunction diffusion unit and a fourth-cell superjunction diffusion unit stacked in the thickness direction, the third-cell superjunction diffusion unit being offset from the first-cell superjunction diffusion unit by a predetermined distance in the width direction to a first side, the fourth-cell superjunction diffusion unit being offset from the first-cell superjunction diffusion unit by a predetermined distance in the width direction to a second side opposite to the first side, the fourth-cell superjunction diffusion region including one or a plurality of fifth-cell superjunction diffusion units stacked in the thickness direction, the fifth-cell superjunction diffusion units being located directly above the first-cell superjunction diffusion unit; A terminal superstructure pillar is located in the epitaxial layer, and the bottom surface of the terminal superstructure pillar is higher than the bottom surface of the epitaxial layer. The widths of the first cell region superjunction doped unit corresponding to the first cell region superjunction diffusion unit, the second cell region superjunction doped unit corresponding to the second cell region superjunction diffusion unit, the third cell region superjunction doped unit corresponding to the third cell region superjunction diffusion unit, the fourth cell region superjunction doped unit corresponding to the fourth cell region superjunction diffusion unit, and the fifth cell region superjunction doped unit corresponding to the fifth cell region superjunction diffusion unit are the same.

8. The multilayer epitaxial superjunction field-effect transistor according to claim 7, characterized in that: The third cell region superjunction diffusion unit is offset from the first cell region superjunction diffusion unit by a distance of 10%-40% of the width of the first cell region superjunction diffusion unit in the width direction towards the first side, and the fourth cell region superjunction diffusion unit is offset from the first cell region superjunction diffusion unit by a distance of 10%-40% of the width of the first cell region superjunction diffusion unit in the width direction towards the second side opposite to the first side.

9. The multilayer epitaxial superjunction field-effect transistor according to claim 7, characterized in that, Also includes: A field oxygen layer is located on the epitaxial layer, and the field oxygen layer covers the terminal region superjunction pillar; A gate structure is located on the epitaxial layer and disposed on one side of the cell region superjunction pillar. The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer. The body region is located on the upper surface of the epitaxial layer and directly opposite the fifth cell region superjunction diffusion unit. The bottom surface of the body region is higher than the bottom surface of the fifth cell region superjunction diffusion unit located at the top layer. The source region is located on the upper surface layer of the body region; An interlayer dielectric layer is located on the epitaxial layer and covers the gate structure; Contact holes are located in the interlayer dielectric layer; A front-side metal interconnect layer is located on the interlayer dielectric layer and in the contact hole; A back metal layer is located on the back side of the substrate.

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