Semiconductor structure and method of forming the same, memory

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a semiconductor structure, a forming method thereof and a memory. The forming method comprises the following steps: providing a carrier plate; forming a chip set on one side of the carrier plate, the chip set comprising a plurality of chip units stacked in a direction perpendicular to the carrier plate, and the orthographic projection of each chip unit on the carrier plate, which is close to the one side of the carrier plate, is within the orthographic projection of the chip unit farthest from the carrier plate on the carrier plate; forming an insulating medium layer covering the chip set; and performing a grinding process to expose a predetermined surface of the chip unit farthest from the carrier plate outside the insulating medium layer. The forming method can reduce the probability of uneven grinding, avoid scratches on the surface of the top chip during the grinding process, and improve the appearance of the product.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology

[0002] Memory chips are widely used in mobile devices such as mobile phones and tablets due to their advantages of small size, high integration, and high transmission speed. To increase the storage capacity of memory chips, multiple chip units are usually stacked together.

[0003] After stacking the chip units, an insulating layer needs to be laid on the surface and periphery of each chip unit. After the insulating layer is formed, the surface of the insulating layer needs to be ground to expose the surface of the chip unit located on top. However, the surface of the chip unit is easily damaged during the grinding process, which affects the appearance of the product.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a memory, which can reduce the probability of uneven grinding, avoid scratches on the surface of the top chip during the grinding process, and improve the product appearance.

[0006] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] Provide carrier board;

[0008] A chipset is formed on one side of the carrier board. The chipset includes a plurality of chip units stacked in a direction perpendicular to the carrier board. The orthographic projection of each chip unit on the carrier board closest to the carrier board is within the orthographic projection of the chip unit furthest from the carrier board on the carrier board.

[0009] An insulating dielectric layer is formed covering the chipset;

[0010] A polishing process is performed to expose the predetermined surface of the chip cell furthest from the carrier plate outside the insulating dielectric layer.

[0011] In one exemplary embodiment of this disclosure, there are multiple chipsets, which are spaced apart. The insulating dielectric layer fills the gaps between the chipsets. Each chipet includes a bottom chip unit and a top chip unit. In a direction parallel to the carrier board, adjacent bottom chip units have a first gap, and adjacent top chip units have a second gap. The width of the second gap is smaller than the width of the first gap.

[0012] In one exemplary embodiment of this disclosure, the bottom chip unit has a first width and the top chip unit has a second width in a direction parallel to the carrier plate, the second width being greater than the first width.

[0013] In one exemplary embodiment of this disclosure, the polishing process to expose a predetermined surface of the chip cell furthest from the carrier substrate outside the insulating dielectric layer includes:

[0014] The insulating dielectric layer of the first target thickness is removed by grinding to expose the top surface of the top chip cell;

[0015] Continue grinding to remove the top chip unit and the insulating dielectric layer to a second target thickness, thereby exposing the predetermined surface of the top chip unit, wherein the second target thickness is not greater than the first target thickness.

[0016] In one exemplary embodiment of this disclosure, the chip unit includes a substrate and a circuit module formed on the surface of the substrate, with the surface of the top chip unit in which the circuit module is formed facing the carrier plate.

[0017] In one exemplary embodiment of this disclosure, the forming method further includes:

[0018] A logic chip is formed between the chipset and the carrier board, and the orthographic projection of the chipset on the carrier board is within the orthographic projection of the logic chip on the carrier board.

[0019] In one exemplary embodiment of this disclosure, the forming method further includes:

[0020] After the cutting process is performed, the carrier board is removed, and the surface of the logic chip facing away from the chipset is electrically connected to a substrate.

[0021] In one exemplary embodiment of this disclosure, the forming method further includes:

[0022] After the grinding process, a cutting process is performed in the first and second intervals between each of the chipsets to separate each of the chipsets.

[0023] In one exemplary embodiment of this disclosure, during the cutting process, at least a portion of the insulating dielectric layer is retained in the first interval.

[0024] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0025] substrate;

[0026] A chipset is disposed on one side of the substrate and includes a plurality of chip units stacked in a direction perpendicular to the substrate, wherein the orthographic projection of each chip unit on the substrate closest to the substrate is within the orthographic projection of the chip unit furthest from the substrate on the substrate.

[0027] An insulating layer covers the outer periphery of the chipset, and the predetermined surface of the chip cell furthest from the substrate is exposed outside the insulating layer.

[0028] In one exemplary embodiment of this disclosure, the chipset includes a bottom chip unit and a top chip unit, wherein, in a direction parallel to the substrate, the thickness of the insulating layer on the sidewall of the top chip unit is not greater than the thickness of the insulating layer on the sidewall of the bottom chip unit.

[0029] In one exemplary embodiment of this disclosure, the bottom chip unit has a first width in a direction parallel to the substrate, and the top chip unit has a second width, the second width being greater than the first width.

[0030] In one exemplary embodiment of this disclosure, the chip unit includes a substrate and a circuit module formed on the surface of the substrate, with the surface of the top chip unit in which the circuit module is formed facing the substrate.

[0031] In one exemplary embodiment of this disclosure, the semiconductor structure further includes:

[0032] A logic chip is disposed between the substrate and the chipset, wherein the orthographic projection of the chipset on the substrate is within the orthographic projection of the logic chip on the substrate.

[0033] According to one aspect of this disclosure, a memory is provided, comprising the semiconductor structure described in any one of the foregoing claims.

[0034] The semiconductor structure and its formation method disclosed herein, as well as the memory, help to increase storage capacity by stacking multiple chip cells vertically. Furthermore, since the orthographic projections of the chip cells closest to the carrier substrate onto the carrier substrate fall within the orthographic projection of the chip cell furthest from the carrier substrate, the area of ​​the top chip cell is increased. While maintaining the overall size of the semiconductor structure, the thickness of the insulating layer around the top chip cell is reduced, thereby reducing the proportion of the insulating dielectric layer during polishing. This reduces the probability of uneven polishing due to differences in hardness between the insulating dielectric layer and the chip cell surface, lowering the probability of scratches or cracks on the surface of the top chip cell during polishing and improving the product appearance. Moreover, since the structure formed after polishing exposes the predetermined surface of the top chip cell, heat exchange between the chip cell and the external environment is increased, improving heat dissipation efficiency and reducing power consumption during chip cell operation.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0037] Figure 1 This is a schematic diagram of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0038] Figure 2 This is a schematic diagram of a semiconductor structure according to one embodiment of the present disclosure;

[0039] Figure 3 This is a top view of a semiconductor structure according to an embodiment of the present disclosure;

[0040] Figure 4 This is a schematic diagram of the conductive unit in the disclosed embodiment;

[0041] Figure 5 This is a schematic diagram showing the result after step S130 is completed in the disclosed embodiment;

[0042] Figure 6 This is a schematic diagram of the grinding area in the disclosed embodiment;

[0043] Figure 7 This is a schematic diagram of the conductive structure in the disclosed embodiment;

[0044] Figure 8This is a schematic diagram of a semiconductor structure according to one embodiment of the present disclosure.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1. Substrate; 2. Chipset; 21. Chip unit; 211. Top chip unit; 212. Bottom chip unit; 3. Insulating dielectric layer; 4. Insulating layer; 5. Conductive structure; 51. Conductive unit; 6. Logic chip; 7. Insulating filler layer; 8. Adhesive layer; 100. Carrier board; 200. Insulating adhesive. Detailed Implementation

[0047] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0048] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0049] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0050] This disclosure provides a method for forming a semiconductor structure. Figure 1 A schematic diagram of the method for forming the semiconductor structure of this disclosure is shown. See also... Figure 1 As shown, the forming method may include steps S110-S140, wherein:

[0051] Step S110: Provide a carrier board;

[0052] Step S120: A chip group is formed on one side of the carrier board. The chip group includes a plurality of chip units stacked in a direction perpendicular to the carrier board. The orthographic projection of each chip unit on the carrier board closest to the carrier board is within the orthographic projection of the chip unit farthest from the carrier board on the carrier board.

[0053] Step S130: Form an insulating dielectric layer covering the chipset;

[0054] Step S140: A polishing process is performed to expose the predetermined surface of the chip cell furthest from the carrier plate outside the insulating dielectric layer.

[0055] The semiconductor structure formation method disclosed herein, on the one hand, stacks multiple chip cells 21 vertically, which helps to increase storage capacity. On the other hand, since the orthographic projection of each chip cell 21 on the side closest to the carrier 100 is within the orthographic projection of the chip cell 21 furthest from the carrier 100, the area of ​​the top chip cell 211 is increased. While maintaining the overall size of the semiconductor structure, the thickness of the insulating layer 4 located on the outer periphery of the top chip cell 211 is reduced, thereby reducing the proportion of the insulating dielectric layer 3 during polishing. This reduces the probability of uneven polishing due to the difference in hardness between the insulating dielectric layer 3 and the chip cell 21 surface, and decreases the probability of scratches or cracks forming on the surface of the top chip cell 211 during polishing, improving the product appearance. Furthermore, since the structure formed after polishing exposes the predetermined surface of the top chip cell 211, heat exchange between the chip cell 21 and the outside environment is increased. During the operation of the chip cell 21, heat dissipation efficiency is improved and power consumption is reduced.

[0056] The steps and details of the semiconductor structure formation method disclosed herein are described in detail below:

[0057] like Figure 1 As shown, in step S110, a carrier plate is provided.

[0058] Figure 2 A schematic diagram of a semiconductor structure according to an embodiment of this disclosure is shown. See also Figure 2 As shown, the carrier plate 100 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular shape, and its material may be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the carrier plate 100 here.

[0059] like Figure 1As shown, in step S120, a chip group is formed on one side of the carrier board. The chip group includes a plurality of chip units stacked in a direction perpendicular to the carrier board. The orthographic projection of each chip unit on the carrier board closest to the carrier board is within the orthographic projection of the chip unit farthest from the carrier board on the carrier board.

[0060] See also Figure 2 As shown, chipset 2 can be formed on one side of carrier board 100, and chipset 2 can include multiple chip units 21. Chipset 2 can be used in integrated circuits, for example, it can be dynamic random access memory (DRAM) or static random access memory (SRAM), or it can be a core component in dynamic random access memory (DRAM) or static random access memory (SRAM). In some embodiments of this disclosure, in order to reduce the size of DRAM or SRAM while maintaining storage capacity, multiple chip units 21 can be stacked in a direction perpendicular to carrier board 100 to form chipset 2. For example, the number of chip units 21 in chipset 2 can be 2, 3, 4, 5, 6, or 7, and other numbers are not specifically limited here.

[0061] In some embodiments of this disclosure, each chip unit 21 in the chipset 2 can be electrically connected to each other, which facilitates the mutual transmission of data in multiple chip units 21, thereby making it easier to transmit data from multiple different chip units 21 to the same chip unit 21. This also facilitates the simultaneous transmission of electrical signals from each chip unit 21 in the chipset 2 to the substrate through the same chip unit 21, so as to connect each chip unit 21 to the external circuit in the substrate and thus realize signal transmission.

[0062] In some embodiments of this disclosure, each chip unit 21 in the chipset 2 may be spaced apart along a direction perpendicular to the carrier 100. For example, each chip unit 21 may be equally spaced along a direction perpendicular to the carrier 100; for instance, adjacent chip units 21 may be spaced apart by a predetermined distance. Of course, the spacing between each chip unit 21 may not be completely equal; for example, the spacing between at least two of the multiple chip units 21 may not be equal to the spacing between other adjacent chip units 21.

[0063] In some embodiments of this disclosure, the preset distance can be 10um to 150um. For example, the preset distance can be 10um, 40um, 70um, 100um, 130um or 150um. Of course, the preset distance can also be other values, which will not be listed here.

[0064] In one exemplary embodiment of this disclosure, the chip unit 21 may be in the form of a sheet structure, and its shape may be rectangular, circular, elliptical, or irregular, without particular limitation. The thickness of each chip unit 21 may be the same or different, without particular limitation. For example, the thickness of the chip unit 21 may be 40um to 80um, specifically 40um, 50um, 60um, 70um, or 80um, and of course, other thicknesses are also possible, which will not be listed here.

[0065] In some embodiments of this disclosure, each chip unit 21 in the chipset 2 may have the same thickness. For example, the thickness of each chip unit 21 may be 50 μm, or the thickness of each chip unit 21 may be 60 μm, or the thickness of each chip unit 21 may be 70 μm; of course, each chip unit 21 may also have other thicknesses, which will not be listed here.

[0066] In one exemplary embodiment of this disclosure, the chip unit 21 may include a substrate and a circuit module. The circuit module may be disposed on the surface of the substrate. At least a portion of the chip units 21 have the surface of the substrate containing the circuit module facing the carrier plate 100, while the surface of the chip unit 21 without the circuit module facing the side of the chip unit 21 away from the carrier plate 100. For example, the surface of the substrate containing the circuit module of the chip unit 21 farthest from the carrier plate 100 may face the carrier plate 100. For example, the substrate may be a wafer.

[0067] In one exemplary embodiment of this disclosure, the orthographic projection of each chip unit 21 on the side closest to the carrier board 100 in the chipset 2 lies within the orthographic projection of the chip unit 21 furthest from the carrier board 100. For ease of distinction, the chip unit 21 furthest from the carrier board 100 can be defined as the top chip unit 211, and the chip unit 21 located between the top chip unit 211 and the carrier board 100 can be defined as the bottom chip unit 212. The number of bottom chip units 212 can be one or more, without special limitation. In the direction parallel to the carrier board 100, the bottom chip unit 212 may have a first width, and the top chip unit 211 may have a second width, which may be greater than the first width. That is, in the chipset 2, the area of ​​the top chip unit 211 is greater than the area of ​​any other chip unit 21 in the chipset 2.

[0068] It should be noted that in chipset 2, the areas of each chip unit 21 located between the top chip unit 211 and the carrier board 100 may be equal or unequal. That is, the areas of each chip unit 21 in the bottom chip unit 212 may be equal or unequal, and no special limitation is made here.

[0069] In some embodiments of this disclosure, an insulating filler layer 7 may be provided between adjacent chip units 21. The insulating filler layer 7 can isolate adjacent chip units 21 and prevent signal crosstalk or coupling between chip units 21.

[0070] In one exemplary embodiment of this disclosure, the material of the insulating filling layer 7 can be insulating adhesive or encapsulating adhesive. The insulating filling layer 7 can isolate external water and oxygen, prevent external water and oxygen from entering the chip unit 21, thereby avoiding water and oxygen from corroding the internal structure of the chip unit 21 and extending the service life of the chip unit 21.

[0071] In some embodiments of this disclosure, the insulating filler layer 7 can fill the gap between adjacent chip units 21. The insulating filler layer 7 can support the gap between two adjacent chip units 21, and at the same time, it can balance the stress between two adjacent chip units 21, reduce the warpage of each chip unit 21, and thus improve the product yield.

[0072] Figure 3 A top view of a semiconductor structure according to an embodiment of the present disclosure is shown, see below. Figure 2 and Figure 3 As shown, there can be multiple chipsets 2, and multiple chipsets 2 can be formed on the same side of the carrier board 100. The orthographic projection of each chipet 2 on the carrier board 100 can be located within the array area. For example, the chipsets 2 can be distributed at intervals and can be arranged in an array within the array area of ​​the carrier board 100.

[0073] In some embodiments of this disclosure, see Figure 4 As shown, adjacent chip units 21 in the same chipset 2 are electrically connected. For example, adjacent chip units 21 can be electrically connected through conductive units 51, and multiple conductive units 51 can be arranged at intervals between adjacent chip units 21. In the direction perpendicular to the carrier plate 100, each conductive unit 51 located in different chip units 21 can be connected to each other to form a conductive structure 5.

[0074] It should be noted that, see Figure 2 As shown, when an insulating filler layer 7 is formed between adjacent chip units 21, the conductive structure 5 can penetrate each insulating filler layer 7.

[0075] like Figure 1As shown, in step S130, an insulating dielectric layer is formed to cover the chipset.

[0076] See Figure 3 and Figure 5 As shown, the insulating dielectric layer 3 can be formed simultaneously on the sidewalls and top of the chipset 2 using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the insulating dielectric layer 3, which will not be listed here. The material of the insulating dielectric layer 3 can be an insulating material. The insulating dielectric layer 3 can be used to insulate and isolate the chipset 2 to avoid coupling or short circuits between the chipset 2 and other surrounding structures, thereby improving product yield.

[0077] It should be noted that when multiple chipsets 2 are formed on one side of the carrier board 100, the insulating dielectric layer 3 can fill the gaps between each chipet 2, thereby avoiding coupling or short circuits between adjacent chipets 2 and improving product yield.

[0078] In one exemplary embodiment of this disclosure, adjacent bottom chip units 212 may have a first gap in a direction parallel to the carrier 100, while adjacent top chip units 211 may have a second gap, the width of the second gap being smaller than the width of the first gap. For example, the width of the first gap may be greater than or equal to 200 micrometers, and the width of the second gap may be greater than or equal to 50 micrometers and less than or equal to 100 micrometers.

[0079] like Figure 1 As shown, in step S140, grinding is performed to expose the predetermined surface of the chip cell furthest from the carrier plate outside the insulating dielectric layer.

[0080] The insulating dielectric layer 3 can be polished using a polishing process. After polishing, the insulating dielectric layer 3 can expose the predetermined surface of the top chip unit 211, so as to increase the heat exchange between the chip group 2 and the outside world. During the operation of the chip unit 21, the heat dissipation efficiency can be improved and the power consumption can be reduced.

[0081] During the polishing process, since the area of ​​the top chip unit 211 in the chipset 2 is larger than that of other chip units 21, the thickness of the insulating dielectric layer 3 located on the outer periphery of the top chip unit 211 is smaller when the overall size of the semiconductor structure remains unchanged. This reduces the proportion of the insulating dielectric layer 3 during polishing, which can reduce the probability of uneven polishing caused by the difference in surface hardness between the insulating dielectric layer 3 and the chip unit 21. It can also reduce the probability of scratches or cracks on the surface of the top chip unit 211 during polishing, thereby improving the product appearance.

[0082] In some embodiments of this disclosure, in the direction parallel to the carrier plate 100, the ratio of the width of the top chip unit 211 to the thickness of the insulating dielectric layer 3 located on the sidewall of the top chip unit 211 can be 5 to 20. For example, the ratio of the width of the top chip unit 211 to the thickness of the insulating dielectric layer 3 located on the sidewall of the top chip unit 211 is 5, 10, 15 or 20. Of course, other ratios are also possible, which will not be listed here.

[0083] In some embodiments of this disclosure, the thickness of the insulating dielectric layer 3 on the sidewall of the top chip unit 211 may be greater than or equal to 50 micrometers and less than or equal to 100 micrometers. For example, the thickness of the insulating dielectric layer 3 on the sidewall of the top chip unit 211 may be 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, or 100 micrometers. Of course, the thickness of the insulating dielectric layer 3 on the sidewall of the top chip unit 211 may also be other, which will not be listed here.

[0084] It should be noted that, in the direction perpendicular to the carrier plate 100, each chip unit 21 between the top chip unit 211 and the carrier plate 100 can be aligned at both ends, that is, each chip unit 21 in the bottom chip unit 212 can be aligned at both ends, and the thickness of the insulating dielectric layer 3 on the outer periphery of each chip unit 21 in the bottom chip unit 212 can be equal, and the thickness of the insulating dielectric layer 3 on the outer periphery of each chip unit 21 in the bottom chip unit 212 can be greater than the thickness of the chip unit 21 on the outer periphery of the top chip unit 211.

[0085] It should be noted that, since the insulating dielectric layer 3 is only thinned in its thickness direction during the polishing process, and not in the direction parallel to the carrier plate 100, when there are multiple chip groups 2, the final insulating dielectric layer 3 can fill the gaps between each chip group 2 in the direction parallel to the carrier plate 100. Furthermore, during the polishing process, the insulating dielectric layer 3 and the substrate of each top chip unit 211 in each chip group 2 can be polished simultaneously. Thus, through the same polishing process, the surface of the chip unit 21 furthest from the carrier plate 100 in each chip group 2, facing away from the carrier plate 100, can be exposed simultaneously.

[0086] In some embodiments of this disclosure, performing a polishing process to expose a predetermined surface of the chip cell 21 furthest from the carrier 100 to the insulating dielectric layer 3 (i.e., step S140) may include:

[0087] Step S210: Grind away the insulating dielectric layer 3 of the first target thickness to expose the top surface of the top chip unit 211.

[0088] The insulating dielectric layer 3 of a first target thickness can be removed by a grinding process. The first target thickness can be equal to the thickness of the insulating dielectric layer 3 covering the surface of the top chip unit 211. After the insulating dielectric layer 3 of the first target thickness is removed by grinding, the top surface of the top chip unit 211 can be exposed, that is, the surface of the substrate of the top chip unit 211 that is away from the circuit module can be exposed.

[0089] For example, the thickness of the first target can be 100um to 150um. For instance, the thickness of the first target can be 100um, 110um, 120um, 130um, 140um or 150um. Of course, the thickness of the first target can also be other thicknesses, which will not be listed here.

[0090] Step S220: Continue grinding to remove the top chip unit 211 and the insulating dielectric layer 3 to the second target thickness, so as to expose the predetermined surface of the top chip unit 211, wherein the second target thickness is not greater than the first target thickness.

[0091] The top chip unit 211 and the insulating dielectric layer 3 can be further polished, thereby thinning the surface of the substrate in the top chip unit 211 that is away from the circuit module, so as to reduce the thickness of the chip group 2, further increase the heat dissipation efficiency of the chip group 2 during operation, and further reduce power consumption.

[0092] For example, during the polishing process, the top chip unit 211 and the insulating dielectric layer 3 of the second target thickness can be removed. The second target thickness can be less than the thickness of the substrate of the top chip unit 211, and the second target thickness is not greater than the first target thickness. For example, the second target thickness can be 100nm to 140nm. For instance, the second target thickness can be 100nm, 110nm, 120nm, 130nm or 140nm. Of course, the second target thickness can also be other thicknesses, which will not be listed here.

[0093] In some embodiments of this disclosure, a polishing apparatus can be used to simultaneously polish the insulating dielectric layer 3 on the surface of the top chip unit 211 and the substrate of the top chip unit 211, and the polished area is as follows: Figure 6 As shown in the dashed box, during this process, the insulating dielectric layer 3 located on the outer periphery of the top chip unit 211 has a small thickness, which results in a small proportion of the insulating dielectric layer 3 during the polishing process. During the polishing process, a polishing head that matches the hardness of the substrate can be used for polishing, which can reduce the probability of scratches or cracks on the surface of the top chip unit 211 during the polishing process and help improve the product appearance.

[0094] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include:

[0095] In step S160, a logic chip 6 is formed between the chipset 2 and the carrier board 100, wherein the orthographic projection of the chipset 2 on the carrier board 100 is within the orthographic projection of the logic chip 6 on the carrier board 100.

[0096] The logic chip 6 can be formed between the carrier board 100 and the chipset 2. The logic chip 6 can be bonded to the carrier board 100 using insulating adhesive 200. The insulating adhesive 200 can be made of non-conductive adhesive, UV adhesive, etc. (See also...) Figure 7 As shown, the logic chip 6 has a conductive structure 5 on the surface opposite to the chipset 2. That is, each chip unit 21 in each chipset 2 can be electrically connected to the logic chip 6, so that the signals in each chip unit 21 in each chipset 2 can be interconnected with the substrate through the logic chip 6.

[0097] In some embodiments of this disclosure, the orthographic projection of the chipset 2 on the carrier board 100 may be within the orthographic projection of the logic chip 6 on the carrier board 100. That is, the area of ​​the logic chip 6 may be larger than the area of ​​each chip unit 21 located between the top chip unit 211 and the carrier board 100, and also larger than the area of ​​the top chip unit 211.

[0098] When there are multiple chipsets 2, all chipsets 2 can be electrically connected to the logic chip 6. It should be noted that either one logic chip 6 can be formed between the carrier board 100 and each chipset 2, or multiple logic chips 6 can be formed at intervals along a direction parallel to the carrier board 100; no special limitation is made here. When one logic chip 6 is formed between the carrier board 100 and each chipset 2, each chip unit 21 in each chipset 2 closest to the carrier board 100 can be electrically connected to the same logic chip 6. When multiple logic chips 6 are formed between the carrier board 100 and each chipset 2 at intervals along a direction parallel to the carrier board 100, each logic chip 6 can be electrically connected to at least one chipset 2, and different logic chips 6 are connected to different chipsets 2.

[0099] In one exemplary embodiment of this disclosure, the conductive structure 5 may extend from the interior of the chipset 2 into the logic chip 6, thereby enabling an electrical connection between the chipset 2 and the logic chip 6 through the conductive structure 5.

[0100] In one exemplary embodiment of this disclosure, the method for forming the semiconductor structure may further include:

[0101] Step S170: After the grinding process, a cutting process is performed in the first interval and the second interval between each of the chip groups 2 to separate each of the chip groups 2.

[0102] After grinding the insulating dielectric layer 3 and the top chip unit 211, adjacent chip groups 2 can be cut to separate each chip group 2. For example, each chip group 2 can be separated at the first and second intervals between adjacent chip groups 2, and the insulating dielectric layer 3 is retained on the outer periphery of each chip group 2 after separation. The insulating dielectric layer 3 on the outer periphery of each separated chip group 2 can be defined as the insulating layer 4.

[0103] It should be noted that during the cutting process, at least a portion of the insulating dielectric layer 3 can be retained in the first gap, that is, at least a portion of the insulating layer 4 can be retained on the sidewall of the bottom chip unit 212.

[0104] In one exemplary embodiment of this disclosure, see [link to relevant documentation]. Figure 8 As shown, the method for forming the semiconductor structure disclosed herein may further include:

[0105] Step S180: After performing the cutting process, remove the carrier board 100 and electrically connect the surface of the logic chip 6 away from the chip group 2 to a substrate 1.

[0106] The substrate 1 may include an array area and a peripheral area, which may be adjacent to each other. The peripheral area may surround the outer perimeter of the array area. The array area can be used to form external circuits connected to the chipset 2, and the peripheral area can be used to form other external circuits. For example, the array area may be a circular area, a rectangular area, or an irregularly shaped area; of course, it may also be an area of ​​other shapes, without special limitation. The peripheral area may be an annular area and may surround the outer perimeter of the array area. It may be a circular annular area, a rectangular annular area, or an annular area of ​​other shapes, which will not be listed here.

[0107] In one exemplary embodiment of this disclosure, before connecting the logic chip 6 to the substrate 1, each chip group 2, each insulating fill layer 7, an insulating layer 4, the logic chip 6, and the conductive structure 5 can be formed on a carrier board 100. Subsequently, the carrier board 100 and the insulating adhesive 200 that bonds the carrier board 100 to the logic chip 6 can be removed, thereby exposing the conductive structure 5 located on the surface of the logic chip 6 facing away from the chip group 2. Figure 7 As shown.

[0108] In some embodiments of this disclosure, see Figure 8As shown, the logic chip 6 can be bonded to the array area of ​​the substrate 1 via the adhesive layer 8. It should be noted that when the logic chip 6 is bonded to the substrate 1 via the adhesive layer 8, the conductive structures 5 on the surface of the logic chip 6 facing away from the chipset 2 can be connected to the external circuitry in the substrate 1, facilitating signal transmission via the external circuitry. Since all chip units 21 in the chipset 2 are electrically connected together, and the chip unit 21 closest to the substrate 1 is electrically connected to the logic chip 6, the data signals of all chip units 21 in the chipset 2 can be transmitted to the logic chip 6 via the chip unit 21 closest to the substrate 1, and then the data signals can be transmitted to the external circuitry in the substrate 1 via the logic chip 6.

[0109] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0110] This disclosure also provides a semiconductor structure, which can be formed by the semiconductor structure formation method in any of the above embodiments, such as... Figure 8 As shown, the semiconductor structure includes a substrate 1, a chipset 2, and an insulating layer 4, wherein:

[0111] Chipset 2 is disposed on one side of substrate 1 and includes a plurality of chip units 21 stacked in a direction perpendicular to substrate 1. The orthographic projection of each chip unit 21 on the substrate 1 is within the orthographic projection of the chip unit 21 farthest from substrate 1 on substrate 1.

[0112] An insulating layer 4 covers the outer periphery of the chipset 2, and the predetermined surface of the chip unit 21 furthest from the substrate 1 is exposed outside the insulating layer 4.

[0113] The semiconductor structure disclosed herein, on the one hand, stacks multiple chip units 21 vertically, which helps to increase storage capacity. On the other hand, since the orthographic projection of each chip unit 21 on the substrate 1 that is closest to the substrate 1 is within the orthographic projection of the chip unit 21 that is furthest from the substrate 1, the area of ​​the top chip unit 211 is increased. While keeping the overall size of the semiconductor structure unchanged, the thickness of the insulating layer 4 located on the outer periphery of the top chip unit 211 is reduced, which helps to dissipate heat. Furthermore, since the insulating layer 4 exposes a predetermined surface of the top chip unit 211, heat exchange between the chip unit 21 and the outside world can be further increased. During the operation of the chip unit 21, heat dissipation efficiency can be improved and power consumption can be reduced.

[0114] The specific details of each part of the semiconductor structure disclosed herein are described in detail below:

[0115] See Figure 8 As shown, substrate 1 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of substrate 1 here.

[0116] The substrate 1 may include an array area and a peripheral area, which may be adjacent to each other. The peripheral area may surround the outer perimeter of the array area. The array area can be used to form external circuits connected to the chipset 2, and the peripheral area can be used to form other external circuits. For example, the array area may be a circular area, a rectangular area, or an irregularly shaped area; of course, it may also be an area of ​​other shapes, without special limitation. The peripheral area may be an annular area and may surround the outer perimeter of the array area. It may be a circular annular area, a rectangular annular area, or an annular area of ​​other shapes, which will not be listed here.

[0117] See also Figure 8As shown, the chipset 2 can be formed on one side of the substrate 1 and can be electrically connected to external circuits in the substrate 1 to facilitate signal transmission. For example, the chipset 2 can be disposed in an array area of ​​the substrate 1. The chipset 2 may include multiple chip units 21. The chipset 2 can be used in integrated circuits, for example, it can be a dynamic random access memory (DRAM) or a static random access memory (SRAM), or it can be a core component in a dynamic random access memory (DRAM) or a static random access memory (SRAM). In some embodiments of this disclosure, in order to reduce the size of DRAM or SRAM while ensuring storage capacity, multiple chip units 21 can be stacked in a direction perpendicular to the substrate 1 to form the chipset 2. For example, the number of chip units 21 in the chipset 2 can be 2, 3, 4, 5, 6 or 7, and of course, other numbers are also possible, which are not specifically limited here.

[0118] In some embodiments of this disclosure, each chip unit 21 in the chipset 2 can be electrically connected to each other, which facilitates the mutual transmission of data in multiple chip units 21, thereby making it easier to transmit data from multiple different chip units 21 to the same chip unit 21. This also facilitates the simultaneous transmission of electrical signals from each chip unit 21 in the chipset 2 to the substrate 1 through the same chip unit 21, so as to connect each chip unit 21 to an external circuit and thus realize signal transmission.

[0119] In some embodiments of this disclosure, each chip unit 21 in the chipset 2 may be spaced apart along a direction perpendicular to the substrate 1. For example, each chip unit 21 may be equally spaced along a direction perpendicular to the substrate 1; for instance, adjacent chip units 21 may be spaced apart by a predetermined distance. Of course, the spacing between each chip unit 21 may not be completely equal; for example, the spacing between at least two of the multiple chip units 21 may not be equal to the spacing between other adjacent chip units 21.

[0120] In some embodiments of this disclosure, the preset distance can be 10um to 150um. For example, the preset distance can be 10um, 40um, 70um, 100um, 130um or 150um. Of course, the preset distance can also be other values, which will not be listed here.

[0121] In one exemplary embodiment of this disclosure, the chip unit 21 may be in the form of a sheet structure, and its shape may be rectangular, circular, elliptical, or irregular, without particular limitation. The thickness of each chip unit 21 may be the same or different, without particular limitation. For example, the thickness of the chip unit 21 may be 40um to 80um, specifically 40um, 50um, 60um, 70um, or 80um, and of course, other thicknesses are also possible, which will not be listed here.

[0122] In some embodiments of this disclosure, each chip unit 21 in the chipset 2 may have the same thickness. For example, the thickness of each chip unit 21 may be 50 μm, or the thickness of each chip unit 21 may be 60 μm, or the thickness of each chip unit 21 may be 70 μm; of course, each chip unit 21 may also have other thicknesses, which will not be listed here.

[0123] In one exemplary embodiment of this disclosure, the chip unit 21 may include a substrate and a circuit module. The circuit module may be disposed on the surface of the substrate. At least a portion of the chip units 21 may have the surface of the substrate with the circuit module facing the substrate 1, while the surface of the chip unit 21 without the circuit module may face the side of the chip unit 21 away from the substrate 1. For example, the surface of the substrate with the circuit module of the chip unit 21 farthest from the substrate 1 may face the substrate 1. For example, the substrate may be a wafer.

[0124] In one exemplary embodiment of this disclosure, the orthographic projection of each chip unit 21 on the substrate 1 of each chip unit 21 in the chipset 2, the side closest to the substrate 1, falls within the orthographic projection of the chip unit 21 furthest from the substrate 1. For ease of distinction, the chip unit 21 furthest from the substrate 1 can be defined as the top chip unit 211, and the chip unit 21 located between the top chip unit 211 and the substrate 1 can be defined as the bottom chip unit 212. In a direction parallel to the substrate 1, the bottom chip unit 212 may have a first width, and the top chip unit 211 may have a second width, which may be greater than the first width. That is, in the chipset 2, the area of ​​the top chip unit 211 is greater than the area of ​​any other chip unit 21 in the chipset 2.

[0125] It should be noted that in chipset 2, the areas of each chip unit 21 located between the top chip unit 211 and the substrate 1 may be equal or unequal. That is, the areas of each chip unit 21 in the bottom chip unit 212 may be equal or unequal, and no special limitation is made here.

[0126] In some embodiments of this disclosure, an insulating filler layer 7 may be provided between adjacent chip units 21. The insulating filler layer 7 can isolate adjacent chip units 21 and prevent signal crosstalk or coupling between chip units 21.

[0127] In one exemplary embodiment of this disclosure, the material of the insulating filling layer 7 can be insulating adhesive or encapsulating adhesive. The insulating filling layer 7 can isolate external water and oxygen, prevent external water and oxygen from entering the chip unit 21, thereby avoiding water and oxygen from corroding the internal structure of the chip unit 21 and extending the service life of the chip unit 21.

[0128] In some embodiments of this disclosure, the insulating filler layer 7 can fill the gap between adjacent chip units 21. The insulating filler layer 7 can support the gap between two adjacent chip units 21, and at the same time, it can balance the stress between two adjacent chip units 21, reduce the warpage of each chip unit 21, and thus improve the product yield.

[0129] There can be multiple chipsets 2, and multiple chipsets 2 can be formed on the same side of the substrate 1. The orthographic projection of each chipet 2 on the substrate 1 can be located within the array area. For example, the chipsets 2 can be distributed at intervals and can be arranged in an array within the array area of ​​the substrate 1.

[0130] In some embodiments of this disclosure, see Figure 4 As shown, adjacent chip units 21 in the same chipset 2 are electrically connected. For example, adjacent chip units 21 can be electrically connected through conductive units 51, and multiple conductive units 51 can be arranged at intervals between adjacent chip units 21. In the direction perpendicular to the substrate 1, each conductive unit 51 located in different chip units 21 can be connected to each other to form a conductive structure 5.

[0131] It should be noted that, see Figure 8 As shown, when an insulating filler layer 7 is formed between adjacent chip units 21, the conductive structure 5 can penetrate each insulating filler layer 7.

[0132] See Figure 8 As shown, an insulating layer 4 can be formed on the sidewall of the chipset 2 using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the insulating layer 4, which will not be listed here. The material of the insulating layer 4 can be an insulating material. The insulating layer 4 can be used to insulate and isolate the chipset 2 to avoid coupling or short circuits between the chipset 2 and other surrounding structures, thereby improving product yield.

[0133] It should be noted that when multiple chipsets 2 are formed on one side of the substrate 1, each chipet 2 can be provided with an insulating layer 4 on its sidewall, thereby avoiding coupling or short circuit between adjacent chipets 2 and improving product yield.

[0134] In some embodiments of this disclosure, in the direction parallel to the substrate 1, the ratio of the width of the top chip unit 211 to the thickness of the insulating layer 4 located on the sidewall of the top chip unit 211 can be 5 to 20. For example, the ratio of the width of the top chip unit 211 to the thickness of the insulating layer 4 located on the sidewall of the top chip unit 211 is 5, 10, 15 or 20. Of course, other ratios are also possible, which will not be listed here.

[0135] In some embodiments of this disclosure, and in one exemplary embodiment, the thickness of the insulating layer 4 on the sidewall of the top chip unit 211 is no greater than the thickness of the insulating layer 4 on the sidewall of the bottom chip unit 212 in a direction parallel to the substrate. For example, the thickness of the insulating layer 4 on the sidewall of the top chip unit 211 may be greater than or equal to 50 micrometers and less than or equal to 100 micrometers. Compared to the 200 micrometers in the prior art, the thickness of the insulating layer 4 on the sidewall of the top chip unit 211 in this disclosure is significantly reduced. For example, the thickness of the insulating layer 4 on the sidewall of the top chip unit 211 may be 50 micrometers, 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, or 100 micrometers. Of course, the thickness of the insulating layer 4 on the sidewall of the top chip unit 211 may also be other thicknesses, which will not be listed here.

[0136] It should be noted that, in the direction perpendicular to the substrate 1, each chip unit 21 between the top chip unit 211 and the substrate 1 can be aligned at both ends, that is, each chip unit 21 in the bottom chip unit 212 can be aligned at both ends, and the thickness of the insulating layer 4 on the outer periphery of each chip unit 21 in the bottom chip unit 212 can be equal, and the thickness of the insulating layer 4 on the outer periphery of each chip unit 21 in the bottom chip unit 212 can be greater than the thickness of the chip unit 21 on the outer periphery of the top chip unit 211.

[0137] In some embodiments of this disclosure, the semiconductor structure may further include a logic chip 6, see further details. Figure 7 and Figure 8As shown, the logic chip 6 can be formed between the substrate 1 and the chipset 2. The logic chip 6 can be bonded to the substrate 1 by an adhesive layer 8. The material of the adhesive layer 8 can be non-conductive adhesive, UV adhesive, etc. The logic chip 6 has a conductive structure 5 on the side surface away from the chipset 2, that is, each chip unit 21 in each chipset 2 can be electrically connected to the logic chip 6 so that the signals in each chip unit 21 in each chipset 2 can be interconnected with the substrate 1 through the logic chip 6.

[0138] In some embodiments of this disclosure, the logic chip 6 can be electrically connected to the chip unit 21 closest to the substrate 1 in the chipset 2. Since all the chip units 21 in the chipset 2 are electrically connected together, and the chip unit 21 closest to the substrate 1 is electrically connected to the logic chip 6, the data signals of each chip unit 21 in the chipset 2 can be transmitted to the logic chip 6 through the chip unit 21 closest to the substrate 1, and then the data signals can be transmitted to the external circuit in the substrate 1 through the logic chip 6.

[0139] In some embodiments of this disclosure, the orthographic projection of the chipset 2 onto the substrate 1 can be within the orthographic projection of the logic chip 6 onto the substrate 1. That is, the area of ​​the logic chip 6 can be larger than the area of ​​each chip unit 21 located between the top chip unit 211 and the substrate 1, and also larger than the area of ​​the top chip unit 211.

[0140] When there are multiple chipsets 2, all chipsets 2 can be electrically connected to the logic chip 6. It should be noted that either one logic chip 6 can be formed between the substrate 1 and each chipset 2, or multiple logic chips 6 can be formed at intervals along a direction parallel to the substrate 1; no special limitation is made here. When one logic chip 6 is formed between the substrate 1 and each chipset 2, each chip unit 21 in each chipset 2 closest to the substrate 1 can be electrically connected to the same logic chip 6. When multiple logic chips 6 are formed between the substrate 1 and each chipset 2 at intervals along a direction parallel to the substrate 1, each logic chip 6 can be electrically connected to at least one chipset 2, and different logic chips 6 are connected to different chipsets 2.

[0141] In one exemplary embodiment of this disclosure, the conductive structure 5 may extend from the interior of the chipset 2 into the logic chip 6, thereby enabling an electrical connection between the chipset 2 and the logic chip 6 through the conductive structure 5.

[0142] This disclosure also provides a memory, which may include the semiconductor structure in any of the above embodiments. The specific details, formation process and beneficial effects of the memory have been described in detail in the corresponding semiconductor structure and the method for forming the semiconductor structure, and will not be repeated here.

[0143] For example, the memory can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed here.

[0144] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide carrier board; A chipset is formed on one side of the carrier board. The chipset includes a plurality of chip units stacked in a direction perpendicular to the carrier board. The orthographic projection of each chip unit on the carrier board closest to the carrier board is within the orthographic projection of the chip unit furthest from the carrier board on the carrier board. An insulating dielectric layer is formed covering the chipset; A polishing process is performed to expose the predetermined surface of the chip cell furthest from the carrier plate outside the insulating dielectric layer; The number of chipsets is multiple, and the chipsets are spaced apart. The insulating dielectric layer fills the gaps between the chipsets. Each chipset includes a bottom chip unit and a top chip unit. In a direction parallel to the carrier board, adjacent bottom chip units have a first gap, and adjacent top chip units have a second gap. The width of the second gap is smaller than the width of the first gap.

2. The forming method according to claim 1, characterized in that, In a direction parallel to the carrier plate, the bottom chip unit has a first width, and the top chip unit has a second width, the second width being greater than the first width.

3. The forming method according to claim 2, characterized in that, The polishing process, which exposes a predetermined surface of the chip cell furthest from the carrier substrate outside the insulating dielectric layer, includes: The insulating dielectric layer of the first target thickness is removed by grinding to expose the top surface of the top chip cell; Continue grinding to remove the top chip unit and the insulating dielectric layer to a second target thickness, thereby exposing the predetermined surface of the top chip unit, wherein the second target thickness is not greater than the first target thickness.

4. The forming method according to claim 1, characterized in that, The chip unit includes a substrate and a circuit module formed on the surface of the substrate, with the surface of the top chip unit in which the circuit module is formed facing the carrier board.

5. The forming method according to any one of claims 1-4, characterized in that, The forming method further includes: A logic chip is formed between the chipset and the carrier board, and the orthographic projection of the chipset on the carrier board is within the orthographic projection of the logic chip on the carrier board.

6. The forming method according to claim 5, characterized in that, The forming method further includes: After the grinding process, a cutting process is performed in the first and second intervals between each of the chipsets to separate each of the chipsets.

7. The forming method according to claim 6, characterized in that, During the cutting process, at least a portion of the insulating dielectric layer is retained in the first interval.

8. The forming method according to claim 6, characterized in that, The forming method further includes: After the cutting process is performed, the carrier board is removed, and the surface of the logic chip facing away from the chipset is electrically connected to a substrate.

9. A semiconductor structure, characterized in that, include: substrate; A chipset is disposed on one side of the substrate and includes a plurality of chip units stacked in a direction perpendicular to the substrate, wherein the orthographic projection of each chip unit on the substrate closest to the substrate is within the orthographic projection of the chip unit furthest from the substrate on the substrate. The chipset includes a bottom chip unit and a top chip unit. In a direction parallel to the substrate, the bottom chip unit has a first width, and the top chip unit has a second width, the second width being greater than the first width. An insulating layer covers the outer periphery of the chipset, and a predetermined surface of the chip cell furthest from the substrate is exposed outside the insulating layer; The insulating layer is formed through the following process: An insulating dielectric layer is formed to cover the chipset. The insulating dielectric layer is then polished using a polishing process to expose the predetermined surface of the chip unit furthest from the substrate. The insulating dielectric layer remaining after polishing is the insulating layer.

10. The semiconductor structure according to claim 9, characterized in that, In a direction parallel to the substrate, the thickness of the insulating layer on the sidewall of the top chip unit is no greater than the thickness of the insulating layer on the sidewall of the bottom chip unit.

11. The semiconductor structure according to claim 10, characterized in that, The chip unit includes a substrate and a circuit module formed on the surface of the substrate, with the surface of the top chip unit in which the circuit module is formed facing the substrate.

12. The semiconductor structure according to claim 11, characterized in that, The semiconductor structure also includes: A logic chip is disposed between the substrate and the chipset, wherein the orthographic projection of the chipset on the substrate is within the orthographic projection of the logic chip on the substrate.

13. A memory, characterized in that, Includes the semiconductor structure described in any one of claims 9-12.

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