Metal line of semiconductor device and method for manufacturing metal line
By combining a buffer dielectric layer and a dielectric antireflective layer on the metal layer, the problem of chamfering the top of the metal line is solved, improving the reliability and dielectric isolation performance of the semiconductor device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CANSEMI TECH INC
- Filing Date
- 2024-02-05
- Publication Date
- 2026-07-31
AI Technical Summary
In the prior art, the metal wires of semiconductor devices are prone to top chamfering during the manufacturing process, which affects the reliability of the devices.
A buffer dielectric layer of a predetermined thickness is formed on the upper surface of the metal layer, and a dielectric anti-reflection layer and a photoresist layer are formed on it. Grooves are formed by patterning to avoid chamfering at the top of the metal lines. An isolation dielectric layer is then filled to ensure morphology and isolation performance.
This effectively avoids the need for beveling at the top of the metal wire, improving the reliability and dielectric isolation performance of the semiconductor device and ensuring its normal operation.
Smart Images
Figure CN117712034B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a metal wire for a semiconductor device and a method for manufacturing the metal wire. Background Technology
[0002] With the development of integrated circuit technology, the size of semiconductor devices is becoming smaller and smaller, and the density of metal lines in semiconductor devices is becoming larger and larger, making the morphology of the metal lines increasingly significant to the performance of the devices. Currently, in the back-end metal line fabrication process of semiconductor devices, a silicon oxynitride layer is usually formed directly on the top surface of the metal. This silicon oxynitride layer is used as a dielectric anti-reflective coating (DARC) for photolithography. Photoresist is then spin-coated onto the top surface of the silicon oxynitride layer, followed by exposure and development of the photoresist in the photolithography process. Finally, the metal layer is etched to obtain the metal line. However, this method of directly forming a silicon oxynitride layer on the top surface of the metal before photolithography results in a poor morphology of the metal line, and the top of the metal line is prone to chamfering. Metal lines with chamfered tops can cause malfunctions in semiconductor devices and affect their reliability.
[0003] Therefore, there is an urgent need to find a method for manufacturing metal wire that avoids the formation of beveled edges at the top of the wire. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a metal wire for a semiconductor device and a method for manufacturing the metal wire, so as to solve the problem that the top of the metal wire is prone to beveling in the prior art.
[0005] To achieve the above and other related objectives, the present invention provides a method for manufacturing a metal wire, comprising the following steps: A semiconductor structure is provided, wherein the upper surface layer of the semiconductor structure includes an interlayer dielectric layer and a metal layer stacked sequentially; A buffer dielectric layer of a predetermined thickness is formed on the upper surface of the metal layer, and a dielectric anti-reflection layer is formed covering the upper surface of the buffer dielectric layer; A photoresist layer is formed covering the upper surface of the dielectric antireflective layer, and the photoresist layer is patterned. Based on the patterned photoresist layer, trenches are formed that penetrate the dielectric antireflective layer, the buffer dielectric layer, and the metal layer, with the remaining portion of the metal layer after the trenches being formed serving as metal lines; An insulating dielectric layer is formed to fill the trench.
[0006] Optionally, the method for forming the buffer medium layer includes chemical vapor deposition and physical vapor deposition.
[0007] Optionally, the method for forming the dielectric antireflective layer includes chemical vapor deposition and physical vapor deposition.
[0008] Optionally, the thickness of the buffer dielectric layer is not less than the thickness of the dielectric antireflective layer.
[0009] Optionally, the dielectric antireflective layer may be made of silicon oxynitride.
[0010] Optionally, the photoresist layer includes a photoresist layer.
[0011] Optionally, after forming the trench and before forming the isolation dielectric layer, the step further includes removing the photoresist layer covering the upper surface of the dielectric antireflective layer.
[0012] Optionally, the method for forming the isolation dielectric layer includes chemical vapor deposition and physical vapor deposition.
[0013] Optionally, the material of the buffer dielectric layer is the same as the material of the isolation dielectric layer.
[0014] The present invention also provides a metal wire for a semiconductor device, wherein the metal wire for the semiconductor device is fabricated using the metal wire fabrication method described above.
[0015] As described above, the semiconductor device metal wire and its fabrication method of the present invention improve the process of forming the metal wire by forming a buffer dielectric layer of a predetermined thickness between the dielectric anti-reflection layer and the metal layer. This shifts the chamfer at the top opening of the trench during trench formation to the upper surface of the buffer dielectric layer, avoiding chamfering at the top of the formed metal wire, ensuring the morphology of the metal wire, and preventing semiconductor device malfunctions caused by chamfering at the top of the metal wire, thus improving the reliability of the semiconductor device. Furthermore, due to the formation of the isolation dielectric layer filling the trench, the combination of the buffer dielectric layer and the isolation dielectric layer ensures that the chamfer located on the upper surface of the buffer dielectric layer has no impact on the isolation performance of the device, further guaranteeing the reliability of the semiconductor device and possessing high industrial application value. Attached Figure Description
[0016] Figure 1 The diagram shown illustrates the process flow of the method for manufacturing the metal wire according to the present invention.
[0017] Figure 2 The diagram shows a cross-sectional view of the upper surface layer of a semiconductor structure used in the method for fabricating the metal wires of the present invention.
[0018] Figure 3The diagram shows a cross-sectional structure after forming a buffer medium layer, which is a method for manufacturing metal wires according to the present invention.
[0019] Figure 4 The diagram shows a cross-sectional structure after the formation of the dielectric antireflective layer in the method for manufacturing the metal wire of the present invention.
[0020] Figure 5 The diagram shows a cross-sectional structure of the patterned photoresist layer after the metal wire fabrication method of the present invention.
[0021] Figure 6 The diagram shows a cross-sectional structure after the formation of the groove in the method for manufacturing the metal wire of the present invention.
[0022] Figure 7 The diagram shows a cross-sectional structure after removing the photoresist layer in the method for manufacturing the metal wire of the present invention.
[0023] Figure 8 The diagram shows a cross-sectional structure after the formation of the isolation buffer layer in the method for manufacturing the metal wire of the present invention.
[0024] Figure 9 The diagram shown is a cross-sectional view of the metal wire fabrication method of the present invention after the formation of the isolation filler layer.
[0025] Explanation of reference numerals: 1 Semiconductor structure, 11 Interlayer dielectric layer, 12 Metal layer, 13 Metal line, 2 Buffer dielectric layer, 21 Trench, 3 Dielectric antireflective layer, 4 Photoresist layer, 5 Isolation dielectric layer, 51 Isolation buffer layer, 52 Isolation fill layer. Detailed Implementation
[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0027] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0028] Example 1
[0029] This embodiment provides a method for manufacturing a metal wire, such as... Figure 1 The diagram shown is a process flow chart of the method for manufacturing the metal wire, including the following steps: S1: A semiconductor structure is provided, wherein the upper surface layer of the semiconductor structure includes an interlayer dielectric layer and a metal layer stacked sequentially; S2: A buffer dielectric layer of a predetermined thickness is formed on the upper surface of the metal layer, and a dielectric anti-reflection layer is formed covering the upper surface of the buffer dielectric layer; S3: Form a photoresist layer covering the upper surface of the dielectric antireflective layer, and pattern the photoresist layer; S4: Based on the patterned photoresist layer, a trench is formed that penetrates the dielectric antireflective layer, the buffer dielectric layer, and the metal layer, and the remaining part of the metal layer after the trench is formed serves as a metal line; S5: Form an isolation dielectric layer that fills the trench.
[0030] Please see Figures 2 to 4 The steps S1 and S2 are performed as follows: a semiconductor structure 1 is provided, the upper surface of the semiconductor structure 1 includes an interlayer dielectric layer 11 and a metal layer 12 stacked sequentially; a buffer dielectric layer 2 of a predetermined thickness is formed on the upper surface of the metal layer 12, and a dielectric antireflection layer 3 is formed covering the upper surface of the buffer dielectric layer 2.
[0031] Specifically, such as Figure 2 The diagram shown is a cross-sectional view of the upper surface layer of the semiconductor structure 1. While ensuring the performance of the semiconductor device, the thickness and shape of the semiconductor structure 1 can be selected according to actual conditions, and are not limited here. The thickness and shape of the interlayer dielectric layer 11 can be selected according to actual conditions, and are not limited here. The thickness and shape of the metal layer 12 can be selected according to actual conditions, and are not limited here.
[0032] Specifically, the material of the interlayer dielectric layer 11 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials.
[0033] Specifically, the metal layer 12 is made of titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, nickel, zinc, lead, or other suitable conductive materials.
[0034] As an example, such as Figure 3 The diagram shown is a cross-sectional view of the buffer medium layer 2 after its formation. The method for forming the buffer medium layer 2 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
[0035] Specifically, the material of the buffer medium layer 2 includes silicon oxide, silicon nitride, or other suitable materials.
[0036] Specifically, the buffer dielectric layer 2 is used to increase the distance between the dielectric antireflective layer 3 and the metal layer 12, so that the chamfered portion generated during the formation of the trench can only extend downward into the buffer dielectric layer 2, thus avoiding the chamfering of the top of the metal line during the etching process.
[0037] Specifically, the thickness of the buffer medium layer 2 can be selected according to the actual situation, provided that the top of the metal layer 12 is not chamfered during the formation of the subsequent trench. This is not limited here.
[0038] As an example, such as Figure 4 The diagram shown is a cross-sectional view of the dielectric antireflective layer 3 after its formation. The method for forming the dielectric antireflective layer 3 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
[0039] Specifically, the dielectric antireflection layer 3 is used to reduce the amount of reflected light during the photolithography process and improve the quality of the pattern formed by subsequent photoresist. While ensuring the quality of the pattern in the subsequent photoresist layer, the thickness of the dielectric antireflection layer 3 can be selected according to the actual situation, and is not limited here.
[0040] As an example, the thickness of the buffer dielectric layer 2 is not less than the thickness of the dielectric antireflection layer 3, so as to ensure that the chamfering phenomenon generated during the subsequent etching process to form trenches has no impact on the morphology of the formed metal lines.
[0041] As an example, the dielectric antireflection layer 3 may be made of silicon oxynitride or other suitable dielectric materials that can reduce photolithographic optical reflectivity while increasing photolithographic light transmittance.
[0042] Specifically, the dielectric antireflective layer 3 can also serve as a buffer layer for the subsequent formation of the photoresist layer, thereby enhancing the bonding force between the subsequently formed photoresist layer and the metal layer 12 below the dielectric antireflective layer 3.
[0043] Please see Figures 5 to 9 Then, perform steps S3, S4, and S5: form a photoresist layer 4 covering the upper surface of the dielectric antireflection layer 3, and pattern the photoresist layer 4; form a trench 21 through the dielectric antireflection layer 3, the buffer dielectric layer 2, and the metal layer 12 based on the patterned photoresist layer 4, and the remaining part of the metal layer 12 after forming the trench 21 serves as a metal line 13; form an isolation dielectric layer 5 to fill the trench 21.
[0044] As an example, the photoresist layer 4 includes a photoresist layer or other suitable photoresist film layer. In this embodiment, a photoresist layer is used as the photoresist layer 4.
[0045] Specifically, while ensuring the quality of the photolithography process, the thickness of the photoresist layer 4 can be selected according to the actual situation, and is not limited here.
[0046] Specifically, the method for forming the photoresist layer 4 includes coating or other suitable methods. In this embodiment, a photoresist layer of a predetermined thickness is formed on the upper surface of the dielectric antireflective layer 3 by spin coating, and the photoresist layer is dried to obtain the photoresist layer 4.
[0047] Specifically, such as Figure 5 The diagram shown is a cross-sectional view of the patterned photoresist layer 4. The method for patterning the photoresist layer 4 is a conventional photoresist exposure and development process, which will not be described in detail here.
[0048] Specifically, such as Figure 6 The diagram shown is a cross-sectional view of the trench 21 after it has been formed. The method for forming the trench 21 includes dry etching, wet etching, or other suitable methods.
[0049] Specifically, while ensuring the performance of the semiconductor device, the opening size, shape, and depth of the trench 21 can be selected according to actual conditions, and are not limited here. The depth here refers to the distance between the bottom surface of the trench 21 and the opening of the trench 21.
[0050] Specifically, while ensuring that the trench 21 penetrates the metal layer 12, the bottom surface of the trench 21 can be flush with the bottom surface of the metal layer 12, or it can extend into the interlayer dielectric layer 11. In this embodiment, the bottom surface of the trench 21 extends into the interlayer dielectric layer 11.
[0051] Specifically, after the trench 21 is formed, the thickness of the metal line 13 obtained by etching the metal layer 12 is the same as the thickness of the metal layer 12. While ensuring the performance of the semiconductor device, the size and shape of the metal line 13 can be selected according to the actual situation, and are not limited here.
[0052] As an example, such as Figure 7 The diagram shown is a cross-sectional view of the structure after the photoresist layer 4 is removed. After the trench 21 is formed and before the isolation dielectric layer 5 is formed, the process also includes removing the photoresist layer 4 covering the upper surface of the dielectric antireflective layer 3.
[0053] Specifically, the method for removing the photoresist layer 4 is a commonly used photoresist glass method, which can be dry etching or wet etching, and will not be described in detail here.
[0054] As an example, the method for forming the isolation dielectric layer 5 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
[0055] Specifically, such as Figure 8 and Figure 9 The figures shown are cross-sectional structural diagrams after the formation of the isolation buffer layer 51 and the isolation filling layer 52, respectively. The formation of the isolation dielectric layer 5 includes the following steps: forming an isolation buffer layer 51 that covers the bottom surface of the trench 21, the inner wall of the trench 21, and the exposed surface of the dielectric anti-reflection layer 3; forming an isolation filling layer 52 that covers the exposed upper surface of the isolation buffer layer 51 and fills the remaining space of the trench 21 after removing the isolation buffer layer 51. The isolation buffer layer 51 and the isolation filling layer 52 constitute the isolation dielectric layer 5.
[0056] Specifically, the material of the isolation buffer layer 51 includes silicon oxide, silicon oxynitride, or other suitable isolation dielectric materials; the material of the isolation fill layer 52 includes silicon oxide, silicon oxynitride, or other suitable isolation dielectric materials.
[0057] As an example, the material of the buffer dielectric layer 2 is the same as that of the isolation dielectric layer 5, that is, the materials of the buffer dielectric layer 2, the isolation buffer layer 51, and the isolation fill layer 52 are the same. In this embodiment, silicon oxide is used as the buffer dielectric layer 2, the isolation buffer layer 51, and the isolation fill layer 52.
[0058] Specifically, while ensuring the performance of the semiconductor device, the materials of the buffer dielectric layer 2, the isolation buffer layer 51, and the isolation fill layer 52 can also be different.
[0059] Specifically, by improving the process of forming the metal line 13 of the semiconductor device, a buffer dielectric layer 2 of a predetermined thickness is formed between the metal layer 12 and the dielectric antireflection layer 3. During the etching process of forming the trench 21, the chamfer generated at the opening of the trench 21 is located on the upper surface of the dielectric antireflection layer 3 and the buffer dielectric layer 2. This causes the chamfer generated by the etching to move upward into the buffer dielectric layer 2, avoiding the problem of chamfering at the top of the metal line 13 during the formation of the metal line 13, and ensuring the morphology of the formed metal line 13.
[0060] Specifically, since the buffer dielectric layer 2, the dielectric antireflection layer 3, and the isolation dielectric layer 5 filling the trench 21 are all dielectric materials, after being chamfered and transferred to the upper surface of the buffer dielectric layer 2, they are then filled by the isolation dielectric layer 5. This has no impact on the dielectric isolation performance of each part in the semiconductor device, thus ensuring the performance of the device.
[0061] The method for fabricating the metal wire in this embodiment improves the process of forming the metal wire 13. After forming the buffer dielectric layer 2 of a predetermined thickness on the upper surface of the metal layer 12, the dielectric antireflection layer 3 and the photoresist layer 4 covering the upper surface of the dielectric antireflection layer 3 are formed. The photoresist layer 4 is then patterned, and the trench 21 is formed based on the patterned photoresist layer 4. Since the buffer dielectric layer 2 is formed between the dielectric antireflection layer 3 and the metal layer 12, the chamfer generated at the opening of the trench 21 during the etching process is transferred to the upper surface of the buffer dielectric layer 2. This avoids the problem of chamfering at the top of the metal wire 13 during the formation of the metal wire 13, ensuring the morphology of the formed metal wire 13. At the same time, due to the formation of the isolation dielectric layer 5 filling the trench 21, the chamfer located on the upper surface of the buffer dielectric layer 2 has no impact on the isolation performance of the device, ensuring the performance of the device.
[0062] Example 2
[0063] This embodiment provides a metal wire for a semiconductor device, such as... Figure 9 The diagram shown is a cross-sectional view of the metal wire portion of the semiconductor device. The metal wire of the semiconductor device is fabricated using the metal wire fabrication method described in Embodiment 1.
[0064] Specifically, since the metal wire 13 in the semiconductor device is fabricated using the metal wire fabrication method described in Embodiment 1, the problem of top chamfering of the metal wire 13 is avoided, ensuring the morphology of the fabricated metal wire and avoiding device malfunctions caused by top chamfering of the metal wire 13.
[0065] Specifically, by using the metal wire fabrication method described in Embodiment 1 to fabricate the metal wire 13 in the semiconductor device, the reliability of the semiconductor device is improved.
[0066] The metal wires of the semiconductor device in this embodiment are fabricated using the metal wire fabrication method described in Embodiment 1, which ensures the morphology of the obtained metal wire 13, avoids the abnormality of the semiconductor device caused by the top chamfer of the metal wire 13, and improves the reliability of the semiconductor device.
[0067] In summary, the metal wire and its fabrication method for the semiconductor device of the present invention improve the metal wire formation process by forming a buffer dielectric layer of a predetermined thickness on the upper surface of the metal layer before forming the dielectric anti-reflection layer. This shifts the chamfer at the top opening of the trench generated during trench formation to the upper surface of the buffer dielectric layer, avoiding the problem of chamfering at the top of the formed metal wire, ensuring the morphology of the formed metal wire, and preventing semiconductor device malfunctions caused by chamfering at the top of the metal wire, thus improving the reliability of the semiconductor device. Furthermore, the formation of the isolation dielectric layer filling the trench ensures that the chamfer on the upper surface of the buffer dielectric layer has no impact on the isolation performance of the device, further guaranteeing the reliability of the semiconductor device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0068] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a metal wire, characterized in that, Includes the following steps: A semiconductor structure is provided, wherein the upper surface layer of the semiconductor structure includes an interlayer dielectric layer and a metal layer stacked sequentially; A buffer dielectric layer of a predetermined thickness is formed on the upper surface of the metal layer, and a dielectric anti-reflection layer is formed covering the upper surface of the buffer dielectric layer; A photoresist layer is formed covering the upper surface of the dielectric antireflective layer, and the photoresist layer is patterned. Based on the patterned photoresist layer, a trench is formed that penetrates the dielectric antireflective layer, the buffer dielectric layer, and the metal layer. The remaining portion of the metal layer after the trench is formed serves as a metal line. The thickness of the buffer dielectric layer is not less than the thickness of the dielectric antireflective layer, so as to increase the distance between the dielectric antireflective layer and the metal layer, so that the chamfered portion generated during the formation of the trench can only extend downward into the buffer dielectric layer. Remove the photoresist layer covering the upper surface of the dielectric antireflective layer to form an isolation dielectric layer that fills the trench.
2. The method for manufacturing a metal wire according to claim 1, characterized in that: Methods for forming the buffer medium layer include chemical vapor deposition and physical vapor deposition.
3. The method for manufacturing a metal wire according to claim 1, characterized in that: The methods for forming the dielectric antireflective layer include chemical vapor deposition and physical vapor deposition.
4. The method for manufacturing a metal wire according to claim 1, characterized in that: The dielectric antireflective layer is made of silicon oxynitride.
5. The method for manufacturing a metal wire according to claim 1, characterized in that: The photoresist layer includes a photoresist layer.
6. The method for manufacturing a metal wire according to claim 1, characterized in that: Methods for forming the isolation dielectric layer include chemical vapor deposition and physical vapor deposition.
7. The method for manufacturing a metal wire according to claim 1, characterized in that: The material of the buffer dielectric layer is the same as that of the isolation dielectric layer.
8. A metal wire for a semiconductor device, characterized in that, The metal wires of the semiconductor device are fabricated using the metal wire fabrication method described in any one of claims 1 to 7.