Io circuit and chip

Abstract

The application discloses an IO circuit and a chip. The IO circuit comprises an ESD protection device, a first metal layer, a second metal layer, a first wiring layer and a PAD body arranged in sequence. The second metal layer comprises a second comb structure, and the second comb structure comprises a second base and a plurality of second comb strips. The first wiring layer comprises a first comb structure, and the first comb structure comprises a first base and a plurality of first comb strips. The first base is arranged opposite to the second base, and the first comb strip is arranged opposite to the second comb strip. The first base is electrically connected to the second base through a third through hole. The first comb strip is electrically connected to the corresponding second comb strip through a second through hole. The second comb strip is electrically connected to the first metal layer through a first through hole. The vertical projection of a second hole area for arranging the second through hole overlaps with the vertical projection of a first hole area for arranging the first through hole. The PAD body is electrically connected to the first base. The technical scheme of the embodiment of the application improves the ESD protection capability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to I / O circuits and chips. Background Technology

[0002] Mixed-signal chips typically include I / O (input / output) ports. These ports consist of the PAD (Pad Object) itself and an ESD (Electrostatic Discharge) device. The PAD connects to the ESD protection device, which forms a discharge path to dissipate the ESD current, preventing irreversible damage to the chip. However, in related technologies, the wiring path from the PAD to the ESD protection device is prone to burn-out, leading to weakened ESD protection capabilities. Summary of the Invention

[0003] This invention provides an IO circuit and chip to improve the layout design defects of the connection path from the PAD body to the ESD protection device, thereby reducing the possibility of failure on the connection path from the PAD body to the ESD protection device and improving ESD protection capability.

[0004] According to one aspect of the present invention, an I / O circuit is provided, comprising:

[0005] A first metal layer is located above the ESD protection device; the connection terminals of the ESD protection device are led into the first metal layer;

[0006] The second metal layer is located on the side of the first metal layer away from the ESD protection device; the second metal layer includes a second comb-like structure, the second comb-like structure including a second base and multiple second comb strips;

[0007] The first trace layer is located on the side of the second metal layer away from the first metal layer; the first trace layer includes a first comb structure, the first comb structure includes a first base and a plurality of first comb strips, the first base is disposed opposite to the second base, and the first comb strips are disposed opposite to the second comb strips;

[0008] The first base is electrically connected to the second base through the third through hole, the first comb bar is electrically connected to the corresponding second comb bar through the second through hole, and the second comb bar is electrically connected to the first metal layer through the first through hole; the vertical projection of the second hole area used to set the second through hole overlaps with the vertical projection of the first hole area used to set the first through hole.

[0009] The PAD body is located on the side of the first trace layer away from the second metal layer; one end of the PAD body is electrically connected to the first base.

[0010] Optionally, the first trace layer includes a first electrostatic discharge trace and multiple first power traces, wherein the first electrostatic discharge trace and the first power trace extend in the same direction.

[0011] The first electrostatic discharge trace forms the first base, and the first part of the first power trace adjacent to the first electrostatic discharge trace forms the plurality of first combs.

[0012] Optionally, the second part of the first power line adjacent to the first electrostatic discharge line forms a third comb structure, and the third comb structure and the first comb structure form a first interdigital structure.

[0013] The third comb-like structure includes a third base and multiple third comb strips, the width of which is smaller than the width of the first comb strip.

[0014] Optionally, the first power trace adjacent to the first electrostatic discharge trace is the first first power trace, and the first power trace adjacent to the first first power trace is the second first power trace.

[0015] The third part of the structure of the first power supply trace and the part of the structure of the second power supply trace constitute a fourth comb structure, and the fourth comb structure and the first comb structure constitute a second interdigitated structure.

[0016] The fourth comb-like structure includes a fourth base and multiple fourth comb strips, the width of which is smaller than the width of the first comb strip.

[0017] Optionally, the first trace layer includes a first electrostatic discharge trace and multiple first power traces, wherein the first electrostatic discharge trace and the first power trace extend in the same direction.

[0018] The first base is formed by the first electrostatic discharge trace and the fourth part of the first power trace adjacent to the first electrostatic discharge trace.

[0019] The plurality of first combs are formed by the fifth part of the first power supply trace adjacent to the first electrostatic discharge trace.

[0020] Optionally, the first trace layer includes a first electrostatic discharge trace and multiple first power traces, wherein the first electrostatic discharge trace and the first power trace extend in the same direction.

[0021] The IO circuit also includes a second to an nth routing layer sequentially disposed between the first routing layer and the PAD body, where n is a positive integer greater than or equal to 3;

[0022] The m-th routing layer includes the m-th electrostatic discharge routing layer and multiple m-th power routing layers; m is a positive integer greater than or equal to 2 and less than or equal to n.

[0023] The m-th electrostatic discharge trace is arranged opposite to the first electrostatic discharge trace, and the m-th power trace is arranged opposite to the first power trace;

[0024] One end of the PAD body is electrically connected to the first base via the nth electrostatic discharge line to the second electrostatic discharge line.

[0025] Optionally, the second comb bar is electrically connected to a metal wire in the first metal layer through the first through hole, and the metal wire is disposed opposite to the second comb bar.

[0026] Optionally, the vertical projection of the first base does not overlap with the vertical projection of the metal wire; the length of the first comb bar is less than the length of the metal wire, and the length of the metal wire is less than the length of the second comb bar.

[0027] Optionally, the metal wire is electrically connected to the connection terminal of the ESD protection device through the fourth through hole; the vertical projection of the fourth hole area used to set the fourth through hole overlaps with the vertical projection of the first hole area.

[0028] Optionally, the first comb bar corresponds one-to-one with the second comb bar; the second comb bar corresponds one-to-one with the metal wire.

[0029] According to another aspect of the present invention, a chip is provided, comprising the I / O circuit described in the preceding aspect.

[0030] The technical solution of this invention includes an IO circuit comprising a PAD body, an ESD protection device, a first metal layer, a second metal layer, and a first trace layer; the first metal layer is located above the ESD protection device; the connection terminals of the ESD protection device are led into the first metal layer; the second metal layer is located on the side of the first metal layer away from the ESD protection device; the second metal layer includes a second comb-like structure, the second comb-like structure including a second base and multiple second comb strips; the first trace layer is located on the side of the second metal layer away from the first metal layer; the PAD body is located on the side of the first trace layer away from the second metal layer.

[0031] Based on this, a first wiring layer is provided, including a first comb-shaped structure. The first comb-shaped structure includes a first base and multiple first comb bars. The first base and a second base are arranged opposite to each other, and the first comb bars and the second comb bars are arranged opposite to each other. The first base is electrically connected to the second base through a third through hole, the first comb bar is electrically connected to the corresponding second comb bar through a second through hole, and the second comb bar is electrically connected to the first metal layer through a first through hole. The vertical projection of the second hole area used to set the second through hole overlaps with the vertical projection of the first hole area used to set the first through hole. One end of the PAD body is electrically connected to the first base. This ensures that the connection path from the PAD body to the ESD protection device no longer has only a single layer of metal wiring at certain local locations, but always has at least two layers of metal wiring. This improves the bottleneck situation of the total width of the local wiring path, and also improves the layout design defects of the connection path from the PAD body to the ESD protection device. This reduces the possibility of burnout due to electromigration effect on the connection path, reduces the possibility of failure on the connection path from the PAD body to the ESD protection device, and improves the ESD protection capability.

[0032] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a cross-sectional structural diagram of an I / O circuit in related technologies;

[0035] Figure 2 This is a top view schematic diagram of an I / O circuit provided in an embodiment of the present invention;

[0036] Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure of the IO circuit shown along the section line CC'.

[0037] Figure 4 This is a top view schematic diagram of a second metal layer provided in an embodiment of the present invention;

[0038] Figure 5 This is a top view of a first wiring layer provided in an embodiment of the present invention;

[0039] Figure 6This is a top view schematic diagram of another first wiring layer provided in an embodiment of the present invention;

[0040] Figure 7 This is a top view schematic diagram of another first wiring layer provided in an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] As mentioned in the background section, burnout occurs on the wiring path from the PAD body to the ESD protection device, resulting in weakened ESD protection capability. Through long-term research, the inventors have discovered the following reasons: Figure 1 This is a cross-sectional structural diagram of an I / O circuit in related technologies, for reference. Figure 1The I / O circuit includes an ESD protection device, a first metal film layer M1, a second metal film layer M2, a third metal film layer M3, a fourth metal film layer M4, a fifth metal film layer M5, and a PAD body. The connection terminals of the ESD protection device (e.g., Source, Drain, Gate, or Bulk) are led into the first metal film layer M1. The third to fifth metal film layers M3 are used to set power supply traces (e.g., VSS or VDD traces). The PAD body is electrically connected to the second metal film layer M2 through the film patterns in the fifth to third metal film layers M5. The film pattern of the second metal film layer M2 is electrically connected to the film pattern of the first metal film layer M1. Therefore, the connection path from the PAD body to the ESD protection device is path H. Because there is only a single-layer metal connection at position F on path H, under large ESD current conditions, electromigration can easily occur at position F, leading to burnout.

[0044] In view of this, embodiments of the present invention provide an IO circuit and chip to improve the layout design defects of the connection path from the PAD body to the ESD protection device, thereby reducing the possibility of faults occurring on the connection path from the PAD body to the ESD protection device and improving ESD protection capability. Figure 2 This is a top view schematic diagram of an I / O circuit provided in an embodiment of the present invention. Figure 3 yes Figure 2 The diagram shows a cross-sectional view of the I / O circuit along section line CC'. Figure 4 This is a top view schematic diagram of a second metal layer provided in an embodiment of the present invention. Figure 5 This is a top view of a first wiring layer provided in an embodiment of the present invention, combined with... Figures 2 to 5 The IO circuit provided in this embodiment of the invention includes: an ESD protection device, a first metal layer m1, a second metal layer m2, a first trace layer m3, and a PAD body;

[0045] The first metal layer m1 is located above the ESD protection device, and the connection terminals of the ESD protection device are led into the first metal layer m1; the second metal layer m2 is located on the side of the first metal layer m1 away from the ESD protection device, and the second metal layer m2 includes a second comb structure 200, the second comb structure 200 includes a second base 210 and multiple second comb bars 220; the first wiring layer m3 is located on the side of the second metal layer m2 away from the first metal layer m1, and the first wiring layer m3 includes a first comb structure 100, the first comb structure 100 includes a first base 110 and multiple first comb bars 120, the first base 110 and the second base 210 are disposed opposite to each other, and the first comb bars 120 and the second comb bars 220 are disposed opposite to each other;

[0046] The first base 110 is electrically connected to the second base 210 through a third through hole, the first comb 120 is electrically connected to the corresponding second comb 220 through a second through hole, and the second comb 220 is electrically connected to the first metal layer m1 through a first through hole; the vertical projection of the second hole region 320 used to set the second through hole overlaps with the vertical projection of the first hole region 310 used to set the first through hole; the PAD body is located on the side of the first wiring layer m3 away from the second metal layer m2; one end of the PAD body is electrically connected to the first base 110.

[0047] Specifically, the IO circuit provided in this embodiment is not limited to GPIO (general purpose IO), but can also be applied to other purely analog signal IO or power / ground IO. Multiple ESD protection devices can be used; this embodiment does not specify a particular number of ESD protection devices. ESD protection devices may include diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs), such as NMOS or PMOS. The connection terminals of the ESD protection devices are, for example, Source, Drain, Gate, or Bulk. Each ESD protection device requires at least one metal layer to bring out its four terminals (Source / Drain / Gate / Bulk). In this embodiment, the connection terminals of the ESD protection device are led to the first metal layer m1.

[0048] The PAD body has a flat plate structure. The PAD body can be composed of multiple layers of metal films. Figure 3 The illustration shows that the PAD body is composed of two metal film layers. In this embodiment, the second metal layer m2 is used not only for the electrical connection between the PAD body and the ESD protection device, but also for the electrical connection between other parts of the chip. Based on the layout design according to the actual needs of the chip, Figure 4 The example illustrates a partial pattern of a second metal layer m2, which includes a second comb structure 200 and some in-chip traces 230; the second comb structure 200 includes a second base 210 and multiple second comb bars 220, the second base 210 and the second comb bars 220 extending in the y direction and the x direction, respectively.

[0049] The first routing layer m3 can be used to set up power ground traces, such as VSS or VDD traces. In the first comb structure 100, the extension directions of the first base 110 and the first comb bar 120 are along the y-direction and x-direction, respectively. In the z-direction, the vertical projections of the center lines of the first base 110 and the second base 210 along the y-direction can coincide (in which case the first base 110 and the second base 210 are facing each other) or be parallel; and in the z-direction, the vertical projections of the center lines of the first comb bar 120 and the second comb bar 220 along the x-direction can coincide (in which case the first comb bar 120 and the second comb bar 220 are facing each other) or be parallel.

[0050] Generally, interlayer insulation layers are provided between each metal layer and wiring layer, so these layers can usually be electrically connected via vias. One end of the PAD body is electrically connected to the first base 110. The first base 110 is electrically connected to the second base 210 through a large number of third vias. The first comb 120 is electrically connected to the corresponding second comb 220 through a large number of second vias. The second comb 220 is electrically connected to the first metal layer m1 through a large number of first vias. The area of ​​the interlayer insulation layer used to set all the third vias is designated as the third via area 330, the area of ​​the interlayer insulation layer used to set all the second vias is designated as the second via area 320, and the area of ​​the interlayer insulation layer used to set all the first vias is designated as the first via area 310. (Reference) Figure 3 In the z-direction, the vertical projections of the second hole region 320 and the first hole region 310 overlap.

[0051] contrast Figure 1 and Figure 3The technical solution of this invention embodiment includes a first comb-shaped structure 100 in the first wiring layer m3. The first comb-shaped structure 100 includes a first base 110 and multiple first comb bars 120. The first base 110 is electrically connected to one end of the PAD body. The first base 110 is opposite to a second base 210 and is electrically connected to the second base 210 through a third through-hole. The first comb bars 120 are opposite to second comb bars 220 and are electrically connected to the second comb bars 220 through second through-holes. The second comb bars 220 are electrically connected to the first metal layer m1 through first through-holes. The second hole region 320 is connected to the first hole region. The vertical projections of region 310 overlap, resulting in at least two layers of metal wiring at position F' on the connection path H' from the PAD body to the ESD protection device. This improves the bottleneck situation of the total width of the local trace (at position F') on the connection path H', thus correcting the layout design flaws of the connection path H' from the PAD body to the ESD protection device. This reduces the possibility of burnout due to electromigration effects on the connection path H', lowers the probability of failure on the connection path H' from the PAD body to the ESD protection device, and improves the ESD protection capability. Figure 3 The text also uses a "dot-line" example to illustrate the ESD current as I.

[0052] In this embodiment of the invention, optionally, each first comb bar 120 in the first comb structure 100 corresponds to one second comb bar 220 in the second comb structure 200. This embodiment does not specifically limit the number of first comb bars 120 in the first comb structure 100 and the number of second comb bars 220 in the second comb structure 200. Generally, the number of first comb bars 120 in the first comb structure 100 can be set to be less than or equal to the number of second comb bars 220 in the second comb structure 200.

[0053] Combination Figure 3 and Figure 5 Based on the above embodiments, optionally, the first wiring layer m3 includes a first electrostatic discharge line 410 and multiple first power lines 510. The first electrostatic discharge line 410 and the first power lines 510 extend in the same direction, both along the y-direction. The IO circuit also includes a second wiring layer m4 to an nth wiring layer sequentially disposed between the first wiring layer m3 and the PAD body, where n is a positive integer greater than or equal to 3. Figure 3 The example diagram illustrates that the IO circuit also includes a second routing layer m4 to a third routing layer m5 sequentially disposed between the first routing layer m3 and the PAD body; the m-th routing layer includes the m-th electrostatic discharge routing line and multiple m-th power supply routing lines, where m is a positive integer greater than or equal to 2 and less than or equal to n. Figure 3The diagram illustrates that the second wiring layer m4 includes a second electrostatic discharge (ESD) trace 420 and multiple second power traces 520, and the third wiring layer m5 includes a third ESD trace 430 and multiple third power traces 530. The m-th ESD trace is positioned opposite to the first ESD trace 410 (e.g., facing each other), and the m-th power trace is positioned opposite to the first power trace 510 (e.g., facing each other). One end of the PAD body is electrically connected to the first base 110 via the n-th ESD trace to the second ESD trace 420. The widths of the first ESD trace 410 and the m-th ESD trace along the x-direction can be the same or different; the widths of the first power trace 510 and the m-th power trace along the x-direction can be the same; each of the first power traces 510 and the m-th power trace can be connected to VSS or VDD.

[0054] Continue to refer to Figure 3 Based on the above embodiments, optionally, the second comb bar 220 is electrically connected to the metal wire 800 in the first metal layer m1 through the first through hole, and the metal wire 800 and the second comb bar 220 are arranged opposite to each other (e.g., facing each other). For example, in the first metal layer m1, the structure of the metal wire 800 can be strip-shaped, the extension direction of the metal wire 800 is along the x-direction, and the width of the metal wire 800 along the y-direction can be smaller than the width of the second comb bar 220 along the y-direction. The metal wire 800 and the second comb bar 220 can have a one-to-one correspondence.

[0055] Continue to refer to Figure 3 Based on the above embodiments, optionally, the length of the metal wire 800 along the x-direction is less than the length of the second comb bar 220 along the x-direction, the length of the metal wire 800 along the x-direction is greater than the length of the first comb bar 120 along the x-direction, and in the z-direction, the vertical projection of the metal wire 800 does not overlap with the vertical projection of the first base 110. In this embodiment, the specific length of the first comb bar 120 along the x-direction can be set according to actual needs and is not specifically limited thereto.

[0056] Continue to refer to Figure 3Based on the above embodiments, optionally, the metal line 800 is electrically connected to the connection terminals of the ESD protection device through a large number of fourth through holes; the area of ​​the interlayer insulation layer used to set all the fourth through holes is designated as the fourth hole area 340, and the vertical projection of the fourth hole area 340 overlaps with the vertical projection of the first hole area 310. Thus, the technical solution of this embodiment, while reducing the possibility of faults occurring on the connection path between the first trace layer m3 and the second metal layer m2, also avoids faults on the connection path between the second metal layer m2 and the first metal layer m1 due to layout design defects, thereby further reducing the possibility of faults occurring on the connection path H' from the PAD body to the ESD protection device and improving ESD protection capability.

[0057] In this embodiment of the invention, there are many ways to form the first comb structure 100 in the first wiring layer m3. Several of them are described below as examples, but they are not intended to limit the invention.

[0058] In one embodiment of the present invention, reference continues... Figure 5 Optionally, the first electrostatic discharge trace 410 constitutes the first base 110, and the first portion of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410 constitutes multiple first combs 120. (Continue to refer to...) Figure 6 Optionally, the second part of the first power supply line 510_1 adjacent to the first electrostatic discharge line 410 constitutes a third comb structure 600. The third comb structure 600 and the first comb structure 100 constitute a first interdigital structure. The third comb structure 600 includes a third base 610 and multiple third comb bars 620. The width of the third comb bars 620 is smaller than the width of the first comb bars 120.

[0059] Specifically, the accompanying drawings only illustrate a few first power traces 510, while the actual first trace layer m3 includes a large number of first power traces 510. In this embodiment, to improve the layout design defects of the connection path H' from the PAD body to the ESD protection device by ensuring that position F' always has at least two layers of metal interconnects instead of just a single layer, a small portion of the structure of the first power trace 510_1 adjacent to the first electrostatic discharge trace 410 is allocated to the connection path H' from the PAD body to the ESD protection device. This involves redistributing the metal resources of the first trace layer m3 so that position F' always has at least two layers of metal interconnects instead of just a single layer. Furthermore, this design does not affect or damage the layout design of other trace layers, thus not affecting or damaging the original architecture of the IO circuit, and eliminating the need for additional structures in the IO circuit.

[0060] Furthermore, after a small portion of the structure of the first power line 510_1 adjacent to the first electrostatic discharge line 410 is used to make the first comb bar 120 of the first comb structure 100, a small portion of the structure of the first power line 510_1 can be further used to make the third comb structure 600. The third comb structure 600 and the remaining structure of the first power line 510_1 can continue to be used as power lines. The third comb bar 620 in the third comb structure 600 can facilitate the electrical connection between the first power line 510_1 and the ESD protection device below, for example, by connecting the third comb bar 620 to the connection terminal of the ESD protection device through a through hole.

[0061] In another embodiment of the present invention Figure 6 This is a top view schematic diagram of another first wiring layer m3 provided in an embodiment of the present invention, for reference. Figure 6 Optionally, the first electrostatic discharge trace 410 constitutes the first base 110, and the first portion of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410 constitutes multiple first combs 120. (Continue to refer to...) Figure 5 Optionally, the first power line 510 adjacent to the first electrostatic discharge line 410 is the first power line 510_1, and the first power line 510 adjacent to the first power line 510_1 is the second power line 510_2; the third part of the structure of the first power line 510_1 and part of the structure of the second power line 510_2 constitute a fourth comb structure, and the fourth comb structure and the first comb structure 100 constitute a second interdigitated structure; the fourth comb structure includes a fourth base 710 and multiple fourth comb bars 720, and the width of the fourth comb bar 720 is smaller than the width of the first comb bar 120.

[0062] Specifically, when the length of the first comb bar 120 along the x-direction is set to be relatively long, the structure of the first power line 510_1 adjacent to the first electrostatic discharge line 410 along the y-direction is still sufficient to be used to make the third comb bar 620. However, the structure of the first power line 510_1 along the x-direction is no longer sufficient to make the third base 610. Therefore, a part of the structure of the second first power line 510_2 is used as the third base 610. At this time, the third comb bar 620 and the third base 610 constitute the fourth comb structure.

[0063] In another embodiment of the present invention Figure 7 This is a top view schematic diagram of another first wiring layer m3 provided in an embodiment of the present invention, for reference. Figure 7Optionally, the first base 110 is formed by the first electrostatic discharge line 410 and the fourth part of the first power supply line 510_1 adjacent to the first electrostatic discharge line 410; and multiple first combs 120 are formed by the fifth part of the first power supply line 510_1 adjacent to the first electrostatic discharge line 410.

[0064] Specifically, when the width of the first electrostatic discharge trace 410 along the x-direction is small enough that the first electrostatic discharge trace 410 alone is insufficient to serve as the first base 110, a small portion of the structure of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410 may be used to make the first base 110, so that a portion of the structure of the first power supply trace 510_1 and the first electrostatic discharge trace 410 together constitute the first base 110.

[0065] In summary, the specific ways in which the metal resources of the first power trace 510 in the first trace layer m3 are misappropriated in the embodiments of the present invention are only examples. As long as the first comb structure 100 and the third comb structure 600 that meet the actual needs can be formed, or the first comb structure 100 and the fourth comb structure that meet the actual needs can be formed, it does not constitute a specific limitation of the present invention.

[0066] The technical solution of this invention is to redistribute the metal resources of the first trace layer m3 in the IO circuit without affecting or damaging the original architecture of the IO circuit, and without adding any additional structures to the IO circuit. Specifically, the structure of the first power trace 510 in the first trace layer m3 and the first electrostatic discharge trace 410 is repurposed so that there are always at least two layers of metal traces at position F' instead of just a single layer of metal traces. This improves the bottleneck situation of the total width of the local traces (at position F') on the connection path H', that is, it improves the layout design defects of the connection path H' from the PAD body to the ESD protection device, thereby reducing the possibility of burnout due to electromigration effect on the connection path H', reducing the possibility of failure on the connection path H' from the PAD body to the ESD protection device, and improving the ESD protection capability.

[0067] Based on the above embodiments, this invention also provides a chip, which includes the I / O circuit provided by any of the above technical solutions. The chip and I / O circuit provided in this invention belong to the same inventive concept and can achieve the same technical effects; therefore, repeated details will not be elaborated here.

[0068] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An I / O circuit, characterized in that, include: The first metal layer is located above the ESD protection device; The connection terminals of the ESD protection device are led into the first metal layer; The second metal layer is located on the side of the first metal layer away from the ESD protection device; the second metal layer includes a second comb-like structure, the second comb-like structure including a second base and multiple second comb strips; The first trace layer is located on the side of the second metal layer away from the first metal layer; the first trace layer includes a first comb structure, the first comb structure includes a first base and a plurality of first comb strips, the first base is disposed opposite to the second base, and the first comb strips are disposed opposite to the second comb strips; The first base is electrically connected to the second base through a third through hole, the first comb bar is electrically connected to the corresponding second comb bar through a second through hole, and the second comb bar is electrically connected to the first metal layer through a first through hole; the vertical projection of the second hole area used to set the second through hole overlaps with the vertical projection of the first hole area used to set the first through hole. The PAD body is located on the side of the first trace layer away from the second metal layer; one end of the PAD body is electrically connected to the first base.

2. The I / O circuit according to claim 1, characterized in that, The first trace layer includes a first electrostatic discharge trace and multiple first power traces, wherein the first electrostatic discharge trace and the first power trace extend in the same direction. The first electrostatic discharge trace forms the first base, and the first part of the first power trace adjacent to the first electrostatic discharge trace forms the plurality of first combs.

3. The I / O circuit according to claim 2, characterized in that, The second part of the first power line adjacent to the first electrostatic discharge line forms a third comb structure, and the third comb structure and the first comb structure form a first interdigitated structure. The third comb-like structure includes a third base and multiple third comb strips, the width of which is smaller than the width of the first comb strip.

4. The I / O circuit according to claim 2, characterized in that, The first power trace adjacent to the first electrostatic discharge trace is the first first power trace, and the first power trace adjacent to the first first power trace is the second first power trace. The third part of the structure of the first power supply trace and the part of the structure of the second power supply trace constitute a fourth comb structure, and the fourth comb structure and the first comb structure constitute a second interdigitated structure. The fourth comb-like structure includes a fourth base and multiple fourth comb strips, the width of which is smaller than the width of the first comb strip.

5. The I / O circuit according to claim 1, characterized in that, The first trace layer includes a first electrostatic discharge trace and multiple first power traces, wherein the first electrostatic discharge trace and the first power trace extend in the same direction. The first base is formed by the first electrostatic discharge trace and the fourth part of the first power trace adjacent to the first electrostatic discharge trace. The plurality of first combs are formed by the fifth part of the first power supply trace adjacent to the first electrostatic discharge trace.

6. The I / O circuit according to claim 1, characterized in that, The first trace layer includes a first electrostatic discharge trace and multiple first power traces, wherein the first electrostatic discharge trace and the first power trace extend in the same direction. The IO circuit also includes a second to an nth routing layer sequentially disposed between the first routing layer and the PAD body, where n is a positive integer greater than or equal to 3; The m-th routing layer includes the m-th electrostatic discharge routing layer and multiple m-th power routing layers; m is a positive integer greater than or equal to 2 and less than or equal to n; The m-th electrostatic discharge trace is arranged opposite to the first electrostatic discharge trace, and the m-th power trace is arranged opposite to the first power trace; One end of the PAD body is electrically connected to the first base via the nth electrostatic discharge line to the second electrostatic discharge line.

7. The I / O circuit according to claim 1, characterized in that, The second comb bar is electrically connected to the metal wire in the first metal layer through the first through hole, and the metal wire is arranged opposite to the second comb bar.

8. The I / O circuit according to claim 7, characterized in that, The vertical projection of the first base does not overlap with the vertical projection of the metal wire; the length of the first comb bar is less than the length of the metal wire, and the length of the metal wire is less than the length of the second comb bar.

9. The I / O circuit according to claim 7, characterized in that, The metal wire is electrically connected to the connection terminal of the ESD protection device through the fourth through hole; the vertical projection of the fourth hole area used to set the fourth through hole overlaps with the vertical projection of the first hole area.

10. A chip, characterized in that, Includes the I / O circuit as described in any one of claims 1-9.

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