Semiconductor device and method of manufacturing the same

Abstract

Embodiments relate to a semiconductor device and a manufacturing method thereof. The semiconductor device of the present embodiment includes a first electrode, a first semiconductor layer of a first conductivity type connected to the first electrode, containing silicon and carbon, a second semiconductor layer of a second conductivity type disposed on a portion of the first semiconductor layer, containing silicon and carbon, a third semiconductor layer of the first conductivity type disposed on a portion of the second semiconductor layer, facing the first semiconductor layer with the second semiconductor layer interposed, displaced in a manner that a side facing the first semiconductor layer is closer to the first semiconductor layer as it is oriented upward, containing silicon and carbon, a second electrode connected to the third semiconductor layer, and a third electrode disposed at least in a region directly above a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, facing the portion with a first insulating film interposed.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-146368 (filed on September 14, 2022). This application incorporates the entire contents of the basic application by reference. Technical Field

[0002] The implementation methods relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0003] To improve the balance between on-resistance and withstand voltage in semiconductor devices, semiconductor devices using silicon carbide as the semiconductor material have been developed. In such semiconductor devices, to further reduce on-resistance, it is preferable to shorten the channel length. However, shortening the channel length reduces the threshold voltage, sometimes leading to instability in operation. Summary of the Invention

[0004] The semiconductor device of the embodiment includes: a first electrode; a first semiconductor layer of a first conductivity type connected to the first electrode, comprising silicon and carbon; a second semiconductor layer of a second conductivity type disposed on a portion of the first semiconductor layer, comprising silicon and carbon; a third semiconductor layer of a first conductivity type disposed on a portion of the second semiconductor layer, facing the first semiconductor layer across the second semiconductor layer, and displaced such that the side facing the first semiconductor layer is closer to the first semiconductor layer as it faces upwards, comprising silicon and carbon; a second electrode connected to the third semiconductor layer; and a third electrode disposed at least in the region directly above the portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, facing the portion across a first insulating film.

[0005] A method for manufacturing a semiconductor device according to an embodiment includes: a step of forming a mask member on a first semiconductor layer comprising silicon and carbon of a first conductivity type; a step of forming a second semiconductor layer of a second conductivity type on a portion of the upper part of the first semiconductor layer by implanting a first impurity into the first semiconductor layer using the mask member as a mask; a step of forming a spacer film covering the mask member on the first semiconductor layer and the second semiconductor layer; a step of forming a third semiconductor layer of a first conductivity type on a portion of the upper part of the second semiconductor layer by implanting a second impurity into the second semiconductor layer using the mask member as a mask and through the spacer film; a step of removing the spacer film and the mask member; a step of forming a first insulating film at least on a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer; and a step of forming a first electrode connected to the first semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode disposed on the first insulating film.

[0006] According to the embodiments, a semiconductor device and a method for manufacturing the same can be provided that can suppress the decrease of threshold voltage. Attached Figure Description

[0007] Figure 1 This is a top view showing the semiconductor device according to the first embodiment.

[0008] Figure 2 yes Figure 1 The cross-sectional view of line A-A' shown.

[0009] Figure 3 It means Figure 2 A magnified sectional view of region B.

[0010] Figure 4 (a)~ Figure 4 (c) is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figure 5 (a)~ Figure 5 (c) is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0012] Figure 6 (a) and Figure 6 (b) is a process cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment.

[0013] Figure 7 (a) and Figure 7 (b) is a process cross-sectional view showing the manufacturing method of the semiconductor device of the comparative example.

[0014] Figure 8 This is a partially enlarged cross-sectional view of a comparative example semiconductor device.

[0015] Figure 9 (a) is a diagram showing the test method for the first test case. Figure 9 (b) Figure 9 (d) is a graph representing the results of the first test case.

[0016] Figure 10 (a) and Figure 10 (b) is a graph showing the results of the second test case. Detailed Implementation

[0017] <First Implementation>

[0018] Figure 1 This is a top view showing the semiconductor device of this embodiment.

[0019] Figure 2 yes Figure 1The cross-sectional view of line A-A' shown.

[0020] Figure 3 It means Figure 2 A magnified sectional view of region B.

[0021] Furthermore, the figures are schematic and have been appropriately simplified and emphasized. Also, the shapes and dimensions of the constituent elements in the figures may not be strictly matched. The same applies to the other figures discussed later.

[0022] like Figure 1 as well as Figure 2 As shown, in the semiconductor device 1 of this embodiment, a drain electrode 11, a semiconductor portion 20, a source electrode 12, a gate electrode 13, a gate insulating film 31, and an inter-electrode insulating film 32 are provided. The semiconductor portion 20 is disposed between the drain electrode 11 and the source electrode 12. The drain electrode 11 is disposed on the entire or substantially the entire lower surface of the semiconductor portion 20. The source electrode 12 is disposed on the substantially the entire area of ​​the upper surface of the semiconductor portion 20, excluding the gate pad (not shown). Furthermore, in Figure 1 In the diagram, the source electrode 12, the gate insulating film 31, and the inter-electrode insulating film 32 are omitted from the illustration; the gate electrode 13 is represented by a double-dotted line. The semiconductor device 1 is a vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0023] For ease of explanation, an XYZ orthogonal coordinate system is used in this specification. The arrangement direction of the drain electrode 11 and the source electrode 12 is defined as the "Z direction," the direction of the channel length of the MOSFET formed in the semiconductor device 1 is defined as the "X direction," and the direction of the channel width is defined as the "Y direction." In addition, the direction in the Z direction from the drain electrode 11 to the source electrode 12 is also called "up," and its opposite direction is also called "down," but these interpretations are for convenience and are independent of the direction of gravity.

[0024] The semiconductor section 20 is composed of single-crystal silicon carbide (SiC) and contains impurities in certain areas, thereby defining the conductivity type of each section. Within the semiconductor section 20, a section with conductivity type n is provided. + Type 21, n drain layer - Type 22 drift layer, p-type basal layer 23, p + Type 24 contact layer, and n + The source layer of type 25. Additionally, "n" + "Type" indicates that the carrier concentration is higher than "n". - "p-type" indicates a higher carrier concentration than "p-type". -"Type" is high. "Carrier concentration" refers to the effective impurity concentration that functions as a donor or acceptor.

[0025] Drain layer 21 is connected to and connected to drain electrode 11. In this specification, "connection" refers to electrical connection. Drift layer 22 is disposed on drain layer 21 and is connected to drain layer 21. Base layer 23 is disposed on a portion of drift layer 22 and is connected to drift layer 22. The remaining portion 22a of drift layer 22, i.e., the upper surface of the portion 22a on which base layer 23 is not disposed, constitutes a part of the upper surface 20a of semiconductor portion 20.

[0026] A contact layer 24 is disposed on a portion of the substrate layer 23 and is in contact with the substrate layer 23. A source layer 25 is disposed on another portion of the substrate layer 23 and is in contact with the substrate layer 23. The contact layer 24 and the source layer 25 may also be in contact with each other. The contact layer 24 and the source layer 25 are separated from the drift layer 22 via the substrate layer 23. On the upper surface 20a of the semiconductor portion 20, the source layer 25 is opposed to the drift layer 22 across the substrate layer 23. The remaining portion 23a in the substrate layer 23, that is, the upper surface of the portion on which the contact layer 24 or the source layer 25 is not disposed, constitutes a part of the upper surface 20a of the semiconductor portion 20.

[0027] In semiconductor device 1, for example, a plurality of substrate layers 23 are disposed on drift layer 22 and arranged separately from each other along the X direction. Each substrate layer 23 extends in the Y direction. Furthermore, a contact layer 24 and a source layer 25 are disposed on each substrate layer 23. For example, each substrate layer 23 has one contact layer 24 and two source layers 25 sandwiching the contact layer 24. The contact layer 24 and the source layers 25 extend in the Y direction. However, the positional relationship between the contact layer 24 and the source layers 25 in the XY plane is not limited to this example.

[0028] A gate insulating film 31 is disposed on the upper surface 20a of the semiconductor portion 20. The gate insulating film 31 is, for example, made of silicon oxide (SiO). The gate insulating film 31 is in contact with the upper surface of the portion 22a of the drift layer 22, the upper surface of the portion 23a of the substrate layer 23, and the upper surface of the portion 25a on the side of the portion 23a of the substrate layer 23 in the source layer 25.

[0029] Gate electrode 13 is disposed on and connected to gate insulating film 31. Gate electrode 13 is disposed at least above the portion 23a between drift layer 22 and source layer 25 in substrate layer 23, and is opposed to portion 23a across gate insulating film 31. For example, gate electrode 13 is disposed over the portion 22a of drift layer 22 located between two adjacent substrate layers 23, the portion 23a between the portion 22a of these two substrate layers 23 and source layer 25, and the portion 25a on the side of the portion 23a of substrate layer 23 in source layer 25, and is opposed to these portions across gate insulating film 31. Gate electrode 13 extends along the Y direction and is connected to gate pad (not shown).

[0030] An inter-electrode insulating film 32 is disposed on a portion of the semiconductor portion 20 and entirely on the gate insulating film 31, covering the gate electrode 13. The inter-electrode insulating film 32 is made of, for example, silicon oxide. The source electrode 12 is disposed on the semiconductor portion 20 and covers the inter-electrode insulating film 32. Therefore, the source electrode 12 covers the gate electrode 13 through the inter-electrode insulating film 32. Thus, the source electrode 12 is insulated from the gate electrode 13 through the inter-electrode insulating film 32. The source electrode 12 is connected to the contact layer 24 and the source layer 25 on the upper surface 20a of the semiconductor portion 20.

[0031] like Figure 3 As shown, the side 25b of the source layer 25 in the X direction is opposite to the portion 22a of the drift layer 22, separated by a portion 23a of the substrate layer 23. The shape of the side 25b in the XZ cross-section is along the shape of a virtual arc 99. The center 99c of the arc 99 is located above the source layer 25, for example, within the gate electrode 13. Therefore, the side 25b is displaced such that the higher it is, the closer it is to the portion 22a of the drift layer 22. That is, in a certain XZ cross-section, the upper edge 25c of the side 25b is closest to the portion 22a on the side 25b, and the lower edge 25d of the side 25b is farthest from the portion 22a on the side 25b.

[0032] Furthermore, it is preferable that the distance D1 between the upper edge 25c and the lower edge 25d in the X direction, viewed from above (Z direction), is greater than the distance D2 between the upper edge 25c and the lower edge 25d in the Z direction, viewed from the side (Y direction). That is, D1 > D2 is preferred. The distance D2 is the thickness of the source layer 25. Figure 3 The distance D3 shown is the channel length of the MOSFET.

[0033] Next, the manufacturing method of the semiconductor device according to this embodiment will be described.

[0034] Figure 4 (a)~ Figure 5 (c) is a process cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment.

[0035] First, such as Figure 4 As shown in (a), a semiconductor substrate 50 is prepared. The semiconductor substrate 50 is, for example, prepared by n... + n-type silicon carbide wafers are epitaxially grown on them. - A silicon carbide layer of a certain type is formed. In the completed semiconductor device 1, the semiconductor substrate 50 becomes the semiconductor portion 20, the silicon carbide wafer becomes the drain layer 21, and the epitaxially grown silicon carbide layer becomes the drift layer 22. Figure 4 In the stage shown in (a), the base layer 23, contact layer 24 and source layer 25 were not formed.

[0036] Next, as Figure 4 As shown in (b), a mask component 51 is formed on the semiconductor substrate 50. The mask component 51 is formed, for example, from silicon oxide. Next, using the mask component 51 as a mask, impurities 52 that become acceptors are implanted into the upper portion of the semiconductor substrate 50, that is, the portion corresponding to the drift layer 22. As a result, a p-type base layer 23 is formed on a portion of the upper part of the drift layer 22.

[0037] Next, as Figure 4 As shown in (c), a spacer film 53 covering the mask component 51 is formed on the semiconductor substrate 50. The spacer film 53 is formed, for example, from silicon oxide, silicon nitride (SiN), or silicon (Si).

[0038] Next, as Figure 5 As shown in (a), using the mask member 51 as a mask, impurities 54, which become donors, are ion implanted into the substrate layer 23 through the spacer membrane 53. At this time, the acceleration voltage for ion implantation of impurities 54 is set to a voltage such that the impurities 54 implanted from above are scattered within the spacer membrane 53 and reach the upper part of the substrate layer 23.

[0039] Therefore, as Figure 5 As shown in (b), n is formed in a portion of the upper part of the base layer 23. + The source layer 25 is of the type described above. The distribution of ion-implanted impurities 54 extends spherically around a center 99c located within the spacer film 53. Therefore, the shape of the portion of the semiconductor substrate 50 in which the impurities 54 are distributed, i.e., the shape of the source layer 25, becomes a shape in which multiple spheres are continuously distributed along the XY plane. Thus, the shape of the source layer 25 is a generally flat plate extending along the XY plane and having a certain thickness in the Z direction. The upper surface of the source layer 25 is in contact with the spacer film 53, and the side surface 25b of the source layer 25 becomes a shape along a portion of a cylinder. The shape of the side surface 25b in the cross section parallel to the Z direction becomes a shape along a virtual arc 99 centered on the center 99c.

[0040] Next, as Figure 5As shown in (c), the spacer film 53 and the mask component 51 are removed. As a result, the upper surface of the semiconductor substrate 50 is exposed.

[0041] Next, as Figure 2 As shown, a mask component (not shown) is formed and used as a mask for ion implantation of impurities that become acceptors. This results in the formation of p-type impurities in at least a portion of the upper portion of the substrate 23 where the source layer 25 is not formed. + A contact layer 24 of the type is formed. Next, the mask components are removed. Next, an activation heat treatment is performed to activate the impurities injected into the semiconductor substrate 50. Next, a thermal oxidation treatment is performed on the semiconductor substrate 50. As a result, a gate insulating film 31 is formed on the entire upper surface of the semiconductor substrate 50. The gate insulating film 31 is formed at least on the portion 23a between the drift layer 22 and the source layer 25 in the base layer 23.

[0042] Next, a gate electrode 13 is formed on the gate insulating film 31. Then, the gate insulating film 31 is etched using the gate electrode 13 as a mask, leaving the gate insulating film 31 in the region directly below the gate electrode 13 and removing it from the region outside. Next, an inter-electrode insulating film 32 is formed on the semiconductor substrate 50 and on the gate electrode 13. Then, the inter-electrode insulating film 32 is selectively removed. Thus, with the gate electrode 13 covered by the inter-electrode insulating film 32, a portion of the source layer 25 and the contact layer 24 are exposed from the inter-electrode insulating film 32.

[0043] Next, a source electrode 12 is formed on the semiconductor substrate 50 and the inter-electrode insulating film 32. The source electrode 12 is insulated from the gate electrode 13 by the inter-electrode insulating film 32 and is in contact with the source layer 25 and the contact layer 24. Additionally, a drain electrode 11 is formed on the lower surface of the semiconductor substrate 50. The drain electrode 11 is in contact with the lower surface of the semiconductor substrate 50. Next, the structure including the drain electrode 11, the semiconductor substrate 50, the gate insulating film 31, the gate electrode 13, the inter-electrode insulating film 32, and the source electrode 12 is cut and monolithically assembled. Thus, multiple semiconductor devices 1 are manufactured.

[0044] Next, the effects of this embodiment will be explained.

[0045] like Figure 3 As shown, in the semiconductor device 1 of this embodiment, the side 25b of the source layer 25 is displaced such that the portion 22a of the drift layer 22 is closer to the portion 22a as it moves upward. Therefore, the portion 23a in the substrate layer 23 that forms the inversion layer and the portion 22b located directly below the portion 23a in the drift layer 22 (see reference) Figure 2There is no source layer 25 between the drain electrode 11 and the drain electrode 23a. Therefore, the potential of the drain electrode 11 is easily transferred to the drain electrode 23a, making it difficult to form an inversion layer. As a result, the threshold voltage of the MOSFET becomes higher. Thus, the channel length, i.e., the distance D3, can be shortened to reduce the on-resistance and ensure the specified threshold voltage, thereby stabilizing the operation of the semiconductor device 1. For example, when the MOSFET is in the off state, it is possible to suppress the situation where the inversion layer is formed unintentionally due to noise, etc., and the MOSFET is turned on.

[0046] Furthermore, by making the distance D1 in the X direction between the upper edge 25c and the lower edge 25d of the side surface 25b of the source layer 25 larger than the distance D2 in the Z direction (i.e., the thickness of the source layer 25), the aforementioned effect can be obtained more reliably. This also ensures the threshold voltage of the semiconductor device 1, making its operation more stable.

[0047] <Second Implementation>

[0048] This embodiment is another method of manufacturing the semiconductor device according to the first embodiment.

[0049] Figure 6 (a) and Figure 6 (b) is a process cross-sectional view showing the manufacturing method of the semiconductor device according to this embodiment.

[0050] First, implementation Figure 4 (a)~ Figure 4 The process shown in (c).

[0051] Next, as Figure 6 As shown in (a), anisotropic etching such as RIE (Reactive Ion Etching) is performed on the spacer film 53. At this time, the spacer film 53 is not completely removed from the upper surface of the semiconductor substrate 50. As a result, the spacer film 53 becomes thinner on both the upper surface of the semiconductor substrate 50 and the upper surface of the mask member 51. On the other hand, the spacer film 53 is not very thin on the side surfaces of the mask member 51.

[0052] Therefore, the thickness t1 in the Z direction on the upper surface of the semiconductor substrate 50 in the spacer film 53 and the thickness t2 in the X direction on the side surface of the mask member 51 in the spacer film 53 can be controlled independently. In this embodiment, the thickness t1 is thinner than the thickness t2. That is, t1 < t2.

[0053] Next, as Figure 6 As shown in (b), using the mask component 51 as a mask, impurities 54, which become donors, are ion implanted into the substrate layer 23 through the spacer film 53. This forms an n-type impurity 54 in a portion of the upper part of the substrate layer 23. +The source layer 25 is of the type. The acceleration voltage for ion implantation of impurity 54 is set to a voltage such that the impurity 54 implanted from above is scattered within the spacer film 53 and reaches the upper part of the substrate layer 23. Next, the implementation is carried out. Figure 5 The process shown in (c) is as follows. Subsequent processes are the same as in the first embodiment.

[0054] Next, the effects of this embodiment will be explained.

[0055] like Figure 6 As shown in (a) and (b), in this embodiment, the thickness t1 in the Z direction of the spacer film 53 is thinner than in the first embodiment. Therefore, in order to form a source layer 25 of a predetermined thickness, the accelerating voltage of the impurity 54 can be reduced. As a result, the propagation of the impurity 54 along the XY plane can be suppressed. Consequently, the shape of the source layer 25 can be controlled with high precision.

[0056] Thus, according to this embodiment, the shape of the source layer 25 can be controlled by adjusting the thickness t1 in the Z direction of the spacer 53. On the other hand, the channel length (distance D3) can be controlled by adjusting the thickness t2 in the X direction of the spacer 53. The thickness t2 of the spacer 53 can be adjusted by... Figure 4 In the process shown in (c), the deposition amount of the spacer film 53 is adjusted by controlling the amount of deposition. Thus, according to this embodiment, the shape of the source layer 25 and the channel length (distance D3) can be controlled independently. The structure, manufacturing method, and effects in this embodiment other than those described above are the same as in the first embodiment.

[0057] <Comparative Example>

[0058] Figure 7 (a) and Figure 7 (b) is a process cross-sectional view showing the manufacturing method of the semiconductor device of this comparative example.

[0059] Figure 8 This is a partially enlarged cross-sectional view of the semiconductor device of this comparative example.

[0060] Figure 8 Indicates and Figure 3 A considerable area.

[0061] First, implementation Figure 4 (a)~ Figure 4 The process shown in (c).

[0062] Next, as Figure 7 As shown in (a), anisotropic etching is performed on the spacer film 53 to remove it from the upper surface of the semiconductor substrate 50. At this time, the spacer film 53 remains on the side surface of the mask member 51. That is, the spacer film 53 is removed. Figure 6The thickness t1 shown in (a) is set to 0, and the thickness t2 is set to a value greater than 0.

[0063] Next, as Figure 7 As shown in (b), using the mask component 51 and the spacer film 53 as a mask, impurities 54, which become donors, are ion implanted into the substrate layer 23. At this time, the impurities 54 are implanted directly into the semiconductor substrate 50 without passing through the spacer film 53. As a result, the impurities 54 expand into a spherical shape centered at the center 99c located within the semiconductor substrate 50. Thus, the source layer 25 is formed.

[0064] like Figure 8 As shown, in the semiconductor device 101 of this comparative example, the center 99c of the virtual arc 99 is located within the source layer 25. Therefore, the portion 23b above the substrate layer 23 and on the side of the source layer 25, and the portion 22b of the drift layer 22 disposed directly below it (see reference) Figure 2 A portion 25e of the source layer 25 is sandwiched between the two portions. As a result, the potential of the drain electrode is difficult to transfer to portion 23b, making it easy to form an inversion layer. Consequently, the threshold voltage of the MOSFET decreases. Therefore, compared to the semiconductor device 1 of the first embodiment, if the channel length (distance D3) is the same, the threshold voltage of semiconductor device 101 is lower. If the threshold voltage is lower, there is a possibility that the operation becomes unstable.

[0065] Furthermore, in semiconductor device 101, to ensure a sufficient threshold voltage, simply extending the channel length (distance D3) is sufficient, but this increases the on-resistance. Alternatively, forming the semiconductor substrate using silicon (Si) instead of silicon carbide (SiC) is also considered, allowing for thermal diffusion of impurities shallowly implanted near the upper surface of the semiconductor substrate, thereby forming a near-… Figure 3 The source layer 25 shown is a source layer with a specific shape. However, in this case, the band gap of silicon is narrower than that of silicon carbide, thus reducing the balance between on-resistance and breakdown voltage.

[0066] <First Experimental Case>

[0067] Figure 9 (a) is a diagram illustrating the experimental method used in this experimental example. Figure 9 (b) Figure 9 (d) is a graph representing the results of this experimental example.

[0068] Figure 9 (b) Figure 9 (d) is a graph that tracks the simulation results.

[0069] like Figure 9As shown in (a), in this experimental example, three samples were envisioned in which a spacer film 53 made of polycrystalline silicon was formed on a semiconductor substrate 50 made of silicon carbide. The thickness of the spacer film 53 varied between the samples. Then, for these samples, a simulation was performed to implant nitrogen ions, which served as an impurity, into the semiconductor substrate 50, and the behavior of nitrogen was simulated. The acceleration voltage for ion implantation was adjusted in each sample in such a way that the depth and concentration of nitrogen in the semiconductor substrate 50 were approximately equal between the samples.

[0070] like Figure 9 As shown in (b), in sample 201, the thickness of the spacer film 53 was set to 200 nm. As a result, nitrogen was mainly scattered within the spacer film 53, and the portion of nitrogen distribution within the semiconductor substrate 50 formed a shape with its center close to the lower part of a sphere located within the spacer film 53, with an extension of approximately 300 nm.

[0071] like Figure 9 As shown in (c), in sample 202, the thickness of the spacer film 53 is set to 50 nm. As a result, nitrogen is scattered within the spacer film 53 and within the semiconductor substrate 50, and the portion of nitrogen distributed within the semiconductor substrate 50 becomes a sphere centered within the semiconductor substrate 50, with an extension of approximately 160 nm.

[0072] like Figure 9 As shown in (d), in sample 203, the thickness of the spacer film 53 is set to 0 nm. That is, no spacer film 53 is provided. As a result, nitrogen is scattered within the semiconductor substrate 50, and the portion of nitrogen distribution within the semiconductor substrate 50 becomes a shape with a center close to a sphere located within the semiconductor substrate 50, with an extension of approximately 100 nm.

[0073] <Second Test Case>

[0074] Figure 10 (a) and Figure 10 (b) is a graph showing the results of this test case.

[0075] In this experimental example, the manufacturing methods of the semiconductor devices of the first embodiment and the comparative example described above were simulated, and their respective threshold voltages were calculated. Figure 10 (a) and Figure 10 In (b), the darker the color, the higher the donor concentration. Figure 10 (a) and Figure 10 (b) is a graph obtained by tracking the simulation results of the impurity concentration distribution. Due to tracking limitations, it is impossible to represent all simulation results. However, based on the original simulation results, the interface between the substrate layer 23 and the source layer 25 can be determined, therefore... Figure 10 (a) and Figure 10 The interface is shown in (b).

[0076] Figure 10 Sample 301 shown in (a) is a test example of the first embodiment. In sample 301, the spacer film 53 was deposited to a thickness of 200 nm without etch-back of the spacer film 53. Therefore, the thickness t1 of the spacer film 53 is 200 nm. Then, an accelerating voltage was selected to form a source layer 25 of a specified thickness and impurity concentration, and impurities 54 were ion implanted. As a result, as shown in (a) Figure 10 As shown in (a), the shape of the side 25b of the source layer 25 in sample 301 is such that the center 99c is along the arc 99 located above the semiconductor portion 20. The threshold voltage Th of sample 301 is 4.6V.

[0077] Figure 10 Sample 302 shown in (b) is a comparative example. In sample 302, the spacer film 53 was deposited to a thickness of 80 nm, and then etched back by 80 nm. That is, no spacer film 53 remained, and the thickness t1 was 0 nm. Then, an accelerating voltage was selected to form a source layer 25 of a specified thickness and impurity concentration, and impurities 54 were implanted with ions. The result is as follows: Figure 10 As shown in (b), the shape of the side 25b of the source layer 25 in sample 302 is such that the center 99c follows the shape of the arc 99 located within the semiconductor portion 20. The threshold voltage Th of sample 302 is 4.0V.

[0078] As described above, the threshold voltage Th (4.6V) of sample 301 in the first embodiment is higher than the threshold voltage Th (4.0V) of sample 302 in the comparative example.

[0079] Based on the embodiments described above, a semiconductor device and a method for manufacturing the same can be realized that can suppress the decrease in threshold voltage even when the channel length is shortened.

[0080] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention and its equivalents as described in the claims.

[0081] The present invention includes the following methods.

[0082] (Postscript 1)

[0083] A semiconductor device comprising:

[0084] First electrode;

[0085] A first semiconductor layer of a first conductivity type is connected to the first electrode and comprises silicon and carbon.

[0086] A second semiconductor layer of a second conductivity type is disposed on a portion of the first semiconductor layer and comprises silicon and carbon.

[0087] A third semiconductor layer of a first conductivity type, a portion disposed on the second semiconductor layer, facing the first semiconductor layer across the second semiconductor layer, and displaced in such a way that the side facing the first semiconductor layer is closer to the first semiconductor layer as it faces upwards, includes silicon and carbon;

[0088] The second electrode is connected to the third semiconductor layer; and

[0089] The third electrode is disposed at least in the region directly above the portion between the first semiconductor layer and the third semiconductor layer in the second semiconductor layer, and is opposite to the portion separated by the first insulating film.

[0090] (Postscript 2)

[0091] According to the semiconductor device described in Appendix 1, the cross-sectional shape of the side surface of the third semiconductor layer is a virtual arc centered above the third semiconductor layer.

[0092] (Note 3)

[0093] According to the semiconductor device described in Appendix 1 or 2, the distance between the upper and lower edges of the side surface viewed from above is greater than the thickness of the third semiconductor layer viewed from the side.

[0094] (Postscript 4)

[0095] The semiconductor device according to any one of Appendices 1 to 3, wherein the third electrode is disposed on the portion of the first semiconductor layer above which the second semiconductor layer is not disposed, and on the portion of the third semiconductor layer on the side of the second semiconductor layer, separated by the first insulating film.

[0096] (Note 5)

[0097] In the semiconductor device according to any one of Appendices 1 to 4, the second electrode is connected to the third semiconductor layer.

[0098] The second electrode covers the third electrode through a second insulating film.

[0099] (Note 6)

[0100] The semiconductor device according to any one of Appendices 1 to 5, wherein the first semiconductor layer is disposed on the first electrode and is connected to the first electrode.

[0101] (Note 7)

[0102] A method for manufacturing a semiconductor device includes the following steps:

[0103] The process of forming a mask component on a first semiconductor layer of a first conductivity type comprising silicon and carbon;

[0104] The process of using the mask component as a mask to implant a first impurity into the first semiconductor layer, thereby forming a second semiconductor layer of a second conductivity type on a portion of the upper part of the first semiconductor layer;

[0105] The process of forming a spacer film covering the mask component on the first semiconductor layer and the second semiconductor layer;

[0106] The process of using the mask component as a mask to implant a second impurity into the second semiconductor layer through the spacer film, thereby forming a third semiconductor layer of the first conductivity type on a portion of the upper part of the second semiconductor layer;

[0107] The process of removing the spacer membrane and the mask component;

[0108] The process of forming a first insulating film at least on the portion between the first semiconductor layer and the third semiconductor layer in the second semiconductor layer; and

[0109] The process of forming a first electrode connected to the first semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode disposed on the first insulating film.

[0110] (Postscript 8)

[0111] According to the method for manufacturing a semiconductor device as described in Appendix 7, wherein,

[0112] After the process of forming the spacer film and before the process of forming the third semiconductor layer,

[0113] It also includes a process of thinning the spacer membrane.

[0114] During the process of forming the third semiconductor layer, the spacer film remains on the second semiconductor layer.

[0115] (Note 9)

[0116] According to the method of manufacturing a semiconductor device as described in Appendix 7 or 8, in the process of forming the third semiconductor layer, the second impurity is scattered within the spacer film and reaches the upper part of the second semiconductor layer.

Claims

1. A semiconductor device comprising: First electrode; A first semiconductor layer of a first conductivity type is connected to the first electrode and comprises silicon and carbon. A second semiconductor layer of a second conductivity type is disposed on a portion of the first semiconductor layer and comprises silicon and carbon. A third semiconductor layer of a first conductivity type, a portion disposed on the second semiconductor layer, facing the first semiconductor layer across the second semiconductor layer, comprising silicon and carbon; The second electrode is connected to the third semiconductor layer; as well as The third electrode is disposed at least in the region directly above the portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, and is opposite to the portion separated by the first insulating film. The side surface of the third semiconductor layer is opposite to the first semiconductor layer and has a shape that gets closer to the first semiconductor layer in the direction from the first electrode toward the second electrode. The cross-sectional shape of the side of the third semiconductor layer is a virtual arc centered above the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The distance between the upper and lower edges of the side surface in the cross-sectional view viewed from above is greater than the thickness of the third semiconductor layer as viewed from the side.

3. The semiconductor device according to claim 1, wherein, The third electrode is disposed on the portion of the first semiconductor layer above which the second semiconductor layer is not disposed, and on the portion of the third semiconductor layer on the side of the second semiconductor layer, separated by the first insulating film.

4. The semiconductor device according to claim 1, wherein, The second electrode is connected to the third semiconductor layer. The second electrode covers the third electrode via a second insulating film.

5. The semiconductor device according to claim 1, wherein, The first semiconductor layer is disposed on the first electrode and is connected to the first electrode.

6. A method for manufacturing a semiconductor device, comprising the following steps: The process of forming a mask component on a first semiconductor layer of a first conductivity type comprising silicon and carbon; The process of using the mask component as a mask to implant a first impurity into the first semiconductor layer, thereby forming a second semiconductor layer of a second conductivity type on a portion of the upper part of the first semiconductor layer; The process of forming a spacer film covering the mask component on the first semiconductor layer and the second semiconductor layer; The process of using the mask component as a mask to implant a second impurity into the second semiconductor layer through the spacer film, thereby forming a third semiconductor layer of a first conductivity type on a portion of the upper part of the second semiconductor layer, wherein the third semiconductor layer has a side facing the first semiconductor layer, and the cross-sectional shape of the side facing the third semiconductor layer is a virtual arc shape with its center located above the third semiconductor layer. The process of removing the spacer membrane and the mask component; The process of forming a first insulating film at least in the portion between the first semiconductor layer and the third semiconductor layer in the second semiconductor layer; as well as The process of forming a first electrode connected to the first semiconductor layer, a second electrode connected to the third semiconductor layer, and a third electrode disposed on the first insulating film.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, After the process of forming the spacer film and before the process of forming the third semiconductor layer, It also includes a process of thinning the spacer membrane. During the process of forming the third semiconductor layer, the spacer film remains on the second semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 6, wherein, During the process of forming the third semiconductor layer, the second impurity is scattered within the spacer film and reaches the upper part of the second semiconductor layer.

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