A zero-crossing comparator applied to a buck circuit

Abstract

The application discloses a zero-crossing comparator applied to a BUCK circuit and belonging to the field of integrated circuits, which comprises a comparator input circuit, a two-stage comparator module and a capacitor sampling transmission circuit. The comparator input circuit samples a PGND signal and an LX low-level signal to the input end of the two-stage comparator module for comparison. The two-stage comparator module comprises a first-stage comparator and a second-stage comparator, and outputs a high-low level signal through an OUT end after comparing the PGND signal and the LX low-level signal. The capacitor sampling transmission circuit is connected by two capacitors between the output of the first-stage comparator and the input of the second-stage comparator, and the direct current bias voltage of the input end of the second-stage comparator is controlled by a switch.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a zero-crossing comparator applied to a BUCK circuit. Background Technology

[0002] When the DC / DC converter is under light load, the system will enter DCM mode. At this time, the inductor current drops to zero. If the synchronous transistor is not turned off, the energy stored in the output filter capacitor will discharge to the inductor, resulting in a reverse current flow to ground, which reduces the conversion efficiency of the system. Summary of the Invention

[0003] The purpose of this invention is to provide a zero-crossing comparator for use in BUCK circuits to solve the problems in the prior art.

[0004] To address the aforementioned technical problems, this invention provides a zero-crossing comparator for use in BUCK circuits.

[0005] It includes a comparator input circuit, a two-stage comparator module, and a capacitor sampling and transmission circuit;

[0006] The comparator input circuit samples the PGND signal and the LX low-level signal to the input of the two-stage comparator module for comparison.

[0007] The two-stage comparator module includes a first-stage comparator and a second-stage comparator, which compare the PGND signal and the LX low-level signal and output high and low level signals through the OUT terminal;

[0008] In the capacitor sampling and transmission circuit, the output of the first-stage comparator and the input of the second-stage comparator are connected by two capacitors, and the DC bias voltage at the input of the second-stage comparator is controlled by a switch.

[0009] In one embodiment, the comparator input circuit includes NMOS transistors MN1-MN2, PMOS transistors MP1-MP7, resistor R1, and switches S1-S2; wherein PMOS transistor MP4 is a bias current transistor, and PMOS transistors MP6 and MP7 are both current bias mirror transistors.

[0010] One end of switch S1 is connected to the PGND signal, and the other end is connected to the gate of PMOS transistor MP2 and the drain of NMOS transistor MN2. The gate of NMOS transistor MN2 is connected to the CRTL control signal. When NMOS transistor MN2 is turned on, switch S1 is turned off, and when NMOS transistor MN2 is turned off, switch S1 is turned on.

[0011] One end of resistor R1 is connected to the LX signal, and the other end is connected to the source of PMOS transistor MP3 and one end of switch S2. The gate and drain of PMOS transistor MP3 are grounded. The other end of switch S2 is connected to the gate of PMOS transistor MP1 and the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 is connected to the CRTL control signal. When NMOS transistor MN1 is turned on, switch S2 is turned off, and when NMOS transistor MN1 is turned off, switch S2 is turned on. The source of PMOS transistor MP2 is connected to the drain of current bias mirror transistor MP6.

[0012] The source terminal of PMOS transistor MP1 is connected to the drain terminal of current bias mirror transistor MP7. The gate terminal of current bias mirror transistor MP6 is simultaneously connected to the gate terminal of current bias mirror transistor MP7, the gate terminal of bias current transistor MP4, the drain terminal of bias current transistor MP4, and the 1:1 mirrored IBIAS current. The gate terminal of PMOS transistor MP5 is connected to the gate terminal of bias current transistor MP4.

[0013] In one embodiment, the two-stage comparator module includes comparators COMP1 and COMP2; the positive input of comparator COMP1 is connected to the source of PMOS transistor MP1 to sample the low-level signal LX, the negative input of comparator COMP1 is connected to the source of PMOS transistor MP2 to sample the PGND signal, the positive output of PMOS transistor COMP1 is connected to the positive input of comparator COMP2 through capacitor C1, and the negative output of comparator COMP1 is connected to the negative input of comparator COMP2 through capacitor C2.

[0014] In one embodiment, the capacitor sampling transmission circuit includes NMOS transistors MN3, MN4, and MN5, and capacitors C1 and C2. The drain and gate terminals of NMOS transistor MN3 are connected to the drain terminal of NMOS transistor MN5, and the drain and gate terminals of NMOS transistor MN3 are connected to the drain terminal of NMOS transistor MN4. The source terminal of NMOS transistor MN5 is connected to the positive input terminal of comparator COMP2, and the source terminal of NMOS transistor MN4 is connected to the negative input terminal of comparator COMP2. The source terminals of NMOS transistors MN5 and MN4 are connected to the CTRL signal. When the LX signal is high, the CTRL signal is high, controlling NMOS transistors MN4 and MN5 to conduct, setting the input terminal of comparator COMP2 to the same bias voltage point, and the output terminal is low at this time. When the LX signal is low, the CTRL signal is low, and the low-level LX signal is sampled and compared with the PGND signal, and the comparison result is output.

[0015] This invention provides a zero-crossing comparator for use in a BUCK circuit. When reverse discharge of the inductor is detected, the LX terminal is at a low level (positive voltage), switches S1 and S2 are turned on, and NMOS transistors MN1, MN2, MN4, and MN5 are turned off. The voltage at the LX terminal and the PGND voltage are compared at the input terminal via the comparator input circuit. After comparison by a two-stage comparator module, a high level is output. The subsequent control circuit turns off the synchronizing transistor, preventing the inductor current from flowing back into the synchronizing transistor. When the LX terminal is at a high level, switches S1 and S2 are turned off, and NMOS transistors MN1, MN2, MN4, and MN5 are turned on, at which point the output terminal is set to zero. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a zero-crossing comparator applied to a BUCK circuit, provided by the present invention. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a zero-crossing comparator for use in a BUCK circuit according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0018] This invention provides a zero-crossing comparator for use in BUCK circuits, the structure of which is as follows: Figure 1 As shown, the system includes a comparator input circuit, a two-stage comparator module, and a capacitor sampling and transmission circuit. The comparator input circuit includes NMOS transistors MN1-MN2, PMOS transistors MP1-MP7, resistor R1, and switches S1-S2; wherein PMOS transistor MP4 is a bias current transistor, and PMOS transistors MP6 and MP7 are both current-biased mirror transistors; the two-stage comparator module includes comparators COMP1-COMP2; and the capacitor sampling and transmission circuit includes NMOS transistors MN3, MN4, and MN5, and capacitors C1 and C2.

[0019] The PGND signal is connected to one end of switch S1. The other end of switch S1 is connected to the gate of PMOS transistor MP2 and the drain of NMOS transistor MN2. The gate of NMOS transistor MN2 is connected to the CRTL control signal. When NMOS transistor MN2 is on, switch S1 is off; when NMOS transistor MN2 is off, switch S1 is on. The LX signal is connected to one end of resistor R1. The other end of resistor R1 is connected to the source of PMOS transistor MP3 and one end of switch S2. The gate and drain of PMOS transistor MP3 are grounded. The other end of switch S2 is connected to the gate of PMOS transistor MP1 and the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 is connected to the CRTL control signal. When NMOS transistor MN1 is on, switch S2 is off; when NMOS transistor MN1 is off, switch S2 is on. The source of PMOS transistor MP2 is connected to the drain of current-biased mirror transistor MP6.

[0020] The source terminal of PMOS transistor MP1 is connected to the drain terminal of current bias mirror transistor MP7. The gate terminal of current bias mirror transistor MP6 is simultaneously connected to the gate terminal of current bias mirror transistor MP7, the gate terminal of bias current transistor MP4, the drain terminal of bias current transistor MP4, and the 1:1 mirrored IBIAS current. The gate terminal of PMOS transistor MP5 is connected to the gate terminal of bias current transistor MP4.

[0021] The positive input of comparator COMP1 is connected to the source of PMOS transistor MP1 to sample the low-level signal LX. The negative input of comparator COMP1 is connected to the source of PMOS transistor MP2 to sample the PGND signal. The positive output of PMOS transistor COMP1 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the positive input of comparator COMP2. The negative output of comparator COMP1 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the negative input of comparator COMP2.

[0022] The drain and gate of NMOS transistor MN3 are both connected to the drain of NMOS transistor MN5, and the drain and gate of NMOS transistor MN3 are both connected to the drain of NMOS transistor MN4. The source of NMOS transistor MN5 is connected to the positive input of comparator COMP2, and the source of NMOS transistor MN4 is connected to the negative input of comparator COMP2. The sources of NMOS transistors MN5 and MN4 are connected to the CTRL signal. When the LX signal is high, the CTRL signal is high, controlling NMOS transistors MN4 and MN5 to conduct, setting the input of comparator COMP2 to the same bias voltage point, and the output is low at this time. When the LX signal is low, the CTRL signal is low, and the low-level LX signal is sampled and compared with the PGND signal, and the comparison result is output.

[0023] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A zero-crossing comparator applied to a BUCK circuit, characterized in that, It includes a comparator input circuit, a two-stage comparator module, and a capacitor sampling and transmission circuit; The comparator input circuit samples the PGND signal and the LX low-level signal to the input of the two-stage comparator module for comparison. The two-stage comparator module includes a first-stage comparator and a second-stage comparator, which compare the PGND signal and the LX low-level signal and output high and low level signals through the OUT terminal; In the capacitor sampling and transmission circuit, the output of the first-stage comparator and the input of the second-stage comparator are connected by two capacitors respectively, and the DC bias voltage at the input of the second-stage comparator is controlled by a switch. The comparator input circuit includes NMOS transistors MN1~MN2, PMOS transistors MP1~MP7, resistor R1, and switches S1~S2; wherein PMOS transistor MP4 is a bias current transistor, and PMOS transistors MP6 and MP7 are both current bias mirror transistors. One end of switch S1 is connected to the PGND signal, and the other end is connected to the gate of PMOS transistor MP2 and the drain of NMOS transistor MN2. The gate of NMOS transistor MN2 is connected to the CRTL control signal. When NMOS transistor MN2 is turned on, switch S1 is turned off, and when NMOS transistor MN2 is turned off, switch S1 is turned on. One end of resistor R1 is connected to the LX signal, and the other end is connected to the source of PMOS transistor MP3 and one end of switch S2. The gate and drain of PMOS transistor MP3 are grounded. The other end of switch S2 is connected to the gate of PMOS transistor MP1 and the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 is connected to the CRTL control signal. When NMOS transistor MN1 is turned on, switch S2 is turned off, and when NMOS transistor MN1 is turned off, switch S2 is turned on. The source of PMOS transistor MP2 is connected to the drain of current bias mirror transistor MP6. The source terminal of PMOS transistor MP1 is connected to the drain terminal of current bias mirror transistor MP7. The gate terminal of current bias mirror transistor MP6 is simultaneously connected to the gate terminal of current bias mirror transistor MP7, the gate terminal of bias current transistor MP4, the drain terminal of bias current transistor MP4, and the 1:1 mirrored IBIAS current. The gate terminal of PMOS transistor MP5 is connected to the gate terminal of bias current transistor MP4.

2. The zero-crossing comparator applied to a BUCK circuit as described in claim 1, characterized in that, The two-stage comparator module includes comparators COMP1 and COMP2. The positive input of comparator COMP1 is connected to the source of PMOS transistor MP1 to sample the low-level signal LX. The negative input of comparator COMP1 is connected to the source of PMOS transistor MP2 to sample the PGND signal. The output of the positive terminal of PMOS transistor COMP1 is connected to the positive input of comparator COMP2 through capacitor C1. The output of the negative terminal of comparator COMP1 is connected to the negative input of comparator COMP2 through capacitor C2.

3. The zero-crossing comparator applied to the BUCK circuit as described in claim 2, characterized in that, The capacitor sampling and transmission circuit includes NMOS transistors MN3, MN4, and MN5, and capacitors C1 and C2. The drain and gate of NMOS transistor MN3 are connected to the drain of NMOS transistor MN5, and the drain and gate of NMOS transistor MN3 are connected to the drain of NMOS transistor MN4. The source of NMOS transistor MN5 is connected to the positive input of comparator COMP2, and the source of NMOS transistor MN4 is connected to the negative input of comparator COMP2. The sources of NMOS transistors MN5 and MN4 are connected to the CTRL signal. When the LX signal is high, the CTRL signal is high, controlling NMOS transistors MN4 and MN5 to conduct, setting the input of comparator COMP2 to the same bias voltage point, and the output is low at this time. When the LX signal is low, the CTRL signal is low, and the low-level LX signal is sampled and compared with the PGND signal, and the comparison result is output.

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