Amplification circuit with reset mechanism

Abstract

An amplifier circuit with a reset mechanism. A pair of upper branches are electrically coupled between a first supply voltage and a pair of differential output terminals, and are symmetrically connected, each containing at least one P-type transistor. A pair of lower branches are electrically coupled between the pair of differential output terminals and a second supply voltage, and are symmetrically connected, each containing at least one N-type transistor. The P-type transistors in each pair of upper branches and the N-type transistors in each pair of lower branches are divided into multiple transistor groups, which sequentially and alternately perform differential signal reception in an interleaved input mode. When no differential signal reception is being performed, a reset signal reception process is performed, turning the circuit to AC ground, thereby causing the pair of differential output terminals to generate differential outputs.

Description

Technical Field

[0001] This invention relates to signal amplification technology, and more particularly to an amplifier circuit with a reset mechanism. Background Technology

[0002] With the emergence of portable products and mobile communication technologies such as 5G, as well as applications of the Internet of Things (IoT), low power consumption has become a crucial specification requirement in design. In analog circuits, due to amplifiers being the main source of power consumption and rated voltages becoming increasingly lower, complementary input amplifiers are increasingly being designed.

[0003] However, when complementary input amplifiers perform interleaved inputs, the same input terminal often has parasitic capacitance, which causes the current input signal to be affected by the residual charge caused by the input signal at the previous time point, resulting in inter-symbol interference (ISI). Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide an amplifier circuit with a reset mechanism to improve the prior art.

[0005] This invention includes an amplifier circuit with a reset mechanism, comprising: a pair of upper branches and a pair of lower branches. The pair of upper branches are electrically coupled between a first supply voltage and a pair of differential output terminals, and are symmetrically connected, each containing at least one P-type transistor. The pair of lower branches are electrically coupled between the pair of differential output terminals and a second supply voltage, and are symmetrically connected, each containing at least one N-type transistor. The P-type transistors in each pair of upper branches and the N-type transistors in each pair of lower branches are divided into multiple transistor groups, such that the transistor groups sequentially and alternately perform differential signal reception in an interleaved input mode. When not performing differential signal reception, the transistor groups perform a reset signal reception process and are connected to AC ground, thereby causing the pair of differential output terminals to generate differential outputs. Each transistor group contains M pairs of transistors, and each M pairs of transistors has symmetrical input / output characteristics relative to the pair of differential output terminals, where M is a positive integer greater than or equal to 1.

[0006] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description

[0007] Figure 1 This invention shows a circuit diagram of an amplifier circuit with a reset mechanism in one embodiment of the invention.

[0008] Figure 2This invention displays waveform diagrams of the input control signal and the reset control signal in one embodiment of the invention.

[0009] Figure 3A This diagram shows an equivalent circuit diagram of an amplifier circuit in one embodiment of the present invention, in which the amplifier circuit performs a differential signal reception process in the first transistor group and a reset signal reception process in the second transistor group.

[0010] Figure 3B This diagram shows an equivalent circuit diagram of an amplifier circuit performing a differential signal reception process in the second transistor group and a reset signal reception process in the first transistor group, according to one embodiment of the present invention.

[0011] Figure 4 This shows a circuit diagram of the amplification circuit in another embodiment of the present invention;

[0012] Figure 5A This diagram shows an equivalent circuit diagram of an amplifier circuit in one embodiment of the present invention, in which the amplifier circuit performs a differential signal reception process in the first transistor group and a reset signal reception process in the second transistor group.

[0013] Figure 5B This diagram shows an equivalent circuit diagram of an amplifier circuit performing a differential signal reception process in the second transistor group and a reset signal reception process in the first transistor group, according to one embodiment of the present invention.

[0014] Figure 6 This invention displays a circuit diagram of an amplifier circuit in yet another embodiment; and

[0015] Figure 7 This diagram shows the waveforms of the input control signal and the reset control signal in one embodiment of the present invention. Detailed Implementation

[0016] One objective of this invention is to provide an amplifier circuit with a reset mechanism, which performs an AC reset on the transistor group that has not undergone differential signal reception, thereby preventing the residual charge of parasitic capacitance from affecting the differential output signal generated when the transistor group operates in an interleaved manner.

[0017] Please refer to Figure 1 . Figure 1 This diagram shows a circuit diagram of an amplifier circuit 100 with a reset mechanism according to one embodiment of the present invention. The amplifier circuit 100 includes a pair of upper branches 110A and 110B and a pair of lower branches 120A and 120B.

[0018] The upper branches 110A and 110B are electrically coupled between a first supply voltage V1 and a pair of differential output terminals O+ and O-. In one embodiment, the first supply voltage V1 is, for example, but not limited to, 1 volt.

[0019] The upper branches 110A and 110B are symmetrical and each contains at least one P-type transistor. Figure 1 In this embodiment, each of the upper branches 110A and 110B includes two P-type transistors. Upper branch 110A includes a first P-type transistor MP11 and a second P-type transistor MP12 sequentially electrically coupled between the first supply voltage V1 and the differential output terminal O+. Upper branch 110B includes a first P-type transistor MP21 and a second P-type transistor MP22 sequentially electrically coupled between the first supply voltage V1 and the differential output terminal O-.

[0020] The lower branches 120A and 120B are electrically coupled between the differential output terminals O+ and O- and the second supply voltage V2. In one embodiment, the second supply voltage V2 is, for example, but not limited to, 0 volts.

[0021] The lower branches 120A and 120B are symmetrical and each contains at least one N-type transistor. Figure 1 In this embodiment, each of the lower branches 120A and 120B includes two N-type transistors. Lower branch 120A includes a first N-type transistor MN11 and a second N-type transistor MN12 sequentially electrically coupled between the differential output terminal O+ and the second supply voltage V2. Lower branch 120B includes a first N-type transistor MN21 and a second N-type transistor MN22 sequentially electrically coupled between the differential output terminal O- and the second supply voltage V2.

[0022] The P-type transistors of each pair of upper half-branch 110A and 110B, and the N-type transistors of each pair of lower half-branch 120A and 120B, are divided into multiple transistor groups. In interleaved input mode, the transistor groups sequentially and alternately perform differential signal reception processes, and when no differential signal reception process is performed, they perform a reset signal reception process and are turned on and AC grounded, thereby causing the differential output terminals O+ and O- to generate differential outputs.

[0023] The transistor group includes M pairs of transistors, each of the M pairs of transistors having symmetrical input / output characteristics relative to the differential output terminals O+ and O-, where M is a positive integer greater than or equal to 1. In one embodiment, the input / output characteristics include, for example, but not limited to, output impedance, transconductance, gain, power supply rejection ratio, or combinations thereof between the differential signal input received by each of the M pairs of transistors and the differential signal output at the differential output terminals O+ and O-.

[0024] by Figure 1 In one embodiment, the transistors contained in the upper branches 110A and 110B and the lower branches 120A and 120B will be divided into two transistor groups, namely a first transistor group and a second transistor group. Each first transistor group and the second transistor group contains two pairs of transistors.

[0025] exist Figure 1 In the diagram, the transistors grouped into the first transistor group are indicated by dotted dashed boxes, including the first P-type transistor MP11, the first P-type transistor MP21, the second N-type transistor MN12, and the second N-type transistor MN22. The first P-type transistors MP11 and MP21 are a pair of transistors with symmetrical input / output characteristics because they are connected in series in their respective upper branches 110A and 110B. For the same reason, the second N-type transistors MN12 and MN22 are another pair of transistors with symmetrical input / output characteristics.

[0026] The transistors grouped into the second transistor group are indicated by dashed lines and include the second P-type transistor MP12, the second P-type transistor MP22, the first N-type transistor MN11, and the first N-type transistor MN21. The second P-type transistors MP12 and MP22 are a pair of transistors with symmetrical input / output characteristics. The first N-type transistors MN11 and MN21 are another pair of transistors with symmetrical input / output characteristics.

[0027] In order to enable the first transistor group and the second transistor group to perform differential signal reception and reset signal reception processes, the amplifier circuit 100 further includes two sets of input switches SI1 and SI2 and two sets of reset switches SR1 and SR2.

[0028] Input switch SI1 corresponds to the first transistor group and is enabled according to the input enable interval of input control signal CI1, so that the first transistor group performs a differential signal receiving process to receive differential signal feeds, such as the first differential input signals VI1+ and VI1-. Input switch SI2 corresponds to the second transistor group and is enabled according to the input enable interval of input control signal CI2, so that the second transistor group performs a differential signal receiving process to receive differential signal feeds, such as the second differential input signals VI2+ and VI2-.

[0029] Reset switch SR1 corresponds to the first transistor group and is enabled according to the reset enable interval of reset control signal CR1, so that the first transistor group performs a reset signal receiving process to receive reset signal feeds, such as the first reset signal RS1 and the second reset signal RS2. Reset switch SR2 corresponds to the second transistor group and is enabled according to the reset enable interval of reset control signal CR2, so that the second transistor group performs a reset signal receiving process to receive reset signal feeds, such as the third reset signal RS3 and the fourth reset signal RS4.

[0030] Figure 2This diagram shows the waveforms of input control signals CI1 and CI2 and reset control signals CR1 and CR2 in one embodiment of the present invention. Figure 2 In the example, each signal corresponds to an enabled interval as a high state and an disabled interval as a low state. However, the present invention is not limited to this.

[0031] exist Figure 2 During the time interval T1, the input control signal CI1 corresponds to the input enable interval IE1, which enables the input switch SI1, thereby causing the first transistor group to perform a differential signal receiving process to receive the differential signal feed. The reset control signal CR1 corresponds to the reset disable interval RD1, which disables the reset switch SR1, thereby preventing the first transistor group from performing a reset signal receiving process.

[0032] On the other hand, the input control signal CI2 corresponds to the input disable interval ID2, which disables the input switch SI2, thereby preventing the second transistor group from performing the differential signal reception process. The reset control signal CR2 corresponds to the reset enable interval RE2, which enables the reset switch SR2, thereby enabling the second transistor group to perform the reset signal reception process to receive the reset signal feed.

[0033] Please refer to Figure 3A . Figure 3A This diagram shows an equivalent circuit of an amplifier circuit 100 performing a differential signal reception process in a first transistor group and a reset signal reception process in a second transistor group, according to one embodiment of the present invention.

[0034] like Figure 3A As shown, corresponding to Figure 2 During time interval T1, the first transistor group, consisting of first P-type transistor MP11, first P-type transistor MP21, second N-type transistor MN12, and second N-type transistor MN22, receives the first differential input signals VI1+ and VI1- through the enabled input switch SI1, thereby generating the first differential output signals VO1+ and VO1- at the differential output terminals O+ and O-. The disabled reset switch SR1 is not shown.

[0035] The second transistor group receives the third reset signal RS3 through the second P-type transistor MP12 and the second P-type transistor MP22 via the enabled reset switch SR2, and receives the fourth reset signal RS4 through the first N-type transistor MN11 and the first N-type transistor MN21 via the enabled reset switch SR2. The disabled input switch SI2 is not shown.

[0036] The third reset signal RS3 and the fourth reset signal RS4 actually contain both DC and AC components.

[0037] The DC component is configured to turn on the second P-type transistor MP12, the second P-type transistor MP22, the first N-type transistor MN11, and the first N-type transistor MN21. The DC components of the third reset signal RS3 and the fourth reset signal RS4 may have different levels due to the different series connection positions of the corresponding transistors in each branch and the different transistor characteristics.

[0038] For example, when the first supply voltage V1 is 1 volt, the voltage across the first P-type transistors MP11 and MP21 when they are turned on is 0.2 volts, and the threshold voltage of the second P-type transistors MP12 and MP22 is 0.3 volts, the third reset signal RS3 may have a DC component of 0.4 volts. When the second supply voltage V2 is 0 volts, the voltage across the second N-type transistors MN12 and MN22 when they are turned on is 0.2 volts, and the threshold voltage of the first N-type transistors MN11 and MN21 is 0.2 volts, the fourth reset signal RS4 may have a DC component of 0.45 volts.

[0039] On the other hand, the AC component is AC grounded to remove the charge from the parasitic capacitance associated with the differential signal reception process of the second P-type transistor MP12, the second P-type transistor MP22, the first N-type transistor MN11, and the first N-type transistor MN21.

[0040] Please refer to this again. Figure 2 .exist Figure 2 During time interval T2, the input control signal CI1 corresponds to the input disable interval ID1, which disables the input switch SI1, thereby preventing the first transistor group from performing the differential signal reception process. The reset control signal CR1 corresponds to the reset enable interval RE1, which enables the reset switch SR1, thereby enabling the first transistor group to perform the reset signal reception process to receive the reset signal feed.

[0041] On the other hand, the input control signal CI2, corresponding to the input enable interval IE2, enables the input switch SI2, thereby causing the second transistor group to perform a differential signal receiving process to receive the differential signal feed. The reset control signal CR2, corresponding to the reset disable interval RD2, disables the reset switch SR2, thereby preventing the second transistor group from performing a reset signal receiving process.

[0042] Please refer to Figure 3B . Figure 3B This diagram shows an equivalent circuit diagram of an amplifier circuit 100 performing a differential signal reception process in the second transistor group and a reset signal reception process in the first transistor group, according to one embodiment of the present invention.

[0043] like Figure 3B As shown, corresponding to Figure 2 During time interval T2, the first transistor group receives the first reset signal RS1 through the enabled reset switch SR1 by the first P-type transistor MP11 and the first P-type transistor MP21, and receives the second reset signal RS2 through the enabled reset switch SR1 by the second N-type transistor MN12 and the second N-type transistor MN22. The disabled input switch SI1 is not shown.

[0044] Similarly, the first reset signal RS1 and the second reset signal RS2 actually contain both DC and AC components.

[0045] The DC components are configured to turn on the first P-type transistor MP11, the first P-type transistor MP21, the second N-type transistor MN12, and the second N-type transistor MN22. The DC components of the first reset signal RS1 and the second reset signal RS2 may have different levels due to the different series connection positions of the corresponding transistors in each branch and the different transistor characteristics.

[0046] For example, when the first supply voltage V1 is 1 volt, and the threshold voltages of the first P-type transistor MP11 and the first P-type transistor MP21 are 0.3 volts, the first reset signal RS1 may have a DC component of 0.6 volts. When the second supply voltage V2 is 0 volt, and the threshold voltages of the second N-type transistor MN12 and the second N-type transistor MN22 are 0.2 volts, the second reset signal RS2 may have a DC component of 0.3 volts.

[0047] On the other hand, the AC component is AC grounded to remove the charge from the parasitic capacitances associated with the differential signal reception process of the first P-type transistor MP11, the first P-type transistor MP21, the second N-type transistor MN12, and the second N-type transistor MN22.

[0048] The second transistor group, consisting of the second P-type transistor MP12, the second P-type transistor MP22, the first N-type transistor MN11, and the first N-type transistor MN21, receives the second differential input signals VI2+ and VI2- through the enabled input switch SI2, thereby generating the second differential output signals VO2+ and VO2- at the differential output terminals O+ and O-. The disabled reset switch SR2 is not shown.

[0049] Please refer to this again. Figure 2After time interval T2, each signal will repeat the waveforms of time intervals T1 and T2, causing the first and second transistor groups to interleave the above-mentioned operations in interleaved input mode. It should be noted that since the first and second transistor groups can be reset through a reset signal reception process without performing differential signal reception, no additional time is required for resetting. The time difference between two adjacent input enable intervals (e.g., input enable intervals IE1 and IE2) of the input control signals CI1 and CI2 can be less than a preset value, and may even be close to 0.

[0050] Using the transistor array described above, the amplifier circuit 100 in Figure 3A In this configuration, the second transistor group forms a cascaded structure, increasing the output impedance of the differential output terminals O+ and O-, thus providing a larger gain for the first differential input signals VI1+ and VI1- relative to the second differential input signals VI2+ and VI2-. Meanwhile, the amplifier circuit 100... Figure 3B In this configuration, the first transistor group forms a current source structure to provide a second differential input signal VI2+, VI2- with a larger power supply rejection ratio (PSRR) compared to the first differential input signal VI1+, VI1-.

[0051] Please refer to Figure 4 . Figure 4 This diagram shows a circuit diagram of an amplifier circuit 400 according to another embodiment of the present invention. The amplifier circuit 400 includes a pair of upper branches 410A and 410B and a pair of lower branches 420A and 420B.

[0052] The structure of the upper branch 410A and 410B Figure 1 The upper branches 410A and 410B are the same, wherein upper branch 410A includes a first P-type transistor MP11 and a second P-type transistor MP12, and upper branch 410B includes a first P-type transistor MP21 and a second P-type transistor MP22. The structures of the lower branches 420A and 420B are the same. Figure 1 The lower branches 120A and 120B are the same, wherein the lower branch 420A includes a first N-type transistor MN11 and a second N-type transistor MN12, and the lower branch 120B includes a first N-type transistor MN21 and a second N-type transistor MN22.

[0053] However in Figure 4In the first transistor group, there are first P-type transistors MP11, MP21, MN11, and MN21. The second transistor group includes second P-type transistors MP12, MP22, MN12, and MN22.

[0054] Therefore, in Figure 4 In this embodiment, input switch SI1 and reset switch SR1 correspond to the first transistor group, and input switch SI2 and reset switch SR2 also correspond to the second transistor group. The operation of input switches SI1, SI2 and reset switches SR1, SR2 is the same as in the previous embodiment, and therefore will not be described again.

[0055] Please refer to Figure 5A . Figure 5A This diagram shows an equivalent circuit diagram of an amplifier circuit 400 performing a differential signal reception process in a first transistor group and a reset signal reception process in a second transistor group, according to one embodiment of the present invention.

[0056] The first transistor group consists of a first P-type transistor MP11, a first P-type transistor MP21, a first N-type transistor MN11, and a first N-type transistor MN21. These transistors receive first differential input signals VI1+ and VI1- through an enabled input switch SI1, and generate first differential output signals VO1+ and VO1- at the differential output terminals O+ and O-.

[0057] The second transistor group receives the third reset signal RS3 through the second P-type transistor MP12 and the second P-type transistor MP22 via the enabled reset switch SR2, and receives the fourth reset signal RS4 through the second N-type transistor MN12 and the second N-type transistor MN22 via the enabled reset switch SR2.

[0058] Please refer to Figure 5B . Figure 5B This diagram shows an equivalent circuit of an amplifier circuit 400 performing a differential signal reception process in the second transistor group and a reset signal reception process in the first transistor group, according to one embodiment of the present invention.

[0059] The first transistor group receives a first reset signal RS1 from the first P-type transistor MP11 and the first P-type transistor MP21 through the enabled reset switch SR1, and receives a second reset signal RS2 from the first N-type transistor MN11 and the first N-type transistor MN21 through the enabled reset switch SR1.

[0060] The second transistor group consists of the second P-type transistor MP12, the second P-type transistor MP22, the second N-type transistor MN12, and the second N-type transistor MN22 receiving the second differential input signals VI2+ and VI2- through the enabled input switch SI2, so as to generate the second differential output signals VO2+ and VO2- at the differential output terminals O+ and O-.

[0061] Using the transistor array described above, the amplifier circuit 100 in Figure 5A In this configuration, a first gain and a second gain are provided to the first differential input signals VI1+ and VI1- and the second differential input signals VI2+ and VI2-, respectively, and the difference between the first gain and the second gain is less than a preset value. In other words, with... Figure 3A as well as Figure 3B In comparison to the structure, Figure 5A The gains of the first differential input signals VI1+ and VI1- are relatively close to those of the second differential input signals VI2+ and VI2-. Meanwhile, the amplifier circuit 100... Figure 5B In the configuration, the second differential input signals VI2+ and VI2- provide a larger power supply rejection ratio compared to the first differential input signals VI1+ and VI1-.

[0062] Please refer to Figure 6 . Figure 6 This diagram shows a circuit diagram of an amplifier circuit 600 according to another embodiment of the present invention. The amplifier circuit 600 includes a pair of upper branches 610A and 610B and a pair of lower branches 620A and 620B.

[0063] The upper branches 610A and 610B are electrically coupled between the first supply voltage V1 and a pair of differential output terminals O+ and O-. The upper branches 610A and 610B are symmetrical and each contains a P-type transistor, with upper branch 610A containing P-type transistor MP1 and upper branch 610B containing P-type transistor MP2. The lower branches 620A and 620B are electrically coupled between the differential output terminals O+ and O- and the second supply voltage V2. The lower branches 620A and 620B are symmetrical and each contains an N-type transistor, with lower branch 620A containing N-type transistor MN1 and lower branch 620B containing N-type transistor MN2.

[0064] The P-type transistors of each pair of upper branches 610A and 610B, and the N-type transistors of each pair of lower branches 620A and 620B, are divided into multiple transistor groups. In this embodiment, P-type transistors MP1 and MP2 are divided into a first transistor group. N-type transistors MN1 and MN2 are divided into a second transistor group. Each first transistor group and each second transistor group contains a pair of transistors.

[0065] The amplifier circuit 600 further includes two sets of input switches SI1 and SI2 and two sets of reset switches SR1 and SR2. Input switch SI1 corresponds to the first transistor group and is activated according to the input enable interval of the input control signal CI1, enabling the first transistor group to perform a differential signal receiving process to receive differential signal feeds, such as differential input signals VI+ and VI-. Input switch SI2 corresponds to the second transistor group and is activated according to the input enable interval of the input control signal CI2, enabling the second transistor group to receive differential signal feeds, such as differential input signals VI+ and VI-, during the differential signal receiving process.

[0066] Reset switch SR1 corresponds to the first transistor group and is enabled according to the reset enable interval of reset control signal CR1, so that the first transistor group performs a reset signal receiving process to receive a reset signal feed, such as the feed of the first reset signal RS1. Reset switch SR2 corresponds to the second transistor group and is enabled according to the reset enable interval of reset control signal CR2, so that the second transistor group performs a reset signal receiving process to receive a reset signal feed, such as the feed of the second reset signal RS2.

[0067] In addition to being configured to operate in interleaved input mode, the first transistor group and the second transistor group also operate in simultaneous input mode. In interleaved input mode, the first transistor group and the second transistor group receive differential input signals VI+ and VI- at different times to generate differential output signals VO+ and VO- at differential output terminals O+ and O-. In simultaneous input mode, they simultaneously receive the differential input signals VI+ and VI- to generate differential output signals VO+ and VO- at differential output terminals O+ and O-, and simultaneously stop receiving differential input signals VI+ and VI-.

[0068] Please refer to Figure 7 . Figure 7 This diagram shows the waveforms of input control signals CI1 and CI2 and reset control signals CR1 and CR2 in one embodiment of the present invention.

[0069] like Figure 7 As shown, time intervals T1 and T2 correspond to the interleaved input mode. Input control signals CI1 and CI2 will be located in the input enable intervals IE1 and IE2 respectively, causing the first transistor group to receive the differential input signals VI+ and VI- first, and then the second transistor group to receive the differential input signals VI+ and VI-. At this time, reset control signals CR2 and CR1 will be located in the reset enable intervals RE2 and RE1 respectively, causing the second transistor group to be reset first, and then the first transistor group to be reset.

[0070] Time intervals T3 and T4 correspond to the simultaneous input mode. Input control signals CI1 and CI2 will first be simultaneously located in the input enable intervals IE1 and IE2, and then simultaneously located in the input disable intervals ID1 and ID2. This causes the first transistor group and the second transistor group to simultaneously receive differential input signals VI+ and VI-, and then simultaneously stop receiving differential input signals VI+ and VI-. At this time, reset control signals CR1 and CR2 will first be simultaneously located in the reset disable intervals RD1 and RD2, and then simultaneously located in the reset enable intervals RE1 and RE2. This causes the first transistor group and the second transistor group to first not reset together, and then reset together.

[0071] In one embodiment, the amplifier circuit 600 provides a larger transconductance for the differential input signals VI+ and VI- in the simultaneous input mode, compared to the interleaved input mode.

[0072] It should be noted that, in other embodiments, the amplifier circuit 600 may also, under the control of the input control signals CI1 and CI2, receive differential input signals VI+ and VI- first by the second transistor group and then by the first transistor group in the interleaved input mode, and simultaneously stop receiving differential input signals VI+ and VI- and then simultaneously receive differential input signals VI+ and VI- in the simultaneous input mode.

[0073] Similar to the previous embodiments, the time difference between two adjacent input activation intervals of the two input control signals CI1 and CI2 can also be less than a preset value. This will not be elaborated further here.

[0074] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention. For example, the amplifier circuit may contain any number of transistors in each pair of upper branches and each pair of lower branches, and may be divided into two or more transistor groups to perform differential signal reception processes in an interleaved manner, with the transistor group that does not perform differential signal reception processes performing AC reset.

[0075] In summary, the amplifier circuit with a reset mechanism in this invention performs an AC reset on the transistor group that has not undergone differential signal reception, thereby preventing the residual charge of parasitic capacitance from affecting the differential output signal generated when the transistor group operates in an interleaved manner.

[0076] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the claims of this specification.

[0077] Symbol Explanation

[0078] 100, 400, 600: Amplifier circuits

[0079] 110A, 110B, 410A, 410B, 610A, 610B: Upper branch road

[0080] 120A, 120B, 420A, 420B, 620A, 620B: Lower branch road

[0081] CI1, CI2: Input control signals

[0082] CR1, CR2: Reset control signals

[0083] ID1, ID2: Enter the disabled area

[0084] IE1, IE2: Input Enabled Range

[0085] MN1, MN2: N-type transistors

[0086] MN11, MN21: First N-type transistors

[0087] MN12, MN22: Second N-type transistors

[0088] MP1, MP2: P-type transistors

[0089] MP11, MP21: First P-type transistor

[0090] MP12, MP22: Second P-type transistor

[0091] O+, O-: Differential output terminals

[0092] RD1, RD2: Reset the disabled area

[0093] RE1, RE2: Reset the enabled range

[0094] RS1: First reset signal

[0095] RS2: Second reset signal

[0096] RS3: Third reset signal

[0097] RS4: Fourth reset signal

[0098] SI1, SI2: Input switches

[0099] SR1, SR2: Reset Switch

[0100] T1~T4: Time interval

[0101] V1: First supply voltage

[0102] V2: Second supply voltage

[0103] VI+, VI-: Differential input signals

[0104] VI1+, VI1-: First differential input signal

[0105] VI2+, VI2-: Second differential input signals

[0106] VO+, VO-: Differential output signals

[0107] VO1+, VO1-: First differential output signal

[0108] VO2+, VO2-: Second differential output signals

Claims

1. An amplifier circuit with a reset mechanism, comprising: A pair of upper branches are electrically coupled between a first supply voltage and a pair of differential output terminals, and are symmetrical to each other and each contains at least one P-type transistor; as well as A pair of lower half-branches are electrically coupled between the pair of differential output terminals and the second supply voltage, and are symmetrical to each other and each contains at least one N-type transistor; The P-type transistors in each pair of upper branches and the N-type transistors in each pair of lower branches are divided into multiple transistor groups so that the transistor groups sequentially and alternately perform differential signal reception in an interleaved input mode. When the differential signal reception process is not performed, the transistor groups perform a reset signal reception process and are turned on and AC grounded, thereby causing the pair of differential output terminals to generate differential output. Each of these transistor groups contains M pairs of transistors, and each of the M pairs of transistors has symmetrical input-output characteristics relative to the pair of differential output terminals, where M is a positive integer greater than or equal to 1.

2. The amplifier circuit of claim 1, wherein each pair of upper branches includes a first P-type transistor and a second P-type transistor sequentially electrically coupled between the first supply voltage and the pair of differential output terminals, and the pair of lower branches includes a first N-type transistor and a second N-type transistor sequentially electrically coupled between the pair of differential output terminals and the second supply voltage. The first P-type transistor, the second P-type transistor, the first N-type transistor, and the second N-type transistor are divided into a first transistor group and a second transistor group.

3. The amplifier circuit of claim 2, wherein the first P-type transistor included in the pair of upper branches and the second N-type transistor included in the pair of lower branches are classified into the first transistor group, and the second P-type transistor included in the pair of upper branches and the first N-type transistor included in the pair of lower branches are classified into the second transistor group. The first transistor group is configured to receive a first differential input signal by the first P-type transistor included in the upper half branch and the second N-type transistor included in the lower half branch during the differential signal reception process, so as to generate a first differential output signal at the pair of differential output terminals. The first transistor group is configured such that, during the reset signal receiving process, the first P-type transistor included in the upper half-branch receives the first reset signal and the second N-type transistor included in the lower half-branch receives the second reset signal. The second transistor group is configured to receive a second differential input signal by the second P-type transistor included in the upper half branch and the first N-type transistor included in the lower half branch during the differential signal reception process, so as to generate a second differential output signal at the pair of differential output terminals. The second transistor group is configured to receive a third reset signal by the second P-type transistor included in the upper half-branch and a fourth reset signal by the first N-type transistor included in the lower half-branch during the reset signal reception process.

4. The amplifier circuit of claim 3, wherein the amplifier circuit provides a larger gain for the first differential input signal relative to the second differential input signal, and provides a larger power supply rejection ratio for the second differential input signal relative to the first differential input signal.

5. The amplifier circuit of claim 2, wherein the first P-type transistor included in the pair of upper branches and the first N-type transistor included in the pair of lower branches are classified into the first transistor group, and the second P-type transistor included in the pair of upper branches and the second N-type transistor included in the pair of lower branches are classified into the second transistor group. The first transistor group is configured to receive a first differential input signal by the first P-type transistor included in the upper half branch and the first N-type transistor included in the lower half branch during the differential signal reception process, so as to generate a first differential output signal at the pair of differential output terminals. The first transistor group is configured such that, during the reset signal receiving process, the first P-type transistor included in the upper half-branch receives the first reset signal and the first N-type transistor included in the lower half-branch receives the second reset signal. The second transistor group is configured to receive a second differential input signal by the second P-type transistor included in the upper half branch and the second N-type transistor included in the lower half branch during the differential signal reception process, so as to generate a second differential output signal at the pair of differential output terminals. The second transistor group is configured to receive a third reset signal by the second P-type transistor contained in the upper half-branch and a fourth reset signal by the second N-type transistor contained in the lower half-branch during the reset signal reception process.

6. The amplifier circuit as claimed in claim 5, wherein the amplifier circuit provides a first gain and a second gain to the first differential input signal and the second differential input signal respectively, and the difference between the first gain and the second gain is less than a preset value, and provides a power supply rejection ratio of the second differential input signal that is larger than that of the first differential input signal.

7. The amplifier circuit as described in claim 2, further comprising: Two sets of input switches are configured to be activated according to the input enable range of each of the two input control signals, so as to enable the first transistor group and the second transistor group to perform the differential signal receiving process to receive the differential signal feed; and Two sets of reset switches are configured to be activated according to the reset enable interval of each of the two reset control signals, so as to enable the first transistor group and the second transistor group to perform the reset signal receiving process to receive the reset signal feed. The time difference between two adjacent input activation intervals of the two input control signals is less than a preset value.

8. The amplifier circuit of claim 1, wherein each pair of upper branches comprises a P-type transistor and each pair of lower branches comprises an N-type transistor; The P-type transistors in the upper half of the pair are divided into a first transistor group, and the N-type transistors in the lower half of the pair are divided into a second transistor group. The first transistor group and the second transistor group are configured to operate in the interleaved input mode and the simultaneous input mode, so as to receive differential input signals at different times in the interleaved input mode to generate differential output signals at the pair of differential output terminals, and to simultaneously receive the differential input signals in the simultaneous input mode to generate differential output signals at the pair of differential output terminals and simultaneously stop receiving the differential input signals.

9. The amplifier circuit of claim 8, further comprising: Two sets of input switches are configured to be activated according to the input enable range of each of the two input control signals, so as to enable the first transistor group and the second transistor group to receive differential signal input during the differential signal reception process, respectively; and Two sets of reset switches are configured to be activated according to the reset enable interval of each of the two reset control signals, so that the first transistor group and the second transistor group respectively receive the reset signal feed during the reset signal receiving process; The time difference between two adjacent input activation intervals of the two input control signals is less than a preset value.

10. The amplifier circuit of claim 8, wherein in the interleaved input mode, the first transistor group receives the differential input signal first and then the second transistor group receives the differential input signal, or the second transistor group receives the differential input signal first and then the first transistor group receives the differential input signal. In the simultaneous input mode, the first transistor group and the second transistor group first simultaneously receive the differential input signal and then simultaneously stop receiving the differential input signal, or the first transistor group and the second transistor group first simultaneously stop receiving the differential input signal and then simultaneously receive the differential input signal.

Images