Latching device and method of operation thereof

Abstract

The latch device includes a memory cell, a pair of write switches, and an output terminal. The memory cell stores latched data, and the pair of write switches are coupled to the memory cell through a first node and a second node. The pair of write switches maintain the latched data stored in the memory cell when the logic values of the first input signal and the second input signal are predetermined logic values, and the pair of write switches update the latched data stored in the memory cell when the logic values of the first input signal and the second input signal are mutually exclusive logic values. The output terminal is coupled to at least one of the first node and the second node, and outputs an output signal based on the latched data stored in the memory cell. The invention also introduces the operation of the latch memory.

Description

Technical Field

[0001] The present invention generally relates to latching devices, and more specifically, to an operating method and a latching device that can improve the speed of the latching device. Background Technology

[0002] Differential cascode voltage switch (DCVS) latches are commonly used in many systems due to their high speed, low power consumption, and noise immunity. A DCVS latch operates in reset mode for half of the clock cycle and senses or amplifies the voltage difference (i.e., rising or falling edges) on the latched input pair at the clock edges. Because the DCVS latch does not retain the sensed amplified logic value throughout the entire clock cycle, it is paired with a hold latch, which acts as a transparent element when the DCVS latch is in sense or amplify mode and retains the logic value when the DCVS latch is in reset mode. Since the hold latch transfers data directly from the DCVS latch without a clock signal, its speed is important for achieving high operating frequencies in the system.

[0003] Creative designs are needed for latch devices (i.e., hold latches) that can improve speed and reduce the physical area of ​​latches in integrated circuits (ICs). Summary of the Invention

[0004] This invention introduces a latching device and an operating method that can improve the speed of the latching device.

[0005] In some embodiments, the latching device includes a memory cell, a pair of write switches, and an output terminal. The memory cell includes a pair of cross-coupled inverters storing latched data, and the pair of write switches are coupled to the memory cell via a first node and a second node. The pair of write switches are configured to receive a first input signal and a second input signal, retain the latched data stored in the memory cell when the logic values ​​of the first and second input signals are predetermined logic values, and update the latched data stored in the memory cell when the logic values ​​of the first and second input signals are mutually exclusive logic values. The output terminal is coupled to at least one of the first and second nodes and configured to output an output signal based on the latched data stored in the memory cell.

[0006] In some embodiments, the latching device includes a memory cell, a pair of write switches, a pair of inverters, a pair of switches, and an output terminal. The memory cell includes a pair of cross-coupled inverters storing latched data, and the pair of write switches are coupled to the memory cell via a first node and a second node. The pair of write switches are configured to receive a first input signal and a second input signal, retain the latched data stored in the memory cell when the logic values ​​of the first and second input signals are predetermined logic values, and update the latched data stored in the memory cell when the logic values ​​of the first and second input signals are mutually exclusive logic values. The pair of inverters are respectively configured to invert the first and second input signals to generate a first inverted input signal and a second inverted input signal. The first switch of the pair of switches is coupled to the first node and configured to drive the first node to a reference voltage (i.e., a second reference voltage) when the second inverted input signal asserts the first switch. The second switch of the pair of switches is coupled to the second node and configured to drive the second node to a second reference voltage when the first inverted input signal asserts the second switch. The output terminal is coupled to at least one of the first node and the second node and configured to output an output signal based on latched data stored in a memory cell.

[0007] In some embodiments, the operating method is applicable to a latching device including a memory and a pair of write switches coupled to the memory via a first node and a second node. The operating method includes the steps of: receiving a first input signal and a second input signal; maintaining latched data stored in a memory cell in response to determining that the logic values ​​of the first and second input signals are predetermined logic values; updating the latched data stored in the memory cell in response to determining that the logic values ​​of the first and second input signals are mutually exclusive logic values; and outputting an output signal based on the latched data stored in the memory cell.

[0008] In some embodiments, the latching device includes a pair of write switches configured to hold latched data stored in the memory of the latching device or to update the latched data stored in the memory based on the logic values ​​of a first input signal and a second input signal. The latching device holds the latched data stored in the memory when the logic values ​​of the first and second input signals are predetermined logic values; and updates the latched data stored in the memory when the logic values ​​of the first and second input signals are mutually exclusive logic values. Because the pair of write switches can quickly set the latched data of the memory cell to the desired value, the speed of the latching device is improved and the latency of the latching device is reduced. Furthermore, because the number of electronic components in the latching device is relatively small, the latching device has a small physical area in the integrated circuit (IC). Attached Figure Description

[0009] Figure 1A schematic diagram of a system including a differential series voltage switch (DCVS) latch and a latching device according to some embodiments is shown;

[0010] Figures 2 to 8 A schematic diagram of a latching device according to some embodiments is shown;

[0011] Figure 9 A flowchart illustrating the operation method of a latching device according to some embodiments is provided.

[0012] Explanation of icon numbers

[0013] 100: System;

[0014] 101, 102, 103, 104, 109, 110, 113, 114, 115, 116, 809, 810: Transistors;

[0015] 105, 106, 505, 506, 805, 806: Write switch;

[0016] 107: First setting switch;

[0017] 108: Second setting switch;

[0018] 110: Differential series voltage switch latch;

[0019] 111: First switch, first pull-down switch;

[0020] 112: Second switch, second pull-down switch;

[0021] 120, 220, 320, 420, 520, 620, 720, 820: Latching devices;

[0022] 811, 812: Switch, pull-up switch;

[0023] 910, 920, 930, 940: Steps;

[0024] CLK: Clock signal;

[0025] D. DBAR: Data signal;

[0026] DisHi: First control signal;

[0027] DisLo: Second control signal;

[0028] GND: Second reference voltage;

[0029] IN: First input signal;

[0030] INBAR: Second input signal;

[0031] INBAR_PD: Second inverting input signal;

[0032] IN_PD: First inverting input signal;

[0033] INV1, INV2: Inverters;

[0034] MC: Memory Unit;

[0035] N1: First node;

[0036] N2: Second node;

[0037] OUT, OUTF: Output signals;

[0038] VDD: First reference voltage. Detailed Implementation

[0039] Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0040] Figure 1A schematic diagram of a system 100 including a differential series voltage switch (DCVS) latch 110 and a latching device 120 according to some embodiments is shown. The DCVS latch 110 can receive a clock signal CLK, a data signal D, and a data signal DBAR, perform latching operations based on the received clock signal CLK, data signal D, and data signal DBAR, and output signals IN and INBAR to the latching device 120. The DCVS latch 110 can operate in a reset mode where the logic values ​​of both signals IN and INBAR are set to predetermined logic values, or in a transparent mode where the logic values ​​of signals IN and INBAR are set according to the logic values ​​of signals D and DBAR. For example, in the reset mode of the DCVS latch 110, the logic values ​​of signals IN and INBAR are set to "11" or "00". In the transparent mode of the DCVS latch 110, the logic values ​​of signals IN and INBAR can be determined based on the difference between signals D and DBAR. For example, when the value of signal D is greater than the value of signal DBAR, signal IN is set to the first logic value (i.e., logic value "1") and signal INBAR is set to the second logic value (i.e., logic value "0"); and when the value of signal D is less than the value of signal DBAR, signal IN is set to the second logic value and signal INBAR is set to the first logic value. The DCVS 110 can operate in transparent mode when the clock signal CLK is logic value "1"; and the DCVS 110 can operate in reset mode when the clock signal CLK is logic value "0". It should be understood that the first logic value, second logic value, predetermined logic value, and / or CLK reset / transparent mode logic value can be set differently depending on design requirements.

[0041] The latching device 120 (also referred to as a hold latch) may include input terminals and output terminals, wherein the input terminals of the latching device 120 are coupled to the DCVS latch 110 to receive signals IN and INBAR (also referred to as input signals IN and INBAR), and output signals OUT and OUTF are connected to the output terminals of the latching device 120. In some embodiments, the latching device 120 is configured to hold latched data stored in the latching device 120 when the logic values ​​of the input signals IN and INBAR are the same predetermined logic value. For example, the latching device 120 holds latched data stored in the latching device 120 when the logic values ​​of the input signals IN and INBAR are "11". However, the present invention is not intended to limit the predetermined logic value to "11", and in some alternative embodiments, the predetermined logic value may be "00". In some embodiments, the latching device 120 is configured to update latched data stored in the latching device 120 when the logic values ​​of the input signals IN and INBAR are mutually exclusive logic values. For example, when the logic values ​​of input signals IN and INBAR are "10" or "01", the latched data stored in latch device 120 is updated. Latch device 120 can drive output signals OUT and OUTF based on the latched data stored in latch device 120.

[0042] Figure 2 A schematic diagram of a latching device 220 according to some embodiments is shown. Figure 2 The latching device 220 in the middle can be connected with Figure 1 The latching device 220 is identical to the latching device 120 in the previous example. The latching device 220 may include a memory cell MC, a pair of write switches 105 and 106, a first node N1, and a second node N2. The memory cell MC includes a pair of cross-coupled inverters, one of which includes transistors 101 and 102, and the other includes transistors 103 and 104. Transistor 101 is coupled between the first reference node and the first node N1, and transistor 102 is coupled between the first node N1 and the second reference node. The control terminals (i.e., gate terminals) of transistors 101 and 102 are coupled to the second node N2. The first reference node refers to the node receiving the first reference voltage VDD, and the second reference node refers to the node receiving the second reference voltage GND. Transistor 103 is coupled between the first reference node and the second node N2, and transistor 104 is coupled between the second node N2 and the second reference node. The control terminals (i.e., gate terminals) of transistors 103 and 104 are coupled to the first node N1. In some embodiments, transistors 101 and 103 are p-type transistors, and transistors 102 and 104 are n-type transistors, but the invention is not limited thereto.

[0043] A pair of write switches 105 and 106 are coupled to the memory cell MC via a first node N1 and a second node N2, and are configured to receive a first input signal IN and a second input signal INBAR. The first write switch 105 is coupled between a first reference node and the first node N1, and its control terminal receives the first input signal IN. The second write switch 106 is coupled between the first reference node and the second node N2, and its control terminal receives the second input signal INBAR. In some embodiments, each of the first write switch 105 and the second write switch 106 is a transistor, but the invention is not limited thereto. Any circuit structure with switching functionality is within the scope of this invention.

[0044] In some embodiments, the memory cell MC is configured to store latched data of the latching device 220, and the latching device 220 operates according to the logic values ​​of the input signals IN and INBAR. The latching device 220 can hold the latched data stored in the memory cell MC when the logic values ​​of the input signals IN and INBAR are predetermined logic values ​​(i.e., logic values ​​of "11"). For example, when the logic values ​​of the input signals IN and INBAR are "11", both write switches 105 and 106 are turned off, and the latched data stored in the memory MC is held. It should be understood that the predetermined logic value can be set to "00" instead of "11", and the circuit structure of the latching device 220 can be changed to meet design requirements.

[0045] When the logic values ​​of input signals IN and INBAR are mutually exclusive (i.e., logic values ​​of "10" or "01"), latching device 220 can update the latched data stored in memory cell MC by writing an updated value to memory cell MC. For example, when the logic values ​​of input signals IN and INBAR are "0" and "1" respectively, the first write switch 105 is turned on and the second write switch 106 is turned off. Therefore, the first node N1 is pulled up to the first reference voltage VDD, and the transistor 104 of the cross-coupled inverter is turned on to pull the second node N2 down to the second reference voltage GND. In this way, the latched data stored in memory cell MC is updated to the new logic value (i.e., the logic value at the first node N1 is "1"). Similarly, when the logic values ​​of input signals IN and INBAR are "0" and "1" respectively, the first write switch 105 is turned off and the second write switch 106 is turned on. Therefore, the second node N2 is pulled up to the first reference voltage VDD, and the transistor 102 of the cross-coupled inverter is turned on to pull the first node N1 down to the second reference voltage GND. In this way, the latched data stored in the memory cell MC is updated to the new logic value (that is, the logic value at the first node N1 is "0").

[0046] In some embodiments, transistors 102 and 104, as well as the first write switch 105 and the second write switch 106, are optimized for high switching speeds (or low switching delays), and other transistors (i.e., transistors 101 and 103) are optimized for low capacitance or low leakage. For example, the switching speeds of transistors 102, 104, and the first and second write switches 105 and 106 are faster than those of transistors 101 and 103. In this way, the latching speed of the latching device 220 is improved, and the latching delay of the latching device 220 is reduced. Furthermore, since the number of electronic components included in the latching device 220 is relatively small, the physical area in the integrated circuit is small.

[0047] Figure 3 A schematic diagram of a latching device 320 according to some embodiments is shown. Figure 3 The latching device 320 and Figure 2 The same elements of the latching device 220 are shown using the same reference numerals. (Refer to...) Figure 2 and Figure 3 , Figure 3 The latching device 320 in the middle and Figure 2The difference between latching devices 220 is that latching device 320 further includes a first setting switch 107 and a second setting switch 108. The first setting switch 107 is coupled between a first node N1 and a second reference node (i.e., the reference node receiving the reference voltage GND), and its control terminal receives a first control signal DisHi. The second setting switch 108 is coupled between a second node N2 and a second reference node, and its control terminal receives a second control signal DisLo. Even when the logic values ​​of input signals IN and INBAR are both predetermined logic values ​​(i.e., logic value "11"), the first setting switch 107 and the second setting switch 108 allow latching device 320 to set the logic values ​​to the first node N1 and the second node N2. In some embodiments, when the logic values ​​of input signals IN and INBAR are both predetermined logic values ​​(i.e., logic value "11"), the first control signal DisHi or the second control signal DisLo may only be a logic value "1". In other words, when the input signals IN and INBAR are not at predetermined logic values, the first control signal DisHi and the second control signal DisLo are both set to the logic value "0".

[0048] In some embodiments, when the logic values ​​of input signals IN and INBAR are "11" and the logic values ​​of the first control signal DisHi and the second control signal DisLo are "10", the first setting switch 107 is turned on and the second setting switch 108 is turned off. Therefore, the first node N1 is pulled down by the first setting switch 107 to have a logic value of "0", and the second node N2 is pulled up by the transistor 103 to have a logic value of "1". When the logic values ​​of input signals IN and INBAR are "11" and the logic values ​​of the first control signal DisHi and the second control signal DisLo are "01", the first setting switch 107 is turned off and the second setting switch 108 is turned on. Therefore, the second node N2 is pulled down by the second setting switch 108 to have a logic value of "0", and the first node N1 is pulled up by the transistor 101 to have a logic value of "1". In this way, the latching device 320 can set logic values ​​for the first node N1 and the second node N2 even when both input signals IN and INBAR are the predetermined logic value "11".

[0049] Figure 4 A schematic diagram of a latching device 420 according to some embodiments is shown. Figure 4 The latching device 420 and Figure 3 The same elements of the latching device 320 are shown using the same reference numerals. (Refer to...) Figure 3 and Figure 4 , Figure 4 The latching device 420 and Figure 3 The difference between the latching devices 320 is that latching device 420 further includes transistors 109 and 110, wherein transistor 109 is coupled between transistors 101 and 102, and transistor 110 is coupled between transistors 103 and 104. A first terminal of transistor 109 is coupled to transistor 101 via a first node N1, a second terminal of transistor 109 is coupled to transistor 102, and a control terminal of transistor 109 receives a first input signal IN. A first terminal of transistor 110 is coupled to transistor 103 via a second node N2, a second terminal of transistor 110 is coupled to transistor 104, and a control terminal of transistor 110 receives a second input signal INBAR.

[0050] In some embodiments, when the first input signal IN is logic value "0" and the second input signal INBAR is logic value "1", the first write switch 105 and transistor 110 are turned on, and the second write switch 106 and transistor 109 are turned off. Since the first write switch 105 and transistor 110 are turned on and the second write switch 106 is turned off, the first node N1 is pulled up to logic value "1" and the second node N2 is pulled down to logic value "0". Simultaneously, since transistor 109 is turned off, the electrical path between the first node N1 and transistor 102 is cut off, thus preventing pull-down contention of transistor 102. Pull-down contention from transistor 102 is one of the limiting factors that slows down the switching speed of transistors 103, 104, and 110, and the speed of the latching device 420. By preventing pull-down contention of transistor 102 by turning off transistor 109, the switching speed of transistors 103, 104, and 110, and the speed of the latching device 420 are improved.

[0051] When the first input signal IN is logic value "1" and the second input signal INBAR is logic value "0", the first write switch 105 and transistor 110 are turned off, and the second write switch 106 and transistor 109 are turned on. Since the second write switch 106 and transistor 109 are turned on and the first write switch 105 is turned off, the second node N2 is pulled up to logic value "1" and the first node N1 is pulled down to logic value "0". Simultaneously, since transistor 110 is turned off, the electrical path between the second node N2 and transistor 104 is cut off, thus preventing pull-down contention in transistor 104. By preventing pull-down contention in transistor 104 by turning off transistor 110, the switching speed of transistors 101, 102, and 109 and the speed of the latching device 420 are improved.

[0052] Figure 5 A schematic diagram of a latching device 520 according to some embodiments is shown. Figure 5 The latching device 520 and Figure 3 The same elements of the latching device 320 are shown using the same reference numerals. (Refer to...) Figure 3 and Figure 5 , Figure 5 The latching device 520 and Figure 3 The difference between the latching devices 320 is that latching device 520 includes write switches 505 and 506 instead of write switches 105 and 106. Write switch 505 is coupled between the first node N1 and the second reference node (i.e., the reference node receiving the reference voltage GND), and its control terminal receives a first input signal IN. Write switch 506 is coupled between the second node N2 and the second reference node (i.e., the reference node receiving the reference voltage GND), and its control terminal receives a second input signal INBAR. In some embodiments, when the logic values ​​of the first input signal IN and the second input signal INBAR are predetermined logic values ​​(i.e., logic value "00"), write switches 505 and 506 are turned off, and latched data stored in the memory cell MC is retained. When the first input signal IN has a logic value "1" and the second input signal INBAR has a logic value "0", write switch 505 is turned on and write switch 506 is turned off. Therefore, the first node N1 is pulled down to the logic value "0" via write switch 505, and the second node N2 is pulled up to the logic value "1" via transistor 103. When the first input signal IN has a logic value "0" and the second input signal INBAR has a logic value "1", write switch 505 is turned off and write switch 506 is turned on. Therefore, the second node N2 is pulled down to the logic value "0" via write switch 506, and the first node N1 is pulled up to the logic value "1" via transistor 101. In this way, latching device 520 can maintain latched data stored in memory MC when the logic values ​​of input signal IN and input signal INBAR are "00"; and latching device 520 can update latched data stored in memory MC when the logic values ​​of input signal IN and input signal INBAR are mutually exclusive logic values ​​(i.e., logic values ​​"01" or "10"). In some embodiments, transistors 101 and 103 in the memory cell MC, as well as transistors included in write switches 505 and 506, are optimized to have high switching speed (or low switching latency), and other transistors (i.e., transistors 102 and 104) are optimized for low capacitance or low leakage. In this way, the latching speed of the latching device 520 is improved, and the latching latency of the latching device 520 is reduced.

[0053] Figure 6 A schematic diagram of a latching device 620 according to some embodiments is shown. Figure 6The latching device 620 and Figure 3 The same elements of the latching device 320 are shown using the same reference numerals. (Refer to...) Figure 3 and Figure 6 , Figure 6 The latching device 620 and Figure 3 The difference between the latching devices 320 is that latching device 620 further includes a first switch 111 and a second switch 112 (also referred to as a first pull-down switch 111 and a second pull-down switch 112), as well as inverters INV1 and INV2. Inverter INV1 is configured to receive a first input signal IN and invert the first input signal IN to generate a first inverted input signal IN_PD. Inverter INV1 may include transistors 113 and 114 coupled between a first reference node and a second reference node, and the control terminals of transistors 113 and 114 receive the first input signal IN. When the logic value of the first input signal IN is "1", transistor 113 is turned off, transistor 114 is turned on, and the logic value of the first inverted input signal (IN_PD) is "0". When the logic value of the first input signal IN is "0", transistor 113 is turned on, transistor 114 is turned off, and the logic value of the first inverted input signal (IN_PD) is "1". Similarly, inverter INV2 is configured to receive the second input signal INBAR and invert the second input signal INBAR to generate a second inverted input signal INBAR_PD. Inverter INV2 may include transistors 115 and 116 coupled between the first reference node and the second reference node, and the control terminals of transistors 115 and 116 receive the second input signal INBAR. When the logic value of the second input signal INBAR is "0", the logic value of the second inverted input signal INBAR_PD is "1", and vice versa.

[0054] In some embodiments, a first switch 111 is coupled between a first node N1 and a second reference node (i.e., the reference node receiving the reference voltage GND), and the control terminal of the first switch 111 receives a second inverted input signal INBAR_PD. A second switch 112 is coupled between a second node N2 and a second reference node, and the control terminal of the second switch 112 receives a first inverted input signal IN_PD. The first switch 111 is configured to drive the first node N1 to the reference voltage GND according to the second inverted input signal INBAR_PD. The second switch 112 is configured to drive the second node N2 to the reference voltage GND according to the first inverted input signal IN_PD. When the first input signal IN is a logic value "0" and the second input signal INBAR is a logic value "1", the first write switch 105 is turned on, and the first node N1 is pulled up to a logic value "1". Simultaneously, the first inverted input signal IN_PD, having a logic value "1", asserts the second switch 112, thus quickly pulling the second node N2 down to a logic value "0". When the first input signal IN is logic value "1" and the second input signal INBAR is logic value "0", the second write switch 106 is turned on, and the second node N2 is pulled up to logic value "1". Simultaneously, the second inverted input signal INBAR_PD, with logic value "1", enables the first switch 111, thus quickly pulling the first node N1 down to logic value "0". In this way, the first node N1 and the second node N2 can quickly reach the desired logic value, and the switching delay of the latching device 620 is further reduced. Furthermore, since the first switch 111 and the second switch 112 can quickly pull the first node N1 and the second node N2 down to the desired logic value, respectively, transistors 102 and 104 are no longer responsible for the high-speed switching of the latching device 420. Therefore, in some embodiments, transistors 102 and 104 can be optimized for criteria different from high-speed switching, such as low capacitance, low leakage, stable storage, and / or small physical area.

[0055] Figure 7 A schematic diagram of a latching device 720 according to some embodiments is shown. Figure 7 The latching device 720 and Figure 6 The same elements of the latching device 620 are shown using the same reference numerals. (Refer to...) Figure 6 and Figure 7 , Figure 7 The latching device 720 and Figure 6 The difference between latching devices 620 and 720 is that latching device 720 further includes transistor 109 and transistor 110, wherein transistor 109 is coupled between transistor 101 and transistor 102, and transistor 110 is coupled between transistor 103 and transistor 104. The transistors 109 and 110 included in latching device 720 are different from those included in... Figure 4 Transistors 109 and 110 in the latch device 420 shown are identical, therefore a detailed description of their operation is omitted below. Since transistors 109 and 110 can prevent pull-down contention between transistors 102 and 104, the speed of the latch device 720 is improved. Furthermore, since the first switch 111 and the second switch 112 can quickly pull down the first node N1 and the second node N2 to the desired logic value, the first node N1 and the second node N2 can quickly reach the desired logic value, and the switching delay of the latch device 720 is further reduced.

[0056] Figure 8 A schematic diagram of a latching device 820 according to some embodiments is shown. Figure 8 The latching device 820 and Figure 7 The same elements of the latching device 720 are shown using the same reference numerals. (Refer to...) Figure 7 and Figure 8 , Figure 8 The latching device 820 and Figure 7 The difference between the latching devices 720 is that latching device 820 includes write switches 805 and 806 instead of write switches 105 and 106. Write switch 805 is coupled between the first node N1 and the second reference node (i.e., the reference node receiving the reference voltage GND), and its control terminal receives the first input signal IN. Write switch 806 is coupled between the second node N2 and the second reference node (i.e., the reference node receiving the reference voltage GND), and its control terminal receives the second input signal INBAR. Figure 7 The latching device 720 in the middle and Figure 8 Another difference between the latching devices 820 is that latching devices 820 include switches 811 and 812 (also referred to as pull-up switches 811 and 812) instead of switches 111 and 112. Switch 811 is coupled between the first node N1 and the first reference node (i.e., the reference node receiving the reference voltage VDD), and switch 812 is coupled between the second node N2 and the first reference node. Switches 811 and 812 are controlled by the second inverted input signal INBAPR_PD and the first inverted input signal IN_PD, respectively. Figure 7 The latching device 720 and Figure 8Another difference between the latching devices 820 is that latching device 820 includes transistors 809 and 810 instead of transistors 109 and 110. The first terminal of transistor 809 is coupled to transistor 101, the second terminal of transistor 809 is coupled to transistor 102 via a first node N1, and the control terminal of transistor 809 receives a first input signal IN. The first terminal of transistor 810 is coupled to transistor 103, the second terminal of transistor 810 is coupled to transistor 104 via a second node N2, and the control terminal of transistor 810 receives a second input signal INBAR.

[0057] In some embodiments, when the logic values ​​of the first input signal IN and the second input signal INBAR are predetermined logic values ​​(i.e., logic value "00"), the first write switch 805 and the second write switch 806 are turned off, and the latching device 820 retains the data stored in the memory cell MC. When the first input signal IN is a logic value "1" and the second input signal INBAR is a logic value "0", the first write switch 805 is turned on and the second write switch 806 is turned off. Therefore, the first node N1 is pulled down to a logic value "0", and the second node N2 is pulled up to a logic value "1". At the same time, transistor 809 is turned off through the first input signal IN, and transistor 810 is turned on through the second input signal INBAR. In this way, pull-up competition of transistor 101 is prevented, thereby generating a fast transfer speed between the first node N1 and the second node N2. At the same time, switch 812 is turned on through the second inverted input signal INBAR_PD, and switch 811 is turned off through the first inverted input signal IN_PD. In this way, the second node N2 is quickly pulled up to the required logical value (that is, the logical value "1").

[0058] When the first input signal IN is logic value "0" and the second input signal INBAR is logic value "1", the first write switch 805 is turned off and the second write switch 806 is turned on. Therefore, the second node N2 is pulled down to logic value "0", and the first node N1 is pulled up to logic value "1". Simultaneously, transistor 809 is turned on via the first input signal IN, and transistor 810 is turned off via the second input signal INBAR. This prevents pull-up contention in transistor 103, thereby achieving a fast transition speed between the first node N1 and the second node N2. Simultaneously, switch 812 is turned off via the second inverting input signal INBAR_PD, and switch 811 is turned on via the first inverting input signal IN_PD. In this way, the first node N1 is quickly pulled up to the desired logic value (i.e., logic value "1").

[0059] Figure 9A flowchart illustrating an operation method of a latching device according to some embodiments is provided. In step 910, a first input signal and a second input signal are received. For example, the first and second input signals are received via a pair of write switches of the latching device. In step 920, latched data stored in the memory cell of the latching device is maintained in response to determining that the logic values ​​of the first and second input signals are predetermined logic values. In some embodiments, the predetermined logic value may be "11", and in some alternative embodiments, the predetermined logic value may be "00". In step 930, the latched data stored in the memory cell is updated in response to determining that the logic values ​​of the first and second input signals are mutually exclusive logic values. For example, the latched data stored in the memory cell is updated when the logic values ​​of the first and second input signals are "10" or "01". In step 940, an output signal is output based on the latched data stored in the memory cell.

[0060] In the above embodiments, the latching device includes a pair of write switches configured to hold latched data stored in the memory of the latching device or update the latched data stored in the memory based on the logic values ​​of a first input signal and a second input signal. When the logic values ​​of the first and second input signals are predetermined logic values, the latching device can hold the latched data stored in the memory; and when the logic values ​​of the first and second input signals are mutually exclusive logic values, the latching device can update the latched data stored in the memory. Since the pair of write switches can be quickly pulled up or pulled down to the first and second nodes of the memory cell, the speed of the latching device is improved and the latency of the latching device is reduced. Furthermore, since the latching device has relatively few electronic components, it occupies a small physical area in the integrated circuit. Even when the logic values ​​of the first and second input signals are both predetermined logic values, the latching device may further include a first switch and a second switch, which allow the latching device to set the latched data of the memory cell. The latching device may further include a first switch and a second switch, the first switch and the second switch receiving a first inverted input signal and a second inverted input signal to quickly pull down a first node or a second node coupled to the memory cell to a desired logic value. In this way, the speed of the latching device is further improved. Furthermore, the latching device may further include a transistor configured to cut off pull-down contention from the transistor of the memory cell, thereby further improving the speed of the latching device.

[0061] Although embodiments of the invention have been described in detail, the invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the invention disclosed in the claims.

Claims

1. A latching device, comprising: The memory cell includes a pair of cross-coupled inverters for storing latched data; A pair of write switches are coupled to the memory cell via a first node and a second node, respectively receiving a first input signal and a second input signal. The pair of write switches are configured to hold latched data stored in the memory cell when the logic values ​​of the first input signal and the second input signal are predetermined logic values, and the pair of write switches are further configured to update the latched data stored in the memory cell when the logic values ​​of the first input signal and the second input signal are mutually exclusive logic values. An output terminal is coupled to at least one of the first node and the second node, and the output terminal outputs an output signal based on the latched data stored in the memory cell; A first setting switch is coupled between the first node and the second reference node. The first setting switch receives a first control signal and controls the electrical connection between the first node and the second reference node according to the first control signal. as well as A second setting switch is coupled between the second node and the second reference node. The second setting switch receives a second control signal and controls the electrical connection between the second node and the second reference node according to the second control signal.

2. The latching device according to claim 1, wherein The first cross-coupled inverter of the pair of cross-coupled inverters includes a first transistor and a second transistor. The second cross-coupled inverter of the pair of cross-coupled inverters includes a third transistor and a fourth transistor. The control terminals of the first transistor and the second transistor are coupled to the second node. The control terminals of the third transistor and the fourth transistor are coupled to the first node, and The output terminal of the latching device is coupled to at least one of the first node and the second node.

3. The latching device according to claim 1, further comprising: A fifth transistor is coupled between the first node and the transistors of the pair of cross-coupled inverters, the fifth transistor being configured to electrically disconnect the first node from the transistors of the pair of cross-coupled inverters according to the first input signal; as well as A sixth transistor is coupled between the second node and another transistor of the pair of cross-coupled inverters, the sixth transistor being configured to electrically disconnect the second node from the other transistor of the pair of cross-coupled inverters according to the second input signal.

4. The latching device according to claim 1, wherein the pair of write switches comprises: A first write switch is coupled between a first reference node and the first node. The first write switch receives the first input signal and controls the electrical connection between the first reference node and the first node according to the first input signal. as well as A second write switch is coupled between the first reference node and the second node. The second write switch receives the second input signal and controls the electrical connection between the first reference node and the second node according to the second input signal.

5. The latching device according to claim 1, The first setting switch and the second setting switch are configured to set the latched data stored in the memory unit when the logic value of the first input signal and the second input signal is the predetermined logic value.

6. The latching device according to claim 1, further comprising: A pair of inverters invert the first input signal and the second input signal respectively to generate a first inverted input signal and a second inverted input signal.

7. The latching device according to claim 6, further comprising: A first switch is coupled between a second reference node and a first node, and the first switch is configured to drive the first node to a second reference voltage when the second inverting input signal enables the first switch. A second switch is coupled between the second reference node and the second node, and the second switch is configured to drive the second node to the second reference voltage when the first inverting input signal enables the second switch.

8. The latching device according to claim 7, wherein When the second input signal enables the second switch, the second inverted input signal enables the first switch, and When the first input signal enables the first switch, the first inverted input signal enables the second switch.

9. A latching device, comprising: A memory cell includes a pair of cross-coupled inverters, the memory cell storing latched data. A pair of write switches are coupled to the memory cell via a first node and a second node. The pair of write switches receive a first input signal and a second input signal, respectively. The pair of write switches are configured to hold the latched data stored in the memory cell when the logic values ​​of the first input signal and the second input signal are predetermined logic values. The pair of write switches are further configured to update the latched data stored in the memory cell when the logic values ​​of the first input signal and the second input signal are mutually exclusive logic values. A pair of inverters, which respectively invert the first input signal and the second input signal to generate a first inverted input signal and a second inverted input signal; as well as A pair of switches, the pair of switches comprising: A first switch is coupled to the first node. When the second inverted input signal enables the first switch, the first switch drives the first node to a reference voltage. A second switch, coupled to the second node, drives the second node to the reference voltage when the first inverted input signal enables the second switch; and An output terminal is coupled to at least one of the first node and the second node, and the output terminal outputs an output signal based on the latched data stored in the memory cell.

10. The latching device according to claim 9, wherein When the second input signal enables the second switch, the second inverted input signal enables the first switch, and When the first input signal enables the first switch, the first inverted input signal enables the second switch.

11. The latching device according to claim 9, wherein The first cross-coupled inverter of the pair of cross-coupled inverters includes a first transistor and a second transistor. The second cross-coupled inverter of the pair of cross-coupled inverters includes a third transistor and a fourth transistor. The control terminals of the first transistor and the second transistor are coupled to the second node. The control terminals of the third transistor and the fourth transistor are coupled to the first node, and The output terminal of the latching device is coupled to at least one of the first node and the second node.

12. The latching device according to claim 9, further comprising: A fifth transistor is coupled between the first node and the transistors of the pair of cross-coupled inverters, the fifth transistor being configured to electrically disconnect the first node from the transistors of the pair of cross-coupled inverters according to the first input signal; as well as A sixth transistor is coupled between the second node and another transistor of the pair of cross-coupled inverters, the sixth transistor being configured to electrically disconnect the second node from the other transistor of the pair of cross-coupled inverters according to the second input signal.

13. The latching device of claim 9, wherein the pair of write switches comprises: A first write switch is coupled between a first reference node and the first node. The first write switch receives the first input signal and controls the electrical connection between the first reference node and the first node according to the first input signal. as well as A second write switch is coupled between the first reference node and the second node. The second write switch receives the second input signal and controls the electrical connection between the first reference node and the second node according to the second input signal.

14. The latching device according to claim 9, further comprising: A first setting switch is coupled between the first node and the second reference node. The first setting switch receives a first control signal and controls the electrical connection between the first node and the second reference node according to the first control signal. as well as A second setting switch is coupled between the second node and the second reference node. The second setting switch receives a second control signal and controls the electrical connection between the second node and the second reference node according to the second control signal. The first setting switch and the second setting switch are configured to set the latched data stored in the memory unit when the logic value of the first input signal and the second input signal is the predetermined logic value.

15. A method of operating a latching device, the latching device comprising a memory, a pair of write switches coupled to the memory via a first node and a second node, a first setting switch and a second setting switch, the first setting switch being coupled between the first node and a reference node, and the second setting switch being coupled between the second node and the reference node, the method of operating the device comprising: The first input signal and the second input signal are received through the pair of write switches; In response to determining that the logic values ​​of the first input signal and the second input signal are predetermined logic values, latched data stored in the memory cell is maintained by the pair of write switches; The first control signal is received through the first setting switch, and the electrical connection between the first node and the reference node is controlled according to the first control signal. The second control signal is received through the second setting switch, and the electrical connection between the second node and the reference node is controlled according to the second control signal; In response to determining that the logic values ​​of the first input signal and the second input signal are mutually exclusive logic values, the latched data stored in the memory cell is updated via the pair of write switches; as well as Based on the latched data stored in the memory unit, an output signal is output through the output terminal of the latching device.

16. The method of operating the latching device according to claim 15, further comprising: The first input signal and the second input signal are respectively inverted to generate a first inverted input signal and a second inverted input signal; When the second inverting input signal enables the first switch of the latching device, the first node is driven to the reference voltage; When the first inverting input signal enables the second switch of the latching device, the second node is driven to the reference voltage.

17. The method of operating the latching device according to claim 16, wherein... When the second input signal enables the second switch, the second inverted input signal enables the first switch, and When the first input signal enables the first switch, the first inverted input signal enables the second switch.

18. The method of operating the latching device according to claim 15, further comprising: The control terminals of the first and second transistors of the first cross-coupled inverter are coupled to the second node. The control terminals of the third and fourth transistors of the second cross-coupled inverter of the pair of cross-coupled inverters are coupled to the first node.

19. The method of operating the latching device according to claim 18, further comprising: Electrically disconnect the transistor of the first node from the pair of cross-coupled inverters according to the first input signal; as well as The second node is electrically disconnected from the other transistor of the pair of cross-coupled inverters based on the second input signal.

20. The method of operating the latching device according to claim 19, wherein... Electrically disconnecting the transistor of the first node from the pair of cross-coupled inverters according to the first input signal includes: The fifth transistor, which is coupled between the first node and the pair of cross-coupled inverters, is disconnected according to the first input signal; and Electrically disconnecting the second node from the other transistor of the pair of cross-coupled inverters according to the second input signal includes: The sixth transistor, which is coupled between the second node and another transistor of the pair of cross-coupled inverters, is disconnected according to the second input signal.

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