Method and apparatus for dynamic correction of high frequency synchronization signals based on clock reference

Abstract

The application relates to the field of inertial navigation technology and discloses a high-frequency synchronous signal dynamic correction method and device based on a clock reference, which can reduce the requirement of a system on a crystal oscillator and improve the accuracy of a generated high-frequency synchronous reference. The method comprises the following steps: after a reference pulse can be stably and effectively captured, a quotient Q and a remainder R of a quotient of a reference pulse interval counting value after N times of accumulation and averaging divided by a target pulse frequency of a local synchronous clock; when an input capture effective identifier is 1, a counting variable in a module is forced to reset at a rising edge of an input reference pulse to realize synchronization, and the new input quotient Q and remainder R values are latched; then, a modified synchronous clock pulse is obtained by taking the quotient Q as a frequency number and distributing the counting error caused by the remainder R to the first R continuous synchronous pulses.

Description

Technical Field

[0001] This invention relates to the field of inertial navigation technology, and in particular to a method and apparatus for dynamic correction of high-frequency synchronization signals based on a clock reference. Background Technology

[0002] Since there are multiple components in an inertial navigation system, each component usually generates a timing period signal based on its own crystal oscillator clock. When there is a synchronization requirement between components, one component usually acts as the master and outputs a reference pulse to other slave components, which then use this as a standard for synchronization.

[0003] Reference pulses are typically at relatively low frequencies (e.g., second pulses or 10ms pulses), while slave components usually need to implement higher frequency synchronization timing period signals (e.g., 0.5ms sampling references). Due to slight differences in the crystal oscillator clocks of various components and their varying temperature stability, there will inevitably be differences when slave components use external reference pulses for forced synchronization. Generating a higher frequency synchronization signal from a low-frequency reference pulse is an even greater technical challenge.

[0004] Currently used methods:

[0005] First, strictly constrain the stability and temperature characteristics of the crystal oscillator frequencies of the master and slave components to make the crystal clock characteristics between the master and slave as identical as possible.

[0006] Second, the slave component uses its own system clock to count the reference pulses of the master component, obtaining a count value (e.g., M). Then, a processor such as a DSP calculates a new high-frequency synchronization sampling value N. The calculation method is to divide M by F (the high-frequency sampling frequency) and then round it down. Finally, the slave component uses the calculated value N to generate the required high-frequency synchronization reference. This method requires a high-quality crystal oscillator, resulting in high cost. Furthermore, the processing error accumulates in the last high-frequency synchronization signal of each synchronization cycle, which has a certain impact on the system. Summary of the Invention

[0007] The purpose of this invention is to disclose a method and apparatus for dynamic correction of high-frequency synchronization signals based on a clock reference, so as to reduce the system's requirements for crystal oscillators and improve the accuracy of the generated high-frequency synchronization reference.

[0008] To achieve the above objectives, this invention discloses a dynamic correction device for high-frequency synchronization signals based on a clock reference, which includes a local crystal oscillator and further comprises:

[0009] The filtering module is used to filter noise from the input reference pulse;

[0010] The reference period counting and discrimination module is used to count the reference pulse interval time through the clock output of the local crystal oscillator, compare the count value with the upper and lower thresholds of the set standard value, and then perform statistical analysis on the comparison results. When the count value is within the upper and lower thresholds of the set standard value for N consecutive times, it is determined that the reference pulse can be stably and effectively captured, and the capture validity flag is output as 1. Otherwise, the capture validity flag is output as 0 and the module waits for the reference pulse to meet the condition of stable and effective capture. Here, N is the set threshold.

[0011] The new count value generation module is used to calculate the quotient Q and remainder R of the reference pulse interval count value after N cumulative average counts are obtained by dividing the target pulse frequency of the local synchronization clock by the reference pulse frequency.

[0012] The high-frequency pulse generation and synchronization module synchronizes the counting variables within the module by forcibly resetting the module on the rising edge of the input reference pulse when the input capture valid flag is 1, and latches the newly input quotient Q and remainder R values; then, using the quotient Q as the frequency and amortizing the counting error caused by the remainder R onto the first R consecutive synchronization pulses, a corrected synchronization clock pulse is obtained.

[0013] Preferably, the high-frequency pulse generation and synchronization module is further configured to: when not at the rising edge of the input reference pulse, or when the capture validity flag is 0, generate a high-frequency synchronization pulse signal using the local clock, the currently latched quotient Q and remainder R values, and the same correction method used when the rising edge of the reference pulse is valid.

[0014] To achieve the above objectives, the present invention also discloses a method for dynamic correction of high-frequency synchronization signals based on a clock reference, comprising:

[0015] Noise filtering is applied to the input reference pulse;

[0016] The reference pulse interval is counted by the clock output from the local crystal oscillator, and the count value is compared with the upper and lower thresholds of the set standard value. The comparison results are then statistically analyzed. When the count value is within the upper and lower thresholds of the set standard value for N consecutive times, it is determined that the reference pulse can be stably and effectively captured, and the capture validity flag is output as 1. Otherwise, the capture validity flag is output as 0 and the system waits for the reference pulse to meet the condition of stable and effective capture. Here, N is the set threshold.

[0017] After the reference pulse can be stably and effectively captured, the quotient Q and remainder R are calculated by dividing the reference pulse interval count value after N cumulative averages by the target pulse frequency of the local synchronization clock.

[0018] When the input capture valid flag is 1, the counting variable in the module is synchronized by forcibly resetting on the rising edge of the input reference pulse, and the quotient Q and remainder R of the new input are latched; then, the corrected synchronization clock pulse is obtained by using the quotient Q as the frequency and amortizing the counting error caused by the remainder R onto the first R consecutive synchronization pulses.

[0019] The present invention has the following beneficial effects:

[0020] Once the reference pulse stabilizes continuously, the clock count values ​​of the eight consecutive reference pulse intervals are averaged. Using a division module within an FPGA or similar resource, the quotient and remainder for generating a specific frequency (e.g., 2kHz) can be calculated. In the high-frequency pulse generation and synchronization module, if the reference pulse is deemed valid, it is used for synchronization, and a new quotient is used to generate a synchronization pulse. The remainder is used to correct the synchronization pulse, preventing calculation errors from accumulating in the last synchronization pulse of each cycle. If the reference pulse is deemed invalid, synchronization is not performed, and the previously valid quotient and remainder values ​​are used to continue generating high-frequency synchronization pulses, ensuring system robustness. Furthermore, the strategy of distributing the counting error caused by the remainder R across the first R consecutive synchronization pulses unifies the repair standard and ensures the convenience and reliability of the repair implementation.

[0021] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0023] Figure 1 This is a block diagram of a high-frequency synchronization signal dynamic correction device based on a clock reference disclosed in an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram comparing the dynamic correction method for high-frequency synchronization signals based on a clock reference disclosed in this invention with traditional correction methods.

[0025] Figure 3 This is a schematic diagram of the dynamic correction method for high-frequency synchronization signals based on a clock reference disclosed in an embodiment of the present invention. Detailed Implementation

[0026] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention can be implemented in many different ways as defined and covered by the claims.

[0027] Example 1

[0028] This embodiment discloses a high-frequency synchronization signal dynamic correction device based on a clock reference, which is equipped with a local crystal oscillator, such as... Figure 1 As shown, it also includes:

[0029] The filtering module is used to filter noise from the input reference pulse.

[0030] The reference period counting and discrimination module is used to count the reference pulse interval time through the clock output of the local crystal oscillator, compare the count value with the upper and lower thresholds of the set standard value, and then perform statistical analysis on the comparison results. When the count value is within the upper and lower thresholds of the set standard value for N consecutive times, it is determined that the reference pulse can be stably and effectively captured, and the capture validity flag is output as 1. Otherwise, the capture validity flag is output as 0 and the module waits for the reference pulse to meet the condition of stable and effective capture. Here, N is the set threshold.

[0031] The new count generation module is used to calculate the quotient Q and remainder R of the reference pulse interval count value after N cumulative averages are obtained by dividing the target pulse frequency of the local synchronization clock.

[0032] The high-frequency pulse generation and synchronization module synchronizes the counting variable within the module by forcibly resetting the module at the rising edge of the input reference pulse when the input capture valid flag is 1, and latches the newly input quotient Q and remainder R values. Then, using the quotient Q as the frequency and amortizing the counting error caused by the remainder R onto the first R consecutive synchronization pulses, a corrected synchronization clock pulse is obtained. The counting variable is used to dynamically update the current count value. "Synchronizing the counting variable within the module by forcibly resetting the module at the rising edge of the input reference pulse" refers to a reset release process before the specific correction is executed. The reset release can also be considered a waiting process from sleep to startup of the device; see step 4 below for details.

[0033] For example, if N=8, the specific correction process is implemented in the following steps:

[0034] Step 1: The filtering module detects the high and low levels of the input reference pulse, filters out occasional jumping waveforms, and the width of the filtered jumping pulse can be adjusted by parameters, which can effectively avoid the impact of noise caused by occasional strong interference or jitter of the reference signal change on the system.

[0035] Step 2: The reference period counting and judging module uses the system clock to count the interval time of the input reference pulse, starting from the rising edge of the reference pulse and ending at the next rising edge, which can adapt to the reference pulse waveforms under different duty cycle states. The obtained count value is judged against the upper and lower thresholds of the set standard value. If 8 consecutive count values are all within the upper and lower thresholds of the set standard value (the threshold setting is related to the actual situation, and 5us can be taken for a 10ms reference), it indicates that the reference pulse has been stably and effectively captured, which can avoid false triggering of the count value when the reference is unstable or there is an abnormal input. When valid, the capture valid flag is output as 1, otherwise it is output as 0.

[0036] Step 3: When the input capture valid flag is 1, the new count value generation module takes the previous 8 reference pulse count values for cumulative averaging (shifting right by 3 bits is equivalent to dividing by 8 for averaging, which saves resources), and the averaged value is input into the division IP core of the FPGA as the dividend. The calculation formula is as follows:

[0037] M0 / F=Q……R;

[0038] Wherein, M0 is the count value of the reference pulse interval after cumulative averaging, F is the frequency of the high-frequency signal to be generated (i.e., "local synchronous clock target pulse frequency"), and the quotient Q and remainder R are obtained through calculation.

[0039] Step 4: The high-frequency synchronous pulse generation and synchronization module uses the current valid quotient Qv and remainder Rv values (Q is the theoretical value and R is 0 during reset initialization) to generate the high-frequency synchronous pulse signal using the internal clock, which is specifically as follows:

[0040] 1. Upon power-on reset, Qv = theoretical value Q0, number Rv = 0, count value CNT = 0, synchronization number NUM = 0, correction value FIX = 0.

[0041] 2. When the input capture valid flag is 1 and the rising edge of the reference pulse arrives, the reset module sets CNT = 0, NUM = 0, FIX = 0, and at the same time assigns the newly counted quotient Q value to Qv and the remainder R to Rv, which indirectly realizes synchronization.

[0042] 3. In other cases:

[0043] If NUM<Rv, FIX=1, otherwise FIX=0.

[0044] If CNT<Q0 / 2, the high-frequency pulse SYN outputs a high level, otherwise it outputs a low level; when CNT=(Qv+FIX), CNT is cleared to 0, and at the same time NUM increments by 1 (NUM is cleared to 0 when it accumulates to the set number of times F).

[0045] This module uses the quotient Q to count the high-frequency synchronization pulses required for production, and uses the remainder R to correct the output synchronization pulses, so that the remainder error is approximately amortized and will not accumulate in the last synchronization pulse of each cycle.

[0046] Furthermore: When not at the rising edge of the input reference pulse, or when the capture validity flag is 0, a high-frequency synchronization pulse signal is generated using the local clock, the currently latched quotient Q and remainder R values, and the same correction method used when the reference pulse is valid on its rising edge. This ensures that high-frequency synchronization pulses are continued to be generated using previously valid quotient and remainder values, guaranteeing system robustness. When new Q and R values ​​are updated and latched, the next round of correction is performed.

[0047] Example 2

[0048] This embodiment uses a dynamic correction method for high-frequency synchronization signals based on a clock reference, referring to... Figure 2 and Figure 3 ,include:

[0049] Step S21: Filter noise from the input reference pulse.

[0050] Step S22: Count the reference pulse interval time using the clock output from the local crystal oscillator, and compare the count value with the upper and lower thresholds of the set standard value. Then, perform statistics on the comparison results. When the count value is within the upper and lower thresholds of the set standard value for N consecutive times, it is determined that the reference pulse can be stably and effectively captured, and the capture validity flag is output as 1. Otherwise, the capture validity flag is output as 0 and wait for the reference pulse to meet the condition of stable and effective capture. Here, N is the set threshold.

[0051] Step S23: After the reference pulse can be stably and effectively captured, divide the reference pulse interval count value after N cumulative averages by the quotient Q and remainder R of the target pulse frequency of the local synchronization clock.

[0052] Step S24: When the input capture valid flag is 1, the counting variable in the module is synchronized by forcibly resetting on the rising edge of the input reference pulse, and the newly input quotient Q and remainder R values ​​are latched; then, the corrected synchronization clock pulse is obtained by using the quotient Q as the frequency and distributing the counting error caused by the remainder R to the first R consecutive synchronization pulses.

[0053] Furthermore, when not at the rising edge of the input reference pulse, or when the capture validity flag is 0, a high-frequency synchronization pulse signal is generated using the local clock, the currently latched quotient Q and remainder R values, and the same correction method as when the rising edge of the reference pulse is valid.

[0054] Optionally, N = 8.

[0055] In summary, the apparatus and method disclosed in the embodiments of the present invention have at least the following advantages:

[0056] Once the reference pulse stabilizes continuously, the clock count values ​​of the eight consecutive reference pulse intervals are averaged. Using a division module within an FPGA or similar resource, the quotient and remainder for generating a specific frequency (e.g., 2kHz) can be calculated. In the high-frequency pulse generation and synchronization module, if the reference pulse is deemed valid, it is used for synchronization, and a new quotient is used to generate a synchronization pulse. The remainder is used to correct the synchronization pulse, preventing calculation errors from accumulating in the last synchronization pulse of each cycle. If the reference pulse is deemed invalid, synchronization is not performed, and the previously valid quotient and remainder values ​​are used to continue generating high-frequency synchronization pulses, ensuring system robustness. Furthermore, the strategy of distributing the counting error caused by the remainder R across the first R consecutive synchronization pulses unifies the repair standard and ensures the convenience and reliability of the repair implementation.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A dynamic correction device for high-frequency synchronization signals based on a clock reference, comprising a local crystal oscillator, characterized in that, Also includes: The filtering module is used to filter noise from the input reference pulse; The reference period counting and discrimination module is used to count the reference pulse interval time through the clock output of the local crystal oscillator, compare the count value with the upper and lower thresholds of the set standard value, and then perform statistical analysis on the comparison results. When the count value is within the upper and lower thresholds of the set standard value for N consecutive times, it is determined that the reference pulse can be stably and effectively captured, and the capture validity flag is output as 1. Otherwise, the capture validity flag is output as 0 and the module waits for the reference pulse to meet the condition of stable and effective capture. Here, N is the set threshold. The new count value generation module is used to obtain the quotient Q and remainder R by dividing the averaged count value of the reference pulse interval after N accumulations by the target pulse frequency of the local synchronization clock after the reference pulse can be stably and effectively captured. The high-frequency pulse generation and synchronization module synchronizes the counting variables within the module by forcibly resetting the module on the rising edge of the input reference pulse when the input capture valid flag is 1, and latches the newly input quotient Q and remainder R values; then, using the quotient Q as the frequency and amortizing the counting error caused by the remainder R onto the first R consecutive synchronization pulses, a corrected synchronization clock pulse is obtained.

2. The apparatus according to claim 1, characterized in that, The high-frequency pulse generation and synchronization module is also used to generate a high-frequency synchronization pulse signal using the local clock, the currently latched quotient Q and remainder R, and the same correction method as when the rising edge of the reference pulse is valid, when the input reference pulse is not at its rising edge or when the capture valid flag is 0.

3. The apparatus according to claim 1 or 2, characterized in that, N=8。 4. A method for dynamic correction of high-frequency synchronization signals based on a clock reference, characterized in that, include: Noise filtering is applied to the input reference pulse; The reference pulse interval is counted by the clock output from the local crystal oscillator, and the count value is compared with the upper and lower thresholds of the set standard value. The comparison results are then statistically analyzed. When the count value is within the upper and lower thresholds of the set standard value for N consecutive times, it is determined that the reference pulse can be stably and effectively captured, and the capture validity flag is output as 1. Otherwise, the capture validity flag is output as 0 and the system waits for the reference pulse to meet the condition of stable and effective capture. Here, N is the set threshold. After the reference pulse can be stably and effectively captured, the quotient Q and remainder R are obtained by dividing the reference pulse interval count value after N cumulative averages by the target pulse frequency of the local synchronization clock. When the input capture valid flag is 1, the counting variable in the module is synchronized by forcibly resetting on the rising edge of the input reference pulse, and the quotient Q and remainder R of the new input are latched; then, the corrected synchronization clock pulse is obtained by using the quotient Q as the frequency and amortizing the counting error caused by the remainder R onto the first R consecutive synchronization pulses.

5. The method according to claim 4, characterized in that, Also includes: When not at the rising edge of the input reference pulse, or when the capture valid flag is 0, the high-frequency synchronization pulse signal is generated using the local clock, the currently latched quotient Q and remainder R values, and the same correction method as when the rising edge of the reference pulse is valid.

6. The method according to claim 4 or 5, characterized in that, N=8。

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