Capacitance detection circuit, detection method, detection device, and detection apparatus

Abstract

The application relates to the technical field of capacitance detection, in particular to a capacitance detection circuit, a detection method, a detection device and a detection equipment. The circuit comprises a reference voltage unit, a charging and discharging unit, a comparator, a logic control unit and a counter. The reference voltage unit is used for outputting a highest reference voltage, an intermediate reference voltage and a lowest reference voltage. The charging and discharging unit is used for charging or discharging a to-be-detected capacitance and is connected to the second input end of the comparator to provide a power supply voltage for the comparator. The comparator is used for outputting an oscillation control signal to the logic control unit according to the comparison result of the power supply voltage received by the second input end and the reference voltage of the first input end. The logic control unit is used for controlling the counting result of the counter according to the type of the received control signal. The counter is used for counting the counting value in a sampling time, and the counting in the sampling time comprises two counting stages.

Description

Technical Field

[0001] This application relates to the field of capacitance detection technology, specifically to a capacitance detection circuit, detection method, detection device, and detection equipment. Background Technology

[0002] Capacitive touchscreens and buttons are widely used in electronic products due to their excellent performance and long lifespan. Analog front-end circuits using oscillators are commonly used for capacitive touch detection because of their low cost and simplicity. When a user touches or approaches the capacitive sensing terminal, the capacitance value changes, causing a corresponding change in the count value. The change in count value is obtained by subtracting the count value from the previous sampling time. This change is then compared to a preset threshold to further determine the touch action.

[0003] However, in existing capacitance detection schemes, the counting element of the capacitance detection component only counts the oscillation period of the oscillation signal output by the oscillator during the sampling time, without processing and counting the residual voltage of the capacitor under test. Therefore, the accuracy of the count value is insufficient, and consequently, the accuracy of the capacitance detection element for the capacitor under test is also reduced. Therefore, how to improve the accuracy of capacitance detection is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a capacitance detection circuit, detection method, detection device, and detection equipment, which quantifies the residual voltage at the capacitance detection terminal, thereby improving the accuracy of the count value change and thus improving the accuracy of capacitance detection.

[0005] In a first aspect, embodiments of this application provide a capacitance detection circuit applied to a capacitance detection device. The circuit includes: a reference voltage unit, a charging / discharging unit, a comparator, a logic control unit, and a counter. The reference voltage unit outputs a maximum reference voltage, an intermediate reference voltage, and a minimum reference voltage. The charging / discharging unit charges or discharges the capacitor under test and is connected to the second input terminal of the comparator to provide a power supply voltage to the comparator. The comparator determines the type of control signal output to the logic control unit based on the comparison result between the power supply voltage received at the second input terminal and the reference voltage at the first input terminal. The logic control unit controls the counting result of the counter based on the type of the received control signal. The counter is used to count the count value within a sampling time, which includes two counting phases.

[0006] It is understandable that when a user performs a touch operation, the value of the capacitance Cx under test at the capacitance detection terminal changes. Correspondingly, the voltage at the capacitance detection terminal also changes. The comparator outputs an oscillation control signal based on the voltage at the capacitance detection terminal. During the sampling time, in the first counting stage, the counter counts the rising and falling edges of the output oscillation control signal. In the second counting stage, one or more intermediate reference voltages are set and compared with the residual voltage to further quantify the residual voltage, improve the accuracy of the count value, and consequently improve the accuracy of the capacitance detection.

[0007] In one possible implementation of the first aspect above, the circuit further includes: the control signal output by the comparator to the logic control unit includes: a first control signal, a second control signal, and a third control signal; wherein the first control signal is used to control the charging and discharging unit to charge the capacitor under test; the second control signal is used to control the charging and discharging unit to discharge the capacitor under test; and the third control signal is used to control the switching between the charging and discharging unit and the capacitor under test.

[0008] In one possible implementation of the first aspect described above, the circuit further includes: the comparator performing two counting phases during the statistical sampling time for: a first counting phase, for determining to output a first toggle signal to the logic control unit based on a comparison result that the supply voltage of the second input terminal is greater than or equal to the highest reference voltage of the first input terminal, the first toggle signal being used to indicate that the oscillation control signal output by the logic control unit is switched from a first control signal to an inverted second control signal, wherein the first control signal is a high-level signal and the second control signal is a low-level signal; and for determining to output a second toggle signal to the logic control unit based on a comparison result that the supply voltage of the second input terminal is less than or equal to the lowest reference voltage of the first input terminal, the second toggle signal being used to indicate that the oscillation control signal output by the logic control unit is switched from a second control signal to an inverted first control signal; and a second counting phase, for determining the magnitude relationship between the supply voltage of the second input terminal and the intermediate reference voltage of the first input terminal based on a comparison result that the supply voltage of the second input terminal is compared with the intermediate reference voltage of the first input terminal, and the logic control unit determining the counting result of the counter in the second counting phase based on the type of the last counted oscillation control signal in the first counting phase and the comparison result of the second counting phase.

[0009] In one possible implementation of the first aspect described above, the circuit further includes the following steps: when the oscillation control signal of the last count in the first counting stage is a first control signal, the logic control unit determines the counter's counting result as the first counting result based on a comparison result showing that the intermediate reference voltage is less than the supply voltage of the second input terminal; the logic control unit determines the counter's counting result as the second counting result based on a comparison result showing that the intermediate reference voltage is greater than the supply voltage of the second input terminal; when the oscillation control signal of the last count in the first counting stage is a second control signal, the logic control unit determines the counter's counting result as the first counting result based on a comparison result showing that the intermediate reference voltage is greater than the supply voltage of the second input terminal; the logic control unit determines the counter's counting result as the second counting result based on a comparison result showing that the intermediate reference voltage is less than the supply voltage of the second input terminal.

[0010] In one possible implementation of the first aspect above, the method further includes: the counting result is a binary count; wherein the first counting result is count 1 and the second counting result is count 0.

[0011] In one possible implementation of the first aspect above, the circuit further includes: a first counting stage in which the counter counts the oscillation control signal output by the logic control unit, wherein the counting content includes the rising edge and falling edge of the oscillation control signal; and a second counting stage in which the counter determines the counting result of the counter based on the control result of the counter output by the logic control unit.

[0012] In one possible implementation of the first aspect above, the circuit further includes: a data processing unit for processing the count value of the counter to obtain the change in the count value; wherein the change in the count value is the difference between a first count value and a second count value counted by the counter within the same sampling time, wherein the first count value is collected during the period when the user touches the capacitor under test, and the second count value is collected during the period when the user does not touch the capacitor under test.

[0013] In one possible implementation of the first aspect above, the circuit further includes: the accuracy of the change in the count value is positively correlated with the number of intermediate reference voltages, where there can be n intermediate reference voltages, and n is a natural number greater than zero.

[0014] It is understandable that the more intermediate reference voltages there are, the higher the quantification accuracy of the residual voltage at the capacitor detection terminal, the higher the accuracy of the change in the count value, and the higher the corresponding capacitor detection accuracy.

[0015] Secondly, embodiments of this application provide a capacitance detection method.

[0016] In one possible implementation of the second aspect above, the method further includes: generating a reference voltage based on a reference voltage unit, the reference voltage including at least a maximum reference voltage, an intermediate reference voltage, and a minimum reference voltage; determining a count value for a first counting stage based on the maximum reference voltage and the minimum reference voltage; determining a counting result for a second counting stage based on the count value for the first counting stage and the intermediate reference voltage; and counting the count value within the sampling time.

[0017] In one possible implementation of the second aspect above, the method further includes: determining the detection result of the capacitor under test based on the change in the count value, wherein the change in the count value is the degree of change in the count value caused by the user's touch, and the accuracy of the change in the count value is related to the number of intermediate reference voltages.

[0018] In one possible implementation of the second aspect above, the method further includes: the change in the count value is the difference between a first count value and a second count value counted by the counter within the same sampling time, wherein the first count value is collected during the period when the user touches the capacitor under test, and the second count value is collected during the period when the user does not touch the capacitor under test.

[0019] In one possible implementation of the second aspect above, the method further includes: the accuracy of the change in the count value is positively correlated with the number of intermediate reference voltages.

[0020] It is understood that when the change in the aforementioned count value exceeds a preset change threshold, a user touch operation is determined. In some embodiments, the user's touch operation may be further determined as a click or long press based on the change in the count value, and no limitation is made here.

[0021] Thirdly, embodiments of this application provide a capacitance detection device applicable to the aforementioned capacitance detection circuit, wherein the capacitance detection circuit is used to implement the capacitance detection method.

[0022] Fourthly, this application provides a capacitance detection device, characterized in that it includes: a register for storing various instructions or configuration information, wherein the instructions are used to control the sampling time of the capacitance detection circuit for the number of oscillation cycles; and a processor, which is one of the processors of an integrated circuit, for executing the above-described capacitance detection method. Attached Figure Description

[0023] Figure 1 This embodiment shows a schematic diagram of a conventional capacitance detection circuit structure.

[0024] Figure 2 This embodiment shows a schematic diagram of a capacitance detection circuit structure that can improve detection accuracy.

[0025] Figure 3This embodiment illustrates a flowchart of a capacitance detection method.

[0026] Figure 4 This embodiment illustrates a timing diagram of a capacitance detection circuit designed to improve detection accuracy.

[0027] Figure 5 This embodiment illustrates another schematic diagram of a capacitance detection circuit structure that can improve detection accuracy.

[0028] Figure 6 This embodiment illustrates a flowchart of a capacitance detection method.

[0029] Figure 7 This embodiment illustrates another circuit timing diagram for improving detection accuracy. Detailed Implementation

[0030] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.

[0031] As above, Figure 1 This embodiment illustrates a schematic diagram of a conventional capacitance detection circuit structure, such as... Figure 1 As shown, in existing capacitance detection schemes, during the oscillation scanning cycle, a counter counts the rising edges of the output oscillation signal to calculate the total sampled value ΔN. When ΔN exceeds a preset touch threshold, a touch action is determined. However, because the parasitic capacitance at the capacitance detection end is generally large, if only the rising edges of the oscillation signal output by the oscillator are counted, the accuracy of capacitance detection will decrease.

[0032] The oscillation period T in the existing capacitance detection scheme:

[0033]

[0034] Where k′ is a factor related to the parameters of the circuit components, Cx represents the capacitance value of the capacitor under test; ΔtLH represents the charging time, ΔtHL represents the discharging time; R2, R3, and R4 are all... Figure 1 The circuit shown has an adjustable resistor used to output the reference voltage.

[0035] Sampling time T mear The counter records the count value N:

[0036]

[0037] Therefore, the capacitance to be measured increases before and after the touch, resulting in a change in the count value:

[0038]

[0039] As can be seen from the above formula, the sampling technology in the existing scheme only counts the number of square waves output by the oscillator within the sampling time Tmear, that is, the number of rising edges of the oscillation signal. The count value is small and the count value is an integer. Therefore, the accuracy of the capacitor under test of the capacitance detection element is not high.

[0040] To address the aforementioned problems, this application provides a high-precision capacitance detection method applied to a capacitance detection device. Specifically, this method introduces multiple intermediate reference voltages Vrn between the highest reference voltage VTH and the lowest reference voltage VTL of the reference voltage module in the circuit structure. A comparator compares the intermediate reference voltages with the residual voltage to determine the range of the residual voltage, further quantizing the residual voltage at the oscillator's detection pin, thereby improving the capacitance detection count value.

[0041] It is understandable that when a user performs a touch operation, the value of the capacitance Cx under test at the capacitance detection terminal changes. Correspondingly, the voltage at the capacitance detection terminal also changes. The comparator outputs an oscillation control signal based on the voltage at the capacitance detection terminal. During the sampling time, in the first counting stage, the counter counts the rising and falling edges of the output oscillation control signal. In the second counting stage, one or more intermediate reference voltages are set and compared with the residual voltage to further quantify the residual voltage, improve the accuracy of the count value change, and thus improve the accuracy of capacitance detection.

[0042] The specific technical solutions of this application for improving the accuracy of capacitance detection will be described in detail below with reference to Embodiment 1.

[0043] Example 1

[0044] Figure 2 This embodiment shows a schematic diagram of a capacitance detection circuit structure that can improve detection accuracy.

[0045] It is understood that this embodiment combines Figure 1Let's take adding an intermediate reference voltage Vr1 between the highest reference voltage VTH and the lowest reference voltage VTL as an example. In reality, there can be n intermediate reference voltages, for example, intermediate reference voltage Vr1, intermediate reference voltage Vr2, intermediate reference voltage Vr3, intermediate reference voltage Vr4... and intermediate reference voltage Vrn. The larger the value of n for the intermediate reference voltage Vrn, the more accurate the quantization of the residual voltage VA. When there are multiple intermediate reference voltage levels, quantizing the residual voltage VA requires turning on the switches controlling the intermediate reference voltages one by one and comparing each residual voltage VA with the intermediate reference voltage to further quantize the reference voltage.

[0046] like Figure 2 As shown, the capacitance detection circuit of this embodiment includes a reference voltage module 110, an oscillation module 120, a counting module 130, and a capacitance detection terminal. In other embodiments, the capacitance detection circuit further includes a data processing unit connected to the counting module for processing the count values ​​collected by the counting module. The reference voltage module 110 outputs a reference voltage; the oscillation module 120 outputs an oscillation signal that varies with the size of the capacitance under test; the counting module 130 counts the oscillation signal; the capacitance detection terminal includes its own capacitance and parasitic capacitance. In this embodiment, the capacitance under test Cx includes the inherent capacitance of the capacitance detection terminal itself and the internal parasitic capacitance of the capacitance detection terminal. In other embodiments, the capacitance under test Cx also includes external parasitic capacitance between the capacitance detection terminal and ground.

[0047] refer to Figure 2 The reference voltage module 110 is connected to the input terminal of the oscillation module 120, and the counting module 130 is connected to the output terminal of the oscillation module.

[0048] The aforementioned reference voltage module 110 includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5 connected in series between the voltage power supply and ground. The connection between the second resistor R2 and the third resistor R3 serves as the output terminal of the first reference voltage VTH, used to output the highest reference voltage VTH; the connection between the third resistor R3 and the fourth resistor R4 serves as the output terminal of the intermediate reference voltage Vr1; and the connection between the fourth resistor R4 and the fifth resistor R5 serves as the output terminal of the lowest reference voltage VTL.

[0049] The second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 mentioned above serve as voltage divider resistors. The second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 can be composed of one or more voltage resistors connected in parallel and / or in series, without any restrictions.

[0050] It is understood that the aforementioned reference voltage module 110 also includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. It is understood that one end of the first capacitor C1 is grounded, and the other end is connected to the output terminal of the lowest reference voltage VTL; one end of the second capacitor C2 is grounded, and the other end is connected to the output terminal of the intermediate reference voltage Vr1; one end of the third capacitor C3 is grounded, and the other end is connected to the output terminal of the highest reference voltage VTH. The first capacitor C1, the second capacitor C2, and the third capacitor C3, along with the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5, form a low-pass filter to filter out high-frequency interference from the output highest reference voltage VTH, the lowest reference voltage VTL, and the intermediate reference voltage Vr1.

[0051] Continue to refer to Figure 2 The oscillation module 120 includes a comparator 121, a logic control unit 122, and a charging / discharging unit 123.

[0052] Comparator 121 has its first input connected to reference voltage module 110 and its second input connected to capacitor detection. It is used to output a corresponding output signal DOUT based on changes in the input voltage. The first input is positive, and the second input is negative.

[0053] The logic control unit 122 is connected to the output of comparator 121 and is used to output a stable oscillation control signal based on the output signal DOUT of comparator 121. For example, the type of oscillation control signal to be output is determined based on the comparison result of the reference voltage at the first input terminal and the input voltage at the second input terminal of comparator 121. The oscillation control signal includes a first control signal DOH, a second control signal DOL, and a third control signal D01.

[0054] It can be understood that the first control signal DOH is used to control the on / off state of the first switch DOH; the second control signal DOL is used to control the on / off state of the second switch DOL; and the third control signal D01 controls the on / off state of the third switch D01.

[0055] The charging / discharging unit 123 includes a first resistor R1, which forms positive feedback charging / discharging control between the output and second input terminals of the comparator 121, causing the comparator 121 to oscillate between the highest reference voltage VTH and the lowest reference voltage VTL. In this embodiment, the first control signal DOH output by the oscillation control signal 122 is in phase with the signal output by the comparator 121. Further, the charging / discharging unit 123 is connected between the output terminal of the first control signal and the second input terminal of the comparator 121. When DOUT is high, the capacitor Cx under test is charged; when DOUT is low, the capacitor Cx under test is discharged.

[0056] In addition, the charging and discharging unit 123 also includes a fourth switch SW, which is used to disconnect the charging and discharging unit 123 from the capacitor detection terminal when the oscillation ends and EN=0, and compare the participating voltage VA on the capacitor Cx under test with the intermediate reference voltage V01 to further quantify the residual voltage and improve the accuracy of capacitor detection.

[0057] Further reference Figure 2 The aforementioned counting module 130 includes a counter 131 for counting the output signal DOUT within the sampling time. In the first counting phase, relative to... Figure 1 The capacitance detection scheme shown in this embodiment counts not only the rising edge of the output signal DOUT but also the falling edge, increasing the sampling count value N within the scan cycle. Simultaneously, in the second counting stage, the residual voltage VA is compared with the intermediate reference voltage Vrn, improving the accuracy of the count value ΔN.

[0058] The sampling time mentioned above can be controlled by the enable signal EN output by the chip or digital circuit connected to the capacitance detection circuit. For example, in the control process: the time when the output enable signal EN is high is equal to the sampling time, and the time when the output enable signal EN is low is equal to the non-sampling time.

[0059] In this embodiment, the capacitance detection circuit further includes a function where, when the output enable signal EN is high, the output signal DOUT is high. At this time, the output oscillation control signal is the first control signal DOH, the first switch DOH is turned on, and the second switch DOL and the third switch D01 are turned off, charging the capacitor Cx under test. When the voltage across the capacitor Cx rises from VTL to VTH, the square wave signal output by comparator 121 flips. At this time, the second switch DOL is turned on, and the first switch DOH and the third switch D01 are turned off, discharging the capacitor Cx under test. When the voltage drops to VTL, the square wave signal output by comparator 121 flips again, repeating this cycle, causing the voltage across the capacitor Cx under test to oscillate between VTL and VTH. Comparator 121 outputs a square wave signal, and logic control unit 122 outputs the first control signal DOH, which is in phase with the output signal DOUT of comparator 121. Counter 131 counts the rising and falling edges of the output signal DOUT.

[0060] When the output enable signal EN is low, there is a residual voltage VA across the capacitor under test Cx. In order to improve the accuracy of capacitance detection, this embodiment provides a method for quantifying the residual voltage. When EN is low, the residual voltage VA exists across the capacitor under test Cx, at this time the oscillation control signal is the third control signal Vr1, the first switch DOH, the second switch DOL and the fourth switch SW are turned off, and the third switch D01 is turned on. The comparator 121 compares the residual voltage VA with the intermediate reference voltage Vr1 to determine the magnitude relationship between the residual voltage VA and the intermediate reference voltage Vr1, and then sends the comparison result to the logic control unit 122, which outputs the relationship between the residual voltage VA and the intermediate reference voltage Vr1.

[0061] It can be understood that in this embodiment, when EN is low, the capacitor under test Cx is exactly in the discharge falling state. In fact, when EN is low, the capacitor under test Cx may be in any state of charging and discharging, and the comparison principle in the charging state is the same as that in the discharge falling state, which will not be repeated here. It can be understood that in other embodiments, there may be one or more intermediate reference voltages, and the more intermediate reference voltages, the higher the quantization accuracy of the residual voltage VA, which is not limited herein.

[0062] It can be understood that after EN goes low, the fourth switch SW is turned off, and then the third switch D01 is turned on to compare the residual voltage VA with the intermediate reference voltage Vr1. Assume that DOUT_0 represents the least significant bit (i.e., bit0) of the count value. When the third control signal DO1 is high, the intermediate reference voltage Vr1 is compared with the voltage VA. If Vr1>VA, V01 and the oscillation output signal DOUT output high during the voltage comparison period; if Vr1<VA, V01 and the oscillation output signal DOUT output low during the voltage comparison period. In addition, whether bit0 is 0 or 1 is judged according to the parity of the total number of rising edges and falling edges of the comparator output signal DOUT when EN is high.

[0063] even (DOUT_0)bit0 = 1 (DOUT_0)bit0 = 0 odd number (DOUT_0)bit0 = 0 (DOUT_0)bit0 = 1

[0064] Table 1

[0065] It can be understood that when EN is high, if the number of rising and falling edges of DOUT is even, the residual voltage VA is on the discharge falling edge; if the number of rising and falling edges of DOUT is odd, the residual voltage VA is on the charging rising edge. When the residual voltage VA is on the discharge falling edge, if Vr1>VA, it can be known that (DOUT_0)bit0=1; if Vr1<VA, it can be known that (DOUT_0)bit0=0. When the residual voltage VA is on the rising edge, if Vr1>VA, it can be known that (DOUT_0)bit0=0; if Vr1<VA, it can be known that (DOUT_0)bit0=1. Therefore, according to the above rules, the magnitude relationship between the residual voltage VA and the intermediate reference voltage Vr1 is obtained through the comparator, and then the logic judgment of the logic control unit 122 is performed to determine the counting result of the counter 122. When (DOUT_0)bit0=1, the counter 122 counts 1, and when (DOUT_0)bit0=0, the counter 122 counts 0. Further, according to the counting result of the counter 122, the voltage interval where the residual voltage is located is determined and obtained.

[0066] It can be understood that when EN is low, the capacitor Cx is checked to have residual voltage VA left. At this time, the capacitor Cx to be measured may be in a discharge state or a charging state. Generally, the residual voltage VA may be between the rising edge VTL and Vrn, between Vrn and VTH, between VTH and Vrn, and between Vrn and VTL. Since the comparison principles are similar, they will not be described one by one here.

[0067] Based on the above Figure 2 capacitance detection circuit shown, the specific implementation process of a capacitance detection method provided in the embodiments of the present application will be described below in combination with Figure 3 the process shown.

[0068] As shown in Figure 3 the figure, this process includes the following steps:

[0069] 301: Based on the sampling time, the capacitance detection circuit starts to work and generates an oscillation control signal.

[0070] Exemplarily, the capacitance detection circuit starts to work based on the preset sampling time and generates an oscillation control signal.

[0071] It is understandable that during the capacitance detection process, the output enable signal EN has two states. When EN is high, the oscillation control unit is enabled, and the detection circuit begins capacitance detection. Changes in the capacitance value cause changes in the charging and discharging cycle at the capacitance detection terminal, resulting in a corresponding change in the voltage cycle at the capacitance detection terminal. The logic control unit then outputs an oscillation control signal based on the comparator output signal. This oscillation control signal includes a first control signal DOH, a second control signal DOL, and a third control signal Vr1.

[0072] 302: The capacitor detection circuit determines the generated oscillation control signal as the first control signal and charges the capacitor under test.

[0073] For example, if the oscillation control signal output by the capacitance detection circuit is a high-level signal, it can be determined that the control signal is the control signal that triggers the charging of the capacitor under test. In this embodiment, the control signal can be denoted as the first control signal DOH, which is used to control the first switch DOH to turn on, outputting the highest reference voltage VTH to charge the capacitor under test. At this time, in response to the first control signal DOH, the capacitor under test is charged. The first switch DOH is turned on, and the second switch DOL and the third switch D01 are turned off, charging the capacitor under test. When the voltage across the capacitor under test rises from VTL to VTH, the square wave signal output by the comparator flips.

[0074] 303: The capacitor detection circuit determines that the generated oscillation control signal is the second control signal and discharges the capacitor under test.

[0075] For example, if the oscillation control signal output by the capacitance detection circuit is a high-level signal, it can be determined that the control signal is the control signal that triggers the charging of the capacitor under test. In this embodiment, the control signal can be denoted as the first control signal DOH, which is used to control the charging of the capacitor under test. At this time, when the voltage across the capacitor under test rises from VTL to VTH, the square wave signal output by the comparator flips. At this time, the second switch DOL is turned on, and the first switch DOH and the third switch D01 are turned off, discharging the capacitor under test. When the discharge reaches VTL, the square wave signal output by the comparator 121 flips again.

[0076] 304: Count the output oscillation control signal to obtain the count value of the oscillation control signal at each time.

[0077] Based on steps 302 and 303 above, the voltage across the capacitor under test oscillates between VTH and VTL, resulting in a corresponding output signal DOUT from the comparator. A counter then counts the output signal DOUT, including both the rising and falling edges of the output signal DOUT. In other embodiments, the first control signal DOH and the second control signal DOL can be used instead; this is not a limitation.

[0078] It is understood that in this embodiment, the counter counts not only the rising edge of the output signal DOUT, but also the falling edge of the output signal DOUT, which increases the count value and improves the detection accuracy.

[0079] 305: The capacitor detection circuit determines that the generated oscillation control signal is the third control signal, quantizes the residual voltage, and obtains the count value corresponding to the residual voltage.

[0080] For example, when EN is low, there is a residual voltage across the capacitor under test. At this time, the oscillation control signal output is the third control signal Vr1, the first switch DOH, the second switch DOL, and the fourth switch SW are open, and the third switch D01 is turned on. The residual voltage is compared with the intermediate reference voltage Vr1 by a comparator, and the comparison result is sent to the logic control unit. The logic control unit outputs the relationship between the residual voltage VA and the intermediate reference voltage Vr1, further quantifying the residual voltage.

[0081] It is understandable that one or more intermediate reference voltages can be set to quantify the residual voltage. By determining the relationship between the intermediate reference voltage and the residual voltage, and the count value obtained in step 305, it can be determined whether the residual voltage is in the charging rising edge stage or the discharging falling edge stage. This determines whether to count the oscillation control signal corresponding to the residual voltage, thereby improving the accuracy of the overall count value and correspondingly improving the accuracy of the capacitor under test in the capacitance detection element. The more intermediate reference voltages there are, the higher the accuracy of the count value change ΔN, and the higher the accuracy of capacitance detection.

[0082] It is understood that when a single user touches or approaches the capacitance detection terminal, the capacitance value of the capacitance detection terminal changes, causing a corresponding change in the count value. In other embodiments, the capacitance detection circuit of this embodiment further includes a count value processing stage, used to subtract the count value of the current sampling time from the count value of the previous sampling time to obtain the count value change ΔN, and then compare it with a preset threshold to further determine the touch action. When ΔN is greater than the threshold, the user's touch operation is determined. In some embodiments, the type of touch operation can be a click, a long press, etc.

[0083] Figure 4The timing diagram for a high-precision capacitance detection is shown under the condition of discharge decrease.

[0084] It is understandable that a complete capacitance detection includes three stages. The first stage is the detection preparation stage, during which EN is low, the oscillation module 120 does not work, and the comparator 121 is turned on to establish a stable output.

[0085] The second stage is the capacitance detection stage. At this time, EN is high, the oscillation module 120 works, and outputs a stable output signal DOUT. The counter 131 counts the rising and falling edges of the output signal DOUT.

[0086] The third stage is the residual voltage processing stage. During this stage, EN is low, and a residual voltage VA remains across the capacitor Cx under test. To improve the accuracy of capacitor detection, the residual voltage VA is compared with the intermediate reference voltage Vrn in this stage to further quantify the residual voltage VA. Counter 131 then counts the final value.

[0087] Example 2

[0088] Figure 5 This embodiment illustrates another structural diagram for high-precision capacitance detection.

[0089] The capacitance detection circuit of this embodiment includes a reference voltage module 210, an oscillation module 220, a counting module 230, and a capacitance detection terminal. The working principles of the reference voltage module 210, the counter module 230, the capacitance detection module, and the charging / discharging unit 221 can be found in the descriptions of the reference voltage module 110, the counting module 130, and the capacitance detection module described above, and will not be repeated here.

[0090] The oscillation module 220 includes a charge / discharge unit 221, comparators 222 and 223, and a logic control unit 224.

[0091] When EN is high, the comparator in operation is comparator 222. The working principle of each module is as follows: Figure 2 The working principles of each module are similar; please refer to the above for details. Figure 2 The working principle is not described in detail here.

[0092] The following is combined with Figure 5This embodiment describes the operating state of each module when the enable state ends, i.e., when EN is low. When EN is low, a residual voltage VA remains across the capacitor Cx under test. To improve the accuracy of capacitor detection, the residual voltage VA is further quantified. It can be understood that when the enable state ends, the seventh switch SA is turned on, and the eighth switch SB is turned off. Specifically, when the seventh switch SA is turned on, it outputs an intermediate reference voltage Vr2, which is connected to the first input terminal of comparator 223; the eighth switch is turned off, ensuring that the charging / discharging unit 221 is disconnected from the capacitor Cx under test, reducing the influence of the charging / discharging unit 221 on the residual voltage VA. Comparator 223 compares the output intermediate reference voltage Vr2 with the residual voltage VA through the logic control unit 224 to further quantify the residual voltage. The specific comparison process is described above. Figure 2 The detailed explanation is omitted here.

[0093] Understandable. Figure 5 This only illustrates the case with only one intermediate reference voltage level. When the circuit has multiple intermediate reference voltage levels, the number of comparators should be increased accordingly. This way, during comparison, it is not necessary to turn on the corresponding control switches one by one before comparison. At the end of the enable process, multiple intermediate reference voltages Vrn can be compared with the residual voltage VA at once, greatly reducing the comparison time, shortening the capacitor detection time, and improving the user experience.

[0094] Based on the above Figure 5 The capacitance detection circuit shown below, in conjunction with Figure 6 The flowchart shown illustrates the specific implementation process of a capacitance detection method provided in the embodiments of this application.

[0095] like Figure 6 As shown, the process includes the following steps:

[0096] 601: Based on the sampling time, the capacitance detection circuit starts working and generates an oscillation control signal.

[0097] The difference from step 301 above is that in this step, the oscillation module is equipped with two or more comparators. When EN is high, the comparator whose first input is connected to the highest reference voltage VTH and the lowest reference voltage VTL operates. Its working principle is the same as in step 302 above and will not be repeated here. When N is low, the comparator whose first input is connected to the intermediate reference voltage starts working, used to further quantize the intermediate reference voltage Vr1 and the residual voltage VA, and further quantize the residual voltage VA.

[0098] 602: The capacitor detection circuit determines the generated oscillation control signal as the first control signal and charges the capacitor under test.

[0099] 603; The capacitor detection circuit determines the generated oscillation control signal as the second control signal and discharges the capacitor under test.

[0100] 604: Count the output oscillation control signal to obtain the count value of the oscillation control signal at each moment.

[0101] It is understood that steps 602 to 604 refer to the relevant descriptions in steps 302 to 304 above, and will not be repeated here.

[0102] 605: The capacitor detection circuit determines that the generated oscillation control signal is the third control signal, quantizes the residual voltage, and obtains the count value corresponding to the residual voltage.

[0103] For example, when EN is low, there is a residual voltage across the capacitor under test. At this time, the oscillation control signal output is the third control signal Vr1, the first switch DOH, the second switch DOL, and the fourth switch SW are open, and the third switch D01 is turned on. The residual voltage is compared with the intermediate reference voltage Vr1 through a comparator connected to the first input terminal, and the comparison result is sent to the logic control unit. The logic control unit outputs the relationship between the residual voltage VA and the intermediate reference voltage Vr1, further quantifying the residual voltage.

[0104] It is understood that the above describes setting an intermediate reference voltage to quantize the residual voltage. In some embodiments, multiple intermediate reference voltages can be set, and the more intermediate reference voltages there are, the higher the accuracy of capacitance detection. The corresponding comparison period is also longer; therefore, this embodiment is suitable for scenarios with multiple intermediate reference voltage levels. When multiple intermediate reference voltage levels are set in the circuit, the number of comparators is increased accordingly. This way, during comparison, it is not necessary to individually turn on the corresponding control switches for comparison. At the end of the enable process, multiple intermediate reference voltages Vrn can be compared with the residual voltage VA at once, greatly reducing the comparison time, shortening the capacitance detection time, and improving the user experience. Determining the relationship between the intermediate reference voltage and the residual voltage, and determining the count value of the residual voltage, improves the overall accuracy of the count value, and correspondingly improves the accuracy of the capacitor under test in the capacitance detection element.

[0105] It is understood that when a single user touches or approaches the capacitance detection terminal, the capacitance value of the capacitance detection terminal changes, causing a corresponding change in the count value. In other embodiments, the capacitance detection circuit of this embodiment further includes a count value processing stage, used to subtract the count value of the current sampling time from the count value of the previous sampling time to obtain the count value change ΔN, and then compare it with a preset threshold to further determine the touch action. When ΔN is greater than the threshold, the user's touch operation is determined. In some embodiments, the type of touch operation can be a click, a long press, etc.

[0106] The changes in the measured capacitance Cx in steps 601 to 605 above can be referred to... Figure 7 The timing diagram shown is shown.

[0107] Figure 7 The timing diagram for another high-precision capacitance detection is shown under the condition of discharge decrease.

[0108] Specifically, the capacitance detection circuit also includes three stages. The first stage is the detection preparation stage, during which EN is low, the oscillation module 220 does not work, and the comparator 222 establishes a stable output.

[0109] The second stage is the capacitance detection stage. At this time, EN is high, the oscillation module 220 works, and outputs a stable output signal DOUT. The counter 231 counts the rising and falling edges of the output signal DOUT.

[0110] The third stage is the residual voltage VA processing stage. During this stage, EN is low, and a residual voltage VA remains across the capacitor Cx under test. To improve the accuracy of capacitor detection, the residual voltage VA is compared with the intermediate reference voltage Vrn. In this stage, the seventh switch SA is turned on, the eighth switch SB is turned off, and comparator 223 starts working. It compares the output intermediate reference voltage Vr2 with the residual voltage VA through logic control unit 224, further quantifying the residual voltage VA. Counter 231 then counts the final value.

[0111] In some optional embodiments, this application provides a capacitance detection device suitable for the above-described capacitance detection circuit, wherein the capacitance detection circuit is used to implement the capacitance detection method. Furthermore, this application also provides a capacitance detection apparatus, which includes: a register for storing various instructions or configuration information; instructions for controlling the sampling time of the capacitance detection circuit for the number of oscillation cycles; and a processor, one of the processors in an integrated circuit, for executing the above-described capacitance detection method.

[0112] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0113] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A capacitance detection circuit, characterized in that, include: The system includes a reference voltage unit, a charge / discharge unit, a comparator, a logic control unit, and a counter. The reference voltage unit is used to output the highest reference voltage, intermediate reference voltage, and lowest reference voltage. The charging and discharging unit is used to charge or discharge the capacitor under test. It is connected to the second input terminal of the comparator and provides power supply voltage to the comparator. A comparator, used in the first counting phase, compares the supply voltage received at the second input with the highest or lowest reference voltage at the first input and outputs the result to the logic control unit; and, Used in the second counting stage to output the comparison result between the residual voltage of the capacitor under test and the intermediate reference voltage to the logic control unit; The logic control unit is used to determine the type of output control signal based on the received comparison result, and to control the counting result of the counter. A counter is used to count the count value within a sampling time, and the sampling time includes the first counting stage and the second counting stage; wherein, the second counting stage controls the switch between the charging and discharging unit and the capacitor under test to be disconnected through a third control signal, so as to obtain the residual voltage of the capacitor under test; The logic control unit is used to determine the count value of the counter in the second counting stage based on the oscillation control signal type determined by the comparison result in the first counting stage and the comparison result in the second counting stage.

2. The capacitance detection circuit according to claim 1, characterized in that, The control signals output by the comparator to the logic control unit include: a first control signal, a second control signal, and the third control signal; Wherein, the first control signal is used to control the charging and discharging unit to charge the capacitor under test; the second control signal is used to control the charging and discharging unit to discharge the capacitor under test; and the third control signal is used to control the switching between the charging and discharging unit and the capacitor under test.

3. The capacitance detection circuit according to claim 1, characterized in that, The comparator is used during the first counting phase of the statistical sampling time to: Based on the comparison result that the supply voltage of the second input terminal is greater than or equal to the highest reference voltage of the first input terminal, a first flip signal is determined to be output to the logic control unit. The first flip signal is used to indicate that the oscillation control signal output by the logic control unit is switched from the first control signal to the inverted second control signal, wherein the first control signal is a high-level signal and the second control signal is a low-level signal. Based on the comparison result that the supply voltage of the second input terminal is less than or equal to the minimum reference voltage of the first input terminal, a second flip signal is determined to be output to the logic control unit. The second flip signal is used to indicate that the oscillation control signal output by the logic control unit is switched from the second control signal to the inverted first control signal.

4. The capacitance detection circuit according to claim 3, characterized in that, The logic control unit determines the counter's counting result in the second counting stage based on the type of the oscillation control signal of the last count in the first counting stage and the comparison result of the second counting stage, characterized in that: When the oscillation control signal of the last count in the first counting stage is the first control signal, the logic control unit determines the counting result of the counter as the first counting result based on the comparison result that the intermediate reference voltage is less than the supply voltage of the second input terminal; the logic control unit determines the counting result of the counter as the second counting result based on the comparison result that the intermediate reference voltage is greater than or equal to the supply voltage of the second input terminal. When the oscillation control signal of the last count in the first counting stage is the second control signal, the logic control unit determines the counting result of the counter as the first counting result based on the comparison result that the intermediate reference voltage is greater than or equal to the supply voltage of the second input terminal; the logic control unit determines the counting result of the counter as the second counting result based on the comparison result that the intermediate reference voltage is less than the supply voltage of the second input terminal.

5. The capacitance detection circuit according to claim 4, characterized in that, The counting result is a binary count value; The first counting result is count 1, and the second counting result is count 0.

6. The capacitance detection circuit according to claim 3 or 4, characterized in that, The counter is used for: In the first counting stage, the counter counts the oscillation control signal output by the logic control unit, wherein the counting content includes the rising edge and falling edge of the oscillation control signal; In the second counting stage, the counter determines the counting result based on the control result of the logic control unit outputting the counter.

7. The capacitance detection circuit according to claim 1, characterized in that, The capacitance detection circuit further includes: a data processing unit, used to process the counter's count value to obtain the change in the count value; The change in count value is the difference between the first count value and the second count value counted by the counter within the same sampling time. The first count value is collected during the period when the user touches the capacitor under test, and the second count value is collected during the period when the user does not touch the capacitor under test.

8. The capacitance detection circuit according to claim 7, characterized in that, The accuracy of the count is positively correlated with the number of intermediate reference voltages, where there are n intermediate reference voltages, and n is a natural number greater than zero.

9. A capacitance detection method, characterized in that, Applied to an apparatus or device including a capacitance detection circuit according to any one of claims 1 to 8, the method includes: A reference voltage is generated based on a reference voltage unit, and the reference voltage includes at least a maximum reference voltage, an intermediate reference voltage, and a minimum reference voltage. During the first counting phase within the statistical sampling time, the count value of the first counting phase is determined based on the comparison result between the power supply voltage received at the second input terminal and the highest or lowest reference voltage at the first input terminal. The count value of the second counting stage is determined based on the type of oscillation control signal determined by the comparison result in the first counting stage and the comparison result of the residual voltage of the capacitor under test and the intermediate reference voltage in the second counting stage. The statistical sampling time includes the second counting stage, and the residual voltage of the capacitor under test is the voltage obtained by controlling the switch between the charging and discharging unit and the capacitor under test to be disconnected by the third control signal in the second counting stage. The count values ​​within the statistical sampling time period include the count values ​​of the first counting phase and the count values ​​of the second counting phase.

10. The method according to claim 9, characterized in that, The method further includes: determining the detection result of the capacitor under test based on the change in count value, wherein the change in count value is the degree of change in count value caused by user touch, and the accuracy of the change in count value is related to the number of intermediate reference voltages.

11. The method according to claim 9, characterized in that, The change in count value is the difference between the first count value and the second count value counted by the counter within the same sampling time. The first count value is collected during the period when the user touches the capacitor under test, and the second count value is collected during the period when the user does not touch the capacitor under test.

12. The method according to claim 9, characterized in that, The accuracy of the count value and the change in count value is positively correlated with the number of intermediate reference voltages.

13. A capacitance detection device, characterized in that, The method includes the capacitance detection circuit of any one of claims 1 to 8, wherein the capacitance detection circuit is used to perform the capacitance detection method of any one of claims 9 to 12.

14. A capacitance detection device, characterized in that, include: The capacitance detection circuit according to any one of claims 1 to 8, and, Registers are used to store various instructions or configuration information. Instructions are used to control the sampling time of the capacitance detection circuit for the number of oscillation cycles, and configuration information is used to store the information. The processor is one of the processors in an integrated circuit, used to execute the capacitance detection method of any one of claims 9-12.

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