Bandgap reference circuit and low dropout linear regulator

Abstract

The embodiment of the present disclosure provides a band gap reference circuit and a low dropout linear voltage regulator. The band gap reference circuit comprises a band gap main circuit, a starting module and a pull-up module. The pull-up module is configured to generate a reference voltage rising with the rise of a power supply voltage by voltage pull-up when the power supply voltage generated by a power supply circuit is less than the normal working voltage of the band gap main circuit. The band gap main circuit is configured to generate a steady reference voltage according to a first bias current and the power supply voltage when the power supply voltage rises to the normal working voltage of the band gap main circuit. The starting module is configured to generate the first bias current, and the first bias current is also used to provide current bias for the power supply circuit. The problem that the existing band gap reference circuit needs to provide a rough reference voltage and a bias current by a rough band gap reference module when providing Vref for the power supply voltage is solved, thereby reducing the chip area and power consumption, and affecting the chip cost performance.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to bandgap reference circuits and low-dropout linear regulators. Background Technology

[0002] In analog chips, many circuit designs choose to use the bandgap reference voltage Vbg as the reference voltage Vref for the chip's internal power supply voltage VDD. This allows VDD to be regulated to a relatively stable and accurate voltage value. However, VDD is also the power supply for the Vbg module. Therefore, during system power-up, there will be a phase where VDD and Vbg simultaneously regulate each other.

[0003] To ensure proper chip startup, for some bandgap reference structures that only function correctly at around 3V VDD, an additional coarse bandgap reference module might be added. This module provides a coarse reference voltage and bias current to the VDD module before the Vbg module functions correctly, ensuring proper power-on of VDD. Afterward, the coarse reference voltage is switched to a precise Vbg. The specific implementation is as follows... Figure 1 As shown. Figure 1 The diagram shows a schematic of a low dropout regulator (LDO) circuit commonly used to generate the internal power supply VDD, where a negative feedback voltage Vfb is formed by a voltage divider of VDD. When VDD is lower than Vbg, the module ( Figure 2 When the required normal operating voltage is reached, a rough reference voltage Vbg0 and a bias current Ib0 are first generated by a rough bandgap reference circuit I1 that can operate under low supply voltage, ensuring that the VDD voltage rises first and simultaneously powering the Vbg module. When VDD reaches the normal operating voltage of Vbg, the logic signal Bgok = 1, and then the reference voltage Vref of VDD is switched to the Vbg module.

[0004] In practical applications, the inventors discovered that, Figure 1 The implementation of the coarse bandgap reference circuit I1 also requires multiple bipolar junction transistors (BJTs), which consumes a lot of chip area and power consumption, affecting chip cost and performance. Summary of the Invention

[0005] The embodiments described herein provide a bandgap reference circuit and a low-dropout linear regulator. In order to solve the problem that when the existing bandgap reference circuit provides Vref to the power supply voltage, it is necessary to first provide a coarse reference voltage and bias current by a coarse bandgap reference module, which results in large chip area and power consumption, and affects chip cost and performance.

[0006] According to a first aspect of this disclosure, a bandgap reference circuit is provided for providing a reference voltage and bias current to a power supply circuit. The bandgap reference circuit includes: a bandgap main circuit, a startup module, and a pull-up module. The pull-up module is configured to, when the power supply voltage generated by the power supply circuit is less than the normal operating voltage of the bandgap main circuit, pull up the voltage to cause the bandgap main circuit to generate a reference voltage that increases with the rise of the power supply voltage, and to stop operating after the power supply voltage rises to the normal operating voltage of the bandgap main circuit. The bandgap main circuit is configured to, when the power supply voltage rises to the normal operating voltage of the bandgap main circuit, generate a steady-state reference voltage based on a first bias current and the power supply voltage. The startup module is configured to generate the first bias current, which is also used to provide current bias to the power supply circuit.

[0007] Optionally, the pull-up module includes: a first transistor, which is a metal-oxide-semiconductor transistor, wherein the control electrode of the first transistor is coupled to a power supply voltage indication signal, the first electrode of the first transistor is coupled to the power supply voltage, the second electrode of the first transistor is coupled to the control electrode of the second transistor in the bandgap main circuit, the power supply voltage indication signal is used to indicate whether the power supply voltage reaches the normal operating voltage of the bandgap main circuit, and the second transistor is a transistor coupled to the reference voltage.

[0008] Optionally, the startup module includes: a startup voltage generation module, a startup loop module, and a current mirror module, wherein the startup voltage generation module is configured to generate a startup voltage; the startup loop module is configured to start according to the startup voltage and generate a second bias current after the operation is stable; and the current mirror module is configured to mirror the second bias current to obtain the first bias current.

[0009] Optionally, the startup voltage generating module includes: a third to an eighth transistor, wherein the third to an eighth transistor are metal-oxide-semiconductor transistors, wherein the control electrode of the third transistor is coupled to the second electrode of the third transistor and the control electrode of the fourth transistor, respectively, and the first electrode of the third transistor is coupled to a ground terminal; the first electrode of the fourth transistor is coupled to the power supply voltage, and the second electrode of the fourth transistor is coupled to the control electrodes of the fifth transistor, the sixth transistor, and the seventh transistor, respectively; the first electrode of the seventh transistor is coupled to the ground terminal, and the second electrode of the seventh transistor is coupled to the first electrode of the sixth transistor; the second electrode of the sixth transistor is coupled to the first electrode of the fifth transistor; the second electrode of the fifth transistor is coupled to the second electrode of the eighth transistor; the control electrode of the eighth transistor is coupled to a first voltage, the first electrode of the eighth transistor is coupled to the power supply voltage, and the second electrode of the eighth transistor also provides the startup voltage.

[0010] Optionally, the startup loop module includes: a ninth to thirteenth transistor and a first resistor. The ninth to thirteenth transistors are metal-oxide-semiconductor transistors. The control electrode of the ninth transistor is coupled to the startup voltage, the first electrode of the ninth transistor is coupled to the power supply voltage, and the second electrode of the ninth transistor is coupled to the second electrode of the tenth transistor, the second electrode of the twelfth transistor, and the control electrode of the thirteenth transistor, respectively. The first electrodes of the tenth transistor and the eleventh transistor are both coupled to the power supply voltage. The control electrode of the tenth transistor is coupled to the control electrode of the eleventh transistor, the second electrode of the eleventh transistor, and the second electrode of the thirteenth transistor, respectively. The first electrode of the thirteenth transistor is coupled to the control electrode of the twelfth transistor and one end of the first resistor. The other end of the first resistor is coupled to the ground terminal. The current flowing through the first resistor is the second bias current, and the voltage at the control electrode of the tenth transistor is the first voltage.

[0011] Optionally, the current mirror module includes: fourteenth to seventeenth transistors, which are metal-oxide-semiconductor transistors. The control electrode of the fourteenth transistor is coupled to the control electrode of the tenth transistor. The first electrode of the fourteenth transistor is coupled to the power supply voltage. The second electrode of the fourteenth transistor is coupled to the control electrode of the fifteenth transistor, the second electrode of the fifteenth transistor, and the control electrode of the sixteenth transistor, respectively. The first electrodes of the fifteenth transistor and the sixteenth transistor are both coupled to the ground terminal. The second electrode of the sixteenth transistor is coupled to the second electrode of the seventeenth transistor and the control electrode of the seventeenth transistor. The first electrode of the seventeenth transistor is coupled to the power supply voltage. The control electrode of the seventeenth transistor is also coupled to the bandgap main circuit. The current flowing through the seventeenth transistor is the second bias current.

[0012] Optionally, the bandgap main circuit includes: a second transistor, eighteenth to twenty-ninth transistors, second to sixth resistors, and a first current source, wherein the control electrode of the eighteenth transistor is coupled to the startup module, the first electrode of the eighteenth transistor is coupled to the power supply voltage, the second electrode of the eighteenth transistor is coupled to the control electrode of the nineteenth transistor and the second electrode of the nineteenth transistor, the first electrode of the nineteenth transistor is coupled to the second electrode of the twentieth transistor and the control electrode of the twentieth transistor, the first electrode of the twentieth transistor is coupled to the control electrode of the twentieth transistor and the second electrode of the twentieth transistor, and the first electrode of the twentieth transistor is coupled to the control electrode of the twentieth transistor and the second electrode of the twentieth transistor, and the first electrode of the twentieth transistor is coupled to ground; the first electrodes of the twenty-second and twenty-third transistors are both coupled to the power supply voltage, the control electrode of the twenty-second transistor is coupled to the control electrode of the twenty-third transistor, the second electrode of the twenty-second transistor is coupled to the first electrode of the twenty-fourth transistor, the second electrode of the twenty-third transistor is coupled to the first electrode of the twenty-fifth transistor, and the control electrode of the twenty-second transistor is also coupled to one end of the second resistor; the control electrode of the twenty-fourth transistor is coupled to the control electrode of the twenty-fifth transistor, the second electrode of the twenty-fourth transistor is coupled to one end of the second resistor, and the second electrode of the twenty-fifth transistor is coupled to the second current source. The control terminal of the 24th transistor is coupled to the second terminal of the 26th transistor, and the control terminal of the 26th transistor is also coupled to the other end of the second resistor; the control terminal of the 26th transistor is coupled to the control terminal of the 27th transistor and the control terminal of the 19th transistor, the first terminal of the 26th transistor is coupled to the second terminal of the 28th transistor, the first terminal of the 27th transistor is coupled to the second terminal of the 29th transistor, and the second terminal of the 27th transistor is coupled to the other end of the second resistor; the control terminal of the 28th transistor is coupled to the control terminal of the 29th transistor, the first terminal of the 28th transistor is coupled to one end of the third resistor and one end of the fourth resistor, the first terminal of the 29th transistor is coupled to the other end of the third resistor, and the other end of the fourth resistor is coupled to the ground terminal; the control terminal of the 26th transistor is coupled to the second terminal of the 26th transistor, the first terminal of the 26th transistor is coupled to one end of the fifth resistor and the control terminal of the 28th transistor, the second ... sixth resistor, the second terminal of the 28th transistor is coupled to one end of the first current source, the other end of the first current source is coupled to the power supply voltage, the other end of the fifth resistor is coupled to one end of the sixth resistor, the other end of the sixth resistor is coupled to the ground terminal, and the first terminal of the 26th transistor outputs the reference voltage.

[0013] According to a second aspect of this disclosure, a low-dropout linear regulator is provided, comprising an LDO main circuit, a judgment circuit, and a bandgap reference circuit as described in the first aspect, wherein the LDO main circuit is configured to control the generation of a power supply voltage according to a control loop composed of an error amplifier and a power transistor; the judgment circuit is configured to detect changes in the power supply voltage according to a hysteresis comparator and output a power supply voltage indication signal; and the bandgap reference circuit is configured to provide a reference voltage and a first bias current to the LDO main circuit according to the power supply voltage indication signal and the power supply voltage.

[0014] Optionally, the step of detecting the change in the power supply voltage according to the hysteresis comparator and outputting a power supply voltage indication signal includes: when the power supply voltage is less than the normal operating voltage of the bandgap reference circuit, the output power supply voltage indication signal is at a low level; when the power supply voltage is less than the normal operating voltage of the bandgap reference circuit, the output power supply voltage indication signal is at a high level.

[0015] Optionally, the LDO main circuit includes: the error amplifier, a power transistor, and resistors seven to nine, wherein the positive input terminal of the error amplifier is coupled to the feedback voltage, the negative input terminal of the error amplifier is coupled to the reference voltage output by the bandgap reference circuit, the output terminal of the error amplifier is coupled to the control terminal of the power transistor, and the bandgap reference circuit provides a first bias current to the error amplifier; the first terminal of the power transistor is coupled to the input voltage, and the second terminal of the power transistor is coupled to one end of the seventh resistor; the eighth and ninth resistors are connected in series and coupled between the other end of the seventh resistor and the ground terminal, the other end of the seventh resistor also outputs the feedback voltage, and the node between the eighth and ninth resistors is coupled to the input terminal of the hysteresis comparator; one end of the seventh resistor outputs the power supply voltage, and the power supply voltage also provides the operating voltage for the error amplifier and the hysteresis comparator.

[0016] In the bandgap reference circuit and low-dropout linear regulator embodiments of this disclosure, when the power supply voltage is lower than the normal operating voltage of the bandgap main circuit, the bandgap reference circuit forces the reference voltage in the bandgap main circuit to rise via a pull-up module, generating a reference voltage that rises with the power supply voltage. When the power supply voltage rises to the normal operating voltage of the bandgap main circuit, the pull-up module disconnects, and the bandgap main circuit generates a stable reference voltage. It can be seen that the reference voltage is provided by the bandgap reference circuit throughout the entire process, eliminating the need for a coarse bandgap reference circuit. Furthermore, the startup module in this embodiment can provide bias current for both the power supply voltage and the bandgap main circuit, further eliminating the need for a coarse bias current from the bandgap reference circuit. The pull-up module and startup module added in this embodiment are mainly implemented using metal-oxide-semiconductor (MOS) transistors. Compared to the coarse bandgap reference circuits in existing solutions that require multiple BJTs, the chip area occupied is very small, and the quiescent current is also very small, thus reducing chip cost and improving chip performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0018] Figure 1 A schematic diagram of an existing low-dropout linear regulator (LDO) circuit for generating an internal power supply VDD is shown.

[0019] Figure 2 An exemplary circuit diagram of an existing bandgap reference circuit is presented;

[0020] Figure 3 A schematic block diagram of a bandgap reference circuit according to an embodiment of the present disclosure is shown;

[0021] Figure 4 A schematic block diagram of another bandgap reference circuit according to an embodiment of the present disclosure is shown;

[0022] Figure 5 An exemplary circuit diagram of a startup module according to an embodiment of the present disclosure is shown;

[0023] Figure 6 An exemplary circuit diagram of a bandgap main circuit according to an embodiment of the present disclosure is shown;

[0024] Figure 7 An exemplary circuit diagram of a low-dropout linear regulator according to an embodiment of the present disclosure is shown;

[0025] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0028] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0029] To address the problem that existing bandgap reference circuits require a coarse bandgap reference module to provide a coarse reference voltage and bias current when supplying Vref to the power supply voltage, resulting in large chip area and power consumption, and affecting chip cost and performance, a new bandgap reference circuit is proposed. The bandgap reference circuit of this disclosure eliminates the need for a coarse bandgap reference module. Through pull-up modules and a startup module, it can provide reference voltage and bias current even at low voltage conditions. Furthermore, both the pull-up modules and the startup module are circuit structures composed of MOSFETs, resulting in a small footprint and low power consumption. The bandgap reference circuit of this disclosure will be described in detail below.

[0030] Figure 3A schematic block diagram of a bandgap reference circuit 100 according to an embodiment of the present disclosure is shown. The bandgap reference circuit 100 is used to provide a reference voltage and bias current to a power supply circuit. Figure 3 As shown, the bandgap reference circuit 100 includes: a startup module 110, a bandgap main circuit 120, and a pull-up module 130. Both the startup module 110 and the pull-up module 130 are composed of metal-oxide-semiconductor transistors (MOS transistors). Besides the bandgap reference circuit 100... Figure 3 The diagram also shows a power supply circuit 200, which generates a power supply voltage VDD, which in turn serves as the internal power supply for the bandgap reference circuit 100. The reference voltage Vbg and the first bias current Ib1 obtained by the bandgap reference circuit 100 provide a reference voltage and current bias for the power supply circuit 200.

[0031] The pull-up module 130 is coupled to the bandgap main circuit 120. The pull-up module 130 is configured to pull up the voltage to make the bandgap main circuit 120 generate a reference voltage Vbg that rises with the rise of the power supply voltage VDD when the power supply voltage VDD generated by the power supply circuit 200 is less than the normal operating voltage of the bandgap main circuit 120. The pull-up module 130 stops working after the power supply voltage VDD rises to the normal operating voltage of the bandgap main circuit 120.

[0032] The bandgap main circuit 120 is coupled to the pull-up module 130 and the startup module 110, respectively. The bandgap main circuit 120 is configured to generate a steady-state reference voltage Vbg based on the first bias current Ib1 and the power supply voltage VDD when the power supply voltage VDD rises to the normal operating voltage of the bandgap main circuit 120. When the power supply voltage VDD is less than the normal operating voltage of the bandgap main circuit 120, the bandgap main circuit 120 cannot operate.

[0033] The startup module 110 is configured to generate a first bias current Ib1, which is also used to provide current bias for the power supply circuit 200.

[0034] The working principle of the bandgap reference circuit 100 is as follows: From the initial state, the startup module 110 starts working, providing current bias to the power supply circuit 200 as early as possible. When the power supply voltage VDD has not reached the normal operating voltage of the bandgap main circuit 120, the pull-up module 130 forcibly pulls up the reference voltage Vbg in the bandgap main circuit 120, and the voltage increases with the power supply voltage VDD. Therefore, during this stage, the bandgap reference circuit 100 provides a reference voltage Vbg that increases with the power supply voltage VDD. When the power supply voltage VDD reaches the normal operating voltage of the bandgap main circuit 120, the pull-up module 130 is disconnected and stops working, and the bandgap main circuit 120 generates a stable reference voltage Vbg. Therefore, from this point onwards, the bandgap reference circuit 100 provides a stable reference voltage Vbg for the power supply voltage VDD. In addition, the bias current of the power supply circuit 200 and the bias current required by the bandgap main circuit 120 are provided by the startup module 110 throughout the entire process.

[0035] Preferably, the startup module 110 and the pull-up module 130 can be mainly implemented using metal-oxide-semiconductor transistors (MOS). The implementation of existing crude bandgap reference circuits requires multiple BJTs and other electronic components. Compared with MOS, BJTs have a much larger area. Therefore, the bandgap reference circuit of the present invention can greatly reduce the chip area, reduce the chip cost, and also have a very small quiescent current.

[0036] As can be seen from the above description, the bandgap reference circuit 100 of the embodiments of this disclosure, through the addition of pull-up module 130 and startup module 110, can provide reference voltage Vbg and bias current to power supply circuit 200 even under low voltage conditions (when the power supply voltage VDD does not reach the normal operating voltage of bandgap main circuit 120). Moreover, compared with the existing scheme of adding a coarse bandgap reference circuit, it can greatly reduce chip area and power consumption, and improve chip performance.

[0037] Furthermore, such as Figure 4 As shown, the pull-up module 130 includes: a first transistor Mp1, which is a P-type MOS transistor. The control electrode of the first transistor Mp1 is coupled to the power supply voltage indication signal VDD_OK, the first electrode of the first transistor Mp1 is coupled to the power supply voltage VDD, and the second electrode of the first transistor Mp1 is coupled to the control electrode of the second transistor Mn2 in the bandgap main circuit 120. Figure 4(Not shown in the diagram), the power supply voltage indication signal VDD_OK is used to indicate whether the power supply voltage VDD has reached the normal operating voltage of the bandgap main circuit 120. The second transistor Mn2 is a transistor coupled to the reference voltage Vbg. The working principle of the pull-up module 130 is as follows: When the power supply voltage indication signal VDD_OK is low, that is, when the power supply voltage VDD has not yet reached the normal operating voltage of the bandgap main circuit 120, the first transistor Mp1 is turned on, and the reference voltage Vbg is continuously pulled up through the second transistor Mn2, so that the reference voltage Vbg rises with the rise of the power supply voltage VDD; when the power supply voltage indication signal VDD_OK is high, that is, when the power supply voltage VDD reaches the normal operating voltage of the bandgap main circuit 120, the first transistor Mp1 is turned off, the pull-up stops, and the normal operation of the bandgap main circuit 120 is not affected, eventually generating a stable reference voltage Vbg.

[0038] Furthermore, such as Figure 4 As shown, the startup module 110 includes: a startup voltage generation module 111, a startup loop module 112, and a current mirror module 113. The startup voltage generation module 111 is configured to generate a startup voltage Vs; the startup loop module 112 is configured to start according to the startup voltage Vs and generate a second bias current Ib2 after the operation is stable; the current mirror module 113 is configured to mirror the second bias current Ib2 to obtain a first bias current Ib1.

[0039] Specifically, such as Figure 5As shown, an exemplary circuit for a startup module 110 is provided, wherein the startup voltage generation module 111 includes: a third to an eighth transistor, wherein the control electrode of the third transistor Mn3 is coupled to the second electrode of the third transistor Mn3 and the control electrode of the fourth transistor Mp4, respectively, and the first electrode of the third transistor Mn3 is coupled to the ground terminal VSS; the first electrode of the fourth transistor Mp4 is coupled to the power supply voltage VDD, and the second electrode of the fourth transistor Mp4 is coupled to the control electrodes of the fifth transistor Mn5, the sixth transistor Mn6, and the seventh transistor Mn7, respectively, and the first electrode of the seventh transistor Mn7 is coupled to the ground terminal VSS, the second electrode of the seventh transistor Mn7 is coupled to the first electrode of the sixth transistor Mn6, the second electrode of the sixth transistor Mn6 is coupled to the first electrode of the fifth transistor Mn5, and the second electrode of the fifth transistor Mn5 is coupled to the second electrode of the eighth transistor Mp8; the control electrode of the eighth transistor Mp8 is coupled to a first voltage Vbp1, the first electrode of the eighth transistor Mp8 is coupled to the power supply voltage VDD, and the second electrode of the eighth transistor Mp8 also provides a startup voltage Vs. The startup loop module 112 includes: a ninth to a thirteenth transistor and a first resistor R1. The control electrode of the ninth transistor Mp9 is coupled to the startup voltage Vs, the first electrode of the ninth transistor Mp9 is coupled to the power supply voltage VDD, and the second electrode of the ninth transistor Mp9 is coupled to the second electrode of the tenth transistor Mp10, the second electrode of the twelfth transistor Mn12, and the control electrode of the thirteenth transistor Mn13. The first electrodes of the tenth transistor Mp10 and the eleventh transistor Mp11 are both coupled to the power supply voltage VDD, and the control electrode of the tenth transistor Mp10 is coupled to the control electrode of the eleventh transistor Mp11, the second electrode of the eleventh transistor Mp11, and the second electrode of the thirteenth transistor Mn13. The first electrode of the thirteenth transistor Mn13 is coupled to the control electrode of the twelfth transistor Mn12 and one end of the first resistor R1. The other end of the first resistor R1 is coupled to the ground terminal VSS. The current flowing through the first resistor R1 is the second bias current Ib2, and the voltage at the control electrode of the tenth transistor Mp10 is the first voltage Vbp1.The current mirror module 113 includes: fourteenth to seventeenth transistors, wherein the control electrode of the fourteenth transistor Mp14 is coupled to the control electrode of the tenth transistor Mp10, the first electrode of the fourteenth transistor Mp14 is coupled to the power supply voltage VDD, and the second electrode of the fourteenth transistor Mp14 is coupled to the control electrodes of the fifteenth transistor Mn15, the second electrode of the fifteenth transistor Mn15, and the control electrode of the sixteenth transistor Mn16, respectively; the first electrodes of the fifteenth transistor Mn15 and the first electrodes of the sixteenth transistor Mn16 are both coupled to the ground terminal VSS, the second electrode of the sixteenth transistor Mn16 is coupled to the second electrode of the seventeenth transistor Mp17 and the control electrode of the seventeenth transistor Mp17; the first electrode of the seventeenth transistor Mp17 is coupled to the power supply voltage VDD, and the control electrode of the seventeenth transistor Mp17 is also coupled to the bandgap main circuit 120, and the current flowing through the seventeenth transistor Mp17 is the second bias current Ib2. It should be noted that Mn3, Mn5 to Mn7, Mn12, Mn13, Mn15, and Mn16 are all N-type MOSFETs, while Mp4, Mp8 to Mp11, Mp14, and Mp17 are all P-type MOSFETs.

[0040] Combination Figure 5 The working principle of the startup module 110 is explained as follows: The initial power-on state of the node voltage Vgn is 0. When VDD rises to VDD>Vthn+Vthp, Mp4 turns on, pulling up the node voltage VH, where Vthn and Vthp correspond to the threshold voltages of Mn3 and Mp4, respectively. The pull-up of VH causes Vs to decrease, and Vs, as the startup voltage, turns on Mp9. After Mp9 turns on, it pulls up the node voltage V2, and the startup loop module 112 starts working. Finally, the startup loop composed of Mn12, Mn13, Mp10, and Mp11 stabilizes the current at Ib2 = Vgsn / R1, where Vgsn is the gate-source voltage of Mn12. The node voltage Vbp1 generated at this time turns on Mp8 and turns off Mp9. Meanwhile, the second bias current Ib2 is mirrored by Mp11, Mp14 and Mn15, Mn16 to obtain the first bias current Ib1. Ib1 provides current bias for the bandgap main circuit 120 and also provides current bias for the power supply circuit 200.

[0041] Furthermore, such as Figure 6As shown, this disclosure provides an exemplary circuit diagram of a bandgap main circuit 120, which includes: a second transistor Mn2, an eighteenth to twenty-ninth transistor, a second to sixth resistor, and a first current source I1. The control electrode of the eighteenth transistor Mp18 is coupled to a startup module 110, specifically through Mp17 in the startup module 110. The node between Mp17 and Mp18 is V4. The first electrode of the eighteenth transistor Mp18 is coupled to the power supply voltage VDD. The second electrode of the eighteenth transistor Mp18 is coupled to the control electrode of the nineteenth transistor Mn19, the second electrode of the nineteenth transistor Mn19, and the first current source I1. The first terminal of transistor Mn19 is coupled to the second terminal and control terminal of transistor Mn20, respectively. The first terminal of transistor Mn20 is coupled to the control terminal and second terminal of transistor Q21, respectively. The first terminal of transistor Q21 is coupled to ground terminal VSS. The first terminals of transistors Mp22 and Mp23 are both coupled to the power supply voltage VDD. The control terminal of transistor Mp22 is coupled to the control terminal of transistor Mp23. The second terminal of transistor Mp22 is coupled to the first terminal of transistor Mp24. The second terminal of the twenty-third transistor Mp23 is coupled to the first terminal of the twenty-fifth transistor Mp25. The control terminal of the twenty-second transistor Mp22 is also coupled to one end of the second resistor R2. The control terminal of the twenty-fourth transistor Mp24 is coupled to the control terminal of the twenty-fifth transistor Mp25. The second terminal of the twenty-fourth transistor Mp24 is coupled to one end of the second resistor R2. The second terminal of the twenty-fifth transistor Mp25 is coupled to the second terminal of the twenty-sixth transistor Mn26. The control terminal of the twenty-fourth transistor Mp24 is also coupled to the other end of the second resistor R2. The control terminal of the twenty-sixth transistor Mn26 is coupled to the control terminal of the twenty-seventh transistor Mn27, the second terminal of the twenty-third transistor Mp23, and the control terminal of the twenty-fifth transistor Mp25 is coupled to one end of the second resistor R2. The control electrode of transistor Mn19 is connected to the control electrode of transistor Mn26, which is coupled to the second electrode of transistor Q28. The first electrode of transistor Mn27 is coupled to the second electrode of transistor Q29, which is coupled to the other end of the second resistor R2. The control electrode of transistor Q28 is coupled to the control electrode of transistor Q29, which is coupled to the first electrode of transistor Q28, which is coupled to one end of resistor R3 and one end of resistor R4. The first electrode of transistor Q29 is coupled to the other end of resistor R3, which is coupled to the other end of resistor R4.The control electrode of the second transistor Mn2 is coupled to the second electrode of the twenty-sixth transistor Mn26. The first electrode of the second transistor Mn2 is coupled to one end of the fifth resistor R5 and the control electrode of the twenty-eighth transistor Q28. The second electrode of the second transistor Mn2 is coupled to one end of the first current source I1, and the other end of the first current source I1 is coupled to the power supply voltage VDD. The other end of the fifth resistor R5 is coupled to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is coupled to the ground terminal VSS. The first electrode of the second transistor Mn2 outputs the reference voltage Vbg. Among them, Q21, Q28, and Q29 are BJT transistors, and the other transistors are MOSFETs. The bandgap main circuit 120 is similar to the existing bandgap reference circuit. Figure 2 The structure is the same as that of the main circuit, and it can output a stable reference voltage Vbg. It should be noted that after the power supply voltage VDD reaches the normal operating voltage of the bandgap main circuit 120, the power supply circuit 200 will also adjust VDD to a steady-state value, and finally the bandgap main circuit 120 can make the output reference voltage Vbg reach this steady-state value.

[0042] Combination Figure 6 As shown in the circuit example diagram, when VDD is less than the normal operating voltage of the bandgap main circuit 120, the bandgap main circuit 120 cannot operate. However, Mp1 can be turned on by the VDD_OK signal, and the Vbg_gate voltage will be pulled up. Therefore, Vbg will also be pulled up (Vbg = Vbg_gate - Vgs), and will rise as VDD rises. Here, Vgs is the gate-source voltage of Mn2. When VDD is greater than or equal to the normal operating voltage of the bandgap main circuit 120, the VDD_OK signal goes high, Mp1 turns off, and the bandgap main circuit 120 starts to operate normally. The startup module 110 provides current bias for it, and the bandgap main circuit 120 generates a reference voltage Vbg.

[0043] like Figure 7 As shown, embodiments of this disclosure also provide a low-dropout linear regulator 300, specifically as follows: Figure 7 As shown, the low dropout linear regulator 300 includes an LDO main circuit 310, a judgment circuit 320, and the bandgap reference circuit 100 in the aforementioned embodiment.

[0044] The LDO main circuit 310 is configured to generate the power supply voltage VDD according to the control loop composed of the error amplifier EA and the power transistor Mp0. The LDO main circuit 310 is a basic structure of a low dropout linear regulator circuit. It controls the stability of the output voltage through negative feedback regulation, where VDD is the output voltage.

[0045] The judgment circuit 320 is configured to detect the change in power supply voltage VDD according to the hysteresis comparator 321 and output a power supply voltage indication signal VDD_OK; specifically, when the power supply voltage VDD is less than the normal operating voltage of the bandgap reference circuit 100, the output power supply voltage indication signal VDD_OK is low level; when the power supply voltage VDD is less than the normal operating voltage of the bandgap reference circuit 100, the output power supply voltage indication signal VDD_OK is high level.

[0046] The bandgap reference circuit 100 is configured to provide a reference voltage Vbg and a first bias current Ib1 to the LDO main circuit 310 based on the power supply voltage indication signal VDD_OK and the power supply voltage VDD. Specifically, when the power supply voltage indication signal VDD_OK is low, the bandgap reference circuit 100 generates a reference voltage Vbg that rises with the power supply voltage VDD through the included pull-up module 130. When the power supply voltage indication signal VDD_OK is high, the pull-up module 130 is turned off, and the bandgap reference circuit 100 generates a stable reference voltage Vbg through the included bandgap main circuit 120. In addition, throughout the entire process, the bandgap reference circuit 100 generates the first bias current Ib1 through the included startup module 110, and Ib1 provides current bias for the LDO main circuit 310 and the bandgap main circuit 120.

[0047] Furthermore, such as Figure 7 As shown, the judgment circuit 320 includes a hysteresis comparator 321, and the LDO main circuit 310 includes: an error amplifier EA, a power transistor Mp0, and resistors seven to nine. The positive input terminal of the error amplifier EA is coupled to the feedback voltage Vfb, and the negative input terminal of the error amplifier EA is coupled to the reference voltage Vbg output by the bandgap reference circuit 100, using it as a reference voltage. The output terminal of the error amplifier EA is coupled to the control electrode of the power transistor Mp0. The bandgap reference circuit 100 provides a first bias current Ib1 to the error amplifier EA; the power transistor Mp0... The first terminal of transistor Mp0 is coupled to the input voltage Vin, and the second terminal of power transistor Mp0 is coupled to one end of the seventh resistor R7. The eighth resistor R8 and the ninth resistor R9 are connected in series and coupled between the other end of the seventh resistor R7 and the ground terminal VSS. The other end of the seventh resistor R7 also outputs a feedback voltage Vfb. The node between the eighth resistor R8 and the ninth resistor R9 is coupled to the input of the hysteresis comparator 321. One end of the seventh resistor R7 outputs the power supply voltage VDD, which also provides the operating voltage for the error amplifier EA and the hysteresis comparator 321. The output of the hysteresis comparator 321 outputs a power supply voltage indication signal VDD_OK.

[0048] Figure 7In this embodiment, the bandgap reference circuit 100 continuously provides the LDO main circuit 310 with reference voltage Vbg and bias current (Ib1). Compared with the existing method of providing reference voltage Vbg and bias current through the bandgap reference circuit (which also requires the addition of a rough bandgap reference module), this method greatly reduces the chip area, lowers the chip power consumption and cost, and improves the overall chip performance.

[0049] In summary, the bandgap reference circuit in this embodiment can provide reference voltage and bias current to the power supply circuit even at low voltage. Compared with the existing method of providing reference voltage and bias current to the power supply circuit under low voltage by adding a rougher bandgap reference circuit, this greatly reduces the cost of the chip and improves the performance of the chip.

[0050] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0051] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0052] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A bandgap reference circuit for providing a reference voltage and bias current to a power supply circuit, characterized in that, The bandgap reference circuit includes: a bandgap main circuit, a startup module, and a pull-up module. The pull-up module is configured to, when the power supply voltage generated by the power supply circuit is less than the normal operating voltage of the bandgap main circuit, pull up the voltage to make the bandgap main circuit generate a reference voltage that rises with the rise of the power supply voltage, and stop working after the power supply voltage rises to the normal operating voltage of the bandgap main circuit. The bandgap main circuit is configured to generate a steady-state reference voltage based on a first bias current and the power supply voltage when the power supply voltage rises to the normal operating voltage of the bandgap main circuit. The startup module is configured to generate the first bias current, which is also used to provide current bias for the power supply circuit. Throughout the process, the bias current of the power supply circuit and the bias current required by the bandgap main circuit are provided by the startup module.

2. The bandgap reference circuit according to claim 1, characterized in that, The pull-up module includes: a first transistor, wherein the first transistor is a metal-oxide-semiconductor transistor. Wherein, the control electrode of the first transistor is coupled to a power supply voltage indication signal, the first electrode of the first transistor is coupled to the power supply voltage, the second electrode of the first transistor is coupled to the control electrode of the second transistor in the bandgap main circuit, the power supply voltage indication signal is used to indicate whether the power supply voltage has reached the normal operating voltage of the bandgap main circuit, and the second transistor is a transistor coupled to the reference voltage.

3. The bandgap reference circuit according to claim 1, characterized in that, The startup module includes: a startup voltage generation module, a startup loop module, and a current mirror module. The startup voltage generating module is configured to generate a startup voltage. The startup loop module is configured to start according to the startup voltage and generate a second bias current after the operation is stable; The current mirroring module is configured to mirror the second bias current to obtain the first bias current.

4. The bandgap reference circuit according to claim 3, characterized in that, The startup voltage generation module includes: transistors three to eight, wherein transistors three to eight are metal-oxide-semiconductor transistors. The control electrode of the third transistor is coupled to the control electrode of the second and fourth transistors, respectively, and the first electrode of the third transistor is coupled to the ground terminal. The first terminal of the fourth transistor is coupled to the power supply voltage, and the second terminal of the fourth transistor is coupled to the control terminals of the fifth transistor, the sixth transistor, and the seventh transistor, respectively. The first terminal of the seventh transistor is coupled to the ground terminal, and the second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor. The second terminal of the sixth transistor is coupled to the first terminal of the fifth transistor, and the second terminal of the fifth transistor is coupled to the second terminal of the eighth transistor. The control electrode of the eighth transistor is coupled to a first voltage, the first electrode of the eighth transistor is coupled to the power supply voltage, and the second electrode of the eighth transistor also provides the startup voltage.

5. The bandgap reference circuit according to claim 4, characterized in that, The startup loop module includes: transistors nine to thirteen and a first resistor; transistors nine to thirteen are metal-oxide-semiconductor transistors. The control electrode of the ninth transistor is coupled to the startup voltage, the first electrode of the ninth transistor is coupled to the power supply voltage, and the second electrode of the ninth transistor is coupled to the second electrode of the tenth transistor, the second electrode of the twelfth transistor, and the control electrode of the thirteenth transistor, respectively. The first terminal of the tenth transistor and the first terminal of the eleventh transistor are both coupled to the power supply voltage, and the control terminal of the tenth transistor is coupled to the control terminal of the eleventh transistor, the second terminal of the eleventh transistor, and the second terminal of the thirteenth transistor, respectively. The first terminal of the thirteenth transistor is coupled to the control terminal of the twelfth transistor and one end of the first resistor, and the other end of the first resistor is coupled to the ground terminal. The current flowing through the first resistor is the second bias current, and the voltage at the control electrode of the tenth transistor is the first voltage.

6. The bandgap reference circuit according to claim 5, characterized in that, The current mirror module includes: transistors fourteen to seventeen, wherein transistors fourteen to seventeen are metal-oxide-semiconductor transistors. The control electrode of the fourteenth transistor is coupled to the control electrode of the tenth transistor, the first electrode of the fourteenth transistor is coupled to the power supply voltage, and the second electrode of the fourteenth transistor is coupled to the control electrode of the fifteenth transistor, the second electrode of the fifteenth transistor, and the control electrode of the sixteenth transistor, respectively. The first terminal of the fifteenth transistor and the first terminal of the sixteenth transistor are both coupled to the ground terminal, and the second terminal of the sixteenth transistor is coupled to the second terminal of the seventeenth transistor and the control terminal of the seventeenth transistor; The first electrode of the seventeenth transistor is coupled to the power supply voltage, and the control electrode of the seventeenth transistor is also coupled to the bandgap main circuit. The current flowing through the seventeenth transistor is the second bias current.

7. The bandgap reference circuit according to claim 2, characterized in that, The bandgap main circuit includes: the second transistor, the eighteenth to twenty-ninth transistors, the second to sixth resistors, and the first current source. The control electrode of the eighteenth transistor is coupled to the startup module, the first electrode of the eighteenth transistor is coupled to the power supply voltage, the second electrode of the eighteenth transistor is coupled to the control electrode of the nineteenth transistor and the second electrode of the nineteenth transistor, the first electrode of the nineteenth transistor is coupled to the second electrode of the twentieth transistor and the control electrode of the twentieth transistor, the first electrode of the twentieth transistor is coupled to the control electrode of the twentieth transistor and the second electrode of the twentieth transistor, and the first electrode of the twentieth transistor is coupled to the ground terminal. The first terminal of the 22nd transistor and the first terminal of the 23rd transistor are both coupled to the power supply voltage. The control terminal of the 22nd transistor is coupled to the control terminal of the 23rd transistor. The second terminal of the 22nd transistor is coupled to the first terminal of the 24th transistor. The second terminal of the 23rd transistor is coupled to the first terminal of the 25th transistor. The control terminal of the 22nd transistor is also coupled to one end of the second resistor. The control electrode of the 24th transistor is coupled to the control electrode of the 25th transistor, the second electrode of the 24th transistor is coupled to one end of the second resistor, the second electrode of the 25th transistor is coupled to the second electrode of the 26th transistor, and the control electrode of the 24th transistor is also coupled to the other end of the second resistor. The control terminal of the 26th transistor is coupled to the control terminal of the 27th transistor and the control terminal of the 19th transistor. The first terminal of the 26th transistor is coupled to the second terminal of the 28th transistor. The first terminal of the 27th transistor is coupled to the second terminal of the 29th transistor. The second terminal of the 27th transistor is coupled to the other end of the second resistor. The control electrode of the 28th transistor is coupled to the control electrode of the 29th transistor. The first electrode of the 28th transistor is coupled to one end of the third resistor and one end of the fourth resistor, respectively. The first electrode of the 29th transistor is coupled to the other end of the third resistor, and the other end of the fourth resistor is coupled to the ground terminal. The control electrode of the second transistor is coupled to the second electrode of the second sixteenth transistor. The first electrode of the second transistor is coupled to one end of the fifth resistor and the control electrode of the second eighteenth transistor. The second electrode of the second transistor is coupled to one end of the first current source. The other end of the first current source is coupled to the power supply voltage. The other end of the fifth resistor is coupled to one end of the sixth resistor. The other end of the sixth resistor is coupled to the ground terminal. The first electrode of the second transistor outputs the reference voltage.

8. A low-dropout linear regulator, characterized in that, Includes an LDO main circuit, a decision circuit, and a bandgap reference circuit according to any one of claims 1-7. The LDO main circuit is configured to generate the power supply voltage according to the control loop composed of the error amplifier and the power transistor. The judgment circuit is configured to detect changes in the power supply voltage based on a hysteresis comparator and output a power supply voltage indication signal. The bandgap reference circuit is configured to provide a reference voltage and a first bias current to the LDO main circuit based on the power supply voltage indication signal and the power supply voltage.

9. The low-dropout linear regulator according to claim 8, characterized in that, The step of detecting the change in the power supply voltage using a hysteresis comparator and outputting a power supply voltage indication signal includes: When the power supply voltage is lower than the normal operating voltage of the bandgap reference circuit, the output power supply voltage indication signal is low. When the power supply voltage is lower than the normal operating voltage of the bandgap reference circuit, the output power supply voltage indication signal is high.

10. The low-dropout linear regulator according to claim 8, characterized in that, The LDO main circuit includes: the error amplifier, the power transistor, and resistors seven through nine. The positive input terminal of the error amplifier is coupled to the feedback voltage, the negative input terminal of the error amplifier is coupled to the reference voltage output by the bandgap reference circuit, the output terminal of the error amplifier is coupled to the control electrode of the power transistor, and the bandgap reference circuit provides a first bias current for the error amplifier. The first terminal of the power transistor is coupled to the input voltage, and the second terminal of the power transistor is coupled to one end of the seventh resistor; The eighth and ninth resistors are connected in series and coupled between the other end of the seventh resistor and the ground terminal. The other end of the seventh resistor also outputs the feedback voltage. The node between the eighth and ninth resistors is coupled to the input terminal of the hysteresis comparator. One end of the seventh resistor outputs the power supply voltage, which also provides the operating voltage for the error amplifier and the hysteresis comparator.

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