Chip power supply control method and device, storage medium and electronic device

Abstract

The application discloses a chip power supply control method and device, a storage medium and an electronic device. The chip power supply control method comprises the following steps: in the case that it is detected that the power supply voltage of a target chip is abnormal, the type of the abnormal power supply voltage is detected, wherein the power supply voltage is provided by a target power supply to the target chip; according to the sensitivity of each sampling point in a plurality of sampling points arranged on the target chip to the voltage abnormality belonging to the abnormal type, a sampling weight is allocated to each sampling point; the voltage of the plurality of sampling points is sampled according to the sampling weight, and a target chip sampling voltage of the target chip is obtained, wherein the target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage. By adopting the technical scheme, the problems, such as low control accuracy of chip power supply, in the related art are solved, and the technical effect of improving the control accuracy of chip power supply is achieved.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a chip power supply control method and apparatus, a storage medium, and an electronic device. Background Technology

[0002] As hardware devices such as servers, switches, and storage devices become more powerful, the operating voltage of chips such as switching chips, XPUs (Neural Network Processing Units), and accelerator cards is getting lower and lower in order to avoid a significant increase in power consumption.

[0003] To reduce the impact of voltage drops along the PCB path on chip operation, it is typically necessary to sample the voltage on the chip to ensure that the chip voltage remains stable within the positive and negative tolerance range. The current method uses the geometric center point of the chip's power supply load pin as the voltage sampling point. However, factors such as the length of the power supply path to the chip, the shape of the power plane, and the current direction can cause the optimal sampling point to not be at the geometric center point. The voltage sampled using the geometric center point in existing technology cannot represent the current voltage magnitude on the chip. For example, even if the voltage at the geometric center point is normal, the voltage at other geometric points on the chip may be higher or lower than the geometric center point. Therefore, the voltage at other geometric points on the chip may have exceeded the positive and negative tolerance range. Clearly, such voltage anomalies on the chip cannot be detected by sampling the voltage at the geometric center point, resulting in low accuracy in chip power supply control.

[0004] There is still no effective solution to the problem of low accuracy in chip power supply control in related technologies. Summary of the Invention

[0005] This application provides a chip power supply control method and apparatus, storage medium and electronic device, to at least solve the problems of low accuracy in chip power supply control in related technologies.

[0006] According to one embodiment of this application, a chip power supply control method is provided, including:

[0007] If an abnormality is detected in the power supply voltage of the target chip, the abnormality type of the power supply voltage is detected, wherein the power supply voltage is supplied to the target chip by the target power supply.

[0008] Based on the sensitivity of each sampling point among the multiple sampling points deployed on the target chip to voltage anomalies belonging to the anomaly type, a sampling weight is assigned to each sampling point, wherein the higher the sensitivity, the higher the assigned sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip.

[0009] Voltage samples are taken from the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip. The target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage.

[0010] Optionally, assigning a sampling weight to each sampling point based on the sensitivity of each sampling point among the multiple sampling points deployed on the target chip to voltage anomalies belonging to the anomaly type includes:

[0011] Based on the power supply distance between each sampling point deployed on the target chip and the voltage input interface on the target chip, the sensitivity of each sampling point to voltage anomalies of the aforementioned anomaly type is obtained. The voltage input interface is the interface through which the target chip receives power from the target power supply. In the case of an overvoltage anomaly, the sensitivity of the sampling point is negatively correlated with the power supply distance; in the case of an undervoltage anomaly, the sensitivity of the sampling point is positively correlated with the power supply distance. The overvoltage anomaly type indicates that the power supply voltage of the target chip is greater than the upper limit of the target chip's voltage threshold range; the undervoltage anomaly type indicates that the power supply voltage of the target chip is less than the lower limit of the target chip's voltage threshold range. The voltage threshold range is the voltage range allowed for normal operation of the target chip.

[0012] The sampling weights are assigned based on the sensitivity.

[0013] Optionally, assigning the sampling weights based on the sensitivity includes:

[0014] A first constraint condition for obtaining the power supply voltage of the target chip is obtained, wherein the first constraint condition is that after adjusting the power supply voltage according to the sampled voltage of the target chip, the voltage of each of the plurality of sampled points falls within the voltage threshold range;

[0015] Each sampling point is assigned a sampling weight based on its sensitivity and the first constraint.

[0016] Optionally, assigning the sampling weights based on the sensitivity includes:

[0017] A second constraint condition for obtaining the power supply voltage of the target chip is provided, wherein the second constraint condition is that after adjusting the power supply voltage according to the sampled voltage of the target chip, the voltage of each of the plurality of sampled points falls within the voltage threshold range, and the difference between the first parameter value and the second parameter value is less than or equal to the target threshold. The first parameter value is the difference between the maximum voltage value among the sampled points and the upper limit of the voltage threshold range, and the second parameter value is the difference between the minimum voltage value among the sampled points and the lower limit of the voltage threshold range.

[0018] Each sampling point is assigned a sampling weight based on its sensitivity and the second constraint.

[0019] Optionally, the step of sampling the voltage at the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip includes:

[0020] The sampling resistors corresponding to the multiple sampling points in the initial sampling circuit are adjusted according to the sampling weight to obtain the target sampling circuit. The target sampling circuit includes multiple sampling lines for sampling the voltage of the multiple sampling points. One end of each sampling line is connected to one of the multiple sampling points, and the other end is connected to the same target output point. The sampling resistor corresponding to each sampling point is deployed on the corresponding sampling line. The resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller.

[0021] The voltage at the target output point of the target sampling circuit is determined as the target chip sampling voltage.

[0022] Optionally, the plurality of sampling points includes a first sampling point, a second sampling point, and a third sampling point. The first sampling point is the maximum voltage point of the target chip, the second sampling point is the center point of the target chip, and the third sampling point is the minimum voltage point on the target chip. The initial sampling circuit includes a first sampling line, a second sampling line, and a third sampling line. One end of the first sampling line is connected to the first sampling point, one end of the second sampling line is connected to the second sampling point, and the other ends of the first, second, and third sampling lines are connected to the same target output point. A first sampling resistor is deployed between the first sampling point and the target output point on the first sampling line. A second sampling resistor is deployed between the second sampling point and the target output point on the second sampling line. A third sampling resistor is deployed between the third sampling point and the target output point on the third sampling line. The step of sampling the voltage of the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip includes:

[0023] The first sampling resistor is adjusted according to the sampling weight assigned to the first sampling point, the second sampling resistor is adjusted according to the sampling weight assigned to the second sampling point, and the third sampling resistor is adjusted according to the sampling weight assigned to the third sampling point to obtain the target sampling circuit. The resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller.

[0024] The voltage at the target output point of the target sampling circuit is determined as the target chip sampling voltage.

[0025] Optionally, when an abnormality in the power supply voltage of the target chip is detected, detecting the type of abnormality in the power supply voltage includes:

[0026] If the power supply voltage of the target chip is detected to be greater than the upper limit of the voltage threshold range of the target chip, the abnormality type is determined to be an overvoltage abnormality type, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip;

[0027] If the supply voltage of the target chip is detected to be less than the lower limit of the voltage threshold range of the target chip, the abnormality type is determined to be a low voltage abnormality type, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip.

[0028] According to another embodiment of the present application, a chip power supply control device is also provided, comprising:

[0029] The detection module is used to detect the type of abnormality in the power supply voltage when an abnormality is detected in the power supply voltage of the target chip, wherein the power supply voltage is supplied to the target chip by the target power supply.

[0030] The allocation module is used to allocate a sampling weight to each sampling point based on the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage anomalies belonging to the anomaly type. The higher the sensitivity, the higher the allocated sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip.

[0031] A sampling module is used to sample the voltage of the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip, wherein the target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage.

[0032] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0033] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0034] In this embodiment, when an abnormality in the power supply voltage of the target chip is detected, the abnormality type of the power supply voltage is detected, wherein the power supply voltage is provided to the target chip by the target power supply. Based on the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage abnormalities belonging to the abnormality type, a sampling weight is assigned to each sampling point, wherein the higher the sensitivity, the higher the assigned sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage in the chip sampling voltage of the target chip. Voltage sampling is performed on the multiple sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip. The target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage. That is, when an abnormality in the target chip power supply voltage occurs, the abnormality type is first detected, and the abnormality type of voltage abnormality is determined based on the sensitivity of each sampling point among the multiple sampling points deployed on the target chip. The sensitivity of the sampling points is assessed by assigning sampling weights to each sampling point, with higher-sensitivity sampling points receiving higher weights. The sampling weight indicates the proportion of the sampling point's voltage within the target chip's overall sampling voltage. Voltage sampling is then performed on multiple sampling points according to these weights to obtain the target chip's sampling voltage. The target power supply then adjusts its supply voltage based on this sampling voltage. This method obtains the target chip's sampling voltage through multi-point sampling, reflecting the overall supply voltage of the target chip. Furthermore, the sampling weights of each sampling point are assigned based on the sensitivity of each sampling point to voltage anomalies, ensuring a better match between the sampling weights and the current anomaly type of the supply voltage. Therefore, the obtained target chip sampling voltage more accurately reflects the overall supply voltage of the target chip, resulting in higher accuracy for subsequent supply voltage adjustments. This technical solution addresses the problem of low accuracy in chip power supply control in related technologies, achieving a significant improvement in the accuracy of chip power supply control. Attached Figure Description

[0035] Figure 1 This is a hardware structure block diagram of a computer device for a chip power supply control method according to an embodiment of this application;

[0036] Figure 2 This is a schematic diagram of a chip power supply according to an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the sampling points of a chip according to an embodiment of this application;

[0038] Figure 4 This is a flowchart of a chip power supply control method according to an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of a power supply distance according to an embodiment of this application;

[0040] Figure 6 This is a schematic diagram of a sampling circuit according to an embodiment of this application. Figure 1 ;

[0041] Figure 7 This is a schematic diagram of a sampling circuit according to an embodiment of this application. Figure 2 ;

[0042] Figure 8 This is a structural block diagram of a chip-powered control device according to an embodiment of this application. Detailed Implementation

[0043] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0045] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a computer device for a chip power supply control method according to an embodiment of this application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0046] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the chip power supply control method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0047] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0048] The terms used in the embodiments of this application are explained as follows:

[0049] PWM stands for Pulse Width Modulation.

[0050] VFB, Voltage of Feedback.

[0051] Before describing the chip power supply control method proposed in this application, in order to better understand the inventiveness and technical effects of this application, the inventive concept of the chip power supply control method proposed in this application will first be explained:

[0052] Figure 2 This is a schematic diagram of a chip power supply according to an embodiment of this application. For example... Figure 2As shown, this application uses a VRM (Voltage Regulator Module) as a power supply to supply power to the target chip (LoadChip) one-to-one. As mentioned above, the operating voltage of the chip is getting lower and lower, and the current output by the power supply to the chip is getting higher and higher. Since the main purpose of the power supply is to ensure that the load chip can work stably within the positive and negative tolerance range of the voltage (Normal+Tolerance to Normal-Tolerance).

[0053] Existing solutions select the sampling point at the geometric center of the power load pin of the load chip. However, the output of the VRM also has a certain degree of accuracy, meaning that the voltage output by the VRM may be too high (e.g., Normal + Accuracy) or too low (e.g., Normal - Accuracy). In addition, the length of the power path from the VRM to the Load Chip, the shape of the power plane, and the direction of the current can all cause the optimal sampling point to not be at the geometric center of the load chip (target chip). Figure 3 This is a schematic diagram of sampling points of a chip according to an embodiment of this application. For example... Figure 3 As shown, sampling point A is the geometric center of the target chip. Figure 3 The diagram shows the VRM current entering from the left side of sampling point A, passing through points B, A, and C in sequence. Related technologies use single-point sampling, meaning only the voltage at sampling point A is sampled to represent the overall supply voltage of the target chip. Since the current flow from the VRM to the load chip's pins is not necessarily perfectly symmetrical, and the current direction is not necessarily along the axis of symmetry, point A is usually not the optimal sampling point. Furthermore, because the VRM output has a precision range (commonly ±1%), the voltage at some chip pins may be too low or too high. Due to voltage drops along the PCB (Printed Circuit Board) path, point B typically has the highest voltage, and point C has the lowest. If the VRM output is too high, point B may exceed the Normal+Tolerance voltage range; conversely, if the VRM output is too low, point C may be below the Normal-Tolerance range.

[0054] It is evident that the voltage sampled using a single sampling point in related technologies cannot represent the current voltage magnitude on the chip. For example, even if the voltage at the geometric center point is normal, the voltage at other geometric points on the chip may be higher or lower than that at the geometric center point. Therefore, these other geometric points may have exceeded the positive and negative tolerance range of the voltage. Obviously, such voltage anomalies on the chip cannot be detected by sampling the voltage at the geometric center point, resulting in low accuracy in chip power supply control.

[0055] Based on the aforementioned technical problems in related technologies, this application proposes a chip power supply control method. On the one hand, it uses a multi-point sampling method to obtain the target chip sampling voltage, which can reflect the overall power supply voltage of the target chip. On the other hand, during the multi-point sampling process, the sampling weight of each sampling point is allocated according to the sensitivity of each sampling point among the multiple sampling points deployed on the target chip to voltage anomalies of an abnormal type. This makes the sampling weight of each sampling point more closely match the anomaly type of the current power supply voltage. Based on this, the target chip sampling voltage can more accurately reflect the overall power supply voltage of the target chip. Therefore, the accuracy of subsequent power supply voltage adjustment based on the target chip sampling voltage is higher, thereby achieving the technical effect of improving the accuracy of chip power supply control.

[0056] This embodiment provides a method for controlling chip power supply. Figure 4 This is a flowchart of a chip power supply control method according to an embodiment of this application, such as... Figure 4 As shown, the process includes the following steps:

[0057] Step S12: If an abnormality is detected in the power supply voltage of the target chip, the abnormality type of the power supply voltage is detected, wherein the power supply voltage is supplied to the target chip by the target power supply.

[0058] Optionally, in this embodiment, the type of target chip is not limited, such as a switching chip, an XPU chip (Neural network Processing Unit), an accelerator card chip, etc.

[0059] Optionally, in this embodiment, the target power supply can be, but is not limited to, any device or component with power supply function, such as, but is not limited to, using a VRM as the target power supply.

[0060] Step S14: Based on the sensitivity of each sampling point among the multiple sampling points deployed on the target chip to voltage anomalies belonging to the anomaly type, assign a sampling weight to each sampling point, wherein the higher the sensitivity, the higher the assigned sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip.

[0061] Optionally, in this embodiment, such as Figure 3 As shown, unlike the related technologies that treat sampling point A as a single sampling point, the chip power supply control method proposed in this application adopts multi-point sampling. The multiple sampling points deployed on the target chip can be, but are not limited to, sampling point B, sampling point A, and sampling point C.

[0062] Optionally, in this embodiment, the sensitivity of each sampling point to voltage anomalies belonging to the aforementioned anomaly type is described as follows: (e.g.) Figure 3 As shown, the current from the target power supply VRM enters from the left side of sampling point A in the target chip, passing through points B, A, and C in sequence. The voltage output by the VRM may be too low or too high. Due to the voltage drop along the PCB path, the voltage at point B is usually the highest, and the voltage at point C is the lowest. If the VRM output is too high, point B may exceed the Normal+Tolerance voltage range; conversely, if the VRM output is too low, point C may be below the Normal-Tolerance range. Clearly, when the anomaly type is overvoltage, sampling point B has the highest sensitivity (most likely exceeding Normal+Tolerance), followed by sampling points A and C. When the anomaly type is undervoltage, sampling point C has the highest sensitivity (most likely below Normal-Tolerance), followed by sampling points A and B.

[0063] Optionally, in this embodiment, the sampling weight is used to indicate the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip. The higher the sensitivity, the higher the sampling weight is assigned. Therefore, sampling weight is assigned to each sampling point according to the sensitivity of each sampling point among the multiple sampling points deployed on the target chip to voltage anomalies of the abnormal type. More attention is given to sampling points with higher sensitivity. The intuitive way to implement this is that the higher the sensitivity, the higher the sampling weight is assigned, so as to increase the proportion of the sampling point voltage of the sampling point in the chip sampling voltage of the target chip.

[0064] Step S16: Voltage sampling is performed on the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip, wherein the target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage.

[0065] Optionally, in this embodiment, the target chip sampling voltage is used to provide a reference for the target power supply to adjust the supply voltage.

[0066] When an abnormality in the power supply voltage of the target chip is detected, the abnormality type of the power supply voltage is detected, wherein the power supply voltage is supplied to the target chip by the target power supply. Based on the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage abnormalities belonging to the abnormality type, a sampling weight is assigned to each sampling point, wherein the higher the sensitivity, the higher the assigned sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage in the chip sampling voltage of the target chip. Voltage sampling is performed on the multiple sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip. The target chip sampling voltage is used to supply the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage. That is, when an abnormality in the target chip power supply voltage occurs, the abnormality type is first detected, and the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage abnormalities belonging to the abnormality type is determined. A sampling weight is assigned to each sampling point, with higher-sensitivity sampling points receiving higher weights. The sampling weight indicates the proportion of the sampling point's voltage in the target chip's overall sampling voltage. Voltage sampling is then performed on multiple sampling points according to these weights to obtain the target chip's sampling voltage. The target power supply then adjusts its supply voltage based on this sampling voltage. This method obtains the target chip's sampling voltage through multi-point sampling, reflecting the overall supply voltage of the target chip. Furthermore, the sampling weights of each sampling point are assigned based on the sensitivity of each sampling point to voltage anomalies, ensuring a closer match between the sampling weights and the current anomaly type of the supply voltage. Therefore, the obtained target chip sampling voltage more accurately reflects the overall supply voltage of the target chip, resulting in higher accuracy for subsequent supply voltage adjustments. This technical solution addresses the problem of low accuracy in chip power supply control in related technologies, achieving a significant improvement in the accuracy of chip power supply control.

[0067] As an optional approach, based on the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage anomalies belonging to the aforementioned anomaly type, a sampling weight is assigned to each sampling point, further comprising:

[0068] S21, based on the power supply distance between each sampling point among the multiple sampling points deployed on the target chip and the voltage input interface on the target chip, the sensitivity of each sampling point to voltage anomalies belonging to the anomaly type is obtained. The voltage input interface is the interface through which the target chip receives power from the target power supply. When the anomaly type is an overvoltage anomaly, the sensitivity of the sampling point is negatively correlated with the power supply distance. When the anomaly type is a low voltage anomaly, the sensitivity of the sampling point is positively correlated with the power supply distance. The overvoltage anomaly type indicates that the power supply voltage of the target chip is greater than the upper limit of the voltage threshold range of the target chip. The low voltage anomaly type indicates that the power supply voltage of the target chip is less than the lower limit of the voltage threshold range of the target chip. The voltage threshold range is the voltage range allowed for normal operation of the target chip.

[0069] S22, Assign the sampling weights according to the sensitivity.

[0070] Optionally, in this embodiment, the sensitivity of each sampling point to voltage anomalies of the aforementioned anomaly type is obtained based on the power supply distance between each sampling point among the multiple sampling points deployed on the target chip and the voltage input interface on the target chip. Figure 5 This is a schematic diagram of a power supply distance according to an embodiment of this application, such as... Figure 5 As shown, the target power supply VRM delivers power to the target chip from the voltage input interface. The current passes through sampling point B, sampling point A, and sampling point C in sequence. The power supply distance between sampling point B and the voltage input interface is DB, the power supply distance between sampling point A and the voltage input interface is DA, and the power supply distance between sampling point C and the voltage input interface is DC, where DB < DA < DC. Due to the voltage drop along the PCB path, the voltage at sampling point B is usually the highest, and the voltage at sampling point C is the lowest. Therefore, when the anomaly type is an overvoltage anomaly, sampling point B has the highest sensitivity (most likely exceeding Normal + Tolerance), followed by sampling points A and C. That is, the sensitivity of the sampling point is negatively correlated with the power supply distance. When the anomaly type is an undervoltage anomaly, sampling point C has the highest sensitivity (most likely below Normal - Tolerance), followed by sampling points A and B. The sensitivity of the sampling point is positively correlated with the power supply distance.

[0071] As an optional approach, the allocation of sampling weights based on the sensitivity further includes:

[0072] S31, obtain a first constraint condition for the power supply voltage of the target chip, wherein the first constraint condition is that after adjusting the power supply voltage according to the sampling voltage of the target chip, the voltage of each sampling point among the plurality of sampling points falls within the voltage threshold range;

[0073] S32, assign sampling weights to each sampling point according to the sensitivity of each sampling point and the first constraint condition.

[0074] Optionally, in this embodiment, step S22 mentioned above states that the sampling weights can be allocated based on sensitivity. However, allocating the sampling weights based on sensitivity may result in various schemes. For example, when the anomaly type is an overvoltage anomaly, the sensitivity from high to low is sampling point B, sampling point A, and sampling point C. Possible allocation schemes for the sampling weights may include, but are not limited to:

[0075] Option 1: Sampling point B (sampling weight 0.7), sampling point A (sampling weight 0.2), sampling point C (sampling weight 0.1);

[0076] Option 2: Sampling point B (sampling weight 0.6), sampling point A (sampling weight 0.3), sampling point C (sampling weight 0.1);

[0077] Option 3: Sampling point B (sampling weight 0.5), sampling point A (sampling weight 0.3), sampling point C (sampling weight 0.2);

[0078] The problem at this point is how to select the most suitable sampling weight allocation scheme from multiple schemes. This embodiment provides a solution, which is to further allocate sampling weights to each sampling point based on the sensitivity of each sampling point and the first constraint condition mentioned in step S22, on the basis of allocating sampling weights according to the sensitivity of each sampling point. The first constraint condition is that after adjusting the power supply voltage according to the target chip sampling voltage, the voltage of each of the multiple sampling points should fall within the voltage threshold range. That is, after adjusting the power supply voltage according to the target chip sampling voltage, it is necessary to ensure that the voltages of sampling points B, A, and C, VB, VA, and VC, all fall within the voltage threshold range, i.e., VB < Normal + Tolerance, and VC > Normal - Tolerance. If the sampling weight of sampling point B is increased indiscriminately (such as in schemes 1 and 2), although it can ensure that the target chip sampling voltage is greatly referenced to the voltage at sampling point B, thus ensuring that VB < Normal + Tolerance after adjusting the power supply voltage, the proportion of the voltage at sampling point C in the target chip sampling voltage is too small, which may result in the risk that VC < Normal - Tolerance. It is evident that if it is necessary to ensure that the voltages VB, VA, and VC at sampling points B, A, and C all fall within the voltage threshold range, then the voltage at sampling point C should also account for a certain proportion of the target chip's sampled voltage. Therefore, Scheme 3 is the most suitable sampling weight allocation scheme. Of course, the above is only an explanation of the implementation method in conjunction with a specific scenario and does not limit the specific sampling weight allocation method.

[0079] As an optional approach, assigning the sampling weights based on the sensitivity further includes:

[0080] S41, obtain a second constraint condition for the power supply voltage of the target chip, wherein the second constraint condition is that after adjusting the power supply voltage according to the sampling voltage of the target chip, the voltage of each sampling point among the plurality of sampling points falls within the voltage threshold range, and the difference between the first parameter value and the second parameter value is less than or equal to the target threshold, the first parameter value is the difference between the maximum voltage value among the sampling points and the upper limit of the voltage threshold range, and the second parameter value is the difference between the minimum voltage value among the sampling points and the lower limit of the voltage threshold range;

[0081] S42, assign sampling weights to each sampling point according to the sensitivity of each sampling point and the second constraint.

[0082] Optionally, in this embodiment, based on similar considerations as described above, sampling weights can be assigned to each sampling point according to the sensitivity of each sampling point and the second constraint condition. The second constraint condition is more stringent than the first constraint condition. The second constraint condition requires that after adjusting the supply voltage according to the target chip sampling voltage, the voltage of each of the multiple sampling points falls within the voltage threshold range, and the difference between the first parameter value and the second parameter value is less than or equal to the target threshold. The first parameter value is the difference between the maximum voltage value among the sampling points and the upper limit of the voltage threshold range, and the second parameter value is the difference between the minimum voltage value among the sampling points and the lower limit of the voltage threshold range. For example, the voltages of sampling points B, A, and C are VB, VA, and VC, respectively, where VB > VA > VC. The second constraint condition needs to ensure that:

[0083] 1) VB < Normal + Tolerance, while VC > Normal - Tolerance (equivalent to the first constraint condition mentioned above);

[0084] 2) (Normal+Tolerance)-VB=K1, VC-(Normal-Tolerance)=K2, |K1-K2|≤K3;

[0085] Wherein, K1 is the first parameter value mentioned above, K2 is the second parameter value mentioned above, |K1-K2| is the difference between the first parameter value and the second parameter value, K3 is the target threshold, Normal+Tolerance is the upper limit of the voltage threshold range, and Normal-Tolerance is the lower limit of the voltage threshold range.

[0086] As an optional approach, the voltage sampling of the plurality of sampling points is performed according to the sampling weights to obtain the target chip sampling voltage of the target chip, further comprising:

[0087] S51, the sampling resistors corresponding to the plurality of sampling points in the initial sampling circuit are adjusted according to the sampling weight to obtain the target sampling circuit. The target sampling circuit includes a plurality of sampling lines for sampling the voltage of the plurality of sampling points. One end of each sampling line is connected to one of the plurality of sampling points, and the other end is connected to the same target output point. The sampling resistor corresponding to each sampling point is deployed on the corresponding sampling line. The resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller.

[0088] S52, the voltage at the target output point of the target sampling circuit is determined as the target chip sampling voltage.

[0089] Optionally, in this embodiment, the target output point samples the voltage of different sampling points through different sampling lines. Each sampling line is equipped with a corresponding sampling resistor. The resistance value of the sampling resistor is adjusted by adjusting the sampling weight, thereby controlling the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip. The initial sampling circuit will be described below.

[0090] As an optional solution, the plurality of sampling points includes a first sampling point, a second sampling point, and a third sampling point. The first sampling point is the maximum voltage point of the target chip, the second sampling point is the center point of the target chip, and the third sampling point is the minimum voltage point on the target chip. The initial sampling circuit includes a first sampling line, a second sampling line, and a third sampling line. One end of the first sampling line is connected to the first sampling point, one end of the second sampling line is connected to the second sampling point, and the other ends of the first, second, and third sampling lines are connected to the same target output point. A first sampling resistor is deployed between the first sampling point and the target output point on the first sampling line. A second sampling resistor is deployed between the second sampling point and the target output point on the second sampling line. A third sampling resistor is deployed between the third sampling point and the target output point on the third sampling line. The step of sampling the voltage of the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip further includes:

[0091] S61, the first sampling resistor is adjusted according to the sampling weight assigned to the first sampling point, the second sampling resistor is adjusted according to the sampling weight assigned to the second sampling point, and the third sampling resistor is adjusted according to the sampling weight assigned to the third sampling point to obtain the target sampling circuit, wherein the resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller.

[0092] S62, the voltage at the target output point of the target sampling circuit is determined as the target chip sampling voltage.

[0093] Optionally, in this embodiment, Figure 6 This is a schematic diagram of a sampling circuit according to an embodiment of this application. Figure 1 ,like Figure 6As shown, the plurality of sampling points include a first sampling point (sampling point B, shown as "B" in the figure), a second sampling point (sampling point A, shown as "A" in the figure), and a third sampling point (sampling point C, shown as "C" in the figure). The first sampling point is the maximum voltage point of the target chip, the second sampling point is the center point of the target chip, and the third sampling point is the minimum voltage point on the target chip. The initial sampling circuit includes a first sampling line, a second sampling line, and a third sampling line. One end of the first sampling line is connected to the first sampling point, one end of the second sampling line is connected to the second sampling point, and the other ends of the first sampling line, the second sampling line, and the third sampling line are connected to the same target output point. The first sampling line deploys a first sampling resistor RHB between the first sampling point and the target output point, the second sampling line deploys a second sampling resistor RHA between the second sampling point and the target output point, and the third sampling line deploys a third sampling resistor RHC between the third sampling point and the target output point.

[0094] like Figure 6 As shown, the voltage drop along the PCB path from the target power supply VRM to the target chip Load Chip increases proportionally with increasing current, especially in low-voltage designs where this voltage drop has a greater impact. Therefore, for low-voltage, high-current power supply solutions, the VRM on the left side uses a remote feedback method. The working principle is as follows:

[0095] 1. The main power circuit of the VRM includes main power devices such as MOSA1, MOSB1 and L1, as well as the MOS control drive logic circuit and feedback control circuit.

[0096] 2. The feedback voltage divider resistor consists of RHB, RHA, RHC and RL, and the output voltage is sampled through the voltage divider resistor.

[0097] 3. The feedback point voltage VFB obtained from the voltage divider resistors is compared with the chip's internal reference power supply Reference and used as the input for PWM regulation of the main power circuit. VRM can determine the current fault type of the target chip based on VFB. For example, if VFB is greater than Reference, the fault type is an overvoltage fault, which can be controlled by MOSA1 and MOSB1 to decrease Vout until VFB = Reference. Similarly, if VFB is less than Reference, the fault type is an undervoltage fault, which can be controlled by MOSA1 and MOSB1 to increase Vout until VFB = Reference.

[0098] 4. Sampling points B, A, and C were deployed on the target chip (more sampling points can be deployed, for example, Figure 6 The sampling points B1, B2, A1, A2, C1, C2, etc. shown in the figure are illustrated in this embodiment (this example uses the deployment of sampling points B, A, and C as an example for explanation).

[0099] 5. A weighted average voltage value (target chip sampling voltage) is calculated using voltage divider resistors RHB, RHA, and RHC and fed back to the internal VRM (controller). The sampling weight of each sampling point depends on the resistance values ​​of RHB, RHA, and RHC.

[0100] The target power supply adjusts the supply voltage Vout according to the target chip's sampling voltage VFB. The purpose of the adjustment is to ensure that the voltages of sampling points B, A, and C are all stable within the Normal ± Tolerance voltage range, and to ensure that both the upper and lower margins are sufficiently large. The upper margin is K1 mentioned above, and the lower margin is K2 mentioned above. Ideally, the upper and lower margins should be the same size. In this case, the voltages of sampling points B, A, and C will all converge in the central region of the Normal ± Tolerance voltage range.

[0101] If the anomaly type is overvoltage, and the voltage at each sampling point is too high, then RHB can be reduced to increase the feedback weight of sampling point B; if the anomaly type is undervoltage, and the voltage at each sampling point is too low, then RHC can be reduced to increase the feedback weight of sampling point C.

[0102] The adjustment of RHB, RHA, and RHC during the above process must adhere to the following constraint: 1 / RH = 1 / RHA + 1 / RHB + 1 / RHC, where RH is a preset resistance value. For example, decreasing RHA will increase the other two resistance values, thus increasing the sampling weight of sampling point A.

[0103] also, Figure 6 The sampling circuit shown neglects the GND (ground) voltage drop. However, in scenarios where the GND voltage drop is not negligible, Figure 6 The lower voltage divider RL in the circuit can also be sampled using distributed sampling. Figure 7 This is a schematic diagram of a sampling circuit according to an embodiment of this application. Figure 2 ,like Figure 7 As shown, RL can be divided into multiple RLA, RLB, RLC, etc., using the GND pin of the load chip as the sampling point (e.g., Figure 7The sampling points d, e, f, etc. shown in the figure are used to collect the voltage at the corresponding sampling point using each sampling resistor.

[0104] As an optional approach, when an abnormality in the power supply voltage of the target chip is detected, detecting the type of abnormality in the power supply voltage further includes:

[0105] S71, if the power supply voltage of the target chip is detected to be greater than the upper limit of the voltage threshold range of the target chip, the abnormality type is determined to be an overvoltage abnormality type, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip;

[0106] S72, if the power supply voltage of the target chip is detected to be less than the lower limit of the voltage threshold range of the target chip, the abnormality type is determined to be a low voltage abnormality type, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip.

[0107] Optionally, in this embodiment, as mentioned above, the current abnormality type of the target chip can be determined based on VFB. For example, if VFB is greater than Reference, the abnormality type is an overvoltage abnormality type, and Vout can be reduced by controlling MOSA1 and MOSB1 until VFB = Reference. Similarly, if VFB is less than Reference, the abnormality type is an undervoltage abnormality type, and Vout can be increased by controlling MOSA1 and MOSB1 until VFB = Reference. In addition, this embodiment also provides another method, namely, directly determining the abnormality type based on the supply voltage Vout.

[0108] The chip power supply control method proposed in this application adopts distributed multi-point sampling and weighted averages the sampling weights of each sampling point. The sampling weights of each sampling point can be flexibly adjusted so that the voltage of each sampling point is as close as possible to the normal value of the working voltage. At the same time, it ensures that the voltage of all load pins is within the range of Normal-Tolerance and Normal+Tolerance, and ensures that the margin is maximized.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0110] This embodiment also provides a chip-powered control device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware implementations, or a combination of software and hardware, are also possible and contemplated.

[0111] Figure 8 This is a structural block diagram of a chip-powered control device according to an embodiment of this application; as shown below. Figure 8 As shown, it includes:

[0112] The detection module 802 is used to detect the abnormality type of the power supply voltage when an abnormality is detected in the power supply voltage of the target chip, wherein the power supply voltage is provided to the target chip by the target power supply.

[0113] The allocation module 804 is used to allocate a sampling weight to each sampling point based on the sensitivity of each sampling point among the multiple sampling points deployed on the target chip to voltage anomalies belonging to the anomaly type. The higher the sensitivity, the higher the allocated sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip.

[0114] The sampling module 806 is used to sample the voltage of the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip, wherein the target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage.

[0115] When an abnormality in the power supply voltage of the target chip is detected, the abnormality type of the power supply voltage is detected, wherein the power supply voltage is supplied to the target chip by the target power supply. Based on the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage abnormalities belonging to the abnormality type, a sampling weight is assigned to each sampling point, wherein the higher the sensitivity, the higher the assigned sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage in the chip sampling voltage of the target chip. Voltage sampling is performed on the multiple sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip. The target chip sampling voltage is used to supply the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage. That is, when an abnormality in the target chip power supply voltage occurs, the abnormality type is first detected, and the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage abnormalities belonging to the abnormality type is determined. A sampling weight is assigned to each sampling point, with higher-sensitivity sampling points receiving higher weights. The sampling weight indicates the proportion of the sampling point's voltage in the target chip's overall sampling voltage. Voltage sampling is then performed on multiple sampling points according to these weights to obtain the target chip's sampling voltage. The target power supply then adjusts its supply voltage based on this sampling voltage. This method obtains the target chip's sampling voltage through multi-point sampling, reflecting the overall supply voltage of the target chip. Furthermore, the sampling weights of each sampling point are assigned based on the sensitivity of each sampling point to voltage anomalies, ensuring a closer match between the sampling weights and the current anomaly type of the supply voltage. Therefore, the obtained target chip sampling voltage more accurately reflects the overall supply voltage of the target chip, resulting in higher accuracy for subsequent supply voltage adjustments. This technical solution addresses the problem of low accuracy in chip power supply control in related technologies, achieving a significant improvement in the accuracy of chip power supply control.

[0116] In one exemplary embodiment, the allocation module includes:

[0117] The first determining unit is configured to determine the sensitivity of each sampling point to a voltage anomaly of the specified anomaly type based on the power supply distance between each sampling point and the voltage input interface on the target chip. The voltage input interface is the interface through which the target chip receives power from the target power supply. When the anomaly type is an overvoltage anomaly, the sensitivity of the sampling point is negatively correlated with the power supply distance. When the anomaly type is a low voltage anomaly, the sensitivity of the sampling point is positively correlated with the power supply distance. The overvoltage anomaly type indicates that the power supply voltage of the target chip is greater than the upper limit of the voltage threshold range of the target chip. The low voltage anomaly type indicates that the power supply voltage of the target chip is less than the lower limit of the voltage threshold range of the target chip. The voltage threshold range is the voltage range allowed for normal operation of the target chip.

[0118] An allocation unit is used to allocate the sampling weights according to the sensitivity.

[0119] In one exemplary embodiment, the allocation unit is further configured to:

[0120] A first constraint condition for obtaining the power supply voltage of the target chip is obtained, wherein the first constraint condition is that after adjusting the power supply voltage according to the sampled voltage of the target chip, the voltage of each of the plurality of sampled points falls within the voltage threshold range;

[0121] Each sampling point is assigned a sampling weight based on its sensitivity and the first constraint.

[0122] In one exemplary embodiment, the allocation unit is further configured to:

[0123] A second constraint condition for obtaining the power supply voltage of the target chip is provided, wherein the second constraint condition is that after adjusting the power supply voltage according to the sampled voltage of the target chip, the voltage of each of the plurality of sampled points falls within the voltage threshold range, and the difference between the first parameter value and the second parameter value is less than or equal to the target threshold. The first parameter value is the difference between the maximum voltage value among the sampled points and the upper limit of the voltage threshold range, and the second parameter value is the difference between the minimum voltage value among the sampled points and the lower limit of the voltage threshold range.

[0124] Each sampling point is assigned a sampling weight based on its sensitivity and the second constraint.

[0125] In one exemplary embodiment, the sampling module includes:

[0126] The first adjustment unit is used to adjust the sampling resistors corresponding to the plurality of sampling points in the initial sampling circuit according to the sampling weight to obtain the target sampling circuit. The target sampling circuit includes a plurality of sampling lines for sampling the voltage of the plurality of sampling points. One end of each sampling line is connected to one of the plurality of sampling points, and the other end is connected to the same target output point. The sampling resistors corresponding to each sampling point are deployed on the corresponding sampling line. The resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller.

[0127] The second determining unit is used to determine the voltage at the target output point of the target sampling circuit as the target chip sampling voltage.

[0128] In an exemplary embodiment, the plurality of sampling points includes a first sampling point, a second sampling point, and a third sampling point. The first sampling point is the maximum voltage point of the target chip, the second sampling point is the center point of the target chip, and the third sampling point is the minimum voltage point on the target chip. The initial sampling circuit includes a first sampling line, a second sampling line, and a third sampling line. One end of the first sampling line is connected to the first sampling point, one end of the second sampling line is connected to the second sampling point, and the other ends of the first, second, and third sampling lines are connected to the same target output point. A first sampling resistor is deployed between the first sampling point and the target output point on the first sampling line. A second sampling resistor is deployed between the second sampling point and the target output point on the second sampling line. The third sampling line is deployed between the third sampling point and the target output point on the third sampling line. The sampling module includes:

[0129] The second adjustment unit is used to adjust the first sampling resistor according to the sampling weight assigned to the first sampling point, adjust the second sampling resistor according to the sampling weight assigned to the second sampling point, and adjust the third sampling resistor according to the sampling weight assigned to the third sampling point to obtain the target sampling circuit, wherein the resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller.

[0130] The third determining unit is used to determine the voltage at the target output point of the target sampling circuit as the target chip sampling voltage.

[0131] In one exemplary embodiment, the detection module includes:

[0132] The fourth determination unit is used to determine that the abnormality type is an overvoltage abnormality type when the power supply voltage of the target chip is detected to be greater than the upper limit of the voltage threshold range of the target chip, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip;

[0133] The fifth determining unit is used to determine the abnormality type as a low-voltage abnormality type when the power supply voltage of the target chip is detected to be less than the lower limit of the voltage threshold range of the target chip, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip.

[0134] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0135] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0136] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0137] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0138] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0139] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0140] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0141] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for controlling chip power supply, characterized in that, include: If an abnormality is detected in the power supply voltage of the target chip, the abnormality type of the power supply voltage is detected, wherein the power supply voltage is supplied to the target chip by the target power supply. Based on the sensitivity of each sampling point among the multiple sampling points deployed on the target chip to voltage anomalies belonging to the anomaly type, a sampling weight is assigned to each sampling point, wherein the higher the sensitivity, the higher the assigned sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip. Voltage samples are taken from the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip. The target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage. The step of assigning sampling weights to each sampling point based on the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage anomalies of the specified anomaly type includes: obtaining the sensitivity of each sampling point to voltage anomalies of the specified anomaly type based on the power supply distance between each sampling point and the voltage input interface on the target chip; wherein the voltage input interface is the interface through which the target chip receives power from the target power supply; in the case of an overvoltage anomaly, the sensitivity of the sampling point is negatively correlated with the power supply distance; in the case of an undervoltage anomaly, the sensitivity of the sampling point is positively correlated with the power supply distance; the overvoltage anomaly type indicates that the power supply voltage of the target chip is greater than the upper limit of the voltage threshold range of the target chip; the undervoltage anomaly type indicates that the power supply voltage of the target chip is less than the lower limit of the voltage threshold range of the target chip; the voltage threshold range is the voltage range allowed for normal operation of the target chip; and assigning the sampling weights based on the sensitivity. The step of allocating the sampling weights based on the sensitivity includes: obtaining a second constraint condition for the power supply voltage of the target chip, wherein the second constraint condition is that after adjusting the power supply voltage according to the sampling voltage of the target chip, the voltage of each of the plurality of sampling points falls within the voltage threshold range, and the difference between the first parameter value and the second parameter value is less than or equal to the target threshold, the first parameter value is the difference between the maximum voltage value of the sampling point and the upper limit of the voltage threshold range, and the second parameter value is the difference between the minimum voltage value of the sampling point and the lower limit of the voltage threshold range; and allocating sampling weights to each sampling point according to the sensitivity of each sampling point and the second constraint condition.

2. The method according to claim 1, characterized in that, The step of sampling voltage at the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip includes: The sampling resistors corresponding to the multiple sampling points in the initial sampling circuit are adjusted according to the sampling weight to obtain the target sampling circuit. The target sampling circuit includes multiple sampling lines for sampling the voltage of the multiple sampling points. One end of each sampling line is connected to one of the multiple sampling points, and the other end is connected to the same target output point. The sampling resistor corresponding to each sampling point is deployed on the corresponding sampling line. The resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller. The voltage at the target output point of the target sampling circuit is determined as the target chip sampling voltage.

3. The method according to claim 1, characterized in that, The plurality of sampling points includes a first sampling point, a second sampling point, and a third sampling point. The first sampling point is the maximum voltage point of the target chip, the second sampling point is the center point of the target chip, and the third sampling point is the minimum voltage point on the target chip. The initial sampling circuit includes a first sampling line, a second sampling line, and a third sampling line. One end of the first sampling line is connected to the first sampling point, one end of the second sampling line is connected to the second sampling point, and the other ends of the first, second, and third sampling lines are connected to the same target output point. A first sampling resistor is deployed between the first sampling point and the target output point on the first sampling line. A second sampling resistor is deployed between the second sampling point and the target output point on the second sampling line. A third sampling resistor is deployed between the third sampling point and the target output point on the third sampling line. The step of sampling the voltage of the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip includes: The first sampling resistor is adjusted according to the sampling weight assigned to the first sampling point, the second sampling resistor is adjusted according to the sampling weight assigned to the second sampling point, and the third sampling resistor is adjusted according to the sampling weight assigned to the third sampling point to obtain the target sampling circuit. The resistance value of the sampling resistor corresponding to the sampling point with the larger sampling weight is adjusted to be smaller. The voltage at the target output point of the target sampling circuit is determined as the target chip sampling voltage.

4. The method according to claim 1, characterized in that, The method of detecting the type of power supply voltage abnormality when an abnormality is detected in the target chip includes: If the power supply voltage of the target chip is detected to be greater than the upper limit of the voltage threshold range of the target chip, the abnormality type is determined to be an overvoltage abnormality type, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip; If the supply voltage of the target chip is detected to be less than the lower limit of the voltage threshold range of the target chip, the abnormality type is determined to be a low voltage abnormality type, wherein the voltage threshold range is the voltage range allowed for normal operation of the target chip.

5. A chip-powered control device, characterized in that, include: The detection module is used to detect the type of abnormality in the power supply voltage when an abnormality is detected in the power supply voltage of the target chip, wherein the power supply voltage is supplied to the target chip by the target power supply. The allocation module is used to allocate a sampling weight to each sampling point based on the sensitivity of each sampling point among multiple sampling points deployed on the target chip to voltage anomalies belonging to the anomaly type. The higher the sensitivity, the higher the allocated sampling weight. The sampling weight is used to indicate the proportion of the sampling point voltage of the corresponding sampling point in the chip sampling voltage of the target chip. A sampling module is used to sample the voltage of the plurality of sampling points according to the sampling weight to obtain the target chip sampling voltage of the target chip, wherein the target chip sampling voltage is used to provide the target power supply, and the target power supply is used to adjust the power supply voltage according to the target chip sampling voltage; The allocation module includes: a first determining unit, configured to determine the sensitivity of each sampling point to a voltage anomaly of the specified anomaly type based on the power supply distance between each sampling point and the voltage input interface on the target chip, wherein the voltage input interface is the interface through which the target chip receives power from the target power supply; in the case of an overvoltage anomaly, the sensitivity of the sampling point is negatively correlated with the power supply distance; in the case of an undervoltage anomaly, the sensitivity of the sampling point is positively correlated with the power supply distance; the overvoltage anomaly type indicates that the power supply voltage of the target chip is greater than the upper limit of the voltage threshold range of the target chip; the undervoltage anomaly type indicates that the power supply voltage of the target chip is less than the lower limit of the voltage threshold range of the target chip; the voltage threshold range is the voltage range allowed for normal operation of the target chip; and an allocation unit, configured to allocate the sampling weights based on the sensitivity. The allocation unit is further configured to: obtain a second constraint condition for the power supply voltage of the target chip, wherein the second constraint condition is that after adjusting the power supply voltage according to the sampled voltage of the target chip, the voltage of each of the plurality of sampled points falls within the voltage threshold range, and the difference between the first parameter value and the second parameter value is less than or equal to the target threshold, the first parameter value is the difference between the maximum voltage value of the sampled point and the upper limit of the voltage threshold range, and the second parameter value is the difference between the minimum voltage value of the sampled point and the lower limit of the voltage threshold range; and allocate a sampling weight to each sampled point according to the sensitivity of each sampled point and the second constraint condition.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 4.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 4.

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