A data processing method, apparatus, device, and medium

Abstract

The application discloses a data processing method, device and equipment and medium, and relates to the technical field of storage. In the method, the current value of the tail doorbell register of the target queue is modified only when it is detected that the space to be occupied by the current command information to be put into the queue is greater than the remaining capacity of the target queue, and the value of the tail doorbell register is not modified every time the current command information to be put into the queue is written into the target queue, so that the resource consumption caused by frequent modification of the doorbell register is reduced. After the current value of the tail doorbell register of the target queue is modified, the command information in the target queue is taken out at one time, and the current value of the head doorbell register of the target queue is modified, so that the command information is taken out as many times as possible, the central processing unit is notified to take the command information frequently, the occupied central processing unit resources are reduced, and the doorbell register and the central processing unit do not need to be frequently modified and notified, so that the command execution efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a method, apparatus, device and medium for data processing. Background Technology

[0002] Non-Volatile Memory Express (NVMe) is a logical device interface specification used to connect servers and storage devices. It can provide faster data transfer speeds and higher input / output (I / O) throughput to meet the needs of high-performance storage.

[0003] When executing a command compliant with the non-volatile memory protocol standard, the doorbell registers of the Submission Queue (SQ) and the Completion Queue (CQ) are modified whenever a command is written. This means that the doorbell registers of the Submission Queue and the Completion Queue are frequently modified. Furthermore, after the doorbell register of the Completion Queue is changed, requests are frequently sent to the Central Processing Unit (CPU), resulting in high resource consumption for executing a command compliant with the non-volatile memory protocol standard and a long process execution cycle.

[0004] Therefore, it is evident that reducing the number of times the doorbell register is modified during the execution of a command conforming to the non-volatile memory protocol standard, thereby reducing resource consumption and improving execution efficiency, is a technical problem that urgently needs to be solved by those in the field. Summary of the Invention

[0005] The purpose of this invention is to provide a data processing method, apparatus, device, and medium to solve the technical problem that existing methods modify the doorbell register too many times during the execution of a command conforming to the non-volatile memory protocol standard, which increases resource consumption and leads to a decrease in execution efficiency.

[0006] To solve the above-mentioned technical problems, the present invention provides a data processing method, comprising:

[0007] Before placing the command information to be placed into the corresponding target queue, obtain the remaining capacity of the target queue and the space to be occupied by the command information to be placed into the target queue in the target queue; wherein, the command information includes a command or a command return result, the target queue corresponding to the command is a submission queue, and the target queue corresponding to the command return result is a completion queue;

[0008] If the space to be occupied is less than or equal to the remaining capacity, the command information to be placed into the target queue is added to the target queue, and the current value of the tail bell register corresponding to the target queue is kept unchanged; return to the step of obtaining the remaining capacity of the target queue and the space to be occupied by the command information to be placed into the target queue before adding the command information to the target queue to the corresponding target queue.

[0009] If the space to be occupied is greater than the remaining capacity, modify the current value of the tail doorbell register of the target queue, retrieve the command information in the target queue at once, and modify the current value of the head doorbell register corresponding to the target queue; return to the step of obtaining the remaining capacity of the target queue and the space to be occupied by the command information to be placed in the target queue before putting the command information to be placed into the corresponding target queue.

[0010] On one hand, the command information is a command, the target queue is the submission queue, and the host includes a first controller and a first counter; the first controller obtains the remaining capacity of the submission queue by:

[0011] Get the preset number of commands to be added to the submission queue;

[0012] The number of commands in the submission queue is obtained by the first counter from the moment a command is started being placed into the submission queue.

[0013] Obtain a first difference between the preset number of commands to be placed in the submission queue and the number of commands in the submission queue obtained through the first counter;

[0014] The first difference is used as the remaining capacity of the submission queue;

[0015] The command information is the command return result, the target queue is the completion queue, and the memory includes a second controller and a second timer; the second controller obtains the remaining capacity of the completion queue by:

[0016] Obtain the preset number of command return results to be placed in the completed queue;

[0017] From the moment a command return result is started being added to the completion queue, the number of command return results in the completion queue is obtained through the second counter;

[0018] The second difference between the number of command return results to be placed in the preset completion queue and the number of command return results in the completion queue obtained by the second counter is calculated.

[0019] The second difference is taken as the remaining capacity of the completion queue.

[0020] On the other hand, the space to be occupied is the space to be occupied in the submission queue for the command currently to be placed into the queue, and the remaining capacity is the remaining capacity of the submission queue; modifying the current value of the tail doorbell register of the target queue, retrieving the command information from the target queue at once, and modifying the current value of the head doorbell register corresponding to the target queue include:

[0021] The first controller modifies the current value of the tail bell register of the submission queue. When the second controller detects that it has received a signal indicating that the current value of the tail bell register of the submission queue has changed, the second controller retrieves the commands in the submission queue and modifies the current value of the head bell register of the submission queue all at once.

[0022] The space to be occupied is the space to be occupied in the completion queue for the command return results currently to be placed in the queue, and the remaining capacity is the remaining capacity of the completion queue; modifying the current value of the tail doorbell register of the target queue, retrieving the command information in the target queue at once, and modifying the current value of the head doorbell register corresponding to the target queue include:

[0023] The second controller modifies the current value of the tail bell register of the completion queue, receives an interrupt signal that indicates the modification of the current value of the tail bell register of the completion queue, and notifies the first controller, based on the interrupt signal, to retrieve the command return results from the completion queue in one go and modify the current value of the head bell register of the completion queue.

[0024] On the other hand, after retrieving the command information from the target queue all at once, the method further includes:

[0025] The first controller obtains the current value of the head doorbell register and the current value of the tail doorbell register of the submission queue.

[0026] If the current value of the head doorbell register of the submission queue is the same as the current value of the tail doorbell register of the submission queue, then it is determined that the commands retrieved from the submission queue in one go have been completed; and the data on the first counter is cleared to zero.

[0027] The current value of the head doorbell register and the current value of the tail doorbell register of the completion queue are obtained through the second controller.

[0028] If the current value of the head doorbell register of the completion queue is the same as the current value of the tail doorbell register of the completion queue, then it is determined that the command return result is retrieved from the completion queue in one go; and the data on the second counter is cleared to zero.

[0029] On the other hand, the host includes a first timer; the memory includes a second timer; the first timer is connected to the first counter, and the second timer is connected to the second counter; the timing period of the first timer is from the current reset time of the first counter to the next reset time of the first counter; the timing period of the second timer is from the current reset time of the second counter to the next reset time of the second counter; after retrieving the command information from the target queue at once, the method further includes:

[0030] Obtain the first preset timing duration of the first timer and the second preset timing duration of the second timer;

[0031] If the first controller detects that the current timing duration of the first timer is greater than the first preset timing duration, and no clearing operation of the first counter occurs within the current timing duration, the first timer is controlled to trigger information for updating the tail bell register of the submission queue, and the step of modifying the current value of the tail bell register of the submission queue through the first controller is returned.

[0032] If the second controller detects that the current timing duration of the second timer is greater than the second preset timing duration, and no clearing operation of the second counter occurs within the current timing duration, the second timer is controlled to trigger information for updating the tail bell register of the completion queue, and the step of modifying the current value of the tail bell register of the completion queue through the second controller is returned.

[0033] On the other hand, before retrieving the command information from the target queue all at once, the method further includes:

[0034] Obtain the first processing efficiency of the host and the second processing efficiency of the memory;

[0035] Determine whether the first processing efficiency is less than the second processing efficiency;

[0036] If so, a first cache area for storing the retrieved command is set in the memory;

[0037] If not, a second buffer is set up in the host to store the return results of the retrieved commands.

[0038] On the other hand, after the first cache area is set in the memory, and the second controller retrieves all commands from the submission queue at once, the system further includes:

[0039] The commands retrieved from the submission queue are stored in the first cache area;

[0040] Commands are retrieved and processed sequentially from the first cache area according to the order of the commands.

[0041] The host computer sets up a second cache area. After notifying the first controller to retrieve the command return results from the completion queue all at once according to the interrupt signal, the method further includes:

[0042] The command return results retrieved from the completed queue are stored in the second cache area;

[0043] The command return results in the second cache area are processed in the order they are returned.

[0044] To address the aforementioned technical problems, the present invention also provides a data processing apparatus, comprising:

[0045] The acquisition module is used to acquire the remaining capacity of the target queue and the space to be occupied by the command information to be placed in the target queue before putting the command information to be placed into the corresponding target queue; wherein, the command information includes a command or a command return result, the target queue corresponding to the command is a submission queue, and the target queue corresponding to the command return result is a completion queue;

[0046] The judgment module is used to determine whether the space to be occupied is less than or equal to the remaining capacity; if yes, the placement and holding module is triggered; if no, the modification and retrieval module is triggered.

[0047] The insertion and holding module is used to insert the command information of the current queue to be inserted into the target queue, and keep the current value of the tail bell register corresponding to the target queue unchanged; and return to trigger the acquisition module;

[0048] The modification and retrieval module is used to modify the current value of the tail doorbell register of the target queue, retrieve the command information in the target queue at one time, and modify the current value of the head doorbell register corresponding to the target queue; then return to trigger the acquisition module.

[0049] To address the aforementioned technical problems, the present invention also provides a data processing apparatus, comprising:

[0050] Memory, used to store computer programs and data;

[0051] A processor is configured to execute the computer program and, when performing data processing, implement the above-described data processing method.

[0052] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned data processing method.

[0053] In the data processing method provided by this invention, before placing the command information to be placed into the queue into the corresponding target queue, if it is detected that the space occupied by the command information to be placed into the queue is less than or equal to the remaining capacity of the target queue, the command information to be placed into the queue is written into the target queue, and the current value of the tail bell register corresponding to the target queue remains unchanged; otherwise, the current value of the tail bell register corresponding to the target queue is modified, and the command information in the target queue is retrieved at once, and the current value of the head bell register corresponding to the target queue is modified.

[0054] The beneficial effects of this invention are as follows: First, when it is detected that the space occupied by the command information to be placed in the queue is less than the remaining capacity of the target queue, the command information to be placed in the queue is written into the target queue, keeping the current value of the tail doorbell register corresponding to the target queue unchanged. The current value of the tail doorbell register corresponding to the target queue is only modified when it is detected that the space occupied by the command information to be placed in the queue is greater than the remaining capacity of the target queue. That is, the operation of modifying the doorbell register multiple times is merged, and the value of the tail doorbell register is not modified every time the command information to be placed in the queue is written into the target queue, thus reducing the resource consumption caused by frequent modification of the doorbell register. Second, after modifying the current value of the tail doorbell register corresponding to the target queue, the command information in the target queue is retrieved and the current value of the head doorbell register corresponding to the target queue is modified at once. This avoids retrieving the command information multiple times, which would cause frequent triggering of the central processing unit to notify the host to retrieve the command information, thus reducing the central processing unit resources occupied. Moreover, during the command processing, since there is no need to frequently modify the doorbell register and frequently notify the central processing unit, the efficiency of command execution is greatly improved.

[0055] In addition, by setting counters in the host and memory, the remaining quantity of the target queue is determined based on the number of command information in the preset target queue and the number of the target queue counted by the counter, which improves the accuracy and efficiency of determining the remaining quantity.

[0056] After retrieving the command information from the target queue in one go, a judgment is made based on whether the current value of the head doorbell register and the tail doorbell register of the target queue are the same. If they are the same, it is determined that the command information from the target queue has been retrieved in one go, ensuring that the command information in the target queue is completely retrieved.

[0057] Timers are set in the host and memory respectively. Combined with the preset timing duration of the counter and the clearing operation of the counter, the value of the tail bell register of the target queue is updated by triggering the timer. This avoids the situation where the submission queue and the completion queue cannot reach their capacity limit in a short time when the command information is issued slowly, thus avoiding the waste of a long time in the waiting process.

[0058] Based on the host processing efficiency and the memory processor efficiency, cache areas are set in the host and memory. For commands with low processing efficiency, the retrieved command information is first stored in the cache area and waits for execution. The cache area balances the problem of command information blocking caused by the difference in execution efficiency between the host and memory.

[0059] In addition, the present invention also provides a data processing apparatus, a data processing device, and a computer-readable storage medium, which have the same or corresponding technical features as the data processing method mentioned above, and have the same effects. Attached Figure Description

[0060] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 A flowchart of a data processing method provided in an embodiment of the present invention;

[0062] Figure 2 A flowchart illustrating a method for a host to send commands to a memory, as provided in an embodiment of the present invention;

[0063] Figure 3 A flowchart illustrating a method for a memory to return a command result to a host, as provided in an embodiment of the present invention;

[0064] Figure 4 This is a schematic diagram illustrating the interaction between a host and a memory, provided as an embodiment of the present invention.

[0065] Figure 5 A structural diagram of a data processing apparatus provided according to an embodiment of the present invention;

[0066] Figure 6 A structural diagram of a data processing device provided in another embodiment of the present invention. Detailed Implementation

[0067] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0068] The core of this invention is to provide a data processing method, apparatus, device, and medium to solve the existing technical problem that the doorbell register is modified too many times during the execution of a command conforming to the non-volatile memory protocol standard, which increases resource consumption and leads to a decrease in execution efficiency.

[0069] NVMe is a logical device interface specification used to connect storage devices on computer motherboards that conform to the non-volatile memory protocol standard, such as Solid State Drives (SSDs), Peripheral Component Interconnect Express (PCIe) memory cards, and U.2 storage devices. As a new type of non-volatile storage interface used to connect servers and storage devices, it can provide faster data transfer speeds and higher input / output (I / O) throughput to meet the demands of high-performance storage. Due to its faster read / write speeds, higher capacity, lower power consumption, and higher reliability, it has gained increasing popularity among enterprise storage users in recent years, with more and more companies choosing NVMe to implement high-speed and reliable storage systems. The typical processing flow of an NVMe command is as follows: (1) The host puts the command into the submission queue; (2) The host updates the tail doorbell register of the submission queue and notifies the storage (NVMe hard disk) to retrieve the command; (3) The NVMe hard disk retrieves the command from the submission queue and processes it, and updates the head doorbell register of the submission queue; (4) After the NVMe hard disk completes the command, it puts the command return result into the completion queue and updates the tail doorbell register of the completion queue; (5) The host retrieves the command return result from the completion queue and updates the head doorbell register of the completion queue.

[0070] During the execution of an NVMe command, the doorbell registers of the commit queue and the completion queue are modified multiple times. Frequent modifications result in high resource consumption. Furthermore, after modifying the doorbell register of the completion queue, an interrupt request is sent to the CPU. Frequent modifications lead to excessive CPU resource consumption, affecting the CPU usage of other modules and resulting in poor execution efficiency and a longer overall execution cycle. To solve these technical problems, this embodiment of the invention controls the content written by managing the remaining capacity of the commit queue and the completion queue. This merges the doorbell register modifications that would normally require changes for each write operation, reducing resource consumption and consequently decreasing the frequency of interrupt requests to the CPU.

[0071] It should be noted that the method provided in this embodiment of the invention can be extended to data reading and writing of other protocols. When reading and writing uses two types of queues, such as submission queues and completion queues, for accessing input / output commands, the method provided in this embodiment of the invention can be used for processing. For example, in data reading using the Serial Attached SCSI (SAS) protocol, the relevant technical solution is to use an inbound queue (IQ) and an outbound queue (OQ) for issuing commands and responding to results. Modifications similar to those mentioned in this invention can be made to the inbound and outbound queues, setting relevant controllers and buffers, thereby optimizing the efficiency of data reading and writing in SAS, reducing the frequent modification of the doorbell register in the inbound and outbound queues, and resolving the problem of mismatched processing efficiency between the inbound and outbound queues.

[0072] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Figure 1 A flowchart of a data processing method provided in an embodiment of the present invention is shown below. Figure 1 As shown, the method includes:

[0073] S10: Before putting the command information to be put into the queue into the corresponding target queue, obtain the remaining capacity of the target queue and the space to be occupied by the command information to be put into the queue in the target queue.

[0074] S11: Determine whether the space to be occupied is less than or equal to the remaining capacity; if yes, proceed to step S12; if no, proceed to step S13.

[0075] S12: Add the command information of the current queue to the target queue, and keep the current value of the tail bell register corresponding to the target queue unchanged; return to step S10;

[0076] S13: Modify the current value of the tail bell register of the target queue, retrieve the command information in the target queue at once, and modify the current value of the head bell register corresponding to the target queue; return to step S10.

[0077] It should be noted that this embodiment of the invention pertains to input / output (IO) commands in NVMe commands. In this embodiment, command information includes the command or command return result. The target queue corresponding to the command is the submission queue, and the target queue corresponding to the command return result is the completion queue. The host sends a command to the command submission queue and updates the value of the doorbell register of the submission queue. This serves two purposes: firstly, the value of the doorbell register records the command; secondly, updating the value of the submission queue notifies the memory to retrieve the command. The memory retrieves the command from the submission queue, processes it, and updates the head doorbell register of the submission queue. After executing the command, the memory places the command return result into the completion queue and updates the head doorbell register of the completion queue. The host retrieves the command return result from the completion queue and updates the head doorbell register of the completion queue.

[0078] To reduce the number of times the doorbell register needs to be modified, in this embodiment of the invention, before placing the command information currently to be placed into the corresponding target queue, the remaining capacity of the target queue and the space to be occupied by the command information currently to be placed into the target queue are first obtained. The remaining capacity of the target queue can be represented by the number of input / output commands that the target queue can still hold, or the number of results returned by the input / output commands; the space to be occupied by the command information currently to be placed into the target queue can be represented by the number of command information currently to be placed into the target queue.

[0079] After obtaining the remaining capacity and the space occupied by the currently pending command information in the target queue, the remaining capacity and the space occupied by the currently pending command information in the target queue are compared. If the space occupied is less than or equal to the remaining capacity, the currently pending command information can be placed into the corresponding target queue. Simultaneously, to reduce the number of times the doorbell register is modified, the current value of the tail doorbell register of the target queue remains unchanged, and the process continues to wait for the next pending command information, repeating the above process. If the space occupied is greater than the remaining capacity, the remaining capacity is insufficient to accommodate the currently pending command information. Therefore, the current value of the tail doorbell register of the target queue must be modified, and the command information is retrieved from the host or memory. During retrieval, the command information in the target queue is retrieved at once, and the current value of the corresponding head doorbell register of the target queue is modified. After retrieving the command information from the target queue, the process returns to the steps of obtaining the remaining capacity and the space occupied by the currently pending command information in the target queue.

[0080] Specifically, if the remaining capacity is 5 input / output commands, and there are currently 3 input / output commands waiting to be added to the queue, the space to be occupied is less than the remaining capacity. Therefore, the 3 input / output commands to be added to the queue can be placed into the submission queue. To reduce the number of times the tail bell register of the submission queue is frequently modified, the value of the tail bell register of the submission queue is not modified after the 3 input / output commands to be added to the submission queue. That is, the current value of the tail bell register of the submission queue remains unchanged, and it continues to wait for new input / output commands to be added to the queue. If the remaining capacity is 5 input / output commands, and there are currently 7 input / output commands waiting to be added to the queue, the space to be occupied is greater than the remaining capacity. Therefore, the 7 input / output commands to be added to the queue cannot be placed into the submission queue. Therefore, the value of the tail bell register of the submission queue is modified first, and the commands in the submission queue are retrieved from the submission queue all at once through memory. The current value of the head bell register corresponding to the submission queue is also modified.

[0081] In practice, after steps S12 and S13, a timeout mechanism can be set so that if no new command or new command result is received within a certain period of time, it is not necessary to return to step S10.

[0082] In the method provided by this invention, firstly, when it is detected that the space occupied by the command information to be placed in the queue is less than the remaining capacity of the target queue, the command information to be placed in the queue is written into the target queue, keeping the current value of the tail doorbell register corresponding to the target queue unchanged. The current value of the tail doorbell register corresponding to the target queue is modified only when it is detected that the space occupied by the command information to be placed in the queue is greater than the remaining capacity of the target queue. That is, the operation of modifying the doorbell register multiple times is merged, and the value of the tail doorbell register is not modified every time the command information to be placed in the queue is written into the target queue, thus reducing the resource consumption caused by frequent modification of the doorbell register. Secondly, after modifying the current value of the tail doorbell register corresponding to the target queue, the command information in the target queue is retrieved and the current value of the head doorbell register corresponding to the target queue is modified at once. This avoids retrieving the command information multiple times, which would cause frequent triggering of the central processing unit to notify the host to retrieve the command information, thus reducing the central processing unit resources occupied. Moreover, during the command processing, since there is no need to frequently modify the doorbell register and frequently notify the central processing unit, the efficiency of command execution is greatly improved.

[0083] The command information is a command, the target queue is the submission queue, and the host includes a first controller and a first counter; the first controller obtains the remaining capacity of the submission queue by:

[0084] Get the number of commands waiting to be added to the preset submission queue;

[0085] The number of commands in the submission queue is obtained from the first counter, starting from when commands are first put into the submission queue;

[0086] Get the first difference between the number of commands to be added to the preset submission queue and the number of commands in the submission queue obtained by the first counter;

[0087] Use the first difference as the remaining capacity of the submission queue;

[0088] The command information is the command return result, the target queue is the completion queue, and the memory includes a second controller and a second timer; the second controller obtains the remaining capacity of the completion queue by:

[0089] Retrieve the number of command return results in the preset completion queue;

[0090] From the moment a command return result is started being added to the completion queue, the number of command return results in the completion queue is obtained through a second counter;

[0091] Get the second difference between the number of command return results to be added to the preset completion queue and the number of command return results in the completion queue obtained by the second counter;

[0092] The second difference is used as the remaining capacity of the completion queue.

[0093] In the method provided in this embodiment, a counter is set in the host and the memory, and the remaining quantity of the target queue is determined according to the number of command information in the preset target queue and the number in the target queue counted by the counter, which improves the accuracy and efficiency of determining the remaining quantity.

[0094] The space to be occupied is the space in the submission queue that the command currently waiting to be placed into the queue will occupy, and the remaining capacity is the remaining capacity of the submission queue; modifying the current value of the tail doorbell register of the target queue, retrieving the command information from the target queue at once, and modifying the current value of the head doorbell register corresponding to the target queue include:

[0095] The first controller modifies the current value of the tail bell register of the submission queue. When the second controller detects that it has received a signal indicating that the current value of the tail bell register of the submission queue has changed, the second controller retrieves the commands in the submission queue and modifies the current value of the head bell register of the submission queue all at once.

[0096] The space to be occupied is the space in the completion queue for the return results of commands currently to be placed in the queue, and the remaining capacity is the remaining capacity of the completion queue; modifying the current value of the tail doorbell register of the target queue, retrieving command information from the target queue at once, and modifying the current value of the head doorbell register corresponding to the target queue include:

[0097] The second controller modifies the current value of the tail bell register of the completion queue, receives the interrupt signal issued to indicate the modification of the current value of the tail bell register of the completion queue, and notifies the first controller to retrieve the command return results from the completion queue in one go and modify the current value of the head bell register of the completion queue according to the interrupt signal.

[0098] After retrieving the command information, to ensure that all command information in the target queue is retrieved as completely as possible, the process after retrieving all command information from the target queue at once also includes:

[0099] The current value of the head doorbell register and the current value of the tail doorbell register of the submission queue are obtained through the first controller.

[0100] If the current value of the head doorbell register of the submission queue is the same as the current value of the tail doorbell register of the submission queue, then it is determined that the commands retrieved from the submission queue in one go have been completed; and the data on the first counter is cleared to zero.

[0101] The current value of the head doorbell register and the current value of the tail doorbell register of the completed queue are obtained through the second controller.

[0102] If the current value of the head doorbell register of the completion queue is the same as the current value of the tail doorbell register of the completion queue, then it is determined that the command in the completion queue is retrieved all at once and the result is returned; and the data on the second counter is cleared to zero.

[0103] In practice, specifically, to process the command information in the submission queue and completion queue of input / output commands, a first controller is set up on the host side, and a second controller is set up on the memory side. The first controller is responsible for monitoring the writing of input / output commands, reading the return results of input / output commands, and modifying the tail doorbell register of the submission queue and the head doorbell register of the completion queue; the second controller is responsible for monitoring the writing of the completion results of input / output commands, reading input / output commands, and modifying the head doorbell register of the submission queue and the tail doorbell register of the completion queue.

[0104] Figure 2 A flowchart illustrating a method for a host to send commands to a memory, as provided in an embodiment of the present invention, is shown below. Figure 2 As shown, the method includes:

[0105] S14: The first controller checks the submission queue capacity to determine if it can accommodate the upcoming commands; if yes, proceed to step S15; if no, proceed to step S16.

[0106] S15: The host places the command into the commit queue, keeping the tail bell register of the commit queue unchanged; return to step S14;

[0107] S16: Modify the tail bell register of the submission queue to notify the memory to fetch commands;

[0108] S17: The second controller calculates the number of submissions in the queue, retrieves them all at once, modifies the head bell register of the submission queue, and returns to step S14.

[0109] Figure 3 A flowchart illustrating a method for a memory to return command results to a host, as provided in an embodiment of the present invention, is shown below. Figure 3 As shown, the method includes:

[0110] S18: The second controller checks the completion queue capacity to determine if it can accommodate the upcoming command return results; if yes, proceed to step S19; if no, proceed to step S20.

[0111] S19: The second controller puts the command return result into the completion queue, keeping the tail bell register of the completion queue unchanged; return to step S18;

[0112] S20: Modify the tail bell register of the completed queue to notify the host to retrieve the command;

[0113] S21: The first controller calculates the number of queues completed this time, retrieves them all at once, modifies the head bell register of the completed queue, and returns to step S18.

[0114] Before the host puts a command into the submission queue, the first controller calculates the remaining capacity of the submission queue using a built-in counter. If the capacity is sufficient to accommodate the current command, the host is allowed to put the command into the submission queue without changing the tail bell register of the submission queue. When the capacity is insufficient to accommodate the current command, the tail bell register of the submission queue is modified to notify the memory to retrieve the command from the submission queue for processing.

[0115] If the second controller in the memory detects a change in the tail bell register of the submission queue, it will retrieve all commands in the submission queue at once, modify the head bell register of the submission queue, and execute them sequentially.

[0116] When the first controller detects that the contents of the head bell register and the tail bell register of the submission queue are the same, it considers the submission queue to be empty, clears the counter in the first controller to zero, and starts counting again.

[0117] After the command is executed, the memory will put the command return result into the completion queue. The second controller will use a built-in counter to calculate whether the remaining capacity of the completion queue can support the addition of the command return result. If the capacity is sufficient, the command return result will be put into the completion queue. If the capacity is insufficient, the tail bell register of the completion queue will be modified to notify the host to retrieve the command return result from the completion queue.

[0118] When the central processing unit receives an interrupt indicating that the tail bell register of the completion queue has been modified, the host computer retrieves the results returned by the commands in the completion queue all at once and modifies the head bell register of the completion queue.

[0119] When the second controller detects that the contents of the completed head bell register and the tail bell register are the same, it considers the current completed queue to be empty, clears the counter in the second register to zero, and starts counting again.

[0120] In the method provided in this embodiment, after retrieving the command information from the target queue in one go, a judgment is made based on whether the current value of the head doorbell register and the current value of the tail doorbell register of the target queue are the same. If they are the same, it is determined that the command information from the target queue has been retrieved in one go, ensuring that the command information in the target queue is completely retrieved.

[0121] To prevent the submission and completion queues from failing to reach their capacity limits in a short time when input / output commands are issued slowly, thus avoiding wasting a significant amount of time waiting, in some embodiments, the host includes a first timer; the memory includes a second timer; the first timer is connected to a first counter, and the second timer is connected to a second counter; the timing period of the first timer is from the current reset time of the first counter to the next reset time of the first counter; the timing period of the second timer is from the current reset time of the second counter to the next reset time of the second counter; after retrieving the command information from the target queue all at once, the system further includes:

[0122] Obtain the first preset timing duration of the first timer and the second preset timing duration of the second timer;

[0123] If the first controller detects that the current timing duration of the first timer is greater than the first preset timing duration, and no clearing operation of the first counter occurs within the current timing duration, the first timer is controlled to trigger information used to represent the update of the tail bell register of the submission queue, and the step of modifying the current value of the tail bell register of the submission queue through the first controller is returned.

[0124] If the second controller detects that the current timing duration of the second timer is greater than the second preset timing duration, and no clearing operation of the second counter occurs within the current timing duration, the second timer is controlled to trigger information used to represent the tail bell register of the completed queue, and the step of modifying the current value of the tail bell register of the completed queue through the second controller is returned.

[0125] It should be noted that the counters and timers described above can be built into the corresponding controller or can be set independently of the controller. For example, the first controller has a built-in first counter and a first timer; the second controller has a built-in second counter and a second timer.

[0126] In the method provided in this embodiment, timers are set in the host and memory. If no corresponding counter reset operation occurs before the timer reaches its set maximum value, the timer sends a signal to update the tail bell register of the submission queue and the tail bell register of the completion queue. The operation after the bell register is updated is the same as the steps described above, and will not be repeated here. The method provided in this embodiment can prevent the submission queue and completion queue from failing to reach their capacity limits in a short time when input / output command information is issued slowly, thus avoiding wasting a long time in the waiting process. Each counter update triggers the corresponding timer update, recalculating the time period.

[0127] In implementation, the inconsistency in execution efficiency between the host and memory sides can lead to command information blocking. To balance this inconsistency, some embodiments include, before retrieving all command information from the target queue at once:

[0128] Obtain the host's first processing efficiency and the memory's second processing efficiency;

[0129] Determine whether the efficiency of the first processing step is less than the efficiency of the second processing step;

[0130] If so, then a first cache area is set in the memory to store the retrieved command;

[0131] If not, a second buffer is set up in the host to store the results returned by the retrieved command.

[0132] After setting up a first cache area in the memory, and after the second controller retrieves all commands from the submission queue at once, it also includes:

[0133] The commands retrieved from the submission queue are stored in the first cache area;

[0134] Commands are retrieved and processed sequentially from the first cache area in the order of the commands.

[0135] After the host computer sets up a second buffer area and, based on the interrupt signal, notifies the first controller to retrieve the command return results from the completion queue all at once, it also includes:

[0136] The command return results retrieved from the completed queue are stored in the second cache area;

[0137] The command return results in the second cache area are processed in the order they are returned.

[0138] Based on the embodiments described above, this embodiment adds a cache area on the host side and the memory side to store the command return results retrieved from the completion queue at once, as well as the commands retrieved from the submission queue at once. Figure 4 This is a schematic diagram illustrating the interaction between a host and a memory, provided as an embodiment of the present invention. Figure 4 As shown, a first controller and a host cache are set in host 1, and a second controller and a memory cache are set in memory 2.

[0139] The caching mechanism provided in this embodiment is beneficial for handling situations where the host and storage sides cannot quickly process command return results and commands retrieved in one go. It temporarily stores this content in a cache area, waiting for resources to become idle before processing it. It also allows for the timely release of occupied completion and submission queue resources, thus improving the efficiency of NVMe command processing. The entire process from the host issuing a command to the host receiving the command return result includes the following steps:

[0140] (1) A first controller and a second controller are set on the host side and the memory side, and a host cache area is set outside the first controller and a memory cache area is set outside the second controller.

[0141] (2) Before the host puts a command into the submission queue, the first controller will calculate the remaining capacity of the submission queue through the built-in counter. If the capacity is sufficient to accommodate the current command, the host is allowed to put the command into the submission queue without changing the tail bell register of the submission queue. When the capacity is insufficient to accommodate the current command, the tail bell register of the submission queue is modified to notify the memory to retrieve the command in the submission queue for processing.

[0142] (3) If the memory detects a change in the tail bell register of the submission queue, it will retrieve all commands in the submission queue at once and modify the head bell register of the submission queue.

[0143] (4) The retrieved commands will first enter the memory cache, and then the memory will sequentially retrieve and execute the commands in the memory cache.

[0144] (5) When the first controller detects that the contents of the head bell register and the tail bell register of the submission queue are the same, it considers the submission queue to be empty, clears the counter in the first controller to zero, and starts counting again.

[0145] (6) After the command is executed, the memory will put the command return result into the completion queue. The second controller will use the built-in counter to calculate whether the remaining capacity of the completion queue supports the addition of the command return result. If the capacity is sufficient, the command return result will be put into the completion queue. If the capacity is insufficient, the tail bell register of the completion queue will be modified to notify the host to retrieve the command return result in the completion queue.

[0146] (7) When the central processing unit receives the interrupt from the tail doorbell register of the completion queue, the host retrieves the commands in the completion queue at once and returns the results, and modifies the head doorbell register of the completion queue.

[0147] (8) The host will store the command return results retrieved from the queue into the host cache and wait for the central processing unit to process the command return results in the host cache.

[0148] (9) When the second controller detects that the contents of the head bell register and the tail bell register of the completed queue are the same, it considers the completed queue to be empty, clears the counter in the second register to zero, and starts counting again.

[0149] (10) Set timers in the first controller and the second controller. The main responsibility is to issue an update to the tail bell register of the submission queue and the tail bell register of the completion queue when the counter is cleared before the timer reaches the upper limit. Subsequent operations are the same as the above steps.

[0150] (11) The counter and timer in the controller are bound together. When the counter is cleared and updated, the timer will also be cleared and the cycle will start again.

[0151] The method provided in this embodiment is applicable to situations where the processing efficiency of the host side and the memory side is inconsistent. For example, when the host side has high processing efficiency but the memory side has low processing efficiency, commands in the submission queue may not be consumed in time, and the results of completed commands in the queue may not be replenished in time, easily causing queue blocking, resulting in poor execution efficiency and long cycles. Therefore, by setting up cache areas on the host side and the memory side, when commands in the submission queue are blocked, the retrieved commands can be pre-stored in the cache area on the memory side, waiting for the memory to complete its execution, without affecting the subsequent addition of commands from the host to the submission queue. When the host side has low processing efficiency but the memory side has high processing efficiency, the host side cache area set up by this method comes into play, which can balance the inconsistent execution efficiency between the two sides.

[0152] The technical solution proposed in this embodiment of the invention sets up a first controller and a second controller, thereby merging multiple modifications to the doorbell register of the queue and modifying the doorbell register only when the queue is about to be full. This reduces the frequent interrupt requests caused by doorbell register modifications, thereby reducing resource consumption, improving execution efficiency, and improving overall runtime.

[0153] In the above embodiments, the data processing method has been described in detail. The present invention also provides embodiments corresponding to a data processing apparatus and a data processing device. It should be noted that the embodiments of the apparatus portion are described from two perspectives: one based on functional modules, and the other based on hardware.

[0154] Figure 5 This is a structural diagram of a data processing apparatus provided according to an embodiment of the present invention. This embodiment, based on functional modules, includes:

[0155] The acquisition module 10 is used to acquire the remaining capacity of the target queue and the space to be occupied by the command information to be put into the target queue before putting the command information to be put into the queue into the corresponding target queue; wherein, the command information includes the command or the command return result, the target queue corresponding to the command is the submission queue, and the target queue corresponding to the command return result is the completion queue.

[0156] The judgment module 11 is used to determine whether the space to be occupied is less than or equal to the remaining capacity; if yes, the insertion and holding module 12 is triggered; if no, the modification and retrieval module 13 is triggered.

[0157] The insertion and holding module 12 is used to insert the command information of the queue to be inserted into the target queue and keep the current value of the tail bell register corresponding to the target queue unchanged; return to the trigger acquisition module 10;

[0158] The modification and retrieval module 13 is used to modify the current value of the tail doorbell register of the target queue, retrieve the command information in the target queue at one time, and modify the current value of the head doorbell register corresponding to the target queue; then return to the trigger acquisition module 10.

[0159] In one embodiment, the command information is a command, the target queue is a submission queue, and the host includes a first controller and a first counter;

[0160] The data processing apparatus further includes a first acquisition module, used to acquire the remaining capacity of the submission queue through a first controller. The first acquisition module specifically includes:

[0161] The second acquisition module is used to acquire the number of commands waiting to be placed in the preset submission queue;

[0162] The third acquisition module is used to acquire the number of commands in the submission queue from the beginning of putting commands into the submission queue using the first counter.

[0163] The fourth acquisition module is used to obtain the first difference between the number of commands to be put into the preset submission queue and the number of commands in the submission queue obtained by the first counter;

[0164] The first module is used to take the first difference as the remaining capacity of the submission queue;

[0165] The command information is the command return result, the target queue is the completion queue, and the memory includes a second controller and a second timer; the data processing device also includes a fifth acquisition module, used to acquire the remaining capacity of the completion queue through the second controller; the fifth acquisition module specifically includes:

[0166] The sixth acquisition module is used to acquire the number of command return results to be added to the preset completion queue;

[0167] The seventh acquisition module is used to acquire the number of command return results in the completion queue through the second counter, starting from the time the command return results are put into the completion queue.

[0168] The eighth acquisition module is used to acquire the second difference between the number of command return results to be put into the preset completion queue and the number of command return results in the completion queue obtained by the second counter;

[0169] The second module is used to take the second difference as the remaining capacity of the completion queue.

[0170] The space to be occupied is the space in the submission queue that the command currently waiting to be added to the queue will occupy, and the remaining capacity is the remaining capacity of the submission queue; the modification and retrieval module 13 specifically includes:

[0171] The first modification and retrieval module is used to modify the current value of the tail bell register of the submission queue through the first controller. When the second controller detects that the second controller has received a signal indicating that the current value of the tail bell register of the submission queue has changed, the second controller retrieves the command in the submission queue and modifies the current value of the head bell register of the submission queue at one time.

[0172] The space to be occupied is the space in the completion queue for the command return results currently to be added to the queue, and the remaining capacity is the remaining capacity of the completion queue; the modification and retrieval module 13 specifically includes:

[0173] The second modification and retrieval module is used to modify the current value of the tail bell register of the completion queue through the second controller, receive the interrupt signal issued to indicate the modification of the current value of the tail bell register of the completion queue, and notify the first controller to retrieve the command return result in the completion queue in one go and modify the current value of the head bell register of the completion queue according to the interrupt signal.

[0174] The data processing apparatus also includes:

[0175] The ninth acquisition module is used to acquire the current value of the head doorbell register and the current value of the tail doorbell register of the submission queue through the first controller;

[0176] The first determination and clearing module is used to determine that the commands in the submission queue have been retrieved from the submission queue in one go if the current value of the head doorbell register of the submission queue is the same as the current value of the tail doorbell register of the submission queue; and to clear the data on the first counter.

[0177] The ninth acquisition module is used to acquire the current value of the head doorbell register and the tail doorbell register of the completed queue through the second controller;

[0178] The second determination and clearing module determines that if the current value of the head doorbell register of the completion queue is the same as the current value of the tail doorbell register of the completion queue, it determines that the completion queue has been completed and retrieves the command from the completion queue at once to return the result; and clears the data on the second counter to zero.

[0179] In one embodiment, the host includes a first timer; the memory includes a second timer; the first timer is connected to a first counter, and the second timer is connected to a second counter; the timing period of the first timer is from the current reset time of the first counter to the next reset time of the first counter; the timing period of the second timer is from the current reset time of the second counter to the next reset time of the second counter.

[0180] The data processing apparatus also includes:

[0181] The tenth acquisition module is used to acquire the first preset timing duration of the first timer and the second preset timing duration of the second timer.

[0182] The first control module is used to control the first timer to trigger information in the tail bell register used to represent the update of the submission queue when the first controller detects that the current timing duration of the first timer is greater than the first preset timing duration and no clearing operation of the first counter occurs within the current timing duration, and then return to trigger the first modification and retrieval module.

[0183] The second control module, when the second controller detects that the current timing duration of the second timer is greater than the second preset timing duration, and no clearing operation of the second counter occurs within the current timing duration, controls the second timer to trigger the information of the tail bell register used to represent the update completion queue, and returns to trigger the second modification and retrieval module.

[0184] The data processing apparatus also includes:

[0185] The eleventh acquisition module is used to acquire the host's first processing efficiency and the memory's second processing efficiency.

[0186] The first judgment module is used to determine whether the first processing efficiency is less than the second processing efficiency; if yes, the first setting module is triggered; if no, the second setting module is triggered.

[0187] The first setting module is used to set a first cache area in the memory for storing the retrieved commands;

[0188] The second configuration module is used to configure a second buffer in the host for storing the returned results of the retrieved commands.

[0189] The memory includes a first cache region, and the data processing apparatus further includes:

[0190] The first storage module is used to store the commands retrieved from the submission queue in the first cache area;

[0191] The first retrieval and processing module is used to retrieve and process commands sequentially from the first cache area according to the order of the commands.

[0192] The host computer has a second cache area, and the data processing device also includes:

[0193] The second storage module is used to store the command return results retrieved from the completion queue in the second cache area;

[0194] The second retrieval and processing module processes the command return results in the second cache area according to the order of command return results.

[0195] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0196] Figure 6 This is a structural diagram of a data processing device provided according to another embodiment of the present invention. This embodiment is based on a hardware perspective, such as... Figure 6 As shown, the data processing equipment includes:

[0197] Memory 20 is used to store computer programs and data;

[0198] The processor 21 is configured to execute computer programs and, when performing data processing, implement the steps of the data processing method as described in the above embodiments.

[0199] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0200] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the data processing method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the data processing method mentioned above.

[0201] In some embodiments, the data processing device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0202] Those skilled in the art will understand that Figure 6The structure shown does not constitute a limitation on the data processing device and may include more or fewer components than illustrated.

[0203] The data processing device provided in this embodiment of the invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: the data processing method has the same effect as above.

[0204] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0205] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0206] The computer-readable storage medium provided by this invention includes the data processing method mentioned above, and has the same effect.

[0207] The present invention has provided a detailed description of a data processing method, apparatus, device, and medium. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0208] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A data processing method, characterized in that, include: Before placing the command information to be placed into the corresponding target queue, obtain the remaining capacity of the target queue and the space to be occupied by the command information to be placed into the target queue in the target queue; wherein, the command information includes a command or a command return result, the target queue corresponding to the command is a submission queue, and the target queue corresponding to the command return result is a completion queue; If the space to be occupied is less than or equal to the remaining capacity, the command information to be placed into the target queue is added to the target queue, and the current value of the tail bell register corresponding to the target queue is kept unchanged; return to the step of obtaining the remaining capacity of the target queue and the space to be occupied by the command information to be placed into the target queue before adding the command information to the target queue to the corresponding target queue. If the space to be occupied is greater than the remaining capacity, modify the current value of the tail doorbell register of the target queue, retrieve the command information in the target queue at once, and modify the current value of the head doorbell register corresponding to the target queue; return to the step of obtaining the remaining capacity of the target queue and the space to be occupied by the command information to be placed in the target queue before putting the command information to be placed into the corresponding target queue. The command information is a command, the target queue is the submission queue, and the host includes a first controller and a first counter; the first controller obtains the remaining capacity of the submission queue by: Get the preset number of commands to be added to the submission queue; The number of commands in the submission queue is obtained by the first counter from the moment a command is started being placed into the submission queue. Obtain a first difference between the preset number of commands to be placed in the submission queue and the number of commands in the submission queue obtained through the first counter; The first difference is used as the remaining capacity of the submission queue; The command information is the command return result, the target queue is the completion queue, and the memory includes a second controller and a second counter; the second controller obtains the remaining capacity of the completion queue by: Obtain the preset number of command return results to be placed in the completed queue; From the moment a command return result is started being added to the completion queue, the number of command return results in the completion queue is obtained through the second counter; The second difference between the number of command return results to be placed in the preset completion queue and the number of command return results in the completion queue obtained by the second counter is calculated. The second difference is taken as the remaining capacity of the completion queue.

2. The data processing method according to claim 1, characterized in that, The space to be occupied is the space to be occupied by the command currently to be placed in the queue in the submission queue, and the remaining capacity is the remaining capacity of the submission queue; modifying the current value of the tail doorbell register of the target queue, retrieving the command information in the target queue at once, and modifying the current value of the head doorbell register corresponding to the target queue include: The first controller modifies the current value of the tail bell register of the submission queue. When the second controller detects that it has received a signal indicating that the current value of the tail bell register of the submission queue has changed, the second controller retrieves the commands in the submission queue and modifies the current value of the head bell register of the submission queue all at once. The space to be occupied is the space to be occupied in the completion queue for the command return results currently to be placed in the queue, and the remaining capacity is the remaining capacity of the completion queue; modifying the current value of the tail doorbell register of the target queue, retrieving the command information in the target queue at once, and modifying the current value of the head doorbell register corresponding to the target queue include: The second controller modifies the current value of the tail bell register of the completion queue, receives an interrupt signal that indicates the modification of the current value of the tail bell register of the completion queue, and notifies the first controller, based on the interrupt signal, to retrieve the command return results from the completion queue in one go and modify the current value of the head bell register of the completion queue.

3. The data processing method according to claim 2, characterized in that, After retrieving the command information from the target queue all at once, the method further includes: The first controller obtains the current value of the head doorbell register and the current value of the tail doorbell register of the submission queue. If the current value of the head doorbell register of the submission queue is the same as the current value of the tail doorbell register of the submission queue, then it is determined that the commands retrieved from the submission queue in one go have been completed; and the data on the first counter is cleared to zero. The current value of the head doorbell register and the current value of the tail doorbell register of the completion queue are obtained through the second controller. If the current value of the head doorbell register of the completion queue is the same as the current value of the tail doorbell register of the completion queue, then it is determined that the command return result is retrieved from the completion queue in one go; and the data on the second counter is cleared to zero.

4. The data processing method according to claim 2 or 3, characterized in that, The host includes a first timer; the memory includes a second timer; the first timer is connected to the first counter, and the second timer is connected to the second counter; the timing period of the first timer is from the current reset time of the first counter to the next reset time of the first counter; the timing period of the second timer is from the current reset time of the second counter to the next reset time of the second counter. After retrieving the command information from the target queue all at once, the method further includes: Obtain the first preset timing duration of the first timer and the second preset timing duration of the second timer; If the first controller detects that the current timing duration of the first timer is greater than the first preset timing duration, and no clearing operation of the first counter occurs within the current timing duration, the first timer is controlled to trigger information for updating the tail bell register of the submission queue, and the step of modifying the current value of the tail bell register of the submission queue through the first controller is returned. If the second controller detects that the current timing duration of the second timer is greater than the second preset timing duration, and no clearing operation of the second counter occurs within the current timing duration, the second timer is controlled to trigger information for updating the tail bell register of the completion queue, and the step of modifying the current value of the tail bell register of the completion queue through the second controller is returned.

5. The data processing method according to claim 2, characterized in that, Before retrieving the command information from the target queue all at once, the method further includes: Obtain the first processing efficiency of the host and the second processing efficiency of the memory; Determine whether the first processing efficiency is less than the second processing efficiency; If so, a first cache area for storing the retrieved command is set in the memory; If not, a second buffer is set up in the host to store the return results of the retrieved commands.

6. The data processing method according to claim 5, characterized in that, The memory establishes the first cache area. After the second controller retrieves all commands from the submission queue at once, the system further includes: The commands retrieved from the submission queue are stored in the first cache area; Commands are retrieved and processed sequentially from the first cache area according to the order of the commands. The host computer sets up a second cache area. After notifying the first controller to retrieve the command return results from the completion queue all at once according to the interrupt signal, the method further includes: The command return results retrieved from the completed queue are stored in the second cache area; The command return results in the second cache area are processed in the order they are returned.

7. A data processing apparatus, characterized in that, include: The acquisition module is used to acquire the remaining capacity of the target queue and the space to be occupied by the command information to be placed in the target queue before putting the command information to be placed into the corresponding target queue; wherein, the command information includes a command or a command return result, the target queue corresponding to the command is a submission queue, and the target queue corresponding to the command return result is a completion queue; The judgment module is used to determine whether the space to be occupied is less than or equal to the remaining capacity; if yes, the placement and holding module is triggered; if no, the modification and retrieval module is triggered. The insertion and holding module is used to insert the command information of the current queue to be inserted into the target queue, and keep the current value of the tail bell register corresponding to the target queue unchanged; and return to trigger the acquisition module; The modification and retrieval module is used to modify the current value of the tail doorbell register of the target queue, retrieve the command information in the target queue at once, and modify the current value of the head doorbell register corresponding to the target queue; then return to trigger the acquisition module. The command information is the command, the target queue is the submission queue, and the host includes the first controller and the first counter; The data processing apparatus further includes a first acquisition module, used to acquire the remaining capacity of the submission queue through a first controller. The first acquisition module specifically includes: The second acquisition module is used to acquire the number of commands waiting to be placed in the preset submission queue; The third acquisition module is used to acquire the number of commands in the submission queue from the beginning of putting commands into the submission queue using the first counter. The fourth acquisition module is used to obtain the first difference between the number of commands to be put into the preset submission queue and the number of commands in the submission queue obtained by the first counter; The first module is used to take the first difference as the remaining capacity of the submission queue; The command information is the command return result, the target queue is the completion queue, and the memory includes a second controller and a second counter; the data processing device also includes a fifth acquisition module, used to acquire the remaining capacity of the completion queue through the second controller; the fifth acquisition module specifically includes: The sixth acquisition module is used to acquire the number of command return results to be added to the preset completion queue; The seventh acquisition module is used to acquire the number of command return results in the completion queue through the second counter, starting from the time the command return results are put into the completion queue. The eighth acquisition module is used to acquire the second difference between the number of command return results to be put into the preset completion queue and the number of command return results in the completion queue obtained by the second counter; The second module is used to take the second difference as the remaining capacity of the completion queue.

8. A data processing device, characterized in that, include: Memory, used to store computer programs and data; A processor for executing the computer program and, when performing data processing, implementing the steps of the data processing method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data processing method as described in any one of claims 1 to 6.

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