A cache scheduling module verification method based on a UVM verification platform

Abstract

The application discloses a Cache scheduling module verification method based on a UVM verification platform and belongs to the technical field of digital chip verification.The verification method proposed by the application can guarantee that the internal state machine of the RM and the internal state machine of the DUT are synchronous by checking the state of the internal state machine of the RM when the DUT receives the excitation, simultaneously generating corresponding jumps, so that the RM has no delay, and a large number of DUT internal signals are not needed, and only the interface signals or a small number of DUT interface read-write completion signals are needed to realize the synchronization, thereby avoiding the problem of difficulty in building the Cycle level RM, simultaneously solving the problem of high coupling of the platform and the DUT, and greatly simplifying the verification platform building under the above mechanism and facilitating the maintenance.

Description

Technical Field

[0001] This invention relates to the field of digital chip (IC) verification technology, specifically to a method for verifying a cache scheduling module based on a UVM verification platform. Background Technology

[0002] As CPU clock speeds increase, system performance improves. However, performance enhancements also depend on factors such as memory access speed, instruction set, system architecture, and the speed of information transfer between components, especially the CPU / memory access speed. If memory access speed is relatively slower than CPU speed, it causes CPU waiting time, wasting CPU resources. A common solution is caching to reduce the speed difference between memory and CPU. This involves inserting a smaller, faster SRAM between the fast CPU and slower DRAM to act as a buffer, keeping system costs manageable and allowing the CPU to access data in the SRAM at a faster speed.

[0003] The main factors affecting cache performance are the single-command access cycle and the degree of command parallelism. When the CPU performs a single-command access to main memory, it first sends the command to the cache, which then searches for it internally. If a cache hit occurs, the command is returned directly to the CPU; otherwise, the cache accesses main memory and then returns the command to the CPU, resulting in a relatively long single-command access cycle. Therefore, the key to improving cache performance is to process a large number of complex cache access commands simultaneously, requiring a high-performance command scheduling module within the cache. Verification of this module is therefore crucial.

[0004] Currently, verification methods based on UVM verification platforms are commonly used to verify the aforementioned high-performance command scheduling modules. However, for DUTs with such complex scheduling modules, numerous factors influence the output, making it relatively difficult to predict the DUT's output. A common approach is to build a cycle-level Reference Model (RM) and perform cycle-level comparisons with the DUT. Specifically, cycle-level comparison involves adding delays to the RM based on the DUT's processing flow, thereby synchronizing with the DUT's internal state at every step, ensuring consistent output. The advantage of this method is that it makes the output of complex scheduling modules predictable. The disadvantages are that building the RM is difficult and time-consuming; achieving synchronization typically requires pulling a large number of internal DUT signals, resulting in excessive coupling between the verification platform and the DUT; and any slight change in the DUT necessitates corresponding modifications to the RM, which is time-consuming and labor-intensive, leading to high maintenance costs for the verification platform. Summary of the Invention

[0005] To address the challenges of complex scheduling module verification methods that involve lengthy and complex RM (Runtime Controller) setups due to cycle-level comparisons, this invention provides a Cache scheduling module verification method based on a UVM (Virtual Runtime Model) verification platform. This proposed method eliminates RM latency and eliminates the need for extensive DUT (Device Under Test) internal signal monitoring. It synchronizes the state machines in the RM with those in the DUT by monitoring only interface signals or a few read / write completion signals at DUT interfaces. This avoids the difficulties of setting up cycle-level RMs and reduces the coupling between the verification platform and the DUT, significantly simplifying platform setup and maintenance.

[0006] This invention is achieved through the following technical solution:

[0007] A method for verifying a cache scheduling module based on a UVM verification platform, the method comprising:

[0008] The reference model obtains the same stimulus command as the DUT through the agent, and obtains the command thread number by pulling the internal command of the DUT into the queue chain information. Based on the command thread number, the stimulus command is attached to the internal state machine of the reference model.

[0009] When the DUT receives an excitation, the state machine inside the reference model is checked. If the check passes, the state will transition accordingly.

[0010] The expected state after the jump is written into the scoring board and compared with the output of the DUT output interface for verification.

[0011] Existing verification methods for the high-performance command scheduling module (Scheduler) within the cache require building a cycle-level RM to synchronize with the internal state of the DUT. Building a cycle-level RM is difficult and time-consuming. Furthermore, achieving synchronization typically requires pulling a large number of internal DUT signals, resulting in excessive coupling between the platform and the DUT. Even slight changes to the DUT necessitate modifications to the RM, making maintenance inconvenient and costly. The verification method proposed in this invention, however, checks the state of the RM's internal state machine when the DUT receives a stimulus, and simultaneously generates a corresponding state transition. This ensures synchronization between the RM's internal state machine and the DUT's internal state machine, eliminating RM latency. Moreover, it eliminates the need to pull a large number of internal DUT signals; synchronization can be achieved by monitoring interface signals or a few read / write completion signals at DUT interfaces. This avoids the difficulties of building a cycle-level RM and solves the problem of high coupling between the platform and the DUT. Under this mechanism, the verification platform construction is greatly simplified and easier to maintain.

[0012] In a preferred embodiment, the present invention performs a state check on the internal state machine of the reference model when the DUT receives an excitation, specifically as follows:

[0013] When the DUT receives a stimulus, it checks whether the current state of the internal state machine of the reference model is the state corresponding to the stimulus. If it is, the check passes; otherwise, the check fails.

[0014] As a preferred embodiment, the cache scheduling module verification method of the present invention further includes:

[0015] If the status check fails, an error message will be displayed.

[0016] Secondly, this invention proposes a cache scheduling module verification system based on the UVM verification platform, the cache scheduling module verification system comprising:

[0017] The reference model module is configured to execute the following commands:

[0018] The agent module obtains the same access command as the DUT, and simultaneously obtains the command thread number by queuing the internal commands of the DUT. Based on the command thread number, the stimulus command is attached to the internal state machine. When the DUT receives the stimulus, the state of the internal state machine is checked. If the check passes, the state changes accordingly, and the expected state after the change is written into the scoreboard module and compared with the output of the DUT's output interface for verification.

[0019] In a preferred embodiment, the present invention performs a state check on the internal state machine of the reference model when the DUT receives an excitation, specifically as follows:

[0020] When the DUT receives a stimulus, it checks whether the current state of the internal state machine of the reference model is the state corresponding to the stimulus. If it is, the check passes; otherwise, the check fails.

[0021] In a preferred embodiment, the reference model module of the present invention is also configured to execute the following commands:

[0022] If the status check fails, an error message will be displayed.

[0023] As a preferred embodiment, the cache scheduling module verification system of the present invention further includes:

[0024] The sqr module is used to generate the stimulus information required for the verification of the DUT.

[0025] As a preferred embodiment, the cache scheduling module verification system of the present invention further includes:

[0026] Driver-side agent module and output-side agent module;

[0027] The driver agent module is used to convert the stimulus information generated by the sqr module into stimulus commands for the DUT input interface, and simultaneously transmit the stimulus commands to the reference model module.

[0028] The output agent module is used to convert the commands output by the DUT output interface and write them to the scoreboard module for comparison and verification.

[0029] Thirdly, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in the present invention.

[0030] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the present invention.

[0031] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0032] 1. This invention proposes a verification scheme that can output expectations and check complex scheduling modules, and can solve the problems of high difficulty and long cycle in setting up RM due to Cycle-level comparison, as well as high coupling between the verification platform and DUT. It simplifies the construction of the verification platform and makes it easy to maintain.

[0033] 2. The verification technology proposed in this invention can not only verify the execution results of the DUT, but also check and report errors in intermediate states and threads, thereby improving the reliability of verification. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0035] Figure 1 This is a schematic diagram of the basic structure of a cache.

[0036] Figure 2 This is a flowchart of the processing flow of a single thread within the Scheduler.

[0037] Figure 3 This is the state machine for a single thread within the Scheduler.

[0038] Figure 4 This is a flowchart of the verification method according to an embodiment of the present invention.

[0039] Figure 5 This is a block diagram illustrating the principle of the verification system according to an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0041] Example:

[0042] Figure 1 The diagram shows the basic structure of a typical cache. The Scheduler is the command scheduling module inside the cache, which is used to control and schedule the command threads inside the cache. Figure 2 The following is the processing flow of a single thread within the Scheduler: (1) The Scheduler enqueues and chains the command arbitration; (2) It queries Tag_ram to determine if a hit occurs; (3) If a hit occurs, it directly accesses Data_ram, returns ack information to the command source, and releases the thread; (4) If a hit occurs, it accesses the host and rewrites Tag_ram and Data_ram. If it is a write command, it needs to write the data to the host, return ack information to the command source, and release the thread. Generally, to improve efficiency, cache access commands need to have a high degree of parallelism, so the Scheduler usually needs to process a large number of threads in parallel. The solution is to allocate a thread such as a... Figure 3 The state machine shown is used to control and schedule commands. Typically, to ensure efficiency, a DUT (Design Under Test) may contain hundreds of state machines, whose threads operate in parallel and interleaved, posing challenges to verification. Because of the large number of parallel and interleaved threads within the DUT, it is difficult to predict which thread's output corresponds to each interface, leading to comparison difficulties. To solve this problem, it is necessary to instantiate a state machine in the RM (Runtime Manager) with the same number of state machines as within the DUT. Figure 3The state machines shown typically require a delay in the RM to synchronize with the DUT's state machine transitions, necessitating cycle-level comparisons. This leads to a complex and time-consuming RM setup. Furthermore, achieving synchronization often requires pulling numerous internal DUT signals, resulting in excessive coupling between the verification platform and the DUT. Additionally, any slight change to the DUT necessitates modifications to the RM, which is time-consuming, labor-intensive, and costly to maintain. Therefore, to address at least one of these issues, this embodiment proposes a Cache scheduling module verification method based on a UVM verification platform. This method eliminates delays in the RM, eliminates the need for extensive pulling of internal DUT signals, and only requires monitoring interface signals or a few read / write completion signals at DUT interfaces to synchronize the state machines in the RM and DUT. This solves the problems of difficult RM setup and high maintenance costs when verifying complex scheduling modules, avoids strong coupling between the verification platform and the DUT caused by cycle-level comparisons, and facilitates maintenance.

[0043] Specifically, such as Figure 4 As shown, the verification method proposed in this embodiment specifically includes the following steps:

[0044] Step 1: The RM obtains the same stimulus command as the DUT through the agent, and at the same time obtains the command thread number by pulling the DUT's internal command queuing chain information. Based on the thread number, the stimulus command is added to the RM's internal state machine.

[0045] Step 2: When the DUT receives a stimulus, the RM internal state machine is checked. If the check passes, the state will transition accordingly, thereby ensuring that the RM internal state machine is synchronized with the DUT internal state machine.

[0046] Step 3: Write the expected state into the scb and compare it with the output of the DUT output interface for verification.

[0047] Furthermore, the verification method proposed in this embodiment can not only verify the execution result of the DUT, but also check and report errors in the threads and states of the DUT.

[0048] The stimuli involved in verifying the Cache scheduling module include: (1) cpu_req (Cache access command sent by the CPU); (2) rd / wr_host_ack (read / write host return result); (3) rd / wr_tag_ack (read Tag_ram return result); rd / wr_data_ack (read / write Data_ram return result). The expected stimuli include: (1) cpu_ack (command ack returned to the CPU); (2) rd / wr_host_req (read / write host request); (3) rd / wr_tag_req (query / modify Tag_ram request); (4) rd / wr_data_req (read / write Data_ram request).

[0049] This embodiment uses a wr_miss (write miss) as an example to explain the above verification method in detail. The processing flow is as follows:

[0050] (1) The RM obtains the same access command as the DUT through the agent;

[0051] (2) Pull the DUT internal command queuing chain information to obtain the command thread number, and attach the access command to the RM internal state machine according to the thread number;

[0052] (3) Check if the state of the corresponding thread number state machine of RM is IDLE. If not, report an error. If it is, the state jumps to RD_TAG0. Write the expected rd_tag_req into Sch2tag_scb and compare it with the DUT output.

[0053] (4) When the DUT receives rd_tag_ack, it checks whether the RM status is RD_TAG0. If not, it reports an error. If it is, the status jumps to RD_HOST. The expected rd_host_req is written to Sch2host_scb and compared with the DUT output.

[0054] (5) When the DUT receives rd_host_ack, it checks whether the RM status is RD_HOST. If not, it reports an error. If it is, the status jumps to RD_TAG1. The expected wr_tag_req is written to Sch2tag_scb and compared with the DUT output.

[0055] (6) When the DUT receives wr_tag_ack, it checks whether the RM status is RD_TAG1. If not, it reports an error. If it is, the status jumps to WR_MEM, and the expected wr_data_req is written to Sch2data_scb and compared with the DUT output.

[0056] (7) When the DUT receives wr_data_ack, it checks whether the RM status is WR_MEM. If not, it reports an error. If it is, the status jumps to WR_HOST. The expected wr_host_req is written to Sch2host_scb and compared with the DUT output.

[0057] (8) When the DUT receives wr_host_ack, it checks whether the RM status is WR_HOST. If not, it reports an error. If it is, the status jumps to ACK_SRC. The expected cpu_ack is written to Sch2cpu_scb and compared with the DUT output.

[0058] (9) When the cpu_output interface detects that the DUT outputs cpu_ack, check whether the RM status is ACK_SRC. If not, report an error. If so, the status jumps to RLS_RSC to release the thread. After one clock cycle, it jumps to IDLE.

[0059] Similarly, for write access with a hit, read access with a miss, and read access with a hit, the processing flow is to check the state of the RM's internal state machine when the DUT receives the stimulus, and at the same time, the state will generate the corresponding transition to ensure that the RM's internal state machine is synchronized with the DUT's internal state machine. The expected state is written into the SCB, so that the output of the DUT's output interface can be accurately predicted. This solves the problems of high difficulty in building the RM and high maintenance cost when verifying complex control and scheduling modules, greatly simplifies the construction of the verification platform and makes it easy to maintain. At the same time, when the DUT changes, as long as it does not affect the information required for the synchronization of the RM, there is no need to modify the RM.

[0060] Based on the same technical concept described above, this embodiment also proposes a cache scheduling module verification system based on the UVM verification platform, such as... Figure 5 As shown, the verification system proposed in this embodiment specifically includes:

[0061] The RM module obtains the same stimulus command as the DUT through the agent module. It also obtains the command thread number by pulling the DUT's internal command enqueue chain information and adds the stimulus command to the RM's internal state machine based on the thread number. At the same time, when the DUT receives the stimulus, it performs a state check on the RM's internal state machine. If the check passes, the state will change accordingly, thus ensuring that the RM's internal state machine is synchronized with the DUT's internal state machine. The expected state is written into the scb module and compared with the output of the DUT's output interface for verification.

[0062] Furthermore, the RM module in this embodiment can also check and report errors in the threads and states of the DUT.

[0063] Furthermore, the verification system proposed in this embodiment also includes an sqr module, which is used to generate the stimulus information required for DUT verification.

[0064] Furthermore, the verification system proposed in this embodiment also includes a driver-end agent module, which is used to convert stimulus information into stimulus commands for the DUT input interface, and simultaneously transmit the stimulus commands to the RM module.

[0065] Furthermore, the verification system proposed in this embodiment also includes an output agent module, which converts the commands output by the DUT output interface and writes them to the scb module for comparison and verification.

[0066] Furthermore, the verification system proposed in this embodiment also includes an scb module, which is used to compare the DUT output with the expected RM output to verify whether the DUT output meets the expectations.

[0067] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0068] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0069] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0070] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0071] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for verifying a cache scheduling module based on a UVM verification platform, characterized in that, The verification method of the cache scheduling module includes: The reference model obtains the same stimulus command as the DUT through the agent, and obtains the command thread number by pulling the internal command of the DUT into the queue chain information. Based on the command thread number, the stimulus command is attached to the internal state machine of the reference model. When the DUT receives an excitation, the state machine inside the reference model is checked. If the check passes, the state will transition accordingly. The expected state after the jump is written into the scoring board and compared with the output of the DUT output interface for verification.

2. The method for verifying a cache scheduling module based on a UVM verification platform according to claim 1, characterized in that, When the DUT receives an excitation, a state check is performed on the internal state machine of the reference model, specifically as follows: When the DUT receives a stimulus, it checks whether the current state of the internal state machine of the reference model is the state corresponding to the stimulus. If it is, the check passes; otherwise, the check fails.

3. The method for verifying a cache scheduling module based on a UVM verification platform according to claim 2, characterized in that, The cache scheduling module verification method also includes: If the status check fails, an error message will be displayed.

4. A cache scheduling module verification system based on a UVM verification platform, characterized in that, The cache scheduling module verification system includes: The reference model module is configured to execute the following commands: The agent module obtains the same stimulus command as the DUT, and obtains the command thread number by pulling the DUT's internal command queuing chain information. Based on the command thread number, the stimulus command is attached to the internal state machine. When the DUT receives the stimulus, the internal state machine is checked. If the check passes, the state changes accordingly, and the expected state after the change is written into the scoreboard module and compared with the output of the DUT's output interface for verification.

5. The Cache scheduling module verification system based on the UVM verification platform according to claim 4, characterized in that, When the DUT receives an excitation, a state check is performed on the internal state machine of the reference model, specifically as follows: When the DUT receives a stimulus, it checks whether the current state of the internal state machine of the reference model is the state corresponding to the stimulus. If it is, the check passes; otherwise, the check fails.

6. The Cache scheduling module verification system based on the UVM verification platform according to claim 5, characterized in that, The reference model module is also configured to execute the following commands: If the status check fails, an error message will be displayed.

7. A Cache scheduling module verification system based on a UVM verification platform according to any one of claims 4-6, characterized in that, The cache scheduling module verification system also includes: The sqr module is used to generate the stimulus information required for the verification of the DUT.

8. The Cache scheduling module verification system based on the UVM verification platform according to claim 7, characterized in that, The cache scheduling module verification system also includes: Driver-side agent module and output-side agent module; The driver agent module is used to convert the stimulus information generated by the sqr module into stimulus commands for the DUT input interface, and simultaneously transmit the stimulus commands to the reference model module. The output agent module is used to convert the commands output by the DUT output interface and write them to the scoreboard module for comparison and verification.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1-3.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-3.

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