Array substrate testing circuit, method, array substrate, and display device

Abstract

The application relates to the technical field of display, and particularly discloses an array substrate testing circuit, an array substrate testing method, an array substrate and a display device. The array substrate testing circuit comprises N testing sub-circuits. The testing sub-circuit comprises a first switch unit and a second switch unit. The first end of the first switch unit is connected with a signal line. The second end of the first switch unit is connected with the first end of the second switch unit. The second end of the second switch unit is connected with a testing line. The control end of the first switch unit in the nth testing sub-circuit is connected with the first end of the first switch unit in the n+1th testing sub-circuit, wherein n=1, 2, 3,..., N-1. The control end of the first switch unit in the Nth testing sub-circuit is connected with the first end of the first switch unit in the 1st testing sub-circuit. The second switch unit in the odd-numbered testing sub-circuit is configured to be turned on or turned off according to a first control signal. The second switch unit in the even-numbered testing sub-circuit is configured to be turned on or turned off according to a second control signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate testing circuit, method, array substrate, and display device. Background Technology

[0002] AMOLED (Active-matrix organic light-emitting diode) modules achieve image display through the coordinated operation of source signals (data line signals) and various switching signals in the circuit. An abnormality in any signal line within the AMOLED module will cause display errors. Therefore, when debugging and troubleshooting AMOLED modules, the source signals are typically tested.

[0003] Some existing testing solutions utilize display driver ICs (DDICs), which simulate the waveform of a specific source signal line output from a GPIO (General Purpose Input / Output Port) to the test point to debug and analyze the source signal. However, current DDIC designs can only select one or a few fixed source lines for testing, resulting in low testing efficiency for array substrates. Summary of the Invention

[0004] Therefore, it is necessary to provide an array substrate test circuit, method, array substrate, and display device to address the problem of low test efficiency in existing test schemes.

[0005] An array substrate test circuit includes N test sub-circuits, where N is a positive integer. Each test sub-circuit includes a first switching unit and a second switching unit. A first terminal of the first switching unit is connected to a signal line of the array substrate, and a second terminal of the first switching unit is connected to the first terminal of the second switching unit. The second terminal of the second switching unit is connected to a test line. The control terminal of the first switching unit in the nth test sub-circuit is connected to the first terminal of the first switching unit in the (n+1)th test sub-circuit, where n = 1, 2, 3, ..., N-1. The control terminal of the first switching unit in the Nth test sub-circuit is connected to the first terminal of the first switching unit in the 1st test sub-circuit. The second switching unit in the odd-numbered test sub-circuit is configured to turn on or off the connection between the first switching unit in the odd-numbered test sub-circuit and the test line according to a first control signal. The second switching unit in the even-numbered test sub-circuit is configured to turn on or off the connection between the first switching unit in the even-numbered test sub-circuit and the test line according to a second control signal.

[0006] In one embodiment, N is an even number greater than zero.

[0007] In one embodiment, the first switching unit includes a first transistor, the first electrode of the first transistor serving as the first terminal of the first switching unit, the gate of the first transistor serving as the control terminal of the first switching unit, and the second electrode of the first transistor serving as the second terminal of the first switching unit.

[0008] In one embodiment, the second switching unit includes a second transistor, the first terminal of the second transistor serving as the first terminal of the second switching unit, the second terminal of the second transistor serving as the second terminal of the second switching unit, the gate of the second transistor in the odd-numbered test sub-circuit being connected to a first control signal line, and the gate of the second transistor in the even-numbered test sub-circuit being connected to a second control signal line.

[0009] In one embodiment, the first transistor and the second transistor are P-type transistors.

[0010] An array substrate includes multiple signal lines and an array substrate test circuit as described in any of the above embodiments, wherein each signal line is connected to at least one test sub-circuit.

[0011] A display device includes multiple signal lines and an array substrate test circuit as described in any of the above embodiments, wherein each signal line is connected to at least one test sub-circuit.

[0012] A testing method for an array substrate includes determining the level of a first control signal and the level of a second control signal based on a test sub-circuit connected to a signal line under test; and determining the signal transmitted by each signal line based on the test sub-circuit of the signal line under test.

[0013] In one embodiment, determining the level of the first control signal and the level of the second control signal based on the test sub-circuit connected to the signal line under test includes controlling the level of the first control signal to be on and the level of the second control signal to be off when the test sub-circuit connected to the signal line under test is an odd-numbered test sub-circuit.

[0014] In one embodiment, when the test sub-circuit connected to the signal line under test is an even-numbered test sub-circuit, the level of the first control signal is controlled to be a cutoff level, and the level of the second control signal is controlled to be a conduction level.

[0015] In one embodiment, the nth signal line is connected to the nth test sub-circuit, where n = 1, 2, 3, ..., N-1, and N is a positive integer. Determining the signal transmitted by each signal line based on the test sub-circuit of the signal line under test includes controlling the signal line under test to transmit a test signal when the test sub-circuit connected to the nth test sub-circuit is the nth test sub-circuit, controlling the (n+1)th signal line to transmit a first signal, and controlling the other signal lines besides the signal line under test and the (n+1)th signal line to transmit a second signal.

[0016] In one embodiment, when the test sub-circuit connected to the signal line under test is the Nth test sub-circuit, the signal line under test is controlled to transmit a test signal, the first signal line is controlled to transmit a first signal, and the other signal lines besides the signal line under test and the first signal line are controlled to transmit a second signal.

[0017] In one embodiment, the level of the first signal is an on level, and the level of the second signal is an off level.

[0018] In one embodiment, the level of the first signal is lower than the level of the second signal.

[0019] The aforementioned array substrate test circuit includes multiple test sub-circuits, each including a first switching unit and a second switching unit. The second switching unit in the odd-numbered test sub-circuit is turned on or off according to a first control signal, while the second switching unit in the even-numbered test sub-circuit is turned on or off according to a second control signal. The first switching unit in each test sub-circuit is connected to a corresponding signal line in the array substrate. The first switching unit in each test sub-circuit is turned on or off according to the signal transmitted in the signal line connected to the first switching unit in the adjacent test sub-circuit. The first switching unit in the last test sub-circuit is turned on or off according to the signal transmitted in the signal line connected to the first switching unit in the first test sub-circuit. By changing the states of the first and second switching units in each test sub-circuit, the circuit can switch to the corresponding signal line under test, enabling selective measurement of any signal line and significantly improving the testing efficiency for each signal line in the array substrate. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the array substrate test circuit in one embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the circuit structure of the array substrate test circuit in one embodiment of this application;

[0023] Figure 3 This is a flowchart illustrating a testing method for an array substrate in one embodiment of this application;

[0024] Figure 4 This is a flowchart illustrating a method for determining a first control signal and a second control signal in one embodiment of this application.

[0025] Figure 5 This is a flowchart illustrating a method for determining the signals transmitted on each signal line in one embodiment of this application.

[0026] Figure 6 This is a timing diagram of various signals in one embodiment of this application. Detailed Implementation

[0027] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0030] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0032] Some existing testing solutions are implemented using display driver ICs (DDICs). By simulating the waveform of a source signal line output from a GPIO port (General Purpose Input / Output Port) to the test point, the source signal is debugged and problems are analyzed.

[0033] However, current DDIC designs can only select one or a few fixed source lines for testing, resulting in low testing efficiency for the array substrate. Furthermore, since the source signals are not subjected to a load during testing, the waveform of the tested source signals differs significantly from the actual source signals output to the display panel. Therefore, existing testing solutions suffer from poor testing progress, limiting the accuracy of source signal verification during debugging and restricting the ability to resolve related issues.

[0034] Figure 1 This is a schematic diagram of the structure of an array substrate test circuit in one embodiment of this application. In one embodiment, the array substrate test circuit 10 may include N test sub-circuits 100. Wherein, N can be a positive integer. That is, the array substrate test circuit 10 may include one or more test sub-circuits 100.

[0035] In some specific embodiments, the value of N can be determined based on the number of signal lines 200 in the array substrate 20, that is, the number of test sub-circuits 100 in the array substrate test circuit 10 can be determined based on the number of signal lines 200 in the array substrate 20. Preferably, the value N is not less than the number of signal lines 200 in the array substrate 20. For example, the number of test sub-circuits 100 in the array substrate test circuit 10 can be equal to the number of signal lines 200 in the array substrate 20, so that one test sub-circuit 100 is connected to one signal line 200 in the array substrate 20. In this embodiment, the signal line 200 of the array substrate 20 can refer to the source line. In some other embodiments, the signal line 200 can also be other signal transmission lines to be tested in the array substrate 20.

[0036] Each test sub-circuit 100 may include a first switching unit 110 and a second switching unit 120. The first end of the first switching unit 110 in each test sub-circuit 100 may be connected to a signal line 200 in the array substrate 20. For example, the first end of the first switching unit 110 in the first test sub-circuit 100 may be connected to the first signal line 200 in the array substrate 20. The second end of the first switching unit 110 in each test sub-circuit 100 may be connected to the first end of the second switching unit 120 in the same test sub-circuit 100. The second end of the second switching unit 120 in each test sub-circuit 100 is connected to a test line 30. The array substrate test circuit 10 can be connected to a test point T via the test line 30. When any test sub-circuit 100 is turned on, the test signal transmitted in the signal line 200 connected to that test sub-circuit 100 can be transmitted to the test point T. The tester can then determine whether the signal line 200 is abnormal based on the signal waveform detected at the test point T.

[0037] The control terminal of the first switching unit 110 in the nth test sub-circuit 100 can be connected to the first terminal of the first switching unit 110 in the (n+1)th test sub-circuit, where n = 1, 2, 3, ..., N-1. The control terminal of the first switching unit 110 in the Nth test sub-circuit 100 can be connected to the first terminal of the first switching unit 110 in the 1st test sub-circuit. That is, when the N test sub-circuits 100 are arranged in a row, the control terminal of the first switching unit 110 in each test sub-circuit 100 is connected to the first terminal of the first switching unit 110 in the adjacent test sub-circuit 100, and the control terminal of the first switching unit 110 in the last test sub-circuit 100 is connected to the first terminal of the first switching unit 110 in the first test sub-circuit 100, forming a closed-loop control with the beginning and end connected.

[0038] Since the first end of the first switching unit 110 is connected to the signal line 200 of the array substrate 20, the switching state of the first switching unit 110 in any test sub-circuit 100 can be controlled by the signal transmitted in the signal line 200 connected to the adjacent test sub-circuit 100, while the switching state of the first switching unit 110 in the last test sub-circuit 100 is controlled by the signal transmitted in the signal line 200 connected to the adjacent test sub-circuit 100.

[0039] For example, when the signal transmitted in the signal line 200 connected to the first test sub-circuit 100 is S1, the signal transmitted in the signal line 200 connected to the second test sub-circuit 100 is S2, the signal transmitted in the signal line 200 connected to the third test sub-circuit 100 is S3, ..., the signal transmitted in the signal line 200 connected to the (N-1)th test sub-circuit 100 is SN-1, and the signal transmitted in the signal line 200 connected to the Nth test sub-circuit 100 is SN, then the first switching unit 110 in the first test sub-circuit 100 is turned on or off according to S2, the first switching unit 110 in the second test sub-circuit 100 is turned on or off according to S3, and so on, the first switching unit 110 in the (N-1)th test sub-circuit 100 is turned on or off according to SN, and the first switching unit 110 in the Nth test sub-circuit 100 is turned on or off according to S1.

[0040] The second switching unit 120 in the odd-numbered test sub-circuit 100 can be configured to turn on or off the connection between the first switching unit 110 and the test line 30 according to the first control signal GPIO1. The second switching unit 120 in the even-numbered test sub-circuit 100 can be configured to turn on or off the connection between the first switching unit 110 and the test line 30 according to the second control signal GPIO2. That is, the first control signal GPIO1 can be used to control the switching state of the second switching unit 120 in the odd-numbered test sub-circuit 100, and the second control signal GPIO2 can be used to control the switching state of the second switching unit 120 in the even-numbered test sub-circuit 100.

[0041] Since the switching state of the first switching unit 110 in each test sub-circuit 100 is determined by the test signal received by the first switching unit 110 in the adjacent test sub-circuit 100, two first switching units 110 may be in the conducting state simultaneously, thus affecting the test results. For example, if the signal line 200 connected to the second test sub-circuit 100 is set as the signal line under test, then the signal line under test transmits the test signal, the signal line 200 connected to the third test sub-circuit 100 transmits the conduction signal, and the remaining signal lines 200 transmit the cutoff signal. The first switching unit 110 in the second test sub-circuit 100 can be turned on according to the signal transmitted in the signal line 200 connected to the third test sub-circuit 100. After the first switching unit 110 in the second test sub-circuit 100 is turned on, the test signal in the signal line under test can be transmitted to the test point T for observation by the tester. The first switching units 110 in the remaining test sub-circuit 100 are turned off.

[0042] However, if the test signal is also a conduction signal, the first switching unit 110 in the first test sub-circuit 100 will also be turned on according to the test signal, and the signal in the signal line 200 connected to the first test sub-circuit 100 will also be transmitted to the test point T. It can be seen that this will affect the accuracy of the observation of the test signal.

[0043] By having the second switching unit 120 in the odd-even column test sub-circuit 100 be controlled separately by the first control signal GPIO1 and the second control signal GPIO2, during testing, the switching states of two adjacent second switching units 120 can be reversed, so that the test signal will not be interfered with by the signal transmitted in the adjacent signal line 200.

[0044] For example, the signal line 200 connected to the second test sub-circuit 100 is set as the signal line under test. The signal line under test transmits a test signal, the signal line 200 connected to the third test sub-circuit 100 transmits an on signal, and the remaining signal lines 200 transmit off signals. Since the test sub-circuit 100 connected to the signal line under test is an even-numbered circuit, the second control signal GPIO2 can be set to an on signal, and the first control signal GPIO1 can be set to an off signal. This causes the second switching units 120 in the even-numbered test sub-circuits 100 to be turned on, and the second switching units 120 in the odd-numbered test sub-circuits 100 to be turned off. Simultaneously, the first switching unit 110 in the second test sub-circuit 100 is turned on according to the signal transmitted in the signal line 200 connected to the third test sub-circuit 100, while the first switching units 110 in the remaining test sub-circuits 100 are turned off. After the first switching unit 110 in the second test sub-circuit 100 is turned on, the test signal in the signal line under test can be transmitted to the test point T for the test personnel to observe.

[0045] At this time, even if the test signal is also a conducting signal, the first switching unit 110 in the first test sub-circuit 100 is also turned on according to the test signal. However, because the second switching unit 120 in the first test sub-circuit 100 is turned off, the signal in the signal line 200 connected to the first test sub-circuit 100 cannot be transmitted to the test point T. Therefore, by having the first switching unit 110 and the second switching unit 120 cooperate with each other, this application can ensure that only the test signal is transmitted to the test point T during each test, thereby improving the accuracy of the observation of the test signal.

[0046] In the aforementioned array substrate test circuit 10, the second switching unit 120 in the odd-numbered test sub-circuit 100 is turned on or off according to the first control signal GPIO1, and the second switching unit 120 in the even-numbered test sub-circuit 100 is turned on or off according to the second control signal GPIO2. The first switching unit 110 in the test sub-circuit 100 is connected to the signal line 200 in the corresponding array substrate 20. The first switching unit 110 of each test sub-circuit 100 is turned on or off according to the signal transmitted in the signal line 200 connected to the first switching unit 110 of the adjacent test sub-circuit 100, and the first switching unit 110 of the last test sub-circuit 100 is turned on or off according to the signal transmitted in the signal line 200 connected to the first switching unit 110 of the first test sub-circuit 100.

[0047] By using the aforementioned array substrate test circuit 10, the state of the first switching unit 110 and the second switching unit 120 in each test sub-circuit 100 can be changed to switch to the corresponding signal line under test. This enables selective measurement of any signal line 200 in the array substrate 20, thereby greatly improving the testing efficiency for each signal line 200 in the array substrate 20. Simultaneously, the signal line 200 connected to the aforementioned test sub-circuit 100 is transmitted from the array substrate 20 through a load to the test point; therefore, the test signal is essentially the same as the signal actually output to the array substrate 20. It is evident that the waveform of the test signal observed by the tester at the test point differs little from the actual signal waveform, improving the accuracy of the tester when debugging / verifying the signal under test, and thus enhancing the analytical capabilities for related problems.

[0048] In one embodiment, N can be an even number greater than zero. Considering that in practical applications, the number of signal lines 200 in the array substrate 20 is usually an even number, it is preferable that the number of test sub-circuits 100 in the array substrate test circuit 10 is equal to the number of signal lines 200 in the array substrate 20, that is, the number of test sub-circuits 100 in the array substrate test circuit 10 is also set to an even number. In addition, considering that when the value of N is odd, the first switching unit 110 in the Nth test sub-circuit 100 is turned on or off according to the signal transmitted in the signal line 200 connected to the first test sub-circuit, it is possible that signals on two signal lines 200 may be transmitted to the test point simultaneously.

[0049] For example, the signal line 200 connected to the first test sub-circuit 100 is designated as the signal line under test. The signal line under test transmits a test signal, the signal line 200 connected to the second test sub-circuit 100 transmits an on signal, and the remaining signal lines 200 transmit off signals. Since the test sub-circuit 100 connected to the signal line under test is an odd-numbered circuit, the first control signal GPIO1 can be set to an on signal, and the second control signal GPIO2 to an off signal. This causes the second switching units 120 in the odd-numbered test sub-circuits 100 to be turned on, and the second switching units 120 in the even-numbered test sub-circuits 100 to be turned off. Simultaneously, the first switching unit 110 in the first test sub-circuit 100 is turned on according to the signal transmitted in the signal line 200 connected to the second test sub-circuit 100, while the first switching units 110 in the remaining test sub-circuits 100 are turned off. After the first switching unit 110 in the first test sub-circuit 100 is turned on, the test signal in the signal line under test can be transmitted to the test point for the test personnel to observe.

[0050] However, if the test signal is also a conduction signal, the first switching unit 110 in the Nth test sub-circuit 100 will also be turned on according to the test signal. Moreover, when N is an odd number, the second switching unit 120 in the Nth test sub-circuit 100 is also in a conducting state, so the signal in the signal line 200 connected to the Nth test sub-circuit 100 will also be transmitted to the test point. It can be seen that when N is an odd number, the Nth test sub-circuit 100 will affect the observation accuracy of the test signal in the signal line 200 connected to the corresponding first test sub-circuit 100.

[0051] In this embodiment, by making N an even number greater than zero, it can be ensured that the second switching units 120 in the N test sub-circuits 100 are turned on or off in pairs by the first control signal GPIO1 and the second control signal GPIO2 respectively. The second switching units 120 in the first test sub-circuit 100 and the second switching units 120 in the Nth test sub-circuit 100 will not be turned on at the same time. This further ensures that the signal transmitted to the test point during each test is only the test signal, and the signal lines 200 connected to adjacent test sub-circuits 100 will not affect the test of the signal line under test.

[0052] In some other embodiments, the control terminal of the first switching unit 110 in the Nth test sub-circuit 100 can be connected to a third control signal line, that is, the first switching unit 110 in the Nth test sub-circuit 100 can be controlled independently by a third control signal. This ensures that when N is odd, the second switching unit 120 in the first test sub-circuit 100 and the second switching unit 120 in the Nth test sub-circuit 100 will not be turned on simultaneously, so that the Nth test sub-circuit 100 will not affect the testing of the signal line 200 connected to the first test sub-circuit 100.

[0053] Figure 2 This is a schematic diagram of the circuit structure of the array substrate test circuit in one embodiment of this application. In one embodiment, the first switching unit 110 may include a first transistor M1. The first electrode of the first transistor M1 can serve as the first terminal of the first switching unit 110, the gate of the first transistor M1 can serve as the control terminal of the first switching unit 110, and the second electrode of the first transistor M1 can serve as the second terminal of the first switching unit 110.

[0054] In the embodiments of this disclosure, a transistor refers to a device that includes at least a gate, a drain, and a source. In this disclosure, the first terminal of a transistor can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. In the embodiments of this disclosure, the gate of all or part of the transistor can be used as the control terminal, while the first and second terminals can be interchanged as needed.

[0055] The gate of the first transistor M1 in the nth test sub-circuit 100 can be connected to the first terminal of the first transistor M1 in the (n+1)th test sub-circuit, where n = 1, 2, 3, ..., N-1. The gate of the first transistor M1 in the Nth test sub-circuit 100 can be connected to the first terminal of the first transistor M1 in the 1st test sub-circuit. That is, when the N test sub-circuits 100 are arranged in a row, the gate of the first transistor M1 in each test sub-circuit 100 is connected to the first terminal of the first transistor M1 in the adjacent test sub-circuit 100, and the gate of the first transistor M1 in the last test sub-circuit 100 is connected to the first terminal of the first transistor M1 in the first test sub-circuit 100, forming a closed-loop control with the beginning and end connected.

[0056] In one embodiment, the second switching unit 120 may include a second transistor M2. The first terminal of the second transistor M2 may serve as the first terminal of the second switching unit 120, and the second terminal of the second transistor M2 may serve as the second terminal of the second switching unit 120. In the odd-numbered test sub-circuit 100, the gate of the second transistor M2 may be connected to a first control signal line, which may be used to transmit a first control signal GPIO1. In the even-numbered test sub-circuit 100, the gate of the second transistor M2 may be connected to a second control signal line, which may be used to transmit a second control signal GPIO2.

[0057] The second transistor M2 in the odd-numbered test sub-circuit 100 can be turned on or off according to the first control signal GPIO1, connecting the first transistor M1 in the odd-numbered test sub-circuit 100 to the test line 30. Similarly, the second transistor M2 in the even-numbered test sub-circuit 100 can be turned on or off according to the first control signal GPIO1, connecting the first transistor M1 in the odd-numbered test sub-circuit 100 to the test line 30. That is, the first control signal GPIO1 can be used to control the switching state of the second transistor M2 in the odd-numbered test sub-circuit 100, and the second control signal GPIO2 can be used to control the switching state of the second transistor M2 in the even-numbered test sub-circuit 100.

[0058] In one embodiment, considering that P-type TFTs have the characteristics of low driving voltage and low power consumption, and are suitable for low-power applications in test circuits, the first transistor M1 and the second transistor M2 can both be P-type transistors, for example, they can be P-type polycrystalline silicon thin film transistors.

[0059] This invention also provides an array substrate 20, which may include multiple signal lines 200 and the array substrate test circuit 10 described in any of the above embodiments. The array substrate 20 may include one or more array substrate test circuits 10. Each array substrate test circuit 10 may include multiple test sub-units 10, wherein a signal line 200 may be connected to at least one test sub-circuit 100. Preferably, one signal line 200 is correspondingly connected to one test sub-circuit 100. The test sub-circuit 100 can be used to control the connection between the signal line 200 and the test point T. This array substrate 20 can be applied to any product or component with display function, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc. This invention does not impose any special limitations on these categories.

[0060] This invention also provides a display device, which may include the array substrate test circuit 10 described in any of the above embodiments. The display device may also include one or more array substrate test circuits 10. The array substrate test circuit 10 may include multiple test sub-units 100, wherein a signal line 200 may be connected to at least one test sub-circuit 100. Preferably, one signal line 200 is correspondingly connected to one test sub-circuit 100. The test sub-circuit 100 can be used to control the connection between the signal line 200 and the test point. Similarly, this display device can be applied to any product or component with display function, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, automotive displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this invention does not impose any special limitations on these categories.

[0061] This invention also provides a testing method for an array substrate, which can be applied to the array substrate testing circuit 10, the array substrate 20, and / or the display device as described in any of the above embodiments. Figure 3 This is a flowchart illustrating a testing method for an array substrate in one embodiment of the present application. In one embodiment, the testing method for the array substrate may include the following steps S100 to S200.

[0062] Step S100: Determine the level of the first control signal and the level of the second control signal based on the test sub-circuit connected to the signal line under test.

[0063] Based on the signal line under test, it can be determined whether the second switch unit 120 in the test sub-circuit corresponding to the signal line under test is connected to the first control signal line or the second control signal line, thereby adjusting the signals transmitted in the first control signal line and the second control signal line.

[0064] Step S200: Determine the signal transmitted by each signal line according to the test sub-circuit of the signal line under test.

[0065] Similarly, the first switching unit 110 in the corresponding connected test sub-circuit can be determined based on which signal line 200 the signal is transmitted in to turn on or off, thereby adjusting the signal transmitted in each signal line 200 in the array substrate 20.

[0066] Figure 4 This is a flowchart illustrating a method for determining a first control signal and a second control signal in one embodiment of this application. In one embodiment, determining the level of the first control signal and the level of the second control signal based on the test sub-circuit connected to the signal line under test may include the following step S110.

[0067] Step S110: When the test sub-circuit connected to the signal line under test is the odd-numbered test sub-circuit, the level of the first control signal is controlled to be the on level, and the level of the second control signal is controlled to be the off level.

[0068] When the test sub-circuit 100 connected to the signal line under test is the odd-numbered test sub-circuit 100, the level of the first control signal GPIO1 can be set to the on level, and the level of the second control signal GPIO2 can be set to the off level. For example, when the test sub-circuit 100 connected to the signal line under test is the 7th test sub-circuit 100, since 7 is an odd number, the level of the first control signal GPIO1 can be set to the on level, and the level of the second control signal GPIO2 can be set to the off level, so as to turn on the second switching unit 120 in the odd-numbered test sub-circuit 100 and turn off the second switching unit 120 in the even-numbered test sub-circuit 100.

[0069] In one embodiment, determining the level of the first control signal and the level of the second control signal based on the test sub-circuit connected to the signal line under test may further include the following step S120.

[0070] Step S120: When the test sub-circuit connected to the signal line under test is the even-numbered test sub-circuit, control the level of the first control signal to the cut-off level and control the level of the second control signal to the on level.

[0071] When the test sub-circuit 100 connected to the signal line under test is the even-numbered test sub-circuit 100, the level of the first control signal GPIO1 can be set to the off level, and the level of the second control signal GPIO2 can be set to the on level. For example, when the test sub-circuit 100 connected to the signal line under test is the 10th test sub-circuit 100, since 10 is an even number, the level of the first control signal GPIO1 can be set to the off level, and the level of the second control signal GPIO2 can be set to the on level, so as to turn off the second switching unit 120 in the odd-numbered test sub-circuit 100 and turn on the second switching unit 120 in the even-numbered test sub-circuit 100.

[0072] In this embodiment, the second switching unit 120 includes a P-type transistor, so the on-state level can be low and the off-state level can be high. In practical applications, a suitable level can be selected as the on-state level of the transistor according to the type of transistor in the array substrate test circuit 10.

[0073] Figure 5 This is a schematic flowchart of a method for determining the signal transmitted by each signal line in one embodiment of the present application. In one embodiment, determining the signal transmitted by each signal line according to the test sub-circuit of the signal line under test may include the following steps S210 to S220.

[0074] Step S210: When the test sub-circuit connected to the signal line under test is the nth test sub-circuit, control the signal line under test to transmit the test signal, control the (n+1)th signal line to transmit the first signal, and control the other signal lines except the signal line under test and the (n+1)th signal line to transmit the second signal.

[0075] In this embodiment, one signal line 200 is connected to one test sub-circuit 100, and the nth signal line 200 is connected to the nth test sub-circuit 100, where n = 1, 2, 3, ..., N-1, and N is a positive integer. In one embodiment, the level of the first signal can be a conduction level, and the level of the second signal can be a cutoff level.

[0076] In one embodiment, the first switching unit 110 includes a P-type transistor, so that the on-level can be low and the off-level can be high, meaning the level of the first signal can be lower than the level of the second signal. In practical applications, a suitable level can be selected as the on-level of the transistor based on the type of transistor in the array substrate test circuit 10.

[0077] For example, when the signal line under test is the 5th signal line 200, the corresponding test sub-circuit 100 is the 5th test sub-circuit 100. When testing the 5th signal line 200, the 5th signal line 200 can transmit a test signal, the 6th signal line 200 can transmit a first signal, and the other signal lines 200 besides the 5th and 6th signal lines 200 can transmit a second signal. In this embodiment, since the level of the first signal is high, the first switching unit 110 in the 5th test sub-circuit 100 is turned on according to the first signal transmitted by the 6th signal line 200. After the first switching unit 110 in the 5th test sub-circuit 100 is turned on, the test signal transmitted in the 5th signal line 200 can be transmitted to the test point. Meanwhile, since all signal lines 200 except for the 5th and 6th signal lines 200 transmit the second signal, the first switching units 110 in the other test sub-circuits 100 are all turned off.

[0078] Step S220: When the test sub-circuit connected to the signal line under test is the Nth test sub-circuit, control the signal line under test to transmit the test signal, control the first signal line to transmit the first signal, and control the other signal lines except the signal line under test and the first signal line to transmit the second signal.

[0079] When the signal line under test is the Nth signal line 200, the corresponding test sub-circuit 100 is the Nth test sub-circuit 100. When testing the Nth signal line 200, it can transmit a test signal, the first signal line 200 can transmit a first signal, and the other signal lines 200 (excluding the first and Nth signal lines 200) can transmit a second signal. In this embodiment, since the first signal is at a high level, the first switching unit 110 in the Nth test sub-circuit 100 is turned on according to the first signal transmitted by the first signal line 200. After the first switching unit 110 in the Nth test sub-circuit 100 is turned on, the test signal transmitted in the Nth signal line 200 can be transmitted to the test point. Simultaneously, since all signal lines 200 except the first and Nth signal lines 200 transmit the second signal, the first switching units 110 in the other test sub-circuits 100 are all turned off.

[0080] In this embodiment, with Figure 2 Taking the array substrate test circuit 10 shown as an example, the test method for the array substrate will be explained. Figure 2 In the first transistor M1 and the second transistor M2, both are P-type transistors. Therefore, the conduction level of the first transistor M1 and the second transistor M2 is low, and the cutoff level is high. N is an even number greater than 0. Figure 6 This is a timing diagram of various signals in one embodiment of this application. Figure 6 In the diagram, GPIO1 displays the first control signal, GPIO2 displays the signal waveform of the second control signal, S1 displays the signal waveform transmitted in the signal line 200 connected to the first test sub-circuit 100, S2 displays the signal waveform transmitted in the signal line 200 connected to the second test sub-circuit 100, S3 displays the signal waveform transmitted in the signal line 200 connected to the first test sub-circuit 100, and so on, with SN displaying the signal waveform transmitted in the signal line 200 connected to the Nth test sub-circuit 100. Test displays the signal waveform detected at test point T.

[0081] When the signal line under test is the first signal line 200, the first signal line 200 can transmit the test signal, the second signal line 200 can transmit the first signal, and the remaining signal lines 200 can transmit the second signal. The first signal is at a conducting level (low level), and the second signal is at a cutoff level (high level). Simultaneously, since the test sub-circuit 100 corresponding to the signal line under test is the odd-numbered test sub-circuit 100, the first control signal GPIO1 can be at a conducting level (low level), and the second control signal GPIO2 can be at a cutoff level (high level). For example... Figure 6 As shown, the level of the first control signal GPIO1 remains low during the test, the level of the second control signal GPIO2 remains high during the test, the signal S1 transmitted in the first signal line 200 is the test signal, the level of the signal S2 transmitted in the second signal line 200 remains low during the test, and the levels of the signals S3 to SN transmitted in the other signal lines besides the first and second signal lines 200 remain high during the test.

[0082] based on Figure 6 As shown in the diagram, since the gate of the first transistor M1 in the first test sub-circuit 100 is connected to the input terminal of the second test sub-circuit 100, the first transistor M1 in the first test sub-circuit 100 is turned on according to the signal S2 transmitted in the second signal line 200. Simultaneously, since the gate of the second transistor M2 in the odd-numbered test sub-circuit 100 is connected to the second control signal line, the second transistor M2 in the odd-numbered test sub-circuit 100 is turned on according to the first control signal GPIO1, meaning the second transistor M2 in the first test sub-circuit 100 is also turned on. After both the first transistor M1 and the second transistor M2 in the first test sub-circuit 100 are turned on, the test signal in the first signal line 200, i.e., the signal line under test, can be transmitted to the test point T for observation by the tester.

[0083] Furthermore, since the gate of the second transistor M2 in the even-numbered test sub-circuit 100 is connected to the second control signal line, the second transistor M2 in the even-numbered test sub-circuit 100 is turned off according to the second control signal GPIO2, that is, the second transistor M2 in the Nth test sub-circuit 100 is turned off. At this time, even if there is a conduction level in the test signal, the first switching unit 110 in the Nth test sub-circuit 100 is turned on according to the test signal, but because the second switching unit 120 in the Nth test sub-circuit 100 is in the off state, the signal in the signal line 200 connected to the Nth test sub-circuit 100 cannot be transmitted to the test point T.

[0084] When testing other signal lines in the array substrate, different signal lines under test can be switched by adjusting the levels of the first control signal GPIO1, the second control signal GPIO2, and the signals S1 to SN transmitted in each signal line. This enables selective testing of any signal line 200 in the array substrate 20, greatly improving the testing efficiency for each signal line 200 in the array substrate 20. Furthermore, since each signal line 200 is transmitted from the array substrate 20 through a load to the test point, the test signal is essentially the same as the actual signal output to the array substrate 20. Therefore, the waveform of the test signal observed by the tester at the test point differs little from the actual signal waveform, improving the accuracy of the tester when debugging / verifying the signal under test, and thus enhancing the ability to analyze related problems.

[0085] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A test circuit for an array substrate, characterized in that, It includes N test sub-circuits, where N is a positive integer. The test sub-circuit includes a first switching unit and a second switching unit. The first end of the first switching unit is connected to the signal line of the array substrate, the second end of the first switching unit is connected to the first end of the second switching unit, and the second end of the second switching unit is connected to the test line. The control terminal of the first switch unit in the nth test sub-circuit is connected to the first terminal of the first switch unit in the (n+1)th test sub-circuit, where n = 1, 2, 3, ..., N-1, and the control terminal of the first switch unit in the Nth test sub-circuit is connected to the first terminal of the first switch unit in the 1st test sub-circuit. The second switching unit in the odd-numbered test sub-circuit is configured to turn on or off the connection between the first switching unit in the odd-numbered test sub-circuit and the test line according to a first control signal; the second switching unit in the even-numbered test sub-circuit is configured to turn on or off the connection between the first switching unit in the even-numbered test sub-circuit and the test line according to a second control signal.

2. The array substrate test circuit according to claim 1, characterized in that, N is an even number that is greater than zero.

3. The array substrate test circuit according to claim 1, characterized in that, The first switching unit includes a first transistor, the first electrode of the first transistor serves as the first terminal of the first switching unit, the gate of the first transistor serves as the control terminal of the first switching unit, and the second electrode of the first transistor serves as the second terminal of the first switching unit.

4. The array substrate test circuit according to claim 1, characterized in that, The second switching unit includes a second transistor, the first terminal of the second transistor serves as the first terminal of the second switching unit, the second terminal of the second transistor serves as the second terminal of the second switching unit, the gate of the second transistor in the odd-numbered test sub-circuit is connected to the first control signal line; the gate of the second transistor in the even-numbered test sub-circuit is connected to the second control signal line.

5. The array substrate test circuit according to claim 3 or 4, characterized in that, The first and second transistors are P-type transistors.

6. An array substrate, characterized in that, It includes multiple signal lines and the array substrate test circuit according to any one of claims 1 to 5, wherein each signal line is connected to at least one test sub-circuit.

7. A display device, characterized in that, It includes multiple signal lines and the array substrate test circuit according to any one of claims 1 to 5, wherein each signal line is connected to at least one test sub-circuit.

8. A testing method for an array substrate, used to test the array substrate test circuit according to any one of claims 1 to 5, characterized in that, The testing method includes: The levels of the first control signal and the second control signal are determined based on the test sub-circuit connected to the signal line under test; The signal transmitted by each signal line is determined based on the test sub-circuit of the signal line under test.

9. The test method according to claim 8, characterized in that, The step of determining the level of the first control signal and the level of the second control signal based on the test sub-circuit connected to the signal line under test includes: When the test sub-circuit connected to the signal line under test is an odd-numbered test sub-circuit, the level of the first control signal is controlled to be the on level, and the level of the second control signal is controlled to be the off level.

10. The test method according to claim 8, characterized in that, When the test sub-circuit connected to the signal line under test is an even-numbered test sub-circuit, the level of the first control signal is controlled to be off level, and the level of the second control signal is controlled to be on level.

11. The test method according to claim 8, characterized in that, The nth signal line is connected to the nth test sub-circuit, where n = 1, 2, 3, ..., N-1, and N is a positive integer. Determining the signal transmitted by each signal line based on the test sub-circuit of the signal line under test includes: When the test sub-circuit connected to the signal line under test is the nth test sub-circuit, the signal line under test is controlled to transmit a test signal, the (n+1)th signal line is controlled to transmit a first signal, and the other signal lines besides the signal line under test and the (n+1)th signal line are controlled to transmit a second signal.

12. The test method according to claim 8, characterized in that, When the test sub-circuit connected to the signal line under test is the Nth test sub-circuit, the signal line under test is controlled to transmit a test signal, the first signal line is controlled to transmit a first signal, and other signal lines besides the signal line under test and the first signal line are controlled to transmit a second signal.

13. The test method according to claim 12, characterized in that, The first signal has a conduction level, and the second signal has a cutoff level.

14. The test method according to claim 12, characterized in that, The level of the first signal is lower than the level of the second signal.

Images