Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure provides a semiconductor structure preparation method and a semiconductor structure. The semiconductor structure preparation method comprises: providing a stack layer, the stack layer comprising a target layer; forming a plurality of first target patterns arranged at intervals in the target layer; forming an isolation layer covering the target layer with the first target patterns; and forming a plurality of second target patterns arranged at intervals in the target layer, at least part of the isolation layer being located between the first target patterns and the second target patterns. The semiconductor structure preparation method provided by the present disclosure can effectively isolate the first target patterns and the second target patterns, thereby avoiding the short circuit of the contact structures prepared by the first target patterns and the second target patterns, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0003] DRAM comprises multiple repeating memory cells disposed on a substrate, each including a capacitor and a transistor. The gate of the transistor is connected to the word line (WL), the source is connected to the bit line (BL) via a bit line contact (BLC), and the drain is connected to the capacitor. Voltage signals on the word line control the transistor to turn on or off, thereby reading data stored in the capacitor via the bit line, or writing data into the capacitor via the bit line for storage.

[0004] However, as the integration density of DRAM continues to increase, short circuits are prone to occur between adjacent bit line contact structures, affecting the storage performance of semiconductor memory. Summary of the Invention

[0005] This disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure that can effectively isolate a first target pattern and a second target pattern, thereby avoiding short circuits in the contact structures fabricated by the first target pattern and the second target pattern, and improving the performance of the semiconductor structure.

[0006] In a first aspect, this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0007] Provide a stack layer, which includes the target layer;

[0008] Multiple first target patterns are formed at intervals in the target layer;

[0009] An isolation layer is formed, which covers the target layer having the first target pattern;

[0010] Multiple second target patterns are formed at intervals in the target layer, with at least a portion of the isolation layer located between the first target pattern and the second target pattern.

[0011] In the above-described method for fabricating a semiconductor structure, optionally, after forming the isolation layer and before forming the second target pattern, the method further includes:

[0012] A second mask layer is formed, which covers the isolation layer;

[0013] A second mask pattern layer is formed, which is located on the second mask layer.

[0014] In the above-described method for fabricating the semiconductor structure, optionally, forming a second target pattern in the target layer includes:

[0015] A portion of the second mask layer is etched away along the second mask pattern layer, and an intermediate trench is formed in the second mask layer. The intermediate trench exposes a portion of the top surface of the isolation layer, and the bottom of the intermediate trench is flush with the exposed top surface of the isolation layer.

[0016] The isolation layer exposed by the intermediate trench is etched away, and part of the top surface of the target layer is exposed.

[0017] The target layer exposed by the intermediate trench is etched away to form a plurality of spaced second holes in the target layer. The second holes form a second target pattern, and at least part of the isolation layer forms the sidewalls of the second holes.

[0018] In the above-described method for fabricating a semiconductor structure, optionally, a plurality of first target patterns arranged at intervals are formed in the target layer, including:

[0019] A first mask layer is formed, which covers the target layer;

[0020] A first mask pattern layer is formed, and the first mask pattern layer is located on the first mask layer.

[0021] In the above-described method for fabricating a semiconductor structure, optionally, a plurality of first target patterns arranged at intervals are formed in the target layer, including:

[0022] Etch the first mask layer along the first mask pattern layer;

[0023] The target layer is etched along the first etched mask layer to form a plurality of first holes spaced apart in the target layer, and the first holes form a first target pattern.

[0024] In the above-described method for fabricating a semiconductor structure, optionally, an isolation layer is formed, including: the isolation layer covering the bottom of the first hole and forming at least a portion of the sidewall of the first hole;

[0025] In at least partially adjacent first and second holes, the isolation layer forming the hole sidewall of the first hole and the isolation layer forming the hole sidewall of the second hole are the same isolation layer.

[0026] In the above-described method for fabricating a semiconductor structure, optionally, the second mask layer includes a first sub-mask layer and a second sub-mask layer sequentially stacked along a direction away from the isolation layer, wherein the first sub-mask layer and the second sub-mask layer are made of different materials;

[0027] Etching away a portion of the second mask layer along the second mask pattern layer includes:

[0028] A portion of the second sub-mask layer is removed by etching using the first etching process;

[0029] A second etching process is used to etch away part of the first sub-mask layer.

[0030] In the above-mentioned method for fabricating semiconductor structures, the formation of the isolation layer may optionally include: forming the isolation layer using an atomic layer deposition process, wherein the material of the isolation layer includes silicon oxide;

[0031] Etching to remove the isolation layer exposed by the intermediate trench includes: using a third etching process to etch and remove the isolation layer exposed by the intermediate trench.

[0032] In the above-mentioned method for fabricating semiconductor structures, the material of the target layer may optionally include polycrystalline silicon;

[0033] Etching to remove the target layer exposed by the intermediate trench includes: using a fourth etching process to etch and remove the target layer exposed by the intermediate trench.

[0034] In the above-described method for fabricating a semiconductor structure, optionally, the stacked layer further includes a substrate, an intermediate layer, and a transfer mask layer stacked sequentially; the target layer is located on the side of the transfer mask layer opposite to the substrate.

[0035] After forming the first target pattern and the second target pattern, the process also includes:

[0036] The transfer mask layer, intermediate layer and substrate are sequentially etched along the first target pattern and the second target pattern to form multiple contact trenches arranged in an array in the substrate;

[0037] A contact structure is formed in the contact groove.

[0038] In the above-described method for fabricating the semiconductor structure, optionally, a transfer mask layer, an intermediate layer, and a substrate are sequentially etched along the first target pattern and the second target pattern, including:

[0039] A sacrificial mask structure is formed, which fills the first and second holes;

[0040] Remove the target layer and the isolation layer located on the sidewall of the sacrificial mask structure;

[0041] The transfer mask layer, intermediate layer and substrate are etched sequentially along the sacrificial mask structure.

[0042] In the above-mentioned method for fabricating a semiconductor structure, optionally, the transfer mask layer includes a first transfer mask layer, a second transfer mask layer, and a third transfer mask layer sequentially stacked along a direction away from the substrate;

[0043] Etching the transfer mask layer along the sacrificial mask structure includes:

[0044] The third transfer mask layer is etched along the sacrificial mask structure to form a plurality of first transfer structures arranged in an array in the third transfer mask layer;

[0045] A sacrificial layer is formed, which covers the first transfer structure;

[0046] The first transfer structure is removed, and the remaining sacrificial layer forms multiple sacrificial structures arranged in an array;

[0047] The second transfer mask layer and the first transfer mask layer are etched sequentially along the sacrificial structure to form a plurality of second transfer structures arranged in an array in the second transfer mask layer and the first transfer mask layer.

[0048] In the above-described method for fabricating the semiconductor structure, the etching of the intermediate layer and the substrate may optionally include:

[0049] Etch the intermediate layer along the second transfer structure;

[0050] The substrate is etched along the second transfer structure to form contact trenches in the substrate.

[0051] In the above-mentioned method for fabricating semiconductor structures, optionally, the substrate has multiple conductive structures arranged at intervals, and the contact structures are connected to the conductive structures in a one-to-one correspondence and are electrically conductive.

[0052] Secondly, this disclosure provides a semiconductor structure, which is prepared by the above-described semiconductor structure preparation method.

[0053] The semiconductor structure fabrication method and semiconductor structure disclosed herein involve forming a first target pattern in a target layer of a stacked layer. An isolation layer is then formed to cover the first target pattern. A second target pattern is subsequently formed in the target layer, with at least a portion of the isolation layer located between the first and second target patterns. This isolation layer effectively separates the first and second target patterns, ensuring that contact structures fabricated using the first and second target patterns are mutually isolated. This prevents short circuits between different contact structures, guarantees the stability of electrical signal transmission through the contact structures, and thus helps improve the performance of the semiconductor structure.

[0054] The structure of this disclosure, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0057] Figure 2 A schematic diagram showing the positional offset of the first contact structure and the second contact structure of the semiconductor structure provided in the embodiments of this disclosure;

[0058] Figure 3 A schematic diagram showing the dimensional changes of the first and second contact structures of the semiconductor structure provided in the embodiments of this disclosure;

[0059] Figure 4 A schematic flowchart illustrating the method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0060] Figure 5 A schematic diagram of the stacked layer, first mask layer, and first mask pattern layer of the semiconductor structure provided in this embodiment of the disclosure;

[0061] Figure 6 This is a schematic diagram of the structure for forming the first hole provided in an embodiment of the present disclosure;

[0062] Figure 7 This is a schematic diagram of the structure forming the isolation layer provided in an embodiment of the present disclosure;

[0063] Figure 8 A schematic diagram of the structure for forming the second mask layer and the second mask pattern layer provided in an embodiment of this disclosure;

[0064] Figure 9 This is a schematic diagram of the structure of the first sub-mask layer being etched, provided in an embodiment of this disclosure.

[0065] Figure 10 for Figure 9 Top view;

[0066] Figure 11 This is a schematic diagram of the etched isolation layer provided in an embodiment of the present disclosure;

[0067] Figure 12 for Figure 11 Top view;

[0068] Figure 13 This is a schematic diagram of the structure of the etching target layer provided in an embodiment of this disclosure;

[0069] Figure 14 for Figure 13 Top view;

[0070] Figure 15 This is a schematic diagram of the structure for forming a sacrificial mask structure provided in an embodiment of this disclosure;

[0071] Figure 16 This is a schematic diagram of a structure for removing the target layer and part of the isolation layer, provided in an embodiment of this disclosure.

[0072] Figure 17 This is a schematic diagram of the structure forming the first transfer structure provided in an embodiment of the present disclosure;

[0073] Figure 18 This is a schematic diagram of the structure for forming a sacrificial layer provided in an embodiment of the present disclosure;

[0074] Figure 19 This is a schematic diagram of the sacrificial layer for planarization processing provided in an embodiment of this disclosure;

[0075] Figure 20 This is a schematic diagram of the structure with the first transfer structure removed, provided in an embodiment of this disclosure.

[0076] Figure 21 This is a schematic diagram of the structure forming the second transfer structure provided in an embodiment of the present disclosure;

[0077] Figure 22 This is a schematic diagram of the structure of the etching intermediate layer provided in an embodiment of the present disclosure;

[0078] Figure 23 This is a schematic diagram of the structure forming the contact groove provided in an embodiment of the present disclosure;

[0079] Figure 24 This is a schematic diagram of the structure forming the contact structure provided in an embodiment of this disclosure.

[0080] Explanation of reference numerals in the attached figures:

[0081] 100, Substrate; 101, Conductive Structure; 102, Shallow Trench Isolation; 103, Contact Trench; 104, Contact Structure; 104a, First Contact Structure; 104b, Second Contact Structure; 200, Intermediate Layer; 300, Transfer Mask Layer; 301, First Transfer Mask Layer; 302, Second Transfer Mask Layer; 303, Third Transfer Mask Layer; 304, First Transfer Structure; 305, Second Transfer Structure; 400, Target Layer; 401, First Hole; 402, Second aperture; 500, Isolation layer; 600, Sacrificial mask structure; 700, Sacrificial layer; 701, Sacrificial structure; 800, First mask layer; 800a, Third sub-mask layer; 800b, Fourth sub-mask layer; 801, First mask pattern layer; 802, Second mask layer; 802a, First sub-mask layer, 802b, Second sub-mask layer; 802c, Intermediate trench; 803, Second mask pattern layer; 900, Word line; 901, Bit line. Detailed Implementation

[0082] In DRAM, the drain of the transistor is connected to the bit line through the bit line contact structure. The voltage signal on the word line controls the transistor to turn on or off, thereby reading the data information stored in the capacitor through the bit line contact structure and the bit line, or writing the data information into the capacitor for storage through the bit line and the bit line contact structure.

[0083] Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a schematic diagram illustrating the positional offset of the first contact structure and the second contact structure in a semiconductor structure provided in an embodiment of this disclosure. Figure 3 A schematic diagram illustrating the dimensional variations of the first and second contact structures of the semiconductor structure provided in this embodiment of the disclosure. (Refer to...) Figure 1 As shown, the DRAM includes multiple bit lines 901 and multiple word lines 900. The word lines 900 extend along a first direction and are spaced apart along a second direction. The bit lines 901 extend along the second direction and are spaced apart along the first direction. The first direction is shown as X in the figure, and the second direction is shown as Y in the figure. The first direction and the second direction intersect each other. In this disclosure, the first direction and the second direction can be perpendicular to each other.

[0084] The DRAM substrate 100 has multiple active regions arranged in an array, i.e. Figure 1-3The conductive structure 101, as indicated in the figure, includes an active region comprising a source region, a channel region, and a drain region arranged sequentially (not labeled separately in the figure). The bit line contact structure includes a first contact structure 104a and a second contact structure 104b, both arranged in an array. First contact structures 104a in the same row (or column) and second contact structures 104b in adjacent rows (or columns) are staggered. Both first contact structures 104a and 104b can be bit line contact structures. Both ends of the first contact structures 104a and 104b can be connected to the bit line 901 and the source region of the active region, used to transmit the electrical signal from the bit line 901 to the source region, and then write it to the capacitor under transistor control. Alternatively, the electrical signal stored in the capacitor can be read under transistor control. Therefore, the electrical signal transmission capability of the bit line contact structure affects the DRAM storage process.

[0085] In the DRAM manufacturing process, the first contact structure 104a and the second contact structure 104b are fabricated using different mask structures, and the mask structures used to fabricate the first contact structure 104a and the mask structures used to fabricate the second contact structure 104b are formed in different processes. This disclosure uses the example of first fabricating the mask structure of the first contact structure 104a and then fabricating the mask structure of the second contact structure 104b.

[0086] In related technologies, as the integration density of DRAM continues to increase, the following problems typically arise during the fabrication of the mask structure used to fabricate the contact structure 104. (Refer to...) Figure 2 As shown, when fabricating the mask structure of the second contact structure 104b, the position of the mask structure will shift relative to the preset position, resulting in an overlay shift of the second contact structure 104b. Figure 2 The structure represented by the dashed line is the second contact structure 104b, which is offset from the preset position. Figure a shows the deviation displacement between the offset second contact structure 104b and the preset contact structure 104. Figure 2 The diagram shows a mask structure offset along a first direction. In some cases, the mask structure can also be offset along a second direction, or along other directions within the plane formed by the first and second directions. Offsets in other directions will result in the same problems as offsets along the first direction.

[0087] Reference Figure 3 As shown, when fabricating the mask structure for the second contact structure 104b, the size of the mask structure is relatively large compared to the preset size, resulting in the second contact structure 104b having a size larger than the preset size (critical dimension overtarget). Figure 3 The structure represented by the dashed line is the second contact structure 104b, which is larger than the preset size. b shows the size deviation between the larger second contact structure 104b and the preset contact structure 104.

[0088] Both of the above situations can lead to contact between the second contact structure 104b and the adjacent first contact structure 104a, or the adjacent second contact structure 104b, resulting in a short circuit in the bit line contact structure (BLC bridge). This will affect the transmission of electrical signals in the shorted first contact structure 104a and the second contact structure 104b, thus making it impossible to guarantee that the electrical signal of the bit line 901 can be successfully written to the capacitor or successfully read from the capacitor, affecting the storage performance of the DRAM.

[0089] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. The method involves forming a first target pattern in a target layer of a stacked layer. An isolation layer is then formed to cover the first target pattern. A second target pattern is subsequently formed in the target layer. At least a portion of the isolation layer is located between the first and second target patterns, effectively separating them. This ensures that the contact structures fabricated using the first and second target patterns are mutually isolated, preventing short circuits between different contact structures and guaranteeing the stability of electrical signal transmission through the contact structures. This, in turn, helps improve the performance of the semiconductor structure.

[0090] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this disclosure. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0091] Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figure 5 This is a schematic diagram of the stacked layer, first mask layer, and first mask pattern layer of the semiconductor structure provided in the embodiments of this disclosure. Figure 6 This is a schematic diagram of the structure for forming the first hole provided in an embodiment of this disclosure. Figure 7 This is a schematic diagram of the structure for forming an isolation layer provided in an embodiment of this disclosure.

[0092] Reference Figure 4 As shown, this disclosure provides a method for fabricating a semiconductor structure, including:

[0093] S100: Provides a stack layer, which includes the target layer;

[0094] It should be noted that the stacked layers can include multiple layers, and the target layer 400 can be a portion of the stacked layers. This target layer 400 can be used to form a mask structure, which is then transferred to form the contact structure 104. The target layer 400 in this disclosure can be a polysilicon layer (Poly-Si). The polysilicon layer, combined with subsequent etching methods, can effectively reduce the fabrication difficulty of the contact structure 104.

[0095] S200: Form multiple first target patterns arranged at intervals in the target layer.

[0096] Specifically, multiple first target patterns are formed at intervals in the target layer 400, including:

[0097] A first mask layer 800 is formed, which covers the target layer 400; a first mask pattern layer 801 is formed, which is located on the first mask layer 800.

[0098] Reference Figure 5 As shown, the first mask layer 800 includes a third sub-mask layer 800a and a fourth sub-mask layer 800b. The third sub-mask layer 800a is located on the side of the fourth sub-mask layer 800b that is close to the target layer 400. The third sub-mask layer 800a can be a spin-coated hard mask layer (SOH), and the fourth sub-mask layer 800b can be a silicon oxynitride layer (SiON).

[0099] The process of forming a plurality of spaced-apart first target patterns includes: etching a first mask layer 800 along a first mask pattern layer 801; and etching a target layer 400 along the etched first mask layer 800 to form a plurality of spaced-apart first holes 401 in the target layer 400, wherein the first holes 401 form the first target patterns.

[0100] Combination Figure 5 and Figure 6 As shown, the process of etching the first mask layer 800 along the first mask pattern layer 801 may include: etching the fourth sub-mask layer 800b along the first mask pattern layer 801. This process may use a mixed gas of CHF3 and O2, a mixed gas of CF4 and O2, a mixed gas of SF6 and O2, or a mixed gas of CH2F2 and O2 to etch and remove the fourth sub-mask layer 800b that is not covered by the first mask pattern layer 801.

[0101] Then, the third sub-mask layer 800a is etched along the first mask pattern layer 801. This process can be carried out by using a mixture of O2 and C and S or a mixture of SO2 and O2 to etch the third sub-mask layer 800a that is not covered by the first mask pattern layer 801.

[0102] Next, the target layer 400 is etched along the etched third sub-mask layer 800a, forming the first hole 401 in the target layer 400. This process can be achieved by etching the target layer 400 with HBr or Cl2, and the etched portion forms the first hole 401.

[0103] After forming the first target pattern, the process also includes: S300: forming an isolation layer that covers the target layer having the first target pattern.

[0104] Reference Figure 7 As shown, forming the isolation layer 500 includes: forming the isolation layer 500 using an atomic layer deposition (ALD) process, wherein the material of the isolation layer 500 includes silicon oxide (SiO2).

[0105] The thickness of the isolation layer 500 can range from 2 to 3 nm. When the thickness of the isolation layer 500 is too large, it will fill the first hole 401, which may affect the structure of the first target pattern. When the thickness of the isolation layer 500 is too small, the isolation effect on the first target pattern and the subsequently formed second target pattern cannot be guaranteed. In some embodiments, the thickness of the isolation layer 500 can be 2.3 nm, 2.5 nm, or 2.8 nm. Specifically, refer to... Figure 7 As shown, the isolation layer 500 covers the bottom of the first hole 401 and forms at least part of the sidewall of the first hole 401.

[0106] After forming the isolation layer 500 and before forming the second target pattern, the method further includes: forming a second mask layer 802, which covers the isolation layer 500; and forming a second mask pattern layer 803, which is located on the second mask layer 802.

[0107] Figure 8 This is a schematic diagram of the structure for forming the second mask layer and the second mask pattern layer provided in an embodiment of the present disclosure, with reference to... Figure 8 As shown, the second mask layer 802 includes a first sub-mask layer and a second sub-mask layer sequentially stacked along the direction away from the isolation layer 500. The first sub-mask layer and the second sub-mask layer are made of different materials. The first sub-mask layer can be a spin-coated hard mask layer (SOH), and the second sub-mask layer can be a silicon oxynitride layer (SiON).

[0108] S400: A plurality of second target patterns are formed in the target layer at intervals, and at least part of the isolation layer is located between the first target pattern and the second target pattern.

[0109] Specifically, forming the second target pattern in the target layer 400 includes: etching away a portion of the second mask layer 802 along the second mask pattern layer 803, and forming an intermediate trench 802c in the second mask layer 802, the intermediate trench 802c exposing a portion of the top surface of the isolation layer 500, and the bottom of the intermediate trench 802c being flush with the exposed top surface of the isolation layer 500.

[0110] Figure 9 This is a schematic diagram of the structure of the first sub-mask layer being etched according to an embodiment of this disclosure, with reference to... Figure 9 As shown, etching away a portion of the second mask layer 802 along the second mask pattern layer 803 includes:

[0111] A portion of the second sub-mask layer is removed by etching using a first etching process. The first etching process can be chemical etching, specifically using a mixture of CHF3 and O2, CF4 and O2, SF6 and O2, or CH2F2 and O2 to etch and remove the second sub-mask layer not covered by the second mask pattern layer 803.

[0112] A second etching process is used to etch away part of the first sub-mask layer. The second etching process can also be chemical etching, specifically using a mixture of O2 and a gas containing C and S or a mixture of SO2 and O2 to etch the first sub-mask layer that is not covered by the second mask pattern layer 803.

[0113] After the first and second sub-mask layers are etched, an intermediate trench 802c is formed. The intermediate trench 802c exposes part of the top surface of the isolation layer 500, and the bottom of the intermediate trench 802c is flush with the exposed top surface of the isolation layer 500. That is, the top surface of the first sub-mask layer located in the intermediate trench 802c is flush with the exposed top surface of the isolation layer 500.

[0114] Figure 10 for Figure 9 Top view, refer to Figure 10 As shown, the outlines of the first hole 401 and the isolation layer 500 outside the first hole 401 are both displayed. The orthographic projection of the intermediate trench 802c formed by etching the second mask pattern layer 803 onto the target layer 400 partially overlaps with the first hole 401 in the target layer 400. Figure 10 (The part outlined by the dashed line) This overlapping part will cause a short circuit in the subsequently formed contact structure 104.

[0115] After etching the second mask layer 802, the process also includes etching away the isolation layer 500 exposed by the intermediate trench 802c and exposing part of the top surface of the target layer 400. Figure 11 This is a schematic diagram of the etched isolation layer provided in an embodiment of this disclosure. Figure 12 for Figure 11 A top view. (Refer to...) Figure 11 As shown, this step specifically involves using a third etching process to etch and remove the isolation layer 500 exposed by the intermediate trench 802c. The third etching process can use a mixed gas of CHF3 and O2 or a mixed gas of CF4 and O2 to etch and remove the isolation layer 500, with an etching time not exceeding 5 seconds. The main purpose of this step is to open the isolation layer 500, exposing the target layer 400 at the bottom of the isolation layer 500.

[0116] It should be noted that this step mainly involves etching away the isolation layer 500 exposed by the intermediate trench 802c, while the isolation layer 500 covered by the first sub-mask layer is not etched away, and plays the role of isolating the first target pattern and the second target pattern in subsequent processes.

[0117] Reference Figure 12 As shown, in Figure 12 In the portion within the dashed box, the intermediate trench 802c in this step exposes not only the target layer 400, but also a portion of the isolation layer 500 and a portion of the first sub-mask layer. If the target layer 400, isolation layer 500, and first sub-mask layer are directly etched along the intermediate trench 802c to form the second hole 402, then the first hole 401 and the second hole 402 will overlap in the portion outlined in the dashed box, causing a short circuit in the final contact structure 104. The steps following this disclosure can eliminate the short circuit problem caused by this overlapping portion.

[0118] After etching the isolation layer 500, the method further includes etching away the target layer 400 exposed by the intermediate trench 802c to form a plurality of spaced second holes 402 in the target layer 400, the second holes 402 forming a second target pattern, and at least a portion of the isolation layer 500 forming the hole sidewalls of the second holes 402.

[0119] Figure 13 This is a schematic diagram of the structure of the etching target layer provided in an embodiment of this disclosure. Figure 14 for Figure 13 A top view. (Refer to...) Figure 13 As shown, only the target layer 400 is etched away along the intermediate trench 802c. Specifically, the target layer 400 exposed by the intermediate trench 802c is etched away using a fourth etching process. This fourth etching process can use HBr or Cl2 to etch away the target layer 400. HBr or Cl2 has a high selective etching ratio for the silicon oxide of the isolation layer 500, thus avoiding the removal of… Figure 12 and Figure 14 The isolation layer 500 within the dashed box effectively ensures the isolation effect on the first hole 401 and the second hole 402.

[0120] Furthermore, the bottom of the target layer 400 in the stacked layer is the third transfer mask layer 300, and the top of the third transfer mask layer 300 is a SiON layer. The specific structure of the transfer mask layer 300 will be described in detail later. HBr or Cl2 also has a high selective etching ratio for SiON layers. Therefore, an overetch process can be completed using HBr or Cl2, resulting in a profile etch vertical shape at the bottom of the second hole 402. The etching amount of this overetch can be 20% of the normal etching amount of HBr or Cl2. Based on this, the etching endpoint can be determined using an endpoint detector (EPD) process, thereby reducing the fabrication difficulty and ensuring the structural accuracy of the formed second hole 402.

[0121] In at least partially adjacent first holes 401 and second holes 402, the isolation layer 500 forming the sidewall of the first hole 401 and the isolation layer 500 forming the sidewall of the second hole 402 are the same isolation layer 500. This isolation layer 500 can be... Figure 12 The isolation layer 500 is shown in the dashed box.

[0122] This disclosure forms a first hole 401 and a second hole 402 in the target layer 400. An isolation layer 500 is formed between the first hole 401 and the second hole 402. Therefore, the first hole 401 and the second hole 402 can be used as a first target pattern and a second target pattern, respectively. Contact structures 104 are formed in the stack layer using the first target pattern and the second target pattern. An isolation layer 500 is also formed between adjacent contact structures 104. This isolation layer 500 effectively prevents adjacent contact structures 104 from contacting each other, thereby preventing short circuits between different contact structures 104 and ensuring the stability of electrical signal transmission in the contact structure 104. The contact structure 104 can be the bit line contact structure described above. Therefore, this disclosure can ensure that the charge in the bit line 901 can be smoothly written into the capacitor through the bit line contact structure, and that the stored electrical signal can be smoothly read from the capacitor.

[0123] The process of forming contact structure 104 based on the first target pattern and the second target pattern is described below.

[0124] Combination Figure 5As shown, the stack layer also includes a substrate 100, an intermediate layer 200, and a transfer mask layer 300 stacked sequentially; the target layer 400 is located on the side of the transfer mask layer 300 away from the substrate 100.

[0125] It should be noted that the substrate 100 can provide a supporting foundation for the structural layers located on the substrate 100 in the stacked layer. The material of the substrate 100 can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, or silicon-on-insulator (SOI), or other materials known to those skilled in the art.

[0126] The substrate 100 has a plurality of spaced conductive structures 101. In this embodiment, the conductive structure 101 can be an active region in the substrate 100. A shallow trench isolation 102 (STI) is provided between adjacent active regions to separate them and prevent electrical interference between them. The active region can be obtained by ion doping in the substrate 100. In some embodiments, the conductive structure 101 can also be a bit line (buried bit line) or a word line (buried word line) in the substrate 100.

[0127] An intermediate layer 200 and a transfer mask layer 300 are sequentially disposed on a substrate 100. The material of the intermediate layer 200 may include polysilicon (Poly-Si). The transfer mask layer 300 is located on the intermediate layer 200 and can be used to transfer a first target pattern and a second target pattern to the substrate 100.

[0128] Specifically, after forming the first target pattern and the second target pattern, the method further includes: sequentially etching the transfer mask layer 300, the intermediate layer 200 and the substrate 100 along the first target pattern and the second target pattern to form a plurality of contact trenches 103 arranged in an array in the substrate 100.

[0129] The specific steps include: forming a sacrificial mask structure 600, which fills the first hole 401 and the second hole 402. Figure 15 This is a schematic diagram of the structure for forming a sacrificial mask structure provided in an embodiment of this disclosure, with reference to... Figure 15 As shown, the material of the sacrificial mask structure 600 can be silicon nitride (SiN), and the sacrificial mask structure 600 can be formed by chemical vapor deposition (CVD).

[0130] In some embodiments, a silicon nitride layer may be deposited, partially filling the first hole 401 and the second hole 402. Then, a chemical mechanical polishing (CMP) process is used to make the top surface of the silicon nitride layer flush with the top surface of the target layer 400. Thus, the silicon nitride layer located in the first hole 401 and the second hole 402 forms the sacrificial mask structure 600.

[0131] After forming the sacrificial mask structure 600, the process also includes: removing the target layer 400 and the isolation layer 500 located on the sidewall of the sacrificial mask structure 600. Figure 16 This is a schematic diagram of the structure for removing the target layer and part of the isolation layer according to an embodiment of the present disclosure, with reference to... Figure 16 As shown, the target layer 400 can be removed by etching with HBr or Cl2. HBr or Cl2 has a high etching selectivity for both the silicon nitride of the sacrificial mask structure 600 and the silicon oxide of the isolation layer 500, thus avoiding any impact on the sacrificial mask structure 600 and the isolation layer 500.

[0132] The isolation layer 500 can be removed by etching with DHF (hydrofluoric acid solution) for approximately 15 seconds. Since the isolation layer 500 located at the bottom of the sacrificial mask structure 600 is covered by the sacrificial mask structure 600, it will not be removed by DHF. This step only removes the isolation layer 500 located on the sidewall of the sacrificial mask structure 600.

[0133] After removing the target layer 400 and part of the isolation layer 500, the process also includes: sequentially etching the transfer mask layer 300, the intermediate layer 200 and the substrate 100 along the sacrificial mask structure 600.

[0134] Specifically, the transfer mask layer 300 includes a first transfer mask layer 300, a second transfer mask layer 300, and a third transfer mask layer 300 sequentially stacked along a direction away from the substrate 100. The material of the first transfer mask layer 300 may include silicon oxide (SiO2). Both the second and third transfer mask layers 300 include a spin-coated hard mask layer (SOH) and a silicon oxynitride layer (SiON).

[0135] Based on this, the specific etching process of the transfer mask layer 300 can be as follows:

[0136] The third transfer mask layer 300 is etched along the sacrificial mask structure 600 to form a plurality of first transfer structures 304 arranged in an array in the third transfer mask layer 300. Figure 17 This is a schematic diagram of the structure forming the first transfer structure provided in an embodiment of the present disclosure. Figure 17 Multiple first transfer structures 304 are shown. The bottom of the first transfer structure 304 is a spin-coated hard mask layer, and the top is a silicon oxynitride layer.

[0137] After forming the first transfer structure 304, the method further includes: forming a sacrificial layer 700, which covers the first transfer structure 304. Figure 18 This is a schematic diagram of the structure for forming a sacrificial layer provided in an embodiment of the present disclosure. Figure 19 This is a schematic diagram of the sacrificial layer structure for planarization processing provided in an embodiment of this disclosure. (Refer to...) Figure 18 As shown, the sacrificial layer 700 can be formed by a CVD process. Part of the sacrificial layer 700 fills the gap between adjacent first transfer structures 304, and the top surface of the formed sacrificial layer 700 is higher than the top surface of the first transfer structure 304. Subsequently, the sacrificial layer 700 and the first transfer structure 304 can be processed by a CMP process to remove the silicon oxynitride layer on top of the first transfer structure 304, retaining the spin-coated hard mask layer at the bottom of the first transfer structure 304. Furthermore, the top surface of the retained sacrificial layer 700 is made flush with the top surface of the first transfer structure 304. At this point, the thickness of the retained sacrificial layer 700 is [missing information]. Figure 19 The part shown in 'c' is the middle part.

[0138] After the sacrificial layer 700 is formed, the process further includes: removing the first transfer structure 304, and the remaining sacrificial layer 700 forming a plurality of sacrificial structures 701 arranged in an array. Figure 20 This is a schematic diagram of the structure with the first transfer structure removed according to an embodiment of the present disclosure, with reference to... Figure 20 As shown, since the first transfer structure 304 retains only the bottom spin-coated hard mask layer, the spin-coated hard mask layer of the first transfer structure 304 can be consumed and removed using O2. This step does not affect the sacrificial layer 700, and the thickness of the sacrificial structure 701 formed by the sacrificial layer 700 remains the same. Figure 20 The part shown in c (with) Figure 19 (The c in them are equal).

[0139] After forming the sacrificial structure 701, the process further includes: sequentially etching the second transfer mask layer 300 and the first transfer mask layer 300 along the sacrificial structure 701 to form a plurality of second transfer structures 305 arranged in an array in the second transfer mask layer 300 and the first transfer mask layer 300. Figure 21 This is a schematic diagram of the structure forming the second transfer structure provided in an embodiment of the present disclosure, with reference to... Figure 21 As shown, during the etching of the first transfer mask layer 300 and the second transfer mask layer 300 along the sacrificial structure 701, firstly, the silicon oxynitride layer on top of the second transfer mask layer 300 is etched along the sacrificial structure 701. Based on the selective etching ratio of the silicon oxynitride layer and the silicon oxide of the sacrificial structure 701 being 1:1, assuming the thickness of the silicon oxynitride layer is... Figure 20 Therefore, after etching the silicon oxynitride layer on top of the second transfer mask layer 300, the thickness of the sacrificial structure 701 is cd.

[0140] Subsequently, using the sacrificial structure 701 as a mask, the spin-coated hard mask layer at the bottom of the second transfer mask structure is etched. This step can use O2 to consume and remove the spin-coated hard mask layer. Moreover, the selective etching ratio between the silicon of the spin-coated hard mask layer and the silicon oxide of the sacrificial structure 701 is relatively high, so this step will not affect the thickness of the sacrificial structure 701.

[0141] Subsequently, the first transfer mask layer 300 is etched using the sacrificial structure 701 and the etched spin-coated hard mask layer together as a mask. Specifically, the silicon oxynitride layer at the top and the spin-coated hard mask layer at the bottom of the second transfer mask layer 300 are etched using the sacrificial structure 701 as a mask, and then the bottom first transfer mask layer 300 is etched using the spin-coated hard mask layer as a mask.

[0142] Specifically, when etching the first transfer mask layer 300 using a spin-coated hard mask layer as a mask, the selective etching ratio of silicon oxide in the first transfer mask layer 300 to silicon in the spin-coated hard mask layer is 1:4. Therefore, adjusting the thickness of the spin-coated hard mask layer can satisfy the purpose of etching the depth of the bottom first transfer mask layer 300. The thickness of the first transfer mask layer 300 is... Figure 20 In this way, the etching depth along the spin-coated hard mask layer is much greater than cd, so as to meet the etching depth requirements of the bottom substrate 100.

[0143] After etching the transfer mask layer 300, the process also includes etching the intermediate layer 200 along the second transfer structure 305. Figure 22 This is a schematic diagram of the structure of the etching intermediate layer provided in an embodiment of this disclosure, with reference to... Figure 22 As shown, since the intermediate layer 200 is a polysilicon layer, HBr or Cl2 can be used to etch the intermediate layer 200.

[0144] After etching the intermediate layer 200, the process further includes etching the substrate 100 along the second transfer structure 305 to form a contact trench 103 in the substrate 100. Figure 23 This is a schematic diagram of the structure for forming contact trenches provided in an embodiment of this disclosure, with reference to... Figure 23 As shown, this disclosure uses silicon as an example to illustrate that the substrate 100 can be etched with HBr or Cl2 to form a contact trench 103 in the substrate 100. The contact trench 103 exposes the conductive structure 101 (i.e., the active region), which facilitates the subsequent connection of the contact structure 104 with the conductive structure 101 and makes them electrically conductive.

[0145] After forming the contact trench 103, the method further includes forming a contact structure 104 in the contact trench 103. The contact structure 104 is connected to the conductive structure 101 in a one-to-one correspondence and is electrically conductive. Figure 24This is a schematic diagram of the structure forming the contact structure provided in an embodiment of this disclosure. (Refer to...) Figure 24 As shown, the contact structure 104 can be formed by epitaxial growth technology. The material of the contact structure 104 can be single crystal silicon or single crystal silicon doped with ions. When formed by epitaxial growth technology, its resistance is lower than that of polycrystalline silicon. In this way, the conductivity of the contact structure 104 can be improved, thereby improving the performance of the semiconductor structure with the contact structure 104.

[0146] Secondly, this disclosure provides a semiconductor structure, which is fabricated using the aforementioned semiconductor structure fabrication method. This semiconductor structure can be a memory device including the aforementioned bit line contact structure. In the memory device having this bit line contact structure, the electrical signal transmission stability of the bit line contact structure is relatively high. Therefore, the storage performance of the memory device is correspondingly improved, and it also helps to increase the integration density of the memory device.

[0147] The storage device may include, for example, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), flash memory, Electrically Erasable Programmable Read-Only Memory (EEPROM), Phase Change Random Access Memory (PRAM), or Magnetoresistive Random Access Memory (MRAM). The non-storage device may be a logic device (e.g., a microprocessor, digital signal processor, or microcontroller) or a similar device. This embodiment does not limit the specific type of storage device.

[0148] In the description of the embodiments of this disclosure, it should be understood that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. In the description of this disclosure, "a plurality of" means two or more, unless otherwise precisely specified.

[0149] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a stack layer, the stack layer including a target layer; Multiple first target patterns are formed at intervals in the target layer, including: A first mask layer is formed, which covers the target layer; A first mask pattern layer is formed, the first mask pattern layer is located on the first mask layer, the first mask layer is etched along the first mask pattern layer, and the target layer is etched along the etched first mask layer to form a plurality of first holes arranged at intervals in the target layer, the first holes forming the first target pattern; An isolation layer is formed, which covers the target layer having the first target pattern; A second mask layer is formed, which covers the isolation layer; A second mask pattern layer is formed, the second mask pattern layer being located on the second mask layer; Multiple second target patterns are formed at intervals in the target layer, including: A portion of the second mask layer is etched away along the second mask pattern layer, and an intermediate trench is formed in the second mask layer. The intermediate trench exposes a portion of the top surface of the isolation layer, and the bottom of the intermediate trench is flush with the exposed top surface of the isolation layer. The isolation layer exposed by the intermediate trench is etched away, and a portion of the top surface of the target layer is exposed. The target layer exposed by the intermediate trench is etched away to form a plurality of spaced second holes in the target layer, the second holes forming the second target pattern, and at least a portion of the isolation layer forming the hole sidewalls of the second holes; At least a portion of the isolation layer is located between the first target pattern and the second target pattern; The stack layer also includes a substrate, an intermediate layer, and a transfer mask layer stacked sequentially. The target layer is located on the side of the transfer mask layer opposite to the substrate; After forming the first target pattern and the second target pattern, the process further includes: The transfer mask layer, the intermediate layer, and the substrate are sequentially etched along the first target pattern and the second target pattern to form a plurality of contact trenches arranged in an array in the substrate; A contact structure is formed in the contact groove; The transfer mask layer, the intermediate layer, and the substrate are sequentially etched along the first target pattern and the second target pattern, including: A sacrificial mask structure is formed, which fills the first hole and the second hole; Remove the target layer and the isolation layer located on the sidewall of the sacrificial mask structure; The transfer mask layer, the intermediate layer, and the substrate are sequentially etched along the sacrificial mask structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the isolation layer includes: the isolation layer covering the bottom of the first hole and forming at least a portion of the sidewall of the first hole; In at least partially adjacent first holes and second holes, the isolation layer forming the hole sidewall of the first hole and the isolation layer forming the hole sidewall of the second hole are the same isolation layer.

3. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, The second mask layer includes a first sub-mask layer and a second sub-mask layer stacked sequentially along a direction away from the isolation layer, wherein the first sub-mask layer and the second sub-mask layer are made of different materials; Etching away a portion of the second mask layer along the second mask pattern layer includes: A portion of the second sub-mask layer is removed by etching using the first etching process; A second etching process is used to etch away part of the first sub-mask layer.

4. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, Forming the isolation layer includes: forming the isolation layer using an atomic layer deposition process, wherein the material of the isolation layer includes silicon oxide; Etching away the isolation layer exposed by the intermediate trench includes: using a third etching process to etch away the isolation layer exposed by the intermediate trench.

5. The method for preparing a semiconductor structure according to any one of claims 1-2, characterized in that, The material of the target layer includes polycrystalline silicon; Etching away the target layer exposed by the intermediate trench includes: using a fourth etching process to etch away the target layer exposed by the intermediate trench.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The transfer mask layer includes a first transfer mask layer, a second transfer mask layer, and a third transfer mask layer sequentially stacked along a direction away from the substrate; Etching the transfer mask layer along the sacrificial mask structure includes: The third transfer mask layer is etched along the sacrificial mask structure to form a plurality of first transfer structures arranged in an array in the third transfer mask layer; A sacrificial layer is formed, the sacrificial layer covering the first transfer structure; The first transfer structure is removed, and the remaining sacrificial layer forms a plurality of sacrificial structures arranged in an array; The second transfer mask layer and the first transfer mask layer are sequentially etched along the sacrificial structure to form a plurality of second transfer structures arranged in an array in the second transfer mask layer and the first transfer mask layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, Etching the intermediate layer and the substrate includes: The intermediate layer is etched along the second transfer structure; The substrate is etched along the second transfer structure to form the contact trench in the substrate.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate has multiple spaced conductive structures, and the contact structures are connected to the conductive structures one-to-one and are electrically conductive.

9. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method described in any one of claims 1-8.

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