Preparation method of anti-top-injury flip LED

Abstract

The application provides a preparation method of a top-injury-preventing flip LED, which comprises sequentially growing an epitaxial layer, an N-type gallium nitride layer, a light-emitting layer, a P-type gallium nitride layer, a silicon dioxide layer, an indium tin oxide layer, a metal electrode and a DBR layer on a PSS patterned substrate, and arranging a thimble protection block on the DBR layer. The above technical scheme effectively solves the problem that the Bragg reflector layer of the flip LED chip is easily scratched due to the separation of the chip and the blue film during the die bonding process.

Description

Technical Field

[0001] This application relates to the technical field of chip fabrication, and more particularly to a method for preparing a flip-chip LED that is resistant to top damage. Background Technology

[0002] Currently, LED chips mainly include upright LED chips, flip-chip LED chips, and vertical LED chips. Flip-chip LED chips generally have the following characteristics: First, they have sapphire crystal heat dissipation, allowing for high current carrying capacity; second, they can be made smaller, making optical matching easier; third, improved heat dissipation extends chip lifespan; fourth, they offer improved anti-static capabilities; and fifth, they lay the foundation for subsequent packaging technology development.

[0003] During the die bonding process of flip-chip LEDs, the chip is often separated from the blue film by a pin. The pin can easily damage the chip, causing the passivation protective film to break, which can lead to chip leakage or damage to the chip's reflector, reducing reflection and lowering the chip's brightness. Summary of the Invention

[0004] One of the technical problems this application aims to solve is that the Bragg reflector layer of the flip-chip is easily scratched due to the separation of the chip from the blue film during the die bonding process.

[0005] To address the aforementioned technical problems, this application provides a method for fabricating a flip-chip LED with anti-top-damage feature, comprising: S10 growing an epitaxial layer, an N-type gallium nitride layer, a light-emitting layer, and a P-type gallium nitride layer sequentially on a PSS patterned substrate; S20 performing wafer cleaning based on step S10, followed by silicon dioxide deposition using a PECVD device; S30, based on step S20, coating a positive photoresist onto the surface of the silicon dioxide away from the P-type gallium nitride layer, and exposing and developing it, after which part of the silicon dioxide is protected and part is exposed on the surface; S40, based on step 30, etching and removing the photoresist from the silicon dioxide; S50, depositing an indium tin oxide (ITO) layer on the etched surface based on step S40; and S60, based on step S50, coating a positive photoresist onto the surface of the ITO layer, wherein the positive photoresist is located above the silicon dioxide and has an area of ​​[missing information]. The area is larger than that of silicon dioxide, and is exposed and developed. After development, some indium tin oxide is protected, and some is exposed on the surface. In step S70, based on step S60, indium tin oxide is etched and resist is removed. In step S80, based on step S70, the N-electrode platform is etched and resist is removed, and the etching continues until some N-type gallium nitride is etched away. After resist removal, the areas protected by photoresist are not etched, and the areas without photoresist protection are etched. In step S90, based on step S80, a dicing process is performed, positive photoresist is coated, and the area is exposed and developed. After development, some N-type gallium nitride epitaxial layer is exposed on the surface, and other areas are protected by photoresist. In step S100, based on step S90, dicing is performed. This step etches to the PSS patterned substrate, and the resist is removed after etching. In step S110, based on step S100, a metal contact electrode process is performed, negative photoresist is coated, and the area is exposed and developed. Part of the photoresist is developed away, exposing the chip surface; S120, based on S110, involves ion cleaning and acid washing of the wafer, followed by metal deposition and stripping; S130, based on S120, involves the deposition of the Bragg mirror layer; S140, based on S130, involves coating positive photoresist, exposure, and development; S150, based on S140, involves dry etching and photoresist removal of the DBR film layer; S160, based on S150, involves the contact electrode process for packaging and solder paste, coating negative photoresist, exposure, and development, exposing part of the chip surface including the DBR channel; S170, based on S160, involves ion cleaning and acid washing of the wafer, metal deposition, and stripping of the negative photoresist from step S160. The deposited metal includes metal pads and ejector pin protection blocks.

[0006] In some embodiments, there are multiple metal pads, and a pin protection block is disposed between the multiple metal pads.

[0007] In some embodiments, the thickness of the ejector pin protection block is between 2µm and 7µm.

[0008] In some embodiments, a pin protection block is disposed on the surface of the Bragg reflector layer.

[0009] In some embodiments, the surface of the ejector pin protection block away from the patterned substrate is lower than the surface of the metal pad away from the patterned substrate.

[0010] In some embodiments, the thickness of the Bragg reflector layer is between 1.8 μm and 6 μm, and / or the Bragg reflector layer employs a 57-layer stack.

[0011] In some embodiments, the Bragg reflector layer is deposited using a photonic deposition system, and the deposition material is a silicon dioxide and titanium oxide stack structure.

[0012] In some embodiments, in step S150, the Bragg mirror layer presses against the circumferential outer edge of the metal electrode, and the Bragg mirror layer has clearance holes for the metal electrode.

[0013] In some embodiments, the edge of the Bragg mirror layer near the metal electrode has a flange extending away from the patterned substrate.

[0014] In some embodiments, metal pads cover the flanged portion of the metal electrode and the Bragg reflector layer.

[0015] The above technical solution involves setting a protective pin on the Bragg reflector layer. Operating this protective pin prevents scratches on the Bragg reflector layer of the chip during separation from the blue film. Simultaneously, by connecting the protective pin and metal pads to external components, the die-bonding area is increased, improving the chip's die-bonding efficiency. This application effectively solves the problem in existing technologies where the Bragg reflector layer of flip-chip LEDs is easily scratched during die-bonding due to chip separation from the blue film. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of step S10 of the preparation method disclosed in the embodiments of this application is shown;

[0018] Figure 2 It shows Figure 1 A schematic diagram of the structure of step S20 in the preparation method;

[0019] Figure 3 It shows Figure 1 A schematic diagram of step S30 in the preparation method;

[0020] Figure 4 It shows Figure 1 A schematic diagram of step S40 in the preparation method;

[0021] Figure 5 It shows Figure 1 A schematic diagram of the structure of step S50 in the preparation method;

[0022] Figure 6 It shows Figure 1 A schematic diagram of step S60 in the preparation method;

[0023] Figure 7 It shows Figure 1 A schematic diagram of step S70 in the preparation method;

[0024] Figure 8 It shows Figure 1 A schematic diagram of the structure of step S80 in the preparation method;

[0025] Figure 9 It shows Figure 1 A schematic diagram of the structure of step S90 in the preparation method;

[0026] Figure 10 It shows Figure 1 A schematic diagram of step S100 in the preparation method;

[0027] Figure 11 It shows Figure 1 A schematic diagram of step S110 in the preparation method;

[0028] Figure 12 It shows Figure 1 A schematic diagram of step S120 in the preparation method;

[0029] Figure 13 It shows Figure 1 A schematic diagram of step S130 in the preparation method;

[0030] Figure 14 It shows Figure 1 A schematic diagram of step S140 in the preparation method;

[0031] Figure 15 It shows Figure 1 A schematic diagram of step S150 in the preparation method;

[0032] Figure 16 It shows Figure 1 A schematic diagram of step S160 in the preparation method;

[0033] Figure 17 It shows Figure 1 A schematic diagram of step S170 in the preparation method;

[0034] Figure 18 It shows Figure 1 A top view diagram of the product prepared by the method described. Detailed Implementation

[0035] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to illustrate the principles of this application by way of example, but should not be used to limit the scope of this application. This application can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0036] These embodiments are provided to make the application thorough and complete, and to fully express the scope of the application to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, material composition, numerical expressions, and values ​​illustrated in these embodiments should be interpreted as merely exemplary and not as limiting.

[0037] It should be noted that, in the description of this application, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicating orientation or positional relationship, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] Furthermore, the terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. "Vertical" is not strictly vertical, but within the permissible margin of error. "Parallel" is not strictly parallel, but within the permissible margin of error. Terms such as "including" or "contains" mean that the element preceding the word encompasses the element listed after it, and do not exclude the possibility of encompassing other elements as well.

[0039] It should also be noted that, in the description of this application, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application depending on the specific circumstances. When a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device.

[0040] All terms used in this application have the same meaning as understood by one of ordinary skill in the art to which this application pertains, unless otherwise specifically defined. It should also be understood that terms defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and not as idealized or highly formalized, unless expressly defined herein.

[0041] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0042] like Figures 1 to 18As shown, in some embodiments, the fabrication method of a flip-chip LED with anti-top-damage capability includes: S10 growing an epitaxial layer, an N-type gallium nitride layer, a light-emitting layer, and a P-type gallium nitride layer sequentially on a PSS patterned substrate. S20 performing wafer cleaning based on step S10, followed by silicon dioxide deposition using a PECVD device. S30, based on step S20, coating a positive photoresist onto the surface of the silicon dioxide away from the P-type gallium nitride layer, and exposing and developing it; after development, part of the silicon dioxide is protected, and part is exposed on the surface. S40, based on step 30, etching and photoresist removal are performed on the silicon dioxide. S50, indium tin oxide (ITO) is deposited on the etched surface based on step S40 to form an ITO layer. S60, based on step S50, coating a positive photoresist onto the surface of the ITO layer, with the positive photoresist positioned above the silicon dioxide and having an area larger than the silicon dioxide, and exposing and developing it; after development, part of the ITO is protected, and part is exposed on the surface. S70, based on step S60, involves etching and removing the photoresist from the indium tin oxide (ITO) layer. S80, based on step S70, involves etching and removing the photoresist from the N-electrode platform, etching until some N-type gallium nitride (GaN) is etched away. After photoresist removal, areas protected by photoresist remain unetched, while areas without photoresist protection are etched. S90, based on step S80, involves a dicing process, applying positive photoresist, and then exposing and developing the substrate. After development, some of the GaN epitaxial layer is exposed on the surface, while other areas are protected by photoresist. S100, based on step S90, involves dicing down to the patterned substrate, followed by photoresist removal. S110, based on step S100, involves a metal contact electrode process, applying negative photoresist, and then exposing and developing the substrate. Some of the photoresist is developed away, exposing the chip surface. S120, based on step S110, involves ion cleaning and acid washing of the wafer, followed by metal deposition and stripping. S130, based on S120, involves depositing the Bragg mirror layer. S140, based on S130, involves coating positive photoresist, followed by exposure and development. S150, based on S140, involves dry etching and photoresist stripping of the DBR film layer. S160, based on S150, involves the contact electrode process for packaging and solder paste, coating negative photoresist, followed by exposure and development, exposing the chip surface including the DBR channels. S170, based on S160, involves ion cleaning and acid washing of the wafer, metal deposition, and stripping the negative photoresist from step S160. The deposited metal includes metal pads and ejector pin protection blocks.

[0043] The above technical solution involves setting a protective pin on the Bragg reflector layer. Operating this protective pin prevents scratches on the Bragg reflector layer of the chip during separation from the blue film. Simultaneously, by connecting the protective pin and metal pads to external components, the die-bonding area is increased, improving the chip's die-bonding efficiency. This application effectively solves the problem in existing technologies where the Bragg reflector layer of flip-chip LEDs is easily scratched during die-bonding due to chip separation from the blue film.

[0044] It should be noted that the ejector pin protection block is fabricated simultaneously with the metal pads, using the same material and having the same thickness. The protection block is positioned between the two metal pads, with a distance of more than 5µm from both sides and from the chip edge. This effectively prevents short circuits caused by contact with the pads after peeling due to excessive proximity. The metal pads have the same thickness as the chip pads and are formed together via vapor deposition, a highly efficient process. The protection block prevents damage to the ejector pins during chip transfer. The ratio of the protection block's diameter to the side length of the metal pad is between 1:2 and 1:6, resulting in a compact structure where the protection block and metal pads do not interfere with each other. In some embodiments, the protection block is circular, and the metal pad is square, effectively improving visibility.

[0045] In some embodiments, there are multiple metal pads, and the ejector pin protection block is disposed between the multiple metal pads. This ensures that the force is applied more evenly when separating the chip and the blue film.

[0046] In some embodiments, the thickness of the ejector pin protection block is between 2µm and 7µm. This thickness ensures that the ejector pin protection block can be installed within a confined space. The shape of the protection block is not limited; square, circular, and elliptical shapes are all acceptable.

[0047] In some embodiments, the ejector pin protection block is disposed on the surface of the Bragg reflector layer. That is, the ejector pin protection block is located on the outside, which makes it easier to apply external forces to the ejector pin protection block, causing the chip to separate from the blue film, and the external forces are less likely to damage the DBR layer.

[0048] In some embodiments, the surface of the ejector pin protector away from the patterned substrate is lower than the surface of the metal pads away from the patterned substrate. This facilitates the application of force between the ejector pin protector and an external object. To achieve the aforementioned height difference effect, the projection of the ejector pin protector along the chip thickness is at a predetermined distance from, or intersects with, the projection of the silicon dioxide along the chip thickness direction.

[0049] In some embodiments, the thickness of the Bragg reflector layer is between 1.8 μm and 6 μm, and / or the Bragg reflector layer employs a 57-layer stack. The aforementioned Bragg reflector layer has a wider wavelength range, which is more conducive to light reflection.

[0050] In some embodiments, the Bragg reflector layer is deposited using a photonic deposition system, and the deposition material is a silicon dioxide and titanium oxide stack structure.

[0051] In some embodiments, in step S150, the Bragg mirror layer presses against the circumferential outer edge of the metal electrode, and the Bragg mirror layer has clearance holes for the metal electrode. This facilitates the fixation of the metal electrode.

[0052] In some embodiments, the edge of the Bragg mirror layer near the metal electrode has a flange extending away from the patterned substrate. This structure makes the mating between the metal pads and the DBR layer more stable.

[0053] In some embodiments, metal pads cover the flanged portion of the metal electrode and the Bragg reflector layer.

[0054] In summary, to address the above issues, this solution employs a metal protective block to protect the chip contact point of the ejector pin. After the ejector pin contacts the chip, the metal protects the chip, preventing damage to the chip's film layer. Simultaneously, by increasing the module area, the die-bonding area is increased, thereby improving the chip's die-bonding efficiency. The specific steps are as follows:

[0055] Step 1: Epitaxial layers are sequentially grown on the PSS patterned substrate: P-type gallium nitride (P-GaN), MQW light-emitting layer, and N-type gallium nitride (N-GaN), as follows: Figure 1 ;

[0056] Step Two: Based on Step One, perform wafer cleaning. After cleaning, use a PECVD device to deposit a silicon dioxide (SiO2) layer with a thickness of 2100±200 angstroms. Here, the silicon dioxide acts as a current blocking layer to prevent current from conducting downwards along the shortest path. Figure 2 ;

[0057] Step 3: Based on Step 2, apply positive photoresist, expose, and develop. After development, some silicon dioxide is protected, while some is exposed on the surface, such as... Figure 3 ;

[0058] Step Four: Based on Step Three, perform silicon dioxide etching and resist removal. Wet etching is used with BOE as the etching solution. After resist removal, the silicon dioxide protected by photoresist is retained, while the silicon dioxide without photoresist protection is etched away. Figure 4 ;

[0059] Step 5: Based on Step 4, indium tin oxide (ITO) is deposited using the Evatac magnetron sputtering equipment to a thickness of approximately 350 angstroms. Figure 5 ;

[0060] Step Six: Based on Step Five, apply positive photoresist, expose, and develop. After development, some indium tin oxide is protected, while some is exposed on the surface, such as... Figure 6 The positive photoresist coating area is greater than SiO2 and greater than or equal to indium tin oxide.

[0061] Step Seven: Based on Step Six, perform etching and resist removal of indium tin oxide (ITO). Wet etching is used, with a solution of ferric chloride and hydrochloric acid in a 10:24 ratio. After resist removal, the ITO protected by photoresist is retained, while the unprotected areas are etched away. Figure 7 ;

[0062] Step 8: Based on Step 7, perform etching and resist stripping of the N-electrode platform (MESA). Dry ICP etching is used, with an etching depth of approximately 1 ± 0.2 μm, etching until some N-type gallium nitride is removed. After resist stripping, areas protected by photoresist remain unetched, while areas without photoresist protection are etched. Figure 8 ;

[0063] Step Nine: Based on Step Eight, perform the ISO (isolation and etching) process, coat with positive photoresist, and expose and develop. After development, part of the N-type gallium nitride epitaxial layer is exposed on the surface, while other areas are protected by photoresist, such as... Figure 9 ;

[0064] Step 10: Based on Step 9, perform ISO etching and resist stripping. Dry ICP etching is used, with an etching depth of approximately 5-6 μm, etching until the PSS patterned substrate is visible. After etching, resist stripping is performed, preserving the areas protected by the photoresist; such as... Figure 10 .

[0065] Step 11: Based on Step 10, perform the metal contact electrode process, coat with negative photoresist, and expose and develop. Part of the photoresist is developed away, exposing the chip surface, such as... Figure 11 ;

[0066] Step Twelve: Based on Step Eleven, perform ion cleaning and acid washing on the wafer, followed by metal deposition and stripping. Metal deposition uses a multilayer process with metals such as chromium, aluminum, titanium, platinum, and gold, with a total thickness of approximately 2.4 μm. After stripping, some metal and photoresist are removed, leaving some metal as current-conducting electrodes, such as... Figure 12 ;

[0067] Step Thirteen: Based on Step Twelve, the Bragg reflector DBR is deposited using a photocatalytic deposition system. The deposition material is a silicon dioxide and titanium oxide stacked structure. Traditional processes use 39 or 41 layers, but this step uses a 57-layer stack with a thickness of approximately 5.8-6 μm. Compared to traditional stacks, this film has a wider wavelength range and is more conducive to light reflection. Figure 13 ;

[0068] Step Fourteen: Based on Step Thirteen, apply positive photoresist, expose, and develop. After development, part of the DBR film is exposed on the surface, while most of it is protected by the photoresist, such as... Figure 14 Positive photoresist exposed on metal

[0069] Step 15: Based on Step 14, perform dry etching and resist stripping of the DBR film. Etching creates channels that ensure the subsequent connection between the metal electrodes and the solder metal. Then, the resist is removed. After resist removal, the film appears as follows... Figure 15 ;

[0070] Step Sixteen: Based on Step Fifteen, perform the packaging and solder paste contact electrode process (bonding), apply negative photoresist, and expose and develop. The exposed portion after development includes the chip surface containing the DBR channels. Unlike traditional processes, this process also creates photolithographic patterns in the middle of the P / N bonding structure, which can be circular, square, rectangular, etc., preparing for subsequent metal deposition to create the ejector pin protection block structure, such as... Figure 16 ;

[0071] Step 17: Based on Step 16, perform ion cleaning and acid washing on the wafer, followed by metal deposition and stripping. Metal deposition uses a multilayer process with chromium, aluminum, titanium, platinum, and gold, with a total thickness of approximately 4.8µm. After stripping, some metal and photoresist are removed, leaving some metal as contact electrodes for the packaging and solder paste. Similarly, the metal block in the P / N bonding middle layer serves as a protective block for the die bond. This protective block prevents the die bond from damaging the chip during die bonding. Furthermore, by adding protective blocks, the contact area between the solder paste and the chip is increased, improving the die bonding efficiency. Figure 17 Top view as follows Figure 18 .

[0072] In this application, PSS is a patterned substrate; BBR is a Bragg mirror; MQW is a quantum well; Bonding is a metal pad; and metal is a metal electrode.

[0073] The embodiments of this application have now been described in detail. To avoid obscuring the concept of this application, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0074] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any manner.

Claims

1. A method for preparing a flip-chip LED with anti-top-damage feature, characterized in that, include: S10 grows an epitaxial layer, an N-type gallium nitride layer, a light-emitting layer, and a P-type gallium nitride layer sequentially on a PSS patterned substrate; S20 performs wafer cleaning based on step S10, and then uses PECVD equipment to deposit silicon dioxide. S30 Based on step S20, positive photoresist is coated on the surface of silicon dioxide away from the P-type gallium nitride layer, and then exposed and developed. After development, part of the silicon dioxide is protected and part is exposed on the surface. S40, based on step 30, performs silicon dioxide etching and resist removal; S50 involves depositing an indium tin oxide layer onto the etched surface based on step S40. S60, based on step S50, applies a positive photoresist to the surface of the indium tin oxide layer. The positive photoresist is located above the silicon dioxide and has an area larger than that of the silicon dioxide. The layer is then exposed and developed. After development, some of the indium tin oxide is protected, while some is exposed on the surface. S70, based on step S60, involves etching and removing the resist from indium tin oxide; Based on step S70, S80 performs etching and photoresist removal on the N-electrode platform, etching until some N-type gallium nitride is etched away. After photoresist removal, the areas protected by photoresist are not etched, while the areas without photoresist protection are etched. Based on step S80, S90 performs a dicing process, coats positive photoresist, and exposes and develops the surface. After development, part of the N-type gallium nitride epitaxial layer is exposed on the surface, while other areas are protected by photoresist. Based on step S90, S100 performs etching of the cutting path, which is carried out to the patterned substrate. After etching, the resist is removed. Based on step S100, S110 performs the metal contact electrode process, coats negative photoresist, and exposes and develops it. Part of the photoresist is developed away, exposing the chip surface. S120, based on S110, performs ion cleaning and acid washing of the wafer, as well as metal deposition and stripping. S130 is based on S120, and a Bragg mirror layer is deposited; S140 is based on S130, with positive photoresist coated, exposed, and developed; Based on S140, S150 performs dry etching and resist removal processes on the DBR film layer; Based on S150, S160 performs packaging and solder paste contact electrode processes, applies negative photoresist, and exposes and develops the chip surface, including the DBR channel. S170, based on S160, involves ion cleaning and acid washing of the wafer, deposition of metal, and stripping of the negative photoresist from step S160. The deposited metal includes metal pads and pin protection blocks.

2. The preparation method according to claim 1, characterized in that, There are multiple metal pads, and the ejector pin protection block is disposed between the multiple metal pads.

3. The preparation method according to claim 2, characterized in that, The thickness of the ejector pin protection block is between 2µm and 7µm.

4. The preparation method according to claim 1, characterized in that, The pin protection block is disposed on the surface of the Bragg reflector layer.

5. The preparation method according to claim 1, characterized in that, The surface of the ejector pin protection block away from the patterned substrate is lower than the surface of the metal pad away from the patterned substrate.

6. The preparation method according to any one of claims 1 to 5, characterized in that, The thickness of the Bragg reflector layer is between 1.8 μm and 6 μm, and / or the Bragg reflector layer is a 57-layer stack.

7. The preparation method according to claim 6, characterized in that, The Bragg reflector layer was deposited using a photocatalytic deposition system, and the deposition material was a silicon dioxide and titanium oxide stacked structure.

8. The preparation method according to claim 6, characterized in that, In step S150, the Bragg reflector layer presses against the circumferential outer edge of the metal electrode, the Bragg reflector layer having clearance holes for the metal electrode.

9. The preparation method according to claim 8, characterized in that, The Bragg reflector layer has a flange extending away from the patterned substrate at the edge near the metal electrode.

10. The preparation method according to claim 9, characterized in that, The metal pads cover the flanged portion of the metal electrode and the Bragg reflector layer.

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