A method for manufacturing an LED integrated chip

Abstract

The application relates to the technical field of LED chip, in particular to a preparation method of an LED integrated chip, which comprises the following steps: preparing second electrodes, first insulating layers and first electrodes which are longitudinally and spacedly distributed on the front surface of the light-emitting unit of a wafer substrate, bonding the whole surface containing the front surface of the first electrodes and the substrate, peeling off the wafer substrate, and preparing first pads and second pads on the back surface edge areas of the first electrodes and the second electrodes respectively, wherein the polarities of the first pads and the second pads are opposite, so that a transverse structure LED integrated chip is prepared, and the first pads and the second pads are located in the edge area of the substrate, which facilitates the electrical connection between the LED integrated chip and an external circuit.

Description

Technical Field

[0001] This invention relates to the field of LED chip technology, and in particular to a method for fabricating an integrated LED chip. Background Technology

[0002] Currently, based on the electrode distribution of LED chips (light-emitting diodes), LED chips can be divided into two basic structures: horizontal and vertical. The horizontal structure refers to the positive and negative electrodes of the LED chip being located on the same side of the epitaxial wafer, while the vertical structure refers to the positive and negative electrodes of the LED chip being distributed on opposite sides of the epitaxial wafer.

[0003] Currently, horizontal structure LED chips mainly refer to flip chips. Their connection with external circuits is mainly achieved through solder ball welding. That is, an array of solder balls is made on the bottom of the LED chip electrodes as the I / O terminal of the circuit and interconnects with the printed circuit board (i.e., PCB). However, due to the extremely small spacing between pixels (e.g., pixel spacing is 0.21mm~0.26mm), in order to avoid interconnection between adjacent pixels, the thickness of the solder, the spacing of the solder balls (i.e., pads), and the alignment accuracy between the LED chip and the solder balls need to be precisely controlled during the welding process, which increases the difficulty of connecting the LED chip with the external circuit. Summary of the Invention

[0004] To address the aforementioned shortcomings in the existing technology, the present invention provides a method for fabricating an LED integrated chip. This method can fabricate pads located in the edge region of a substrate, thereby facilitating the connection of the lateral LED integrated chip to an external circuit via bonding wires.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A method for fabricating an LED integrated chip, characterized in that the method includes: providing a wafer substrate, wherein a plurality of arrayed light-emitting units are disposed on the wafer substrate, wherein the light-emitting unit includes an epitaxial wafer, and the epitaxial wafer includes a first type semiconductor layer, a light-emitting layer, and a second type semiconductor layer arranged sequentially. A second electrode, a first insulating layer, and a first electrode spaced apart in the horizontal direction are prepared on the front side of the light-emitting unit. The same first electrode is connected to the same column of the first type semiconductor layer, and at least one end extends to the row edge of the wafer substrate. The same second electrode is connected to the same row of the second type semiconductor layer, and at least one end extends to the column edge of the wafer substrate. Provide a substrate; The entire surface containing the front side of the first electrode is bonded to the front side of the substrate; The wafer substrate is peeled off to expose the back side of the light-emitting unit, which is the light-emitting surface; A plurality of first pads spaced laterally and second pads spaced longitudinally are prepared on the back edge of the substrate. The first pads are used to electrically connect to the first electrode and to connect to the first bonding wire. The second pads are used to electrically connect to the second electrode and to connect to the second bonding wire. The polarities of the first pads and the second pads are opposite.

[0006] Its further feature is that, The steps for fabricating an array of light-emitting units include: A wafer substrate is provided, on which an epitaxial wafer is disposed, the epitaxial wafer comprising a second type semiconductor material, a light-emitting material, and a first type semiconductor material sequentially distributed; A conductive material is deposited on the surface of the first type of semiconductor material; A photolithography etching process is used to etch local areas of the conductive material, the first type semiconductor material, the light-emitting material, and the second type semiconductor material to form a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, and several second welding areas spaced apart on the row edge of the wafer substrate, thereby obtaining several arrayed light-emitting units with stepped sides. The outer edge of the second type semiconductor layer protrudes outward to form a step. After etching, the second type semiconductor layer is distributed laterally in strips on the wafer substrate, and at least one end of the second type semiconductor layer extends to the column edge of the wafer substrate to form a first welding area. The first welding area has a fourth groove, and the second welding area has a fifth groove.

[0007] Furthermore, a first metallic material is deposited in the fourth and fifth grooves to form a fourth conductive hole and a fifth conductive hole, respectively.

[0008] Furthermore, a second electrode with a row orientation is prepared on the top of the step of the second type semiconductor layer by photolithography and lift-off process, or a second electrode with a row orientation is prepared on the top of the step of the second type semiconductor layer by photolithography and lift-off process, while a plurality of first connection layers located in the second welding area are prepared. One end of the second electrode extends into the first area to be welded.

[0009] Furthermore, the second electrode includes an ohmic contact layer, a barrier diffusion layer, and a high reflectivity metal layer arranged sequentially.

[0010] Furthermore, the ohmic contact layer is made of a composite material of Cr, Ni, Al, TiAl, Au and GeAuNi alloy (i.e., chromium-gold-nickel alloy), a composite material of Au and AuZn alloy (i.e., gold-zinc alloy), AuZn, GeAuNi alloy or Au, the barrier diffusion layer is made of Pt, Ti or TiW, and the high reflectivity metal layer is made of Al, Ag or Au.

[0011] Furthermore, the material of the first electrode is conductive and adhesive, and is Cr, Ti and / or Al, but not limited to Cr, Ti and / or Al.

[0012] Furthermore, a first insulating material is deposited on the entire surface including the front side of the second electrode to form a first insulating layer; The first insulating layer is etched using a photolithography etching process to form a first through-hole, a second through-hole, and a third through-hole. The etching depth of the first through-hole extends to the current spreading layer, the etching depth of the second through-hole extends to the top of the fifth conductive hole or the first connection layer, and the etching depth of the third through-hole extends to the end of the second electrode.

[0013] Furthermore, the first insulating layer is a DBR reflective layer, a SiO2 layer, or a SiN layer.

[0014] Furthermore, a second metallic material is deposited in the first through hole, the second through hole, and the third through hole to form a first conductive hole, a second conductive hole, and a third conductive hole, respectively.

[0015] Furthermore, a number of first electrodes with longitudinal spacing are prepared on the front side of the first insulating layer using photolithography and lift-off processes, or a number of first electrodes with longitudinal spacing are prepared on the front side of the first insulating layer using photolithography and lift-off processes, while a number of second connecting layers are prepared above the first area to be welded. The first local area at the bottom of the first electrode is electrically connected to the current spreading layer through the first conductive hole, and the second local area at the bottom of the first electrode is electrically connected to the first connecting layer or the fifth conductive hole through the second conductive hole.

[0016] Furthermore, a bonding process is used to bond the entire surface containing the front side of the first electrode to the front side of the substrate.

[0017] Furthermore, the bonding process includes, but is not limited to, metal bonding processes.

[0018] Furthermore, the wafer substrate is peeled off using laser lift-off and / or chemical etching methods.

[0019] Furthermore, the back surface of the light-emitting unit is thinned using dry etching, wet etching, and / or CMP processes, so that the bottom ends of the fourth conductive hole and the fifth conductive hole are exposed. The bottom end of the fourth conductive hole is flush with the light-emitting surface, or there is a height difference between the bottom end of the fourth conductive hole and the surface where the light-emitting surface is located.

[0020] Furthermore, using photolithography and lift-off processes, a second pad is prepared at the bottom of the fourth conductive hole, and a first pad is prepared at the bottom of the fifth conductive hole. The second pad is electrically connected to the end of the second electrode through the fourth conductive hole, and the first pad is electrically connected to the first bonding layer through the fifth conductive hole.

[0021] The above-mentioned method of the present invention can achieve the following beneficial effects: In the LED integrated chip prepared by the method of this application, the first pad and the second pad are located in the edge area of ​​the LED integrated chip, which facilitates the soldering of bonding wires. This makes it convenient for the horizontally structured LED integrated chip to be connected to the external circuit through bonding wires. The light-emitting unit is electrically connected to the positive electrode of the external circuit through the first electrode, the first pad, and the first bonding wire, and electrically connected to the negative electrode of the external circuit through the second electrode, the second pad, and the second bonding wire, thereby forming a cross-distributed common anode and common cathode structure. This structure facilitates the driving IC chip using a passive driving method to drive and control the light-emitting unit. Attached Figure Description

[0022] Figure 1 This is a top-view perspective structural diagram of the LED integrated chip of the present invention; Figure 2 This is a top view schematic diagram of the structure after the light-emitting unit is formed using the method of the present invention; Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure of part AA in the middle; Figure 4 This is a magnified view of a portion of the light-emitting unit prepared using the method of the present invention. Figure 5 This is a top view schematic diagram of the structure after the second electrode is formed using the method of the present invention; Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure of a portion of BB in the middle; Figure 7 This is a magnified view of a portion of the material after the second electrode has been formed using the method of this invention. Figure 8 This is a top view schematic diagram of the structure after the first insulating layer is formed using the method of the present invention; Figure 9 for Figure 8 A schematic diagram of the cross-sectional structure of a portion of CC; Figure 10 This is a magnified view of a portion of the material after the first insulating layer has been formed using the method of this invention. Figure 11 This is a top view schematic diagram of the structure after the first electrode is formed using the method of the present invention; Figure 12 for Figure 11A schematic diagram of the cross-sectional structure of a portion of the DD; Figure 13 This is a magnified view of a portion of the area after the first electrode has been formed using the method of this invention. Figure 14 This is a cross-sectional view after bonding; Figure 15 This is a top view of the structure after the wafer substrate has been peeled off and the first type semiconductor layer has been thinned using the method of the present invention. Figure 16 for Figure 14 A schematic diagram of the cross-sectional structure of a portion of the EE; Figure 17 This is a top view schematic diagram of the structure after the first pad and the second pad are formed using the method of the present invention; Figure 18 for Figure 17 Sectional view along the FF direction; Figure 19 This is a top view of the LED integrated chip of the present invention connected to the PCB board via a first bonding wire and a second bonding wire. Figure 20 This is a cross-sectional view showing the height difference between the fourth conductive hole and the light-emitting surface of the light-emitting unit in this invention.

[0023] Reference numerals: 1. Light-emitting unit; 2. First electrode; 3. Second electrode; 4. First pad; 5. Second pad; 6. First insulating layer; 7. Chip area a; 8. Pad area b. Current spreading layer 11, first type semiconductor layer 12, light emitting layer 13, second type semiconductor layer 14, substrate 101, wafer substrate 102, second insulating layer 103, PCB board 104, bonding layer 105, first area to be soldered 140, second area to be soldered 150; First connecting layer 200, second connecting layer 300, first bonding wire 401, second bonding wire 501; First through hole 601, second through hole 602, third through hole 603, fourth through hole (i.e., fourth groove) 604, fifth through hole (i.e., fifth groove) 605. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product or device.

[0026] To address the technical challenge of precisely aligning horizontally structured LED chips when connecting them to external circuits via solder balls, which is difficult due to the extremely small spacing between adjacent pixels, the following provides two specific embodiments for fabricating horizontally structured LED integrated chips.

[0027] Example 1: A method for fabricating an LED integrated chip, the method comprising: S1, providing a wafer substrate 102, on which a plurality of arrayed light-emitting units 1 are disposed, each light-emitting unit 1 comprising an epitaxial wafer, the epitaxial wafer comprising a second type semiconductor material, a light-emitting material, and a first type semiconductor material arranged sequentially from bottom to top; the fabrication steps of the light-emitting unit 1 include: S11. A conductive material is deposited on the surface of the first type semiconductor material by electron gun evaporation or magnetron sputtering. The conductive material can form a good ohmic contact with the first type semiconductor material and has high light transmittance. In this embodiment, the conductive material is preferably ITO. S12. Using photolithography etching, local areas of the conductive material, the first type of semiconductor material, the light-emitting material, and the second type of semiconductor material are etched to form an array of distributed light-emitting units 1, including: S121. Cover the surface of the conductive material with a first photoresist; S122. Based on the first mask, the first photoresist is exposed and developed to expose a local area of ​​the conductive material. S113. Using plasma dry etching or chemical wet etching, local areas of the exposed conductive material, first type semiconductor material, light-emitting material, and second type semiconductor material are etched to form a strip-shaped second type semiconductor layer 14 with row spacing, a boss protruding from the top of the middle of the second type semiconductor layer, a fourth groove located at the end of the second type semiconductor layer (i.e., the first area to be welded 140) (after the second type semiconductor layer is thinned, the fourth groove forms a fourth through hole 604 / fourth conductive hole), several second areas to be welded located at the row edges of the substrate, and a fifth groove located in the second area to be welded (after the second type semiconductor layer is thinned, the fifth groove forms a fifth through hole 605 / fifth conductive hole). The bottom ends of the fourth and fifth grooves are located inside the second type semiconductor layer 14, and the top ends sequentially penetrate the light-emitting layer 13, the first type semiconductor layer 12, and the current spreading layer 11. The side edges of the second type semiconductor layer 14 protrude from the side surface of the light-emitting unit 1, forming a step, thereby obtaining a stepped light-emitting unit 1. (Refer to...) Figure 2 , Figure 3 , Figure 4 ; S114. Clean and remove residual first photoresist.

[0028] S2. Several second electrodes 3, a first insulating layer 6, and a first electrode 2 are sequentially prepared on the front side of the light-emitting unit 1. The polarities of the first electrode 2 and the second electrode 3 are opposite.

[0029] The specific fabrication steps include: S21, fabricating the second electrode 3 in the step region of the second type semiconductor layer 14 using photolithography and lift-off processes, specifically including: S211. Coat the entire surface containing the current spreading layer with a second photoresist; S212. Based on the second mask, a local area of ​​the second photoresist is exposed and developed to expose the top of the step of the second semiconductor layer 14, the top of the first layer to be soldered and the top of the fourth groove, and the top of the second layer to be soldered and the top of the fifth groove. S213. After development, the first metal material is deposited in the fourth and fifth grooves to form the fourth and fifth conductive holes. A first metal material is deposited on the entire surface including the remaining second photoresist using electron beam evaporation or magnetron sputtering. The first metal material includes an ohmic contact material, a diffusion barrier metal material, and a high reflectivity metal material distributed sequentially. In this application, no specific limitation is made on the ohmic contact material, the diffusion barrier metal material, and the high reflectivity metal material. In this embodiment, the material of the ohmic contact layer is preferably a composite material of Cr, Ni, Al, TiAl, Au and GeAuNi alloy (i.e., chromium-gold-nickel alloy), a composite material of Au and AuZn (i.e., gold-zinc) alloy, AuZn, GeAuNi alloy, or Au. The material of the diffusion barrier layer is preferably Pt, Ti, or TiW. The material of the high reflectivity metal layer is preferably Al, Ag, or Au. S214. Based on the development pattern, the first metal material is stripped to obtain the second electrodes 3 distributed in rows. The same second electrode 3 is located at the top edge region (i.e. the top of the step) of the second type semiconductor layer 14 in that row, and one end (i.e. the end) of the second electrode 3 extends to the upper surface of the first area to be welded 140. The bottom end of the second electrode is electrically connected to the fourth conductive hole.

[0030] It should be noted that this application does not specifically limit the end shape of the second electrode, which may be square, round, or elliptical.

[0031] S22. A first insulating material is deposited on the entire surface including the front side of the second electrode using plasma-enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD / ALD) to form a first insulating layer 6. In this application, the first insulating material is not specifically limited. In this embodiment, to increase the reflectivity of the integrated LED chip and improve light extraction efficiency, the first insulating layer 6 is a DBR reflective layer.

[0032] S23. The first insulating layer 6 is etched using photolithography to form a first through hole 601, a second through hole 602, and a third through hole 603. The etching depth of the first through hole 601 extends to the current spreading layer 11, the etching depth of the second through hole 602 extends to the top of the fifth conductive hole, and the etching depth of the third through hole 603 extends to the end of the second electrode 3.

[0033] S24. The first electrode 2 is fabricated on the front side of the first insulating layer 6 using photolithography and lift-off processes, specifically including: S241. Coat the entire surface including the first insulating layer with a third photoresist; S242. Based on the third mask, expose and develop a local area of ​​the third photoresist to expose a local area of ​​the surface of the first through hole 601 and its corresponding current spreading layer 11, the end of the third through hole and its corresponding second electrode 3, and the top of the second through hole and its corresponding fourth conductive hole. S243. After development, a second metal material is deposited in the first through hole, the second through hole, and the third through hole to form a first conductive hole, a second conductive hole, and a third conductive hole. The second metal material is deposited on the entire surface including the remaining third photoresist surface using electron beam evaporation or magnetron sputtering deposition process. The second metal material is preferably a metal with conductivity, adhesion, and high reflectivity. In this embodiment, Cr, Ti, and Al are preferred. S244. Based on the developed pattern, the second metal material is stripped to form longitudinally spaced first electrodes 2. The bottom first local region of the first electrode is connected to the current spreading layer 11 through a first conductive hole, and the bottom second local region of the first electrode 2 is electrically connected to the second conductive hole. (Reference) Figure 11 , Figure 12 , Figure 13 .

[0034] It should be noted that this application does not specifically limit the shape of the end of the first electrode (i.e., the second local region). In this embodiment, the shape of the second local region is preferably square, circular, or elliptical.

[0035] S3. Provide a substrate 101, which is preferably a silicon substrate.

[0036] S4. A bonding process is used to bond the entire surface including the front side of the first electrode to the front side of the substrate 101. In this embodiment, the specific steps of the bonding process include: S41. A bonding material is deposited on the front side of the substrate 101 using electron beam evaporation or magnetron sputtering to form a bonding layer 105. In this embodiment, the bonding material is not specifically limited. The bonding material is preferably at least one of Sn, In, AuSn, AuIn, NiSn alloy, AgIn alloy, and AgSn alloy. S42. The entire surface containing the front side of the first electrode has a trench. To prevent gaps between the entire surface containing the front side of the first electrode and the bonding layer from affecting the bonding strength, in this application, a second insulating material is deposited on the entire surface containing the front side of the first electrode to form a second insulating layer 103. A partial area on the back side of the second insulating layer 103 is filled in the trench 104. In this embodiment, the second insulating material is not specifically limited. The second insulating material is preferably at least one of benzocyclobutene resin (BCB), polyimide (i.e., PI), poly(p-phenylenebenzodioxazole) fiber (i.e., PBO), silicone, silicon-glass bonding structure (i.e., SOG), and epoxy resin. S43. The front side of the second insulating layer 103 is aligned with the bonding layer 105, and bonding is achieved by heating and applying pressure. (Refer to...) Figure 14 .

[0037] S5. The wafer substrate 102 is removed by laser lift-off or chemical etching.

[0038] In this embodiment, the light-emitting unit 1 emits blue or green light (i.e., the LED integrated chip is a blue light chip or a green light chip). The wafer substrate 102 is a sapphire substrate, which is removed using laser lift-off. The second semiconductor layer 14 is an N-type GaN layer. During lift-off, under the action of the laser beam, GaN decomposes into Ga and N2, allowing the sapphire substrate to quickly separate from the N-type GaN layer. Since the sapphire substrate is transparent and prone to optical crosstalk, in this embodiment, lifting the sapphire substrate helps improve luminous efficiency and overcome reflective crosstalk from the transparent substrate.

[0039] It should be noted that, in another embodiment, the light-emitting unit 1 emits blue light or green light (i.e., the LED integrated chip is a blue light chip or a green light chip), and the wafer substrate 102 is a silicon-based substrate. Since the silicon-based substrate is opaque, it is removed by chemical etching. If the light-emitting unit 1 emits red light (i.e., the LED integrated chip is a red light chip), the wafer substrate 102 is a GaAS substrate. Since the GaAS substrate is opaque, it is removed by chemical etching.

[0040] S6. The back side of the second type semiconductor layer 14 in the light-emitting unit is thinned using dry etching, wet etching or chemical mechanical polishing (CMP process).

[0041] In this embodiment, plasma dry etching or chemical wet etching is used to etch away the area to be etched in the second type semiconductor layer 14, exposing the back side (i.e., the light-emitting surface) of the second type semiconductor layer, the bottom end of the fourth conductive hole, and the bottom end of the fifth conductive hole. (Refer to...) Figure 15 , Figure 16 .

[0042] S7. Using photolithography and stripping processes, a first pad 4 is prepared at the bottom of the fourth conductive hole, and a second pad 5 is prepared at the bottom of the fifth conductive hole. The first pads 4 are laterally spaced along the row edges of the substrate 101, and the second pads 5 are longitudinally spaced along the column edges of the substrate 101.

[0043] The photolithography and stripping process specifically includes: S71, coating the entire back surface of the second type semiconductor layer containing the fourth conductive hole, the fifth conductive hole, and the thinned layer with the fourth photoresist. S72. Based on the fourth photomask, expose and develop a local area of ​​the fourth photoresist to expose the bottom of the fourth conductive hole and the bottom of the fifth conductive hole. S73. After development, a third metal material is deposited on the remaining fourth photoresist surface by electron gun evaporation or magnetron sputtering. In this embodiment, copper is preferred as the third metal material. S74. Based on the developed pattern, the third metal material is stripped to obtain the first pad 4 and the second pad 5, thereby fabricating an LED integrated chip. (Refer to...) Figure 17 , Figure 18 .

[0044] In this application, the first pad 4 and the second pad 5 are both located on both sides of the substrate 101 and are staggered, which can appropriately increase the area and further ensure that the first pad 4 and the second pad 5 can be stably connected with the corresponding first bonding line and second bonding line. Moreover, the first pad 4 and the second pad 5 are both located in the edge area of ​​the substrate, which facilitates the bonding of the bonding lines.

[0045] The specific structure of the LED integrated chip prepared by the above preparation method is as follows: The LED integrated chip includes a substrate 101, a chip area a distributed in the middle of the substrate, and a pad area b distributed at the edge of the substrate. The chip area a includes a plurality of arrayed light-emitting units 1, longitudinally spaced first electrodes 2, and laterally spaced second electrodes 3. The side of the light-emitting unit away from the substrate 101 is the light-emitting surface. The first electrodes 2 and the second electrodes 3 are disposed on the side of the light-emitting unit close to the substrate 101 (i.e., the first electrodes 2 and the second electrodes 3 are both disposed between the light-emitting unit 1 and the substrate 101), and one end of each electrode extends to the row edge and column edge of the substrate 101, respectively.

[0046] The light-emitting unit 1 is composed of an epitaxial wafer and a current spreading layer 11 arranged in sequence. The epitaxial wafer includes a second type semiconductor layer 14, a light-emitting layer 13, and a first type semiconductor layer 12 arranged in sequence. The side of the light-emitting unit has a stepped structure. The second type semiconductor layer 14 is arranged in a strip structure and is spaced apart on the substrate. One end of the second type semiconductor layer 14 extends toward the column edge of the substrate to form a first area to be soldered 140. Its outer edge protrudes outward to form a step. The second electrode is located on the step. The LED integrated chip also includes a number of second areas to be soldered 150 arranged at intervals along the lateral edge of the substrate.

[0047] It should be noted that, in another embodiment, the second type semiconductor layer 14 may not be a strip structure, but may be distributed in an array structure, and the same second electrode can connect the second type semiconductor layers 14 in the same row.

[0048] The LED integrated chip can be a red light chip, a green light chip, a yellow light chip, a blue light chip, an infrared light chip, or an ultraviolet light chip. In this application, the emitted light color of the LED integrated chip is not specifically limited. If the LED integrated chip is a red light chip or a yellow light chip, the material of the first type semiconductor layer 12 is P-type AlGaInP, the material of the second type semiconductor layer 14 is N-type AlGaInP, and the light-emitting layer 13 is a quantum well layer. If the LED integrated chip is a blue light chip or a green light chip, the first type semiconductor layer 12 is P-type GaN, the second type semiconductor layer 14 is N-type GaN, and the light-emitting layer 13 is a quantum well layer.

[0049] In this embodiment, the materials of the substrate 101 and the current spreading layer 11 are not specifically limited. The substrate 101 is preferably silicon, which is mainly used to carry the light-emitting unit 1. The current spreading layer 11 is preferably an ITO layer (i.e., a nano-indium tin oxide layer).

[0050] The pad area b includes several horizontally spaced first pads 4 (positive pads in this embodiment) and vertically spaced second pads 5 (negative pads in this embodiment). Both the first pads 4 and the second pads 5 are used to connect bonding wires and are respectively connected to the circuit in the PCB board 103 through the first bonding wire 401 and the second bonding wire 501. The circuit in the PCB board 103 is connected to the driving unit.

[0051] The same first electrode 2 is electrically connected to the first type semiconductor layer 12 of the same column of light-emitting units 1, and is electrically connected to the corresponding first pad 4. The same second electrode 3 is electrically connected to the second type semiconductor layer 14 of the same row of light-emitting units, and is electrically connected to the corresponding second pad 5. The first area to be soldered 140 has a fourth through hole 604, and the second area to be soldered 150 has a fifth through hole 605. The fourth through hole 604 and the fifth through hole 605 are respectively the fourth conductive hole and the fifth conductive hole filled with the first metal material. The bottom end of the second electrode 3 is electrically connected to the corresponding second pad 5 through the fourth conductive hole.

[0052] A first insulating layer 6 is provided between the first electrode 2 and the second electrode 3. In this embodiment, the first insulating layer 6 is a DBR reflective layer. The first insulating layer 6 not only has an insulating function to prevent leakage between the first electrode 2 and the second electrode 3 from affecting the electrical performance of the LED integrated chip, but also has a light reflection function. The light emitted by the light-emitting unit is reflected by the DBR reflective layer and emitted from the light-emitting surface, which helps to improve its light emission efficiency.

[0053] The first insulating layer 6 has a first through hole 601, a second through hole 602, and a third through hole 603. The first through hole 601 corresponds to a light-emitting unit. A local area at the bottom of the first electrode 2 is electrically connected to the corresponding current spreading layer 11 through the first through hole 601. The second through hole 602 corresponds to the first pad 4. The third through hole 603 corresponds to the top end of the corresponding second electrode 3. The first through hole 601, the second through hole 602, and the third through hole 603 are respectively filled with a second metal material as a first conductive hole, a second conductive hole, and a third conductive hole. The first electrode 2 is electrically connected to the corresponding current spreading layer through the first conductive hole. The second pad 5 is electrically connected to the corresponding second electrode 3 through the fourth conductive hole. The second pad 4 is electrically connected to the corresponding first electrode 2 through the fifth through hole 605 and the second through hole 602.

[0054] When the LED integrated chip is working: the driving voltage is transmitted through the first bonding wire 401, the first bonding pad 4, the fifth conductive hole, the second conductive hole, the first electrode 2, the first conductive hole, and the current spreading layer 11 to the first type semiconductor layer 12 in the light-emitting unit, and through the second bonding wire 501, the second bonding pad 5, the fourth conductive hole, and the second electrode 3 to the second type semiconductor layer 14 in the light-emitting unit. The light-emitting layer 13 between the first type semiconductor layer 12 and the second type semiconductor layer 14 converts electrical energy into light energy, and the generated light is emitted through the light-emitting surface, thereby realizing the addressing control of a single light-emitting unit 1. For example, the addressing control of each light-emitting unit in the LED integrated chip can be set. The position coordinates of element 1 are (X1, Y1), (X2, Y2)...(Xn, Yn), where n is an integer. The first pad 4 includes P1, P2...Pm, which correspond to the first row, second row...m row in the light-emitting unit array, respectively. The second pad 5 includes K1, K2...Km, which correspond to the first column, second column...m column in the light-emitting unit array, respectively, where m is an integer. When P1 and K1 are turned on, the light-emitting unit 1 at position (X1, Y1) in the first row and first column corresponding to them is controlled to light up. Using the above structure of this application, it is also possible to control some or all of the light-emitting units 1 in the LED integrated chip to light up together.

[0055] Example 2: A method for fabricating an LED integrated chip. Steps S1-S7 are largely the same as the method for fabricating the LED integrated chip in Example 1, except that in step S21 of this example, a second electrode 3 is fabricated in the stepped region of the second-type semiconductor layer 14 using photolithography and lift-off processes, while simultaneously forming a first interconnect layer 200. Specifically, this includes: S211. Coat the entire surface containing the current spreading layer with a second photoresist; S212. Based on the second mask, a local area of ​​the second photoresist is exposed and developed to expose the top of the step, the top of the fourth groove, and the top of the fifth groove of the second type semiconductor layer 14. S213. After development, a first metal material is deposited in the fourth and fifth grooves to form a fourth conductive hole and a fifth conductive hole. The first metal material is deposited on the entire surface including the remaining second photoresist surface using electron beam evaporation or magnetron sputtering. The first metal material includes an ohmic contact material, a barrier diffusion metal material, and a high reflectivity metal material. In this application, no specific limitation is made on the ohmic contact material, the barrier diffusion metal material, and the high reflectivity metal material. In this embodiment, the material of the ohmic contact layer is preferably a composite material of Cr, Ni, Al, TiAl, Au and GeAuNi alloy (i.e., chromium-gold-nickel alloy), a composite material of Au and AuZn alloy (i.e., gold-zinc alloy), AuZn, GeAuNi alloy, or Au. The material of the barrier diffusion layer is preferably Pt, Ti, or TiW. The material of the high reflectivity metal layer is preferably Al, Ag, or Au. S214. Based on the developing pattern, the first metal material is stripped to obtain row-spaced second electrodes 3 and a first connecting layer 200 located at the top of the fifth conductive hole. The same second electrode 3 is located at the top edge region (i.e., the top of the step) of the row of second-type semiconductor layer 14, and one end (i.e., the end) of the second electrode 3 extends to the top of the fourth conductive hole. (Refer to...) Figure 5 , Figure 6 , Figure 7 .

[0056] In step S23, photolithography is used to etch the first insulating layer 6 to form a first via 601, a second via 602, and a third via 603. The etching depth of the first via 601 extends to the current spreading layer 11, the etching depth of the second via 602 extends to the first interconnect layer 200, and the etching depth of the third via 603 extends to the end of the second electrode 3. (Refer to...) Figure 8 , Figure 9 , Figure 10 .

[0057] In step S24, the first electrode 2 is fabricated on the front side of the first insulating layer 6 using photolithography and lift-off processes, while simultaneously forming the second interconnecting layer 300. Specifically, this includes: S241. Coat the entire surface including the first insulating layer with a third photoresist; S242. Based on the third mask, expose and develop a local area of ​​the third photoresist to expose a local area of ​​the surface of the first via 601 and its corresponding current spreading layer 11, as well as the top of the third via. S243. After development, a second metal material is deposited in the first through hole, the second through hole, and the third through hole to form the first conductive hole, the second conductive hole, and the third conductive hole. A second metal material is deposited on the entire surface including the remaining third photoresist using electron beam evaporation or magnetron sputtering. The second metal material is preferably a metal with conductivity, adhesion, and high reflectivity. In this embodiment, Cr, Ti, and Al are preferred. S244. Based on the developed pattern, the second metal material is stripped to form a longitudinally spaced first electrode 2 and a second connecting layer 300 located at the top of a third conductive hole. A first local area at the bottom of the first electrode 2 is electrically connected to the current spreading layer 11 through the first conductive hole. A second local area at the bottom of the first electrode 2 is electrically connected to the first connecting layer 200 through the second conductive hole. The bottom of the second connecting layer 300 is connected to the end of the second electrode 3 through the third conductive hole. (Reference) Figure 11 , Figure 12 , Figure 13 .

[0058] It should be noted that, in another embodiment, the third conductive hole may not be provided, and the second connecting layer 300 only serves to support and fill the space between the second pad 5 and the second electrode 3.

[0059] In the above-described fabrication process, the second interconnecting layer 300 is formed simultaneously with the fabrication of the first electrode 2, and the first interconnecting layer 200 is formed simultaneously with the fabrication of the second electrode 3. This eliminates the need for operations such as opening holes and electroplating metal inside the holes to form interconnecting layers after removing the wafer substrate 102, greatly simplifying the fabrication process. Furthermore, in this embodiment, the first interconnecting layer 200 fills the space between the second and fifth conductive holes below the first pad 4, facilitating current conduction between the first pad and the first electrode, and also providing support and preventing the first pad 4 from collapsing. The second interconnecting layer 300 fills the space between the fourth conductive hole and the first insulating layer 6 below the second pad, providing support and preventing the second pad 5 from collapsing. This avoids the problem of the first and second bonding wires failing to connect securely to their respective first and second pads due to collapse, thus affecting current conduction.

[0060] The specific structure of the LED integrated chip prepared by the above method is as follows: (Reference) Figure 1 The structure of the light-emitting unit, the first electrode, the second electrode, and the first insulating layer is the same as that in Embodiment 1. The difference is that the LED integrated chip in this embodiment also includes a first connecting layer 200 and a second connecting layer 300. The second connecting layer 300 is located in the first area to be soldered 140 and is disposed between the ends of the first insulating layer 6 and the second electrode 3. The first connecting layer 200 is located in the second area to be soldered 150 and is disposed between the fifth conductive hole and the second conductive hole, for electrically connecting the first solder pad 4 and the first electrode 2.

[0061] The first insulating layer 6 has a first conductive hole, a second conductive hole, and a third conductive hole. The first conductive hole corresponds to the light-emitting unit 1. The bottom end of the first electrode is electrically connected to the corresponding current extension layer 11 through the first conductive hole. The second conductive hole corresponds to the first connecting layer 200. The bottom end of the first electrode 2 is electrically connected to the corresponding fifth conductive hole through the second conductive hole and the first connecting layer 200. The third through hole 603 corresponds to the end of the second electrode 3. The bottom end of the second connecting layer 300 is connected to the top end of the second electrode through the third conductive hole.

[0062] In this embodiment, the second connecting layer 300 is disposed at the top end of the second electrode 3, and the bottom end of the fourth through hole 604 is flush with the light-emitting surface of the light-emitting unit.

[0063] It should be noted that, to avoid uneven grinding and uneven grinding surfaces during the LED integrated chip fabrication process, especially when using CMP to thin the second type semiconductor layer, the hardness of the second metal material filling the fourth via (used to fabricate the second electrode) being greater than the hardness of the surrounding second type semiconductor material, which could affect subsequent wire bonding processes, in another embodiment, a height difference H1 can be set between the bottom of the fourth conductive hole and the light-emitting surface of the light-emitting unit. In this embodiment, the second pad 5 can be directly disposed at the bottom of the second type semiconductor layer 14, and the driving voltage transmits the current signal to the second electrode 3 through a local area of ​​the second type semiconductor layer and the fourth conductive hole. Figure 20 .

[0064] When the LED integrated chip is working: the driving voltage is transmitted through the first bonding wire 401, the first pad 4, the fifth conductive hole, the first connection layer 200, the second conductive hole, the first electrode 2, and the current spreading layer 11 to the first type semiconductor layer 12 in the light-emitting unit 1, and through the second bonding wire 501, the second pad 5, the fourth conductive hole, and the second electrode 3 to the second type semiconductor layer 14 in the light-emitting unit 1. The light-emitting layer 13 between the first type semiconductor layer 12 and the second type semiconductor layer 14 converts electrical energy into light energy, and the generated light is emitted through the light-emitting surface, thereby realizing the addressing of a single light-emitting unit 1. Control, for example, sets the position coordinates of each light-emitting unit 1 in the LED integrated chip as (X1, Y1), (X2, Y2)...(Xn, Yn), where n is an integer. The first pad 4 includes P1, P2...Pm, corresponding to the first row, second row...m row of the light-emitting unit array, respectively. The second pad 5 includes K1, K2...Km, corresponding to the first column, second column...m column of the light-emitting unit array, respectively, where m is an integer. When P1 and K1 are turned on, the light-emitting unit 1 at position (X1, Y1) in the first row and first column corresponding to them is controlled to light up. Using the above structure of this application, it is also possible to control some or all of the light-emitting units 1 in the LED integrated chip to light up together.

[0065] In Embodiments 1 and 2 above, the first pads 4 at the ends of two adjacent columns of first electrodes are staggered, and the second pads 5 at the ends of two adjacent rows of second electrodes are staggered. Taking the first electrode 2 as an example, the staggered distribution means that the first pads 4 at the ends of one column of first electrodes are located on one side of the chip area, and the first pads 4 at the ends of the adjacent column of first electrodes are located on the other side of that column of light-emitting units 1. This staggered distribution reduces the number of pads on one side of the LED integrated chip, which is beneficial for increasing the area of ​​the first pads 4 and the second pads 5. Thus, the size of the pads is increased without reducing the effective area of ​​the LED integrated chip. This is especially beneficial in scenarios where the LED integrated chip corresponds to a large number of pins on the packaging substrate, as it improves the stability of the subsequent connection between the LED integrated chip and other devices or external circuits.

[0066] The LED integrated chip of Embodiment 1 or Embodiment 2 described above is applied to a display device or lighting equipment. For example, it is applied to a display device composed of several arrayed display modules. Each display module includes a PCB board 104, light-emitting elements arrayed on the front side of the PCB board, and driving units distributed on the back side of the PCB board. The light-emitting elements are the aforementioned LED integrated chip. (See...) Figure 19 The driving unit is driven by PM, including the driver IC.

[0067] Compared to discrete devices, the structural design of the first electrode 2 and the first pad 4, and the second electrode 3 and the second pad 5 in the LED integrated chip of this application enables the LED integrated chip to directly use existing driver IC chips to achieve drive control, and can be used in conjunction with optical systems in medium and large-sized displays (e.g., 100 inches and above).

[0068] In LED integrated chips manufactured using the process method of this application, the size of a single light-emitting unit can reach 10μm~100μm, and the number of integrated light-emitting units can be gradually increased according to the development of the processing technology. For example, at present, the number of light-emitting units in a 1mm*1mm integrated chip is 15*16, that is, 15 rows and 16 columns of light-emitting units are set in a 1mm*1mm LED integrated chip. After the process yield is improved, the number of light-emitting units integrated in an LED integrated chip of the same area can be further increased.

[0069] It is understood that the above detailed description of the present invention is for illustrative purposes only and is not intended to limit the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. A method for fabricating an LED integrated chip, characterized in that, The method includes: providing a wafer substrate (102), on which a plurality of arrayed light-emitting units (1) are disposed, the light-emitting unit (1) including an epitaxial wafer, the epitaxial wafer including a second type semiconductor layer (14), a light-emitting layer (13) and a first type semiconductor layer (12) arranged sequentially. A second electrode (3) with a horizontally spaced distribution, a first insulating layer (6), and a first electrode (2) with a vertically spaced distribution are prepared on the front side of the light-emitting unit. The same first electrode (2) is electrically connected to the same column of the first type semiconductor layer (12), and at least one end extends to the row edge of the wafer substrate (102). The same second electrode (3) is electrically connected to the same row of the second type semiconductor layer (14), and at least one end extends to the column edge of the wafer substrate (102). Provide a substrate (101); The entire surface containing the front side of the first electrode is bonded to the front side of the substrate (101); The wafer substrate (102) is peeled off to expose the back side of the light-emitting unit (1), which is the light-emitting surface; A plurality of first pads (4) spaced laterally and second pads (5) spaced longitudinally are prepared on the back edge of the substrate (101). The first pads (4) are used to electrically connect to the first electrode (2) and to electrically connect to the first bonding wire. The second pads (5) are used to electrically connect to the second electrode (3) and to electrically connect to the second bonding wire. The polarities of the first pads (4) and the second pads (5) are opposite.

2. The method for fabricating an LED integrated chip according to claim 1, characterized in that, The steps for preparing array-distributed light-emitting units (1) include: A wafer substrate (102) is provided, on which an epitaxial wafer is disposed, the epitaxial wafer comprising a second type semiconductor material, a light-emitting material, and a first type semiconductor material arranged sequentially; A conductive material is deposited on the surface of the first type of semiconductor material; Photolithography is used to etch local areas of the conductive material, the first type semiconductor material, the light-emitting material, and the second type semiconductor material to form a first type semiconductor layer (12), a light-emitting layer (13), a second type semiconductor layer (14), and several second welding areas (150) spaced apart on the row edge of the wafer substrate, thereby obtaining several arrayed light-emitting units (1) with stepped sides. The outer edge of the second type semiconductor layer (14) protrudes outward to form a step. After etching, the second type semiconductor layer (14) is distributed horizontally in strips on the wafer substrate (102). At least one end of the second type semiconductor layer (14) extends to the column edge of the wafer substrate (102) to form a first welding area (140). The first welding area (140) has a fourth groove, and the second welding area (150) has a fifth groove.

3. The method for fabricating an LED integrated chip according to claim 2, characterized in that, A first metallic material is deposited in the fourth and fifth grooves to form a fourth conductive hole and a fifth conductive hole, respectively. A second electrode (3) with a row orientation is prepared at the top of the step of the second type semiconductor layer (14) by photolithography and lift-off process, or a second electrode (3) with a row orientation is prepared at the top of the step of the second type semiconductor layer (14) by photolithography and lift-off process, and a number of first interconnect layers (200) located above the second welding area are prepared simultaneously. One end of the second electrode (3) extends to the first area to be welded (140).

4. The method for fabricating an LED integrated chip according to claim 3, characterized in that, The second electrode (3) includes an ohmic contact layer, a barrier diffusion layer, and a high reflectivity metal layer arranged sequentially. The ohmic contact layer is made of a composite material of Cr, Ni, Al, TiAl, Au and GeAuNi alloy, a composite material of Au and AuZn alloy, AuZn, GeAuNi alloy, or Au. The barrier diffusion layer is made of Pt, Ti, or TiW. The high reflectivity metal layer is made of Al, Ag, or Au.

5. The method for fabricating an LED integrated chip according to claim 4, characterized in that, A first insulating material is deposited on the entire surface including the front side of the second electrode to form a first insulating layer (6). The first insulating layer (6) is etched using photolithography to form a first through hole (601), a second through hole (602), and a third through hole (603). The etching depth of the first through hole (601) extends to the current spreading layer (11), the etching depth of the second through hole (602) extends to the top of the fifth conductive hole or the first connecting layer (200), and the etching depth of the third through hole (603) extends to the end of the second electrode (3).

6. The method for fabricating an LED integrated chip according to claim 5, characterized in that, The first insulating layer (6) is a DBR reflective layer, a SiO2 layer, or a SiN.

7. The method for fabricating an LED integrated chip according to claim 6, characterized in that, A second metal material is deposited in the first through hole (601), the second through hole (602), and the third through hole (603) to form a first conductive hole, a second conductive hole, and a third conductive hole, respectively; A first electrode (2) with longitudinal spacing is prepared on the front side of the first insulating layer (6) by photolithography and lift-off process, or a first electrode (2) with longitudinal spacing is prepared on the front side of the first insulating layer (6) by photolithography and lift-off process, and a number of second connecting layers (300) are prepared above the first area to be welded. The first local area at the bottom of the first electrode (2) is electrically connected to the current spreading layer (11) through the first conductive hole, and the second local area at the bottom of the first electrode (2) is electrically connected to the first connecting layer (200) or the fifth conductive hole through the second conductive hole.

8. The method for fabricating an LED integrated chip according to claim 7, characterized in that, The entire surface containing the front side of the first electrode is bonded to the front side of the substrate (101) using a bonding process, and the wafer substrate (102) is peeled off using laser lift-off and / or chemical etching methods.

9. The method for fabricating an LED integrated chip according to claim 8, characterized in that, The back side of the light-emitting unit (1) is thinned by dry etching, wet etching and / or CMP process, so that the bottom end of the fourth conductive hole and the bottom end of the fifth conductive hole are exposed. The bottom end of the fourth conductive hole is flush with the light-emitting surface, or there is a height difference between the bottom end of the fourth conductive hole and the surface where the light-emitting surface is located.

10. The method for fabricating an LED integrated chip according to claim 9, characterized in that, Using photolithography and stripping processes, a second pad (5) is prepared at the bottom of the fourth conductive hole, and a first pad (4) is prepared at the bottom of the fifth conductive hole. The second pad (5) is electrically connected to the end of the second electrode (3) through the fourth conductive hole, and the first pad (4) is electrically connected to the first connecting layer (200) through the fifth conductive hole.

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