A low-power current detection circuit in DC-DC

Abstract

The application relates to the technical field of integrated circuits, in particular to a low-power current detection circuit in a DC-DC. The low-power current detection circuit comprises a first operational amplifier, a first NMOS tube, a first resistor, an eighth HPMOS tube, an eighth PMOS tube, a seventh HNMOS tube, a first HNMOS tube, a second HNMOS tube, a third HNMOS tube, a fourth HNMOS tube, a fifth HNMOS tube, a sixth HNMOS tube, a first comparator, a second operational amplifier, a second NMOS tube, a second resistor, a fourth PMOS tube, a fifth PMOS tube, a third operational amplifier, a third NMOS tube, a third resistor, a sixth NMOS tube, a seventh NMOS tube, a first LNMOS tube, a second LNMOS tube, a third LNMOS tube, a fourth LNMOS tube, a fifth LNMOS tube, a sixth LNMOS tube and a second comparator; the application solves the efficiency problem under light load, simultaneously enables the switching converter to work in low-duty-cycle voltage conversion, realizes that small voltage can be outputted when large input voltage, and can be smoothly switched from the PWM mode to the PFM mode.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-power peak-valley current detection circuit in a DC / DC switching regulator power supply circuit. Background Technology

[0002] DC / DC switching regulators are widely used in power management units due to their high efficiency, adjustable output voltage, and high drive capability. The output voltage of a switching regulator is controlled by an internally generated duty cycle signal. A straightforward method is to continuously monitor the output voltage and adjust the duty cycle accordingly. If the output voltage is lower than the target value, increasing the duty cycle allows more energy to be transferred to the output. If the output voltage exceeds the target value, decreasing the duty cycle reduces the energy transferred to the output. Therefore, the output voltage can be controlled under all load conditions or output voltage variations. To achieve a circuit where load variations do not cause the output voltage to deviate from the target voltage, closed-loop control is necessary. Closed-loop control methods can be broadly categorized into two types: fixed-frequency control and ripple-based control. Fixed-frequency control requires both voltage-mode and current-mode control, which requires additional inductor current information. In contrast, ripple-based control does not require a clock signal to indicate the start of each switching cycle. Instead, the switching frequency varies with the required output voltage or induced current.

[0003] The voltage control mode uses the difference between the feedback voltage Vfb and the reference voltage Vref to represent the trend (i.e., increase or decrease) of the duty cycle. Typically, a single-ended output error amplifier (EA) amplifies the difference between Vfb and Vref to generate an error signal Vc. Next, Vc is compared with a synchronization signal Vramp generated by the clock signal to generate the duty cycle of control signals S1 and S2 that control the switching of the upper and lower transistors. Through closed-loop control, Vfb eventually equals Vref, thus achieving voltage regulation. The voltage control mode is a single-loop control with only an output voltage feedback loop, making its loop design easy to debug, but requiring a complex frequency compensation network to stabilize the system. It also has advantages such as low cost, small size, and strong noise immunity. However, voltage control also has some disadvantages, such as the aforementioned complex compensation network and its relatively slow transient response.

[0004] The current control mode can be divided into three types according to the location of the detected current: peak current mode, average current mode and valley current mode.

[0005] Peak current mode control is the simplest of all current control modes. In a current-mode controlled switching regulator, besides the original voltage-mode control module, the induced inductor current Vs is added to Vramp to generate a summation signal Vsum, i.e., Vsum = Vs + Vramp. Compared to voltage-mode control, which determines the duty cycle by comparing Vramp and Vc, current-mode control obtains the duty cycle T by comparing the induced inductor current Vs and the error amplifier output signal Vc. When the duty cycle is high, the upper transistor is turned on, and the inductor current Vs increases. When Vs equals Vc, the duty cycle is determined. That is, when Vs reaches Vc, the duty cycle is low, the upper transistor is turned off, the lower transistor is turned on, and Vs decreases. In summary, the duty cycle T is controlled by the inductor current; therefore, this control mode is called peak current mode control. Peak current mode control introduces both the output voltage and the inductor current, both serving as feedback variables, thus improving the performance of the switching converter. Peak current mode (CCM) control offers several advantages: faster transient response and higher output voltage regulation accuracy; the introduction of a current control loop reduces the converter to a first-order system, lowering the complexity of the frequency compensation network. However, CCM also has some drawbacks: when the switching regulator performs voltage conversion with a duty cycle higher than 50%, subharmonic oscillations can occur in CCM mode. Therefore, a slope compensation circuit is needed to address this issue, which increases the complexity and cost of the circuit design.

[0006] Valley current control incorporates both voltage and current loops. The current detection circuit detects the current in the freewheeling diode, and the sampled lower diode current signal Vss and the error amplifier output Vc are simultaneously input to a comparator. When the sampled current decreases to equal the error amplifier output signal, the comparator output level flips, turning on the upper diode and increasing the inductor current. After the clock signal Vramp arrives for the next cycle, the duty cycle is reset. It can be seen that the duty cycle is related to the valley inductor current at this point; therefore, this control mode is called valley current control mode. Valley current control mode can achieve a very low duty cycle, enabling large input and low output. Because parasitic effects at the switching node can cause oscillations during inductor current detection, switching converters using peak current mode control have an idle time, or blanking time, typically 200-300ns, before detecting the inductor current. Therefore, the minimum on-time of the switching regulator using peak current mode control is limited by this time. Furthermore, when the switching regulator operates at a low duty cycle, the upper transistor's on-time is very short, making current sampling difficult. However, the lower transistor's on-time is long at this time, so when using valley current mode control, dealing with this duty cycle situation becomes much simpler.

[0007] Peak current mode control generally uses two methods to detect the inductor current flowing through the upper transistor. The first is to detect the voltage drop across the upper transistor's on-resistance Rds when it is turned on. The second is to connect a known resistor in series between the input voltage and the drain of the upper transistor, using this resistor as a sampling resistor to detect the voltage drop across it. However, both methods can cause oscillation at the switching node. Therefore, before detecting the inductor current, the loop control module must wait for a period of time to avoid oscillation; this period is called the blanking time. The blanking time is typically 200ns to 300ns. Introducing this blanking time also introduces several drawbacks, such as fixing the minimum on-time of the upper transistor in the switching regulator. The existence of the minimum on-time makes the upper transistor's on-time independent of the clock pulse signal in the loop. Therefore, when the output voltage is much lower than the minimum on-resistance, the switching regulator needs to achieve a low duty cycle voltage conversion, preventing the system from reaching a high frequency. Even if the inductor current rise time is longer than the blanking time, the internal time used to sample the inductor current is very short. It is difficult to operate at a low duty cycle. However, these drawbacks can be avoided by sampling the valley current. The turn-off time of the upper transistor can be controlled by sampling the signal of the lower transistor, thereby achieving low duty cycle voltage conversion.

[0008] Based on the above analysis, it is urgent to develop and design a low-power current detection circuit in DC-DC converter to solve the efficiency problem under light load, while also enabling the switching converter to operate at low duty cycle voltage transformation, realizing the output of small voltage when the input voltage is large, and smoothly switching from PWM mode to PFM mode. Summary of the Invention

[0009] The purpose of this invention is to provide a low-power current detection circuit in DC-DC converters. Based on the peak current control mode, a valley current mode control is added, which solves the efficiency problem under light load. At the same time, it enables the switching converter to operate in low duty cycle voltage conversion, realizes the output voltage when the input voltage is large, and can smoothly switch from PWM mode to PFM mode.

[0010] To address the aforementioned technical problems, this invention provides a low-power current detection circuit in a DC-DC converter, comprising: a first operational amplifier, a first NMOS transistor, a first resistor, an eighth HPMOS transistor, an eighth PMOS transistor, a seventh HNMOS transistor, a first HNMOS transistor, a second HNMOS transistor, a third HNMOS transistor, a fourth HNMOS transistor, a fifth HNMOS transistor, a sixth HNMOS transistor, a first comparator, a second operational amplifier, a second NMOS transistor, a second resistor, a fourth PMOS transistor, a fifth PMOS transistor, a third operational amplifier, a third NMOS transistor, a third resistor, a sixth NMOS transistor, a seventh NMOS transistor, a first LNMOS transistor, a second LNMOS transistor, a third LNMOS transistor, a fourth LNMOS transistor, a fifth LNMOS transistor, a sixth LNMOS transistor, and a second comparator;

[0011] In this configuration, the positive terminals of both the first and second operational amplifiers are connected to the voltage V generated by the preceding error amplifier. C The first operational amplifier is connected to the first terminal of the first resistor and the source of the first NMOS transistor; the output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor.

[0012] The drain of the first NMOS transistor is connected to the slope-compensated output terminal IRAMP and the source of the eighth HPMOS transistor; the drain of the eighth HPMOS transistor is connected to the drain of the seventh HNMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eighth PMOS transistor; the source of the eighth PMOS transistor is connected to the voltage VIN and the drain of the first HNMOS transistor.

[0013] The source of the first HNMOS transistor is connected to the drain of the second HNMOS transistor; the source of the second HNMOS transistor is connected to the drain of the third HNMOS transistor; the source of the third HNMOS transistor is connected to the drain of the fourth HNMOS transistor; the source of the fourth HNMOS transistor is connected to the drain of the fifth HNMOS transistor; the source of the fifth HNMOS transistor is connected to the drain of the sixth HNMOS transistor; and the source of the sixth HNMOS transistor is connected to the source of the seventh HNMOS transistor and the negative terminal of the first comparator.

[0014] The second end of the first resistor is grounded; the gates of the seventh HNMOS transistor, the first HNMOS transistor, the second HNMOS transistor, the third HNMOS transistor, the fourth HNMOS transistor, the fifth HNMOS transistor, and the sixth HNMOS transistor are all connected to the gate of the power transistor.

[0015] The positive terminal of the first comparator is connected to the switching node SW; the output terminal of the first comparator is connected to the subsequent control logic circuit.

[0016] The negative terminal of the second operational amplifier is connected to the first terminal of the second resistor and the source of the second NMOS transistor; the drain of the second NMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor; the second terminal of the second resistor is grounded.

[0017] The positive terminal of the third operational amplifier is connected to the reference voltage V. REF_ZC The negative terminal of the third operational amplifier is connected to the first terminal of the third resistor and the source terminal of the third NMOS transistor, and the second terminal of the third resistor is grounded.

[0018] The drain of the third NMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the sixth NMOS transistor, and the gate of the sixth NMOS transistor; the drain of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor and the gate of the seventh NMOS transistor.

[0019] The drain of the seventh NMOS transistor is connected to the source of the first LNMOS transistor and the negative terminal of the second comparator; the drain of the first LNMOS transistor is connected to the drain of the second LNMOS transistor; the source of the second LNMOS transistor is connected to the source of the third LNMOS transistor; the drain of the third LNMOS transistor is connected to the drain of the fourth LNMOS transistor; the source of the fourth LNMOS transistor is connected to the source of the fifth LNMOS transistor; and the drain of the fifth LNMOS transistor is connected to the switching node SW.

[0020] The gates of the sixth, fifth, fourth, third, second, and first LNMOS transistors are all connected to the gate of the lower power transistor; the source of the sixth LNMOS transistor is connected to the positive terminal of the second comparator, and the output of the second comparator is connected to the subsequent control logic circuit.

[0021] Preferably, the peak current detection circuit is composed of the first operational amplifier, the first NMOS transistor, the first resistor, the eighth HPMOS transistor, the eighth PMOS transistor, the seventh HNMOS transistor, the first HNMOS transistor, the second HNMOS transistor, the third HNMOS transistor, the fourth HNMOS transistor, the fifth HNMOS transistor, the sixth HNMOS transistor, and the first comparator.

[0022] Preferably, the valley current detection circuit is composed of the second operational amplifier, the second NMOS transistor, the second resistor, the fourth PMOS transistor, the fifth PMOS transistor, the third operational amplifier, the third NMOS transistor, the third resistor, the sixth NMOS transistor, the seventh NMOS transistor, the first LNMOS transistor, the second LNMOS transistor, the third LNMOS transistor, the fourth LNMOS transistor, the fifth LNMOS transistor, the sixth LNMOS transistor, and the second comparator.

[0023] Preferably, the first operational amplifier, the second operational amplifier, the third operational amplifier, the first comparator, and the second comparator are all implemented using a five-transistor operational amplifier structure.

[0024] Preferably, the peak current detection circuit enables modulation of the duty cycle in the inductor current mode PWM control; the valley current detection circuit enables limitation of the inductor current under overcurrent conditions and smooth transition of the inductor current during the switching between PWM and PFM modes.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] This invention solves the efficiency problem under light load by adding valley current mode control on the basis of peak current control mode. It also enables the switching converter to operate in low duty cycle voltage transformation, realizes the output voltage of large input voltage, and can smoothly switch from PWM mode to PFM mode. Moreover, this invention has the characteristics of high precision, low power consumption, simple structure and strong practicality. Attached Figure Description

[0027] Figure 1 This is a circuit diagram of a low-power current detection circuit in a DC-DC converter according to the present invention.

[0028] Figure 2 This is a circuit diagram of the peak current detection circuit of the present invention.

[0029] Figure 3 This is a circuit diagram of the valley current detection circuit of the present invention. Detailed Implementation

[0030] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0031] like Figure 1-3 As shown, this embodiment of the invention provides a low-power current detection circuit in a DC-DC converter, comprising a peak current detection circuit and a valley current detection circuit. The internal amplifiers and comparators in both the peak and valley current detection circuits are implemented using a five-transistor operational amplifier structure, and therefore will not be described in detail. The peak current detection circuit is used to modulate the duty cycle in the peak current-mode PWM control method adopted in this invention, while the valley current detection circuit is mainly used for limiting the inductor current under overcurrent conditions and for achieving a smooth transition of the inductor current during the switching process between PWM and PFM.

[0032] like Figure 2 As shown, the peak current detection circuit consists of a first operational amplifier AMP, a first NMOS transistor M1, a first resistor R1, and an eighth HPMOS transistor M... H8 The eighth PMOS transistor M8, the seventh HNMOS transistor M H7 The first HNMOS transistor M H1 The second HNMOS transistor M H2 The third HNMOS transistor M H3 The fourth HNMOS transistor M H4 The fifth HNMOS transistor M H5 The sixth HNMOS transistor M H6 It is composed of the first comparator CMP1. In the peak current detection circuit, the voltage V generated by the previous stage error amplifier... C First, the input is fed to the positive terminal of the operational amplifier AMP, and a control current I is generated through a unity negative feedback loop consisting of AMP, resistor R1, and M1. C The current value is V C / R1. I C With the slope compensation current I flowing in from the drain of M1 RAMP After superposition, the current flows through the high-voltage switching tube M H8 With M H7 The direction is from M H7 Flow to M H8 M H8 Controlled by the drive signal of the upper transistor, when the upper transistor is turned on, M H7 Open; and M H7 The control signal OEN_Y is high when both the upper and lower transistors are on, therefore M... H8 It is also in the conducting state. The current modulated by the previous part of the circuit flows through M. H1 ~M H6 After the peak current sampling tube is assembled, a voltage drop is generated across the sampling tube. The voltage value generated at point A is shown in equation (1), where R ON_H For M H1 ~M H6 The on-resistance of the peak current sampling transistor is determined. Simultaneously, the voltage value at the switching node SW is as shown in equation (1), where R... DS-ON_H This is the on-resistance of the high-side power transistor. When the high-side transistor is on, the voltage at point SW decreases as the inductor current increases. The comparator compares the voltages at point A and point SW and outputs the result.

[0033]

[0034] V SW =V IN -I L ·R DS-ON_H (2)

[0035] When V SW Decrease to V N_H Next, the comparator output flips, controlling the upper transistor to turn off and the lower transistor to turn on. Combining equations (1) and (2), at this time the inductor current and the output voltage V of the error amplifier are... C The relationship between them is shown in Equation (3), and the result after simplification is shown in Equation (4). When the inductor current reaches its peak, the slope compensation I... RAMP With zero static current, the peak inductor current can be calculated using the formula, which states that the peak inductor current is affected by the error amplifier output voltage V. C The control method uses peak inductor current modulation. Compared to traditional inductor current sampling, the peak current sampling control method designed in this project reduces the signal transmission path, shortens signal delay, and reduces interference and loss during signal transmission, thus offering greater advantages.

[0036]

[0037]

[0038] like Figure 3 As shown, the valley current detection circuit consists of a second operational amplifier AMP1, a second NMOS transistor M2, a second resistor R2, a fourth PMOS transistor M4, a fifth PMOS transistor M5, a third operational amplifier AMP2, a third NMOS transistor M3, a third resistor R3, a sixth NMOS transistor M6, a seventh NMOS transistor M7, and a first LNMOS transistor M1. L1 The second LNMOS transistor M L2 The third LNMOS transistor M L3 The fourth LNMOS transistor M L4 The fifth LNMOS transistor M L5 The sixth LNMOS transistor M L6 It consists of a second comparator CMP2. The valley current detection principle is similar to the peak current detection principle; when the lower transistor is turned on, V... C The control current I generated by the unity negative feedback circuit C2 After being magnified m times by a current mirror, it is compared with a fixed pull-down current I. ZC Superimposed, flowing through switch M L1 ~M L5 The voltage V at point B is obtained. N_L As shown in equation (5), where R ON_L For M L1 ~M L5 The on-resistance of the switching transistor, V REF_ZC To maintain a fixed reference voltage, resistors R2 and R3 are equal. The non-inverting input of the comparator is connected to the switching transistor M. L6 Connected to PGND, therefore the voltage V at the non-inverting input of the comparator is...P_L It equals zero. Meanwhile, the voltage value at the switching node SW is as shown in equation (6), where R... DS-ON_L This is the on-resistance of the low-side power transistor.

[0039]

[0040] V SW =V PGND -I L ·R DS-ON_L =-I L ·R DS-ON_L (6)

[0041] If V C If the voltage remains unchanged, then the current flowing through the switching transistor remains unchanged, and the voltage V at point B remains unchanged. N_L The voltage decreases continuously as the inductor current decreases. Before the inductor current drops to its limit, the voltage at point B remains above zero, and the comparator output is always low. When the voltage at point B drops to zero, V... C With inductor current limiting point I VALLY The relationship is shown in equation (7).

[0042]

[0043] As can be seen, when the control voltage V C As V gradually decreases, the limiting point of the inductor current also gradually decreases. C Reduce to clamp value V REF0 At this point, the limiting point should drop to zero, and since R2 equals R3, V... C It should be equal to V REF_ZC / m. Therefore, a fixed voltage V is set. REF_ZC Slightly higher than m times V C Since M6 and M7 are unidirectional diodes, no current flows through M6 and M7 to point B under PFM conditions. At this time, the voltage at point B is equal to SW, ensuring that the loop will always enter DCM operating mode under PFM. Furthermore, in overcurrent conditions, to limit the inductor current, a fixed voltage V is applied to the non-inverting input of the amplifier. REF_OC Limit the highest inductor current valley value when V C Higher than V REF_OC Then the voltage value at the inverting input terminal of AMP1 is clamped at V. REF_OC Place.

[0044] To reduce static power consumption and improve voltage conversion efficiency under light load, the comparators for peak current detection and valley current detection are turned off after the upper and lower transistors are turned off, respectively; when both transistors are turned off, the bias currents of amplifiers AMP, AMP1, and AMP2 are disconnected.

[0045] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-power current detection circuit in a DC-DC converter, characterized in that, include: First operational amplifier, first NMOS transistor, first resistor, eighth HPMOS transistor, eighth PMOS transistor, seventh HNMOS transistor, first HNMOS transistor, second HNMOS transistor, third HNMOS transistor, fourth HNMOS transistor, fifth HNMOS transistor, sixth HNMOS transistor, first comparator, second operational amplifier, second NMOS transistor, second resistor, fourth PMOS transistor, fifth PMOS transistor, third operational amplifier, third NMOS transistor, third resistor, sixth NMOS transistor, seventh NMOS transistor, first LNMOS transistor, second LNMOS transistor, third LNMOS transistor, fourth LNMOS transistor, fifth LNMOS transistor, sixth LNMOS transistor, and second comparator; In this configuration, the positive terminals of both the first and second operational amplifiers are connected to the voltage V generated by the preceding error amplifier. C The first operational amplifier is connected to the first terminal of the first resistor and the source of the first NMOS transistor; the output terminal of the first operational amplifier is connected to the gate of the first NMOS transistor. The drain of the first NMOS transistor is connected to the slope-compensated output terminal IRAMP and the source of the eighth HPMOS transistor; the drain of the eighth HPMOS transistor is connected to the drain of the seventh HNMOS transistor, the gate of the eighth PMOS transistor, and the drain of the eighth PMOS transistor; the source of the eighth PMOS transistor is connected to the voltage VIN and the drain of the first HNMOS transistor. The source of the first HNMOS transistor is connected to the drain of the second HNMOS transistor; the source of the second HNMOS transistor is connected to the drain of the third HNMOS transistor; the source of the third HNMOS transistor is connected to the drain of the fourth HNMOS transistor; the source of the fourth HNMOS transistor is connected to the drain of the fifth HNMOS transistor; the source of the fifth HNMOS transistor is connected to the drain of the sixth HNMOS transistor; and the source of the sixth HNMOS transistor is connected to the source of the seventh HNMOS transistor and the negative terminal of the first comparator. The second end of the first resistor is grounded; the gates of the seventh HNMOS transistor, the first HNMOS transistor, the second HNMOS transistor, the third HNMOS transistor, the fourth HNMOS transistor, the fifth HNMOS transistor, and the sixth HNMOS transistor are all connected to the gate of the power transistor. The positive terminal of the first comparator is connected to the switching node SW; the output terminal of the first comparator is connected to the subsequent control logic circuit. The negative terminal of the second operational amplifier is connected to the first terminal of the second resistor and the source of the second NMOS transistor; the drain of the second NMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fifth PMOS transistor; the second terminal of the second resistor is grounded. The positive terminal of the third operational amplifier is connected to the reference voltage V. REF_ZC The negative terminal of the third operational amplifier is connected to the first terminal of the third resistor and the source terminal of the third NMOS transistor, and the second terminal of the third resistor is grounded. The drain of the third NMOS transistor is connected to the drain of the fifth PMOS transistor, the source of the sixth NMOS transistor, and the gate of the sixth NMOS transistor; the drain of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor and the gate of the seventh NMOS transistor. The drain of the seventh NMOS transistor is connected to the source of the first LNMOS transistor and the negative terminal of the second comparator; the drain of the first LNMOS transistor is connected to the drain of the second LNMOS transistor; the source of the second LNMOS transistor is connected to the source of the third LNMOS transistor; the drain of the third LNMOS transistor is connected to the drain of the fourth LNMOS transistor; the source of the fourth LNMOS transistor is connected to the source of the fifth LNMOS transistor; and the drain of the fifth LNMOS transistor is connected to the switching node SW. The gates of the sixth, fifth, fourth, third, second, and first LNMOS transistors are all connected to the gate of the lower power transistor; the source of the sixth LNMOS transistor is connected to the positive terminal of the second comparator, and the output of the second comparator is connected to the subsequent control logic circuit.

2. The low-power current detection circuit in a DC-DC converter as described in claim 1, characterized in that, The peak current detection circuit is composed of the first operational amplifier, the first NMOS transistor, the first resistor, the eighth HPMOS transistor, the eighth PMOS transistor, the seventh HNMOS transistor, the first HNMOS transistor, the second HNMOS transistor, the third HNMOS transistor, the fourth HNMOS transistor, the fifth HNMOS transistor, the sixth HNMOS transistor, and the first comparator.

3. The low-power current detection circuit in a DC-DC converter as described in claim 2, characterized in that, The valley current detection circuit is composed of the second operational amplifier, the second NMOS transistor, the second resistor, the fourth PMOS transistor, the fifth PMOS transistor, the third operational amplifier, the third NMOS transistor, the third resistor, the sixth NMOS transistor, the seventh NMOS transistor, the first LNMOS transistor, the second LNMOS transistor, the third LNMOS transistor, the fourth LNMOS transistor, the fifth LNMOS transistor, the sixth LNMOS transistor, and the second comparator.

4. The low-power current detection circuit in a DC-DC converter as described in claim 1, characterized in that, The first operational amplifier, the second operational amplifier, the third operational amplifier, the first comparator, and the second comparator are all implemented using a five-transistor operational amplifier structure.

5. The low-power current detection circuit in a DC-DC converter as described in claim 3, characterized in that, The peak current detection circuit enables modulation of the duty cycle in the inductor current mode PWM control; the valley current detection circuit enables limiting of the inductor current under overcurrent conditions and smooth transition of the inductor current during the switching between PWM and PFM modes.

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