An adjustable circuit structure applied to RS-485 driving stage current

Abstract

The application discloses a kind of adjustable circuit structures applied to RS-485 drive stage current, belong to integrated circuit I / O port field, including input terminal TE, NMOS tube N1~N2, PMOS tube P1~P2, capacitor C1~C2, inverter INV1~INV2, nor gate NOR1 and latching logic ware;The application realizes adjustable of drive stage port current, needs to be combined with detection circuit, when triggering detection, write to latching logic ware, after detection, latching logic ware state restores.Utilize capacitor adjustable, the time of latching logic ware write and restore state can be adjusted, so as to realize the adjustable of the opening and closing time of subsequent stage drive, obtain adjustable drive current;In addition, circuit structure is simple, wide application range, applicable to driver chip design.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit I / O port technology, and in particular to an adjustable circuit structure for RS-485 drive stage current. Background Technology

[0002] With the continuous development of industrial control technology and the widespread application of computer network technology, there is a need for a bus technology capable of long-distance digital communication. The RS-485 bus standard, established by the Electronic Industries Association in 1983, can meet the requirements of long-distance transmission. Furthermore, compared to other bus technologies, RS-485 uses balanced two-wire transmission, offering advantages such as strong noise immunity, high data transmission rate, and high data transmission reliability, while also supporting multi-node, long-distance communication. Due to the long transmission distance of RS-485, the potential difference between the transmitting and receiving ends ensures that the common-mode output voltage meets the range of -7V to +12V. This requires the drive circuit to meet the port withstand voltage while also obtaining a stable drive current within the -7V to +12V voltage range; excessive port current will damage the circuit.

[0003] A typical driver output port uses a high-voltage PMOS for pull-up and a high-voltage NMOS for pull-down. When the pull-up is enabled, the drive current continuously increases as the port voltage changes from VCC to -7V; the same applies to the pull-down, where the drive current continuously increases as the port voltage changes from 0 to 12V. This process can lead to excessive drive stage current, exceeding the application's allowable range. A common design uses two parallel drives; when the current exceeds a certain range, one drive is shut down to reduce the drive stage current. There are also designs that detect voltage; for example, with the pull-up channel, when the port voltage drops below 0V, the detection circuit outputs digital logic to shut down one drive. However, these methods have significant drawbacks. Due to process variations, the drive current after shutting down one drive often fails to meet the circuit design requirements, and there are also discrepancies between different circuits. Summary of the Invention

[0004] The purpose of this invention is to provide an adjustable circuit structure for RS-485 drive stage current, so as to solve the problem that the port current of the existing drive circuit is too large due to process deviation.

[0005] To solve the above technical problems, the present invention provides an adjustable circuit structure for RS-485 drive stage current, including input terminal TE, NMOS transistors N1 to N2, PMOS transistors P1 to P2, capacitors C1 to C2, inverters INV1 to INV2, NOR gate NOR1 and latch logic.

[0006] The first input of the NOR gate NOR1 is connected to the input TE, the second input is connected to the output of the latch logic, and the output is connected to the gate of NMOS transistor N1. The drain of NMOS transistor N1 is simultaneously connected to the first terminal of capacitor C1, the drain of PMOS transistor P1, and the input of inverter INV1. The second terminal of capacitor C1 is connected to the power supply VCC, and the gate of PMOS transistor P1 is connected to node A3. The output of inverter INV1 is connected to the first input of the latch logic.

[0007] The first terminal of capacitor C2 is connected to VCC, and the second terminal is connected to the drain of NMOS transistor N2, the drain of PMOS transistor P2, and the input of inverter INV2. The gate terminal of NMOS transistor N2 is connected to the power supply VCC, and the gate terminal of PMOS transistor P2 is connected to the output of the latch logic. The output of inverter INV2 is connected to the second input of the latch logic.

[0008] The output of the latch logic unit is connected to the subsequent driver in the back end.

[0009] In one embodiment, the latch logic includes NOR2, NOR3 and an inverter INV3;

[0010] The first input of NOR2 is connected to the output of INV1, and the second input is connected to the output of NOR3. The output of NOR2 is connected to node A3, and node A3 is connected to the first input of NOR3. The second input of NOR3 is connected to the output of INV2. The input of INV3 is connected to node A3, and the output is connected to the subsequent driver.

[0011] In one embodiment, the source terminals of the NMOS transistors N1 to N2 are connected to the substrate and to GND; the source terminals of the PMOS transistors P1 to P2 are connected to the substrate and to VCC.

[0012] In one embodiment, the capacitors C1 and C2 have adjustable characteristics.

[0013] This invention provides an adjustable circuit structure for RS-485 driver stage current, enabling adjustable ratio of driver on / off control signal timing, thereby achieving adjustable drive current. Furthermore, this circuit design is simple to implement. This invention uses the output signal TE of an external detection circuit to control the state flipping of the latch logic unit, thereby controlling the on / off time of the subsequent driver stage, achieving adjustable driver drive current, and effectively preventing circuit burnout and bus signal interference due to overcurrent. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of an adjustable circuit structure for RS-485 driver stage current.

[0015] Figure 2 A circuit diagram of a latch logic unit;

[0016] Figure 3 This is a timing diagram of an adjustable circuit structure for RS-485 driver stage current. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of an adjustable circuit structure for RS-485 driver stage current proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0018] This invention provides an adjustable circuit structure for RS-485 driver stage current, such as... Figure 1 As shown, it includes input terminal TE, NMOS transistors N1 to N2, PMOS transistors P1 to P2, capacitors C1 to C2, inverters INV1 to INV2, NOR gate NOR1, and latch logic.

[0019] One input of NOR gate NOR1 is connected to input terminal TE, and the other input is connected to output A5 of latch logic. Output A5 of latch logic is connected to the subsequent driver stage. The output of NOR gate NOR1 is connected to the gate of NMOS transistor N1. The drain of NMOS transistor N1 is connected to one end of capacitor C1, the drain of PMOS transistor P1, and the input of inverter INV1. The other end of capacitor C1 is connected to power supply VCC, and the gate of PMOS transistor P1 is connected to A3. The output of inverter INV1 is connected to one input A1 of latch logic. One end of capacitor C2 is connected to VCC, and the other end is connected to the drain of NMOS transistor N2, which is also connected to the drain of PMOS transistor P2 and the input of inverter INV2. The gate of NMOS transistor N2 is connected to power supply VCC, and the gate of PMOS transistor P2 is connected to output A5 of latch logic. The output of inverter INV2 is connected to the other input A2 of the latch logic; the source terminals of NMOS transistors N1 to N2 are connected to the substrate and then to GND; the source terminals of PMOS transistors P1 to P2 are connected to the substrate and then to VCC.

[0020] Structure reference of latch logic Figure 2 However, it is not limited to Figure 2 The latch logic unit consists of NOR gates NOR2 and NOR3, and an inverter INV3. Its inputs are A1 and A2, and its output is A5. One input of NOR gate NOR2 is A1, and its other input is connected to the output A4 of NOR gate NOR3. The output A3 of NOR gate NOR2 is connected to one input of NOR gate NOR3, and the other input of NOR gate NOR3 is connected to A2. The input of inverter INV3 is connected to A3, and its output is A5.

[0021] The working principle of this invention is as follows:

[0022] 1. When the driver detects overcurrent, the detection circuit outputs a control signal TE. TE is H (high level) when no detection occurs and L (low level) when detection occurs. Figure 3 Point 1 is the trigger detection, and the TE signal is L. Since the output A5 of the latch logic is L at this time, the NOR1 gate outputs H, and the NMOS transistor N1 discharges the capacitor C1. After time T1, the inverter INV1 flips, and the input A1 of the latch logic changes from L to H. The latch logic is written with a value, A3 changes from H to L, and A4 / A5 changes from L to H. At this time, the output A5 of the latch logic is H, making the output of the NOR1 gate fixed at L.

[0023] 2. Within T2 after the trigger detection, since the output A5 of the latch logic is H, the NMOS transistor N2 discharges the capacitor C2. After T2, the inverter INV2 flips, the output of A2 is H, the latch logic is rewritten, and A3 changes from L to H.

[0024] 3. T1 + T2 constitutes one detection cycle. Figure 3 After midpoint 3, the loop is checked again. It can be observed that during time T1, the output signal A5 of the latch logic controls the subsequent driver to turn on, and during time T2, the output signal A5 of the latch logic controls the subsequent driver to turn off. By adjusting the ratio of T1 and T2, different average driver currents can be obtained.

[0025] This invention achieves adjustable current at the driver stage port by incorporating a detection circuit. During trigger detection, a latch logic unit is written to; after detection, the latch logic unit's state is restored. By utilizing adjustable capacitors, the writing and restoring times of the latch logic unit are adjustable, thereby enabling adjustable on / off times of the subsequent driver stage and obtaining an adjustable drive current. Furthermore, the circuit structure is simple, has a wide range of applications, and is suitable for driver chip design.

[0026] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An adjustable circuit structure for RS-485 driver stage current, characterized in that, This includes the input terminal TE, NMOS transistors N1~N2, PMOS transistors P1~P2, capacitors C1~C2, inverters INV1~INV2, NOR gate NOR1, and latch logic; The first input of the NOR gate NOR1 is connected to the input TE, the second input is connected to the output of the latch logic, and the output is connected to the gate of NMOS transistor N1. The drain of NMOS transistor N1 is simultaneously connected to the first terminal of capacitor C1, the drain of PMOS transistor P1, and the input of inverter INV1. The second terminal of capacitor C1 is connected to the power supply VCC, and the gate of PMOS transistor P1 is connected to node A3. The output of inverter INV1 is connected to the first input of the latch logic. The first terminal of capacitor C2 is connected to VCC, and the second terminal is connected to the drain of NMOS transistor N2, the drain of PMOS transistor P2, and the input of inverter INV2. The gate terminal of NMOS transistor N2 is connected to the power supply VCC, and the gate terminal of PMOS transistor P2 is connected to the output of the latch logic. The output of inverter INV2 is connected to the second input of the latch logic. The output of the latch logic unit is connected to the subsequent driver at the back end; The latch logic unit includes NOR2 and NOR3 NOR gates and INV3 inverter; The first input of NOR2 is connected to the output of INV1, and the second input is connected to the output of NOR3. The output of NOR2 is connected to node A3, and node A3 is connected to the first input of NOR3. The second input of NOR3 is connected to the output of INV2. The input of INV3 is connected to node A3, and the output is connected to the subsequent driver.

2. The adjustable circuit structure for RS-485 driver stage current as described in claim 1, characterized in that, The source terminals of the NMOS transistors N1~N2 are connected to the substrate and then to GND; the source terminals of the PMOS transistors P1~P2 are connected to the substrate and then to VCC.

3. The adjustable circuit structure for RS-485 driver stage current as described in claim 1, characterized in that, The capacitors C1 and C2 are adjustable.

Images