Charge pump circuit and driving device

Abstract

Embodiments provide a charge pump circuit and a driving device that efficiently step up voltage. The charge pump circuit of the embodiments includes a first capacitor having a first terminal to which a first voltage is supplied; a second capacitor having a first terminal to which a first pulse signal is supplied and a second terminal connected to a first node; a third capacitor having a first terminal to which the first pulse signal is supplied; a first transistor having a first terminal connected to a second terminal of the first capacitor and a second terminal connected to the first node; a second transistor having a first terminal connected to a first terminal of the first capacitor and a second terminal connected to the first node; and a first circuit having a first input terminal connected to the first node, a second input terminal connected to a second terminal of the third capacitor, a first output terminal connected to a gate of the first transistor, and a second output terminal connected to a gate of the second transistor.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-147957 (filed on September 16, 2022). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0002] Embodiments of the present invention relate to charge pump circuits and driving devices. Background Technology

[0003] A drive device for driving motors and the like with high currents is known, and a charge pump circuit for generating a voltage higher than the power supply voltage in the drive device is known. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a charge pump circuit and driving device for high-efficiency voltage boosting.

[0005] The charge pump circuit of this embodiment includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, and a first circuit. The first capacitor has a first terminal supplied with a first voltage. The second capacitor has a first terminal supplied with a first pulse signal and a second terminal connected to a first node. The third capacitor has a first terminal supplied with the first pulse signal. The first transistor has a first terminal connected to the second terminal of the first capacitor and a second terminal connected to the first node. The second transistor has a first terminal connected to the first terminal of the first capacitor and a second terminal connected to the first node. The first circuit has a first input terminal connected to the first node, a second input terminal connected to the second terminal of the third capacitor, a first output terminal connected to the gate of the first transistor, and a second output terminal connected to the gate of the second transistor. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example of the structure of a motor drive system including the drive device involved in the embodiment.

[0007] Figure 2 This is a circuit diagram illustrating an example of the structure of the charge pump circuit of the driving device according to the embodiment.

[0008] Figure 3 This is a waveform diagram illustrating an example of the boost operation in the charge pump circuit of the drive device according to the embodiment.

[0009] Figure 4 This is a waveform diagram illustrating an example of the boost operation when the clock signal rises in the charge pump circuit of the drive device according to the embodiment.

[0010] Figure 5 This is a diagram illustrating an example of the boost operation when the clock signal rises in the charge pump circuit of the drive device according to the embodiment.

[0011] Figure 6 This is a waveform diagram illustrating an example of the boost operation when the clock signal in the charge pump circuit of the drive device according to the embodiment decreases.

[0012] Figure 7 This is a diagram illustrating an example of the boost operation when the clock signal in the charge pump circuit of the drive device according to the embodiment decreases.

[0013] Figure 8 This is a circuit diagram illustrating an example of the configuration of the charge pump circuit of the drive device involved in the modified example.

[0014] Label Explanation

[0015] 1. Motor drive system; 2. Control unit; 3. Drive device; 4. Motor; 10. Charge pump circuit; E1, E1', E2 power supplies; CK clock generator; IV1, IV2, IV3, IV4, IV5, IV6, IV7, IV8, IV9, IV10, IV11, IV12 inverters; C1, C2, C3, C4, C5 capacitors; NOR1, NOR2 NOR circuits; NAND1, NAND2 NAND circuits; Tr1, Tr2, Tr3, Tr4 transistors; P output terminal. Detailed Implementation

[0016] The embodiments will now be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having substantially the same function and structure will be labeled with the same reference numeral. Sometimes, when elements having the same structure are specifically distinguished from each other, different letters or numbers will be appended to the end of the same reference numeral.

[0017] 1. Structure

[0018] 1.1 Drive unit

[0019] Figure 1 This is a block diagram illustrating an example of the structure of a motor drive system including the drive device according to the embodiment. The motor drive system 1 includes a control unit 2, a drive device 3, and a motor 4. The motor drive system 1 is an application that uses torque obtained from the motor 4 to perform a predetermined action.

[0020] The control unit 2 controls the entire motor drive system 1. The control unit 2 includes, for example, a processor and a memory. The processor of the control unit 2 generates control signals based on a program pre-stored in the memory, and controls the drive device 3.

[0021] The drive unit 3 is, for example, an IC (Integrated Circuit) chip that functions as a motor controller driver (MCD). The drive unit 3 drives the motor 4 according to control signals from the control unit 2. Specifically, the drive unit 3 incorporates a charge pump circuit 10. The charge pump circuit 10 is a voltage generation circuit that generates the voltage used in driving the motor 4. The charge pump circuit 10 is also called a boost circuit. The drive unit 3 uses the voltage generated in the charge pump circuit 10 to drive the motor 4.

[0022] 1.2 Charge Pump Circuit

[0023] Next, the structure of the charge pump circuit of the driving device according to the embodiment will be described. Figure 2 This is a circuit diagram illustrating an example of the structure of the charge pump circuit of the driving device according to the embodiment.

[0024] The charge pump circuit 10 is a synchronous rectification type circuit. The charge pump circuit 10 includes multiple power supplies E, a clock generator CK, multiple inverters IV, multiple capacitors C, multiple NOR circuits, multiple NAND circuits, multiple transistors Tr, and an output terminal P. The multiple power supplies E include power supplies E1 and E2.

[0025] Multiple inverters IV include inverters IV1, IV2, IV3, IV4, IV5, IV6, IV7, IV8, IV9, IV10, IV11, and IV12. Multiple capacitors C include capacitors C1, C2, C3, C4, and C5. Multiple NOR circuits NOR1 and NOR2. Multiple NAND circuits NAND1 and NAND2. Multiple transistors Tr include transistors Tr1, Tr2, Tr3, and Tr4. Transistors Tr1 and Tr3 are P-type MOS transistors (Metal-Oxide-Semiconductor Transistors). Transistors Tr2 and Tr4 are N-type MOS transistors.

[0026] Power supply E1 is a logic power supply. Power supply E1 outputs voltage VDD relative to ground GND. Voltage VDD drives multiple inverters IV, multiple NOR circuits, and multiple NAND circuits.

[0027] The clock generator CK generates a clock signal CLK. The clock signal CLK is, for example, a pulse signal. Based on the period of the clock signal CLK, the charge pump circuit 10 performs a boost operation to increase the voltage output at the output terminal P. Specifically, the voltage output at the output terminal P is boosted according to the rise and fall of the clock signal CLK. Details regarding the boost operation will be described later.

[0028] The first voltage input terminal of each inverter IV1, IV2, IV3, IV4, IV5, IV6, and IV7 is grounded to ground GND. A voltage VDD is supplied to the second voltage input terminal of each inverter IV1, IV2, IV3, IV4, IV5, IV6, and IV7. Thus, each inverter IV1, IV2, IV3, IV4, IV5, IV6, and IV7 is configured to output voltage VDD as the "H" level and output a voltage to ground GND (e.g., 0V) as the "L" level.

[0029] Input the clock signal CLK to the input terminal of inverter IV1. Connect the output terminal of inverter IV1 to the input terminals of inverters IV2 and IV3 respectively. Connect the output terminal of inverter IV2 to terminal 1 of capacitor C1. Connect the output terminal of inverter IV3 to terminal 1 of capacitor C3.

[0030] Input the clock signal CLK to the input terminal of inverter IV4. Connect the output terminal of inverter IV4 to the input terminal of inverter IV5. Connect the output terminal of inverter IV5 to the input terminals of inverters IV6 and IV7 respectively. Connect the output terminal of inverter IV6 to terminal 1 of capacitor C2. Connect the output terminal of inverter IV7 to terminal 1 of capacitor C4.

[0031] Terminal 2 of capacitor C1 is connected to node N1. Terminal 2 of capacitor C2 is connected to node N2. Terminal 2 of capacitor C3 is connected to node N3. Terminal 2 of capacitor C4 is connected to node N4.

[0032] Power supply E2 is the motor power supply. Power supply E2 outputs voltage VM relative to ground GND. Voltage VM is used to boost the voltage supplied from output terminal P. Voltage VM is supplied to node N5.

[0033] The first voltage input terminals of inverters IV7, IV8, IV9, IV10, IV11, and IV12, NOR1 and NOR2, NAND1 and NAND2, and the first terminal of capacitor C5 are connected to node NOUT. The second voltage input terminals of inverters IV7, IV8, IV9, IV10, IV11, IV12, NOR1 and NOR2, NAND1 and NAND2, and the second terminal of capacitor C5 are connected to node N5. Thus, inverters IV7, IV8, IV9, IV10, IV11, and IV12, NOR1 and NOR2, and NAND1 and NAND2 are configured to output the voltage at node NOUT as the "H" level and the voltage VM at node N5 as the "L" level.

[0034] The signal input terminal of inverter IV7 is connected to node N1. The signal output terminal of inverter IV7 is connected to the signal input terminals of inverters IV8 and IV9 respectively. The signal output terminal of inverter IV8 is connected to node N3.

[0035] The first input terminals of both the NOR1 and NAND1 circuits are connected to node N3. The second input terminals of both the NOR1 and NAND1 circuits are connected to the signal output terminal of inverter IV9. That is, the NOR1 circuit outputs an "L" level signal, except when both the voltage at node N3 and the voltage at the signal output terminal of inverter IV9 are at the "L" level. The NOR1 circuit outputs an "H" level signal when both the voltage at node N3 and the voltage at the signal output terminal of inverter IV9 are at the "L" level.

[0036] The source of transistor Tr1 is connected to node NOUT. The drain of transistor Tr1 is connected to node N1. The gate of transistor Tr1 is connected to the signal output terminal of NAND circuit NAND1 via node GIN1.

[0037] The source of transistor Tr2 is connected to node N5. The drain of transistor Tr2 is connected to node N1. The gate of transistor Tr2 is connected to the signal output terminal of NOR1 via node GIN2.

[0038] Thus, inverters IV7, IV8, and IV9, NOR circuit NOR1, and NAND circuit NAND1 have the function of controlling the voltage supplied to the gates of transistors Tr1 and Tr2 respectively. Inverters IV7, IV8, and IV9, NOR circuit NOR1, and NAND circuit NAND1 are also referred to as the gate control circuit GCa. The gate control circuit GCa is configured to generate a time period in which transistors Tr1 and Tr2 are simultaneously in the off state, and on the other hand, to prevent a time period in which transistors Tr1 and Tr2 are simultaneously in the on state.

[0039] The signal input terminal of inverter IV10 is connected to node N2. The signal output terminal of inverter IV10 is connected to the signal input terminals of inverters IV11 and IV12 respectively. The signal output terminal of inverter IV11 is connected to node N4.

[0040] The first input of each of the NOR and NAND circuits is connected to node N4. The second input of each of the NOR and NAND circuits is connected to the signal output of inverter IV12.

[0041] The source of transistor Tr3 is connected to node NOUT. The drain of transistor Tr3 is connected to node N2. The gate of transistor Tr3 is connected to the signal output terminal of NAND circuit NAND2 via node GIN3.

[0042] The source of transistor Tr4 is connected to node N5. The drain of transistor Tr4 is connected to node N2. The gate of transistor Tr4 is connected to the signal output terminal of NOR2 via node GIN4.

[0043] The output terminal P is connected to node NOUT. The output terminal P outputs the voltage boosted by the boosting action of the charge pump circuit 10 in the drive device 3 to the external output.

[0044] In the above structure, the group of transistors Tr1 and Tr2, and the group of transistors Tr3 and Tr4, function as rectifier elements. Capacitors C1 and C2 function as draw capacitors. Capacitors C3 and C4 function as level shifting capacitors configured in parallel with capacitors C1 and C2, respectively. Power supply E1, clock generator CK, and inverters IV1, IV2, IV3, IV4, IV5, IV6, and IV7 function as the drive circuit for the draw capacitors.

[0045] Furthermore, inverters IV10, IV11, and IV12, NOR circuit NOR2, and NAND circuit NAND2 have the function of controlling the voltage supplied to the gates of transistors Tr3 and Tr4 respectively. Inverters IV10, IV11, and IV12, NOR circuit NOR2, and NAND circuit NAND2 are also referred to as the gate control circuit GCb. The gate control circuit GCb is configured to generate a time period in which transistors Tr3 and Tr4 are simultaneously in the off state, and on the other hand, to prevent a time period in which transistors Tr3 and Tr4 are simultaneously in the on state.

[0046] 2. Actions

[0047] 2.1 Overview of the boost operation

[0048] First, a brief overview of the boosting operation will be provided.

[0049] Figure 3 This is a waveform diagram illustrating an example of the boost operation in the charge pump circuit of the drive device according to the embodiment. Figure 3 The diagram shows the time-varying voltages of clock signal CLK, nodes NOUT, GIN1, GIN2, GIN3, and GIN4.

[0050] like Figure 3 As shown, the clock signal CLK periodically varies between the "H" and "L" levels with a period of D. Furthermore, the voltage at node NOUT gradually increases from voltage VM, approaching voltage VOUT, according to the rise and fall of the clock signal CLK.

[0051] The voltage VOUT can be obtained, for example, by subtracting the sum of the drain-source voltages of transistors Tr1 and Tr2, or the sum of the drain-source voltages of transistors Tr3 and Tr4, from the sum of the voltages VM and VDD. That is, when the sum of the drain-source voltages of transistors Tr1 and Tr2, and the sum of the drain-source voltages of transistors Tr3 and Tr4, is approximately equal to the voltage 2Vds, the voltage VOUT can be the voltage (VDD + VM - 2Vds).

[0052] The voltages of node GIN1 and node GIN2 are respectively determined by the rise of the clock signal CLK (e.g., Figure 3 At time T10, the voltage level transitions from "H" to "L". The voltages of nodes GIN1 and GIN2 change according to the decrease in the clock signal CLK (e.g., ...). Figure 3At time T20, the clock signal CLK transitions from the "L" level to the "H" level. Furthermore, during the period when the clock signal CLK is at the "H" level, the voltages of nodes GIN1 and GIN2 gradually increase from voltage VM, approaching voltage VOUT, with each repetition of the clock signal CLK cycle.

[0053] On the other hand, the voltages of nodes GIN3 and GIN4 each increase according to the rise of the clock signal CLK (e.g., Figure 3 At time T10, the voltage level transitions from "L" to "H". The voltages of nodes GIN3 and GIN4 change according to the decrease in the clock signal CLK (e.g., ...). Figure 3 At time T20, the clock signal CLK transitions from "H" level to "L" level. Furthermore, during the period when the clock signal CLK is at "H" level, the voltages of nodes GIN3 and GIN4 gradually increase from voltage VM, approaching voltage VOUT, with each repetition of the clock signal CLK cycle.

[0054] 2.2 Details of the boost operation during the rise of the clock signal

[0055] Next, the details of the boost operation during the rise of the clock signal will be explained.

[0056] Figure 4 This is a waveform diagram illustrating an example of the boost operation when the clock signal rises in the charge pump circuit of the drive device according to the embodiment. Figure 5 This is a diagram illustrating an example of the boost operation when the clock signal rises in the charge pump circuit of the drive device according to the embodiment. Figure 4 and Figure 5 and Figure 3 The time T10 and its vicinity correspond to it.

[0057] Up to time T10, the clock signal CLK is at the "L" level.

[0058] Simultaneously, the first terminals of capacitors C1 and C3 are grounded to ground GND. At this time, the voltages at nodes N1 and N3 are both at the "L" level. Therefore, the signal level output from the NAND circuit NAND1 to node GIN1 and the signal level output from the NOR circuit NOR1 to node GIN2 are both at the "H" level. Therefore, transistor Tr1 is in the off state, and transistor Tr2 is in the on state. Furthermore, through node N1 and connected to node N5 via transistor Tr2, voltage VM is supplied to the second terminal of capacitor C1.

[0059] Additionally, a voltage VDD is supplied to the first terminal of each of capacitors C2 and C4. At this time, the voltages at nodes N2 and N4 are both at the "H" level. Therefore, the signal level output from the NAND circuit NAND2 to node GIN3 and the signal level output from the NOR circuit NOR2 to node GIN4 are both at the "L" level. Therefore, transistor Tr3 is in the on state, and transistor Tr4 is in the off state. Furthermore, capacitor C5 is charged by capacitor C2 through node N2 connected to node NOUT via transistor Tr3.

[0060] At time T10, the clock signal CLK rises from the "L" level to the "H" level.

[0061] Simultaneously, a voltage VDD is supplied to the first terminal of each of capacitors C1 and C3. As a result, the voltage at node N3 changes from a "L" level to a "H" level. On the other hand, node N1 is connected to node N5, so its voltage change occurs later than at node N3. Therefore, the voltage at node N1 is maintained at a "L" level. Consequently, the signal level output from the NAND circuit NAND1 to node GIN1 is maintained at a "H" level. The signal level output from the NOR circuit NOR1 to node GIN2 changes from a "H" level to a "L" level. Therefore, transistors Tr1 and Tr2 both become off.

[0062] Additionally, the second terminals of capacitors C2 and C4 are each grounded to ground GND. Consequently, the voltage at node N4 changes from "H" level to "L" level. On the other hand, since node N2 is connected to node NOUT, its voltage change occurs later than that of node N4. Therefore, the voltage at node N2 is maintained at "H" level. Consequently, the signal level from the NAND circuit NAND2 output to node GIN3 changes from "L" level to "H" level. The signal level from the NOR circuit NOR2 output to node GIN4 is maintained at "L" level. Therefore, transistors Tr3 and Tr4 are both in the off state.

[0063] At time T11, the voltage of node N1 rises to the "H" level, and the voltage of node N2 drops to the "L" level.

[0064] Simultaneously, the signal level output from the NAND circuit NAND1 to node GIN1 changes from "H" level to "L" level. The signal level output from the NOR circuit NOR1 to node GIN2 remains at "L" level. Therefore, while transistor Tr2 remains in the off state, transistor Tr1 becomes the on state. Furthermore, node N1 is connected to node NOUT via transistor Tr1, and charging of capacitor C5 begins through capacitor C1.

[0065] Furthermore, the signal level output from the NAND circuit NAND2 to node GIN3 remains at "H" level. The signal level output from the NOR circuit NOR2 to node GIN4 changes from "L" level to "H" level. Therefore, while transistor Tr3 remains in the off state, transistor Tr4 becomes the on state. And, through node N2 and connected to node N5 via transistor Tr4, voltage VM is supplied to the second terminal of capacitor C2.

[0066] By performing the operation as described above, when the clock signal CLK rises, the state changes from "transistor Tr1 is off and transistor Tr2 is on" through "both transistors Tr1 and Tr2 are off" to "transistor Tr1 is on and transistor Tr2 is off". Similarly, when the clock signal CLK rises, the state changes from "transistor Tr3 is on and transistor Tr4 is off" through "both transistors Tr3 and Tr4 are off" to "transistor Tr3 is off and transistor Tr4 is on".

[0067] 2.3 Details of the boost operation during clock signal decline

[0068] Next, the details of the boost operation during the clock signal decline will be explained.

[0069] Figure 6 This is a waveform diagram illustrating an example of the boost operation when the clock signal in the charge pump circuit of the drive device according to the embodiment decreases. Figure 7 This is a diagram illustrating an example of the boost operation when the clock signal in the charge pump circuit of the drive device according to the embodiment decreases. Figure 6 and Figure 7 and Figure 3 The time T20 and its vicinity correspond to this.

[0070] By time T20, the clock signal CLK is at the "H" level.

[0071] Simultaneously, a voltage VDD is supplied to the first terminal of each of capacitors C1 and C3. At this time, the voltages at nodes N1 and N3 are both at the "H" level. Therefore, the signal level output from the NAND circuit NAND1 to node GIN1 and the signal level output from the NOR circuit NOR1 to node GIN2 are both at the "L" level. Therefore, transistor Tr1 is in the on state, and transistor Tr2 is in the off state. Furthermore, capacitor C5 is charged by capacitor C1 through node N1 connected to node NOUT via transistor Tr1.

[0072] Additionally, the first terminals of capacitors C2 and C4 are grounded to ground GND. At this time, the voltages at nodes N2 and N4 are both at the "L" level. Therefore, the signal level output from the NAND circuit NAND2 to node GIN3 and the signal level output from the NOR circuit NOR2 to node GIN4 are both at the "H" level. Therefore, transistor Tr3 is in the off state and transistor Tr4 is in the on state. Furthermore, a voltage VM is supplied to the second terminal of capacitor C2 through node N2 connected to node N5 via transistor Tr4.

[0073] At time T20, the clock signal CLK drops from the "H" level to the "L" level.

[0074] Simultaneously, the second terminals of capacitors C1 and C3 are grounded to ground GND. The voltage at node N3 changes from "H" level to "L" level. On the other hand, node N1 is connected to node NOUT, therefore, its voltage change occurs later than that of node N3. Consequently, the voltage at node N1 is maintained at "H" level. Therefore, the signal level from the NAND circuit NAND1 output to node GIN1 changes from "L" level to "H" level. The signal level from the NOR circuit NOR1 output to node GIN3 is maintained at "L" level. Therefore, transistors Tr1 and Tr2 are both in the off state.

[0075] Additionally, voltage VDD is supplied to the first terminals of capacitors C2 and C4. This causes the voltage at node N4 to change from "L" level to "H" level. On the other hand, since nodes N2 and N5 are connected, their voltage change occurs later than that of node N4. Therefore, the voltage at node N2 is maintained at "L" level. Consequently, the signal level output from the NAND circuit NAND2 to node GIN3 is maintained at "H" level. The signal level output from the NOR circuit NOR2 to node GIN4 changes from "H" level to "L" level. Therefore, transistors Tr3 and Tr4 both become off.

[0076] At time T21, the voltage of node N1 drops to the "L" level, and the voltage of node N2 rises to the "H" level.

[0077] Correspondingly, the signal level output from the NAND circuit NAND1 to node GIN1 is maintained at "H" level. The signal level output from the NOR circuit NOR1 to node GIN2 changes from "L" level to "H" level. Therefore, while transistor Tr1 remains in the off state, transistor Tr2 becomes in the on state. Furthermore, through node N1 and connected to node N5 via transistor Tr2, voltage VM is supplied to the second terminal of capacitor C1.

[0078] Furthermore, the signal level output from the NAND circuit NAND2 to node GIN3 changes from "H" level to "L" level. The signal level output from the NOR circuit NOR2 to node GIN4 is maintained at "L" level. Therefore, while transistor Tr4 remains in the off state, transistor Tr3 becomes the on state. And, node N2 is connected to node NOUT via transistor Tr3, and charging of capacitor C5 begins through capacitor C2.

[0079] Through the actions described above, when the clock signal CLK decreases, the state changes from "transistor Tr1 is on and transistor Tr2 is off" to "transistor Tr1 and Tr2 are both off" and then to "transistor Tr1 is off and transistor Tr2 is on". Similarly, when the clock signal CLK decreases, the state changes from "transistor Tr3 is off and transistor Tr4 is on" to "transistor Tr3 is on and transistor Tr4 is off" and then to "transistor Tr3 is on and transistor Tr4 is off".

[0080] 3. Effects of the implementation method

[0081] According to the implementation, for the gate control circuit GCa, the voltage of input node N1 serves as the output state signal for "transistors Tr1 and Tr2 as rectifier elements," and the voltage of input node N3 serves as the input signal from the drive circuit of the draw capacitor. Therefore, the gate control circuit GCa can determine the state of "both transistors Tr1 and Tr2 are in the off state," the state of "one of transistors Tr1 and Tr2 is in the on state and the other is in the off state," and the state of "both transistors Tr1 and Tr2 are in the on state" based on these two signals. Thus, the gate control circuit GCa can transition from the state of "transistor Tr1 is in the on state and transistor Tr2 is in the off state" through the state of "both transistors Tr1 and Tr2 are in the off state" to the state of "transistor Tr1 is in the off state and transistor Tr2 is in the on state." The gate control circuit GCa can also transition from the state of "transistor Tr1 is in the off state and transistor Tr2 is in the on state" through the state of "both transistors Tr1 and Tr2 are in the off state" to the state of "transistor Tr1 is in the on state and transistor Tr2 is in the off state." Therefore, it is possible to suppress the current generated when both transistors Tr1 and Tr2 are in the on state, and to suppress the voltage loss VOUT output from the output terminal P that accompanies the current.

[0082] Furthermore, for the gate control circuit GCb, the voltage at input node N2 serves as the output state signal for transistors Tr3 and Tr4, which act as rectifier elements, and the voltage at input node N4 serves as the input signal from the drive circuit of the draw capacitor. Therefore, the gate control circuit GCb can determine the states of "both transistors Tr3 and Tr4 are in the off state," "one of transistors Tr3 and Tr4 is in the on state and the other is in the off state," and "both transistors Tr3 and Tr4 are in the on state" based on these two signals. Thus, the gate control circuit GCb can transition from the state of "transistor Tr3 is in the on state and transistor Tr4 is in the off state" through the state of "both transistors Tr3 and Tr4 are in the off state" to the state of "transistor Tr3 is in the off state and transistor Tr4 is in the on state." The gate control circuit GCb can also transition from the state of "transistor Tr3 is in the off state and transistor Tr4 is in the on state" through the state of "both transistors Tr3 and Tr4 are in the off state" to the state of "transistor Tr3 is in the on state and transistor Tr4 is in the off state." Therefore, it is possible to suppress the current generated when both transistors Tr3 and Tr4 are in the on state, and to suppress the voltage loss VOUT output from the output terminal P that accompanies the current.

[0083] Specifically, the gate control circuit GCa includes a NAND circuit NAND1 with an output terminal connected to the gate of transistor Tr1, and a NOR circuit NOR1 with an output terminal connected to the gate of transistor Tr2. The gate control circuit GCb includes a NAND circuit NAND2 with an output terminal connected to the gate of transistor Tr3, and a NOR circuit NOR2 with an output terminal connected to the gate of transistor Tr4. Thus, a structure that satisfies the functions of the gate control circuits GCa and GCb can be configured while minimizing the number of MOS transistors used. Therefore, the mounting area of ​​the charge pump circuit 10 can be reduced. Therefore, the charge pump circuit 10 can be integrated into the drive device 3.

[0084] 4. Variations

[0085] In the above embodiment, the structure of the charge pump circuit 10 having both a logic power supply and a motor power supply has been described, but it is not limited to this. The charge pump circuit 10 may also have a structure having only one power supply, which can be used as both a logic power supply and a motor power supply. Hereinafter, we will mainly describe the structures and operations that differ from the embodiment. Descriptions of structures and operations that are the same as those in the embodiment will be omitted as appropriate.

[0086] Figure 8 This is a circuit diagram illustrating an example of the structure of the charge pump circuit of the driving device involved in the modified example. For example... Figure 8 As shown, the charge pump circuit 10 may also include a power supply E1'.

[0087] Power supply E1' is a power supply that can be used as both a logic power supply and a motor power supply. Power supply E1' outputs voltage VDD relative to ground GND. Through power supply E1', the voltage VDD is supplied to the second voltage input terminals of inverters IV1, IV2, IV3, IV4, IV5, IV6, and IV7 respectively. In addition, power supply E1' supplies voltage VDD to the first terminal of capacitor C5 via node N5.

[0088] With the structure described above, the voltage VOUT output from the output terminal P along with the through current can also be suppressed in the same way as in the implementation method.

[0089] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and likewise within the scope of the invention as described in the claims and its equivalents.

Claims

1. A charge pump circuit, comprising: The first capacitor has a first terminal that is supplied with a first voltage; The second capacitor has a first terminal that is supplied with the first pulse signal and a second terminal that is connected to the first node; The third capacitor has a first terminal to which the first pulse signal is supplied; The first transistor has a first terminal connected to the second terminal of the first capacitor and a second terminal connected to the first node; A second transistor having a first terminal connected to a first terminal of the first capacitor and a second terminal connected to the first node; and The first circuit has a first input terminal connected to the first node, a second input terminal connected to the second terminal of the third capacitor, a first output terminal connected to the gate of the first transistor, and a second output terminal connected to the gate of the second transistor.

2. The charge pump circuit according to claim 1, The first circuit includes a first NAND circuit and a first NOR circuit. The first NAND circuit has: The first input terminal is connected to the first node; The second input terminal is connected to the second terminal of the third capacitor; and The output terminal is connected to the gate of the first transistor. The first NOR circuit has: The first input terminal is connected to the first node; The second input terminal is connected to the second terminal of the third capacitor; and The output terminal is connected to the gate of the second transistor.

3. The charge pump circuit according to claim 1, The first transistor is a P-type MOS transistor, and the second transistor is an N-type MOS transistor.

4. The charge pump circuit according to claim 3, The first terminal of each of the first transistor and the second transistor is the source. The second terminal of each of the first transistor and the second transistor is a drain.

5. The charge pump circuit according to claim 1, further comprising: The fourth capacitor has a first terminal that is supplied with a second pulse signal to invert the first pulse signal and a second terminal that is connected to the second node. The fifth capacitor has a first terminal to which the second pulse signal is supplied; The third transistor has a first terminal connected to the second terminal of the first capacitor and a second terminal connected to the second node; A fourth transistor having a first terminal connected to a first terminal of the first capacitor and a second terminal connected to the second node; and The second circuit has a first input terminal connected to the second node, a second input terminal connected to the second terminal of the fifth capacitor, a first output terminal connected to the gate of the third transistor, and a second output terminal connected to the gate of the fourth transistor.

6. The charge pump circuit according to claim 5, The first circuit includes a first NAND circuit and a first NOR circuit. The first NAND circuit has: The first input terminal is connected to the first node; The second input terminal is connected to the second terminal of the third capacitor; and The output terminal is connected to the gate of the first transistor. The first NOR circuit has: The first input terminal is connected to the first node; The second input terminal is connected to the second terminal of the third capacitor; and The output terminal is connected to the gate of the second transistor. The second circuit includes a second NAND circuit and a second NOR circuit. The second NAND circuit has: The first input terminal is connected to the second node; The second input terminal is connected to the second terminal of the fifth capacitor; and The output terminal is connected to the gate of the third transistor. The second NOR circuit has: The first input terminal is connected to the second node; The second input terminal is connected to the second terminal of the fifth capacitor; and The output terminal is connected to the gate of the fourth transistor.

7. The charge pump circuit according to claim 5, The first transistor and the third transistor are P-type MOS transistors. The second and fourth transistors are N-type MOS transistors.

8. The charge pump circuit according to claim 7, The first terminal of each of the first, second, third, and fourth transistors is a source. The second terminal of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a drain.

9. The charge pump circuit according to any one of claims 1 to 8, It also has a third output terminal connected to the second terminal of the first capacitor.

10. A driving device, Including the charge pump circuit of claim 9, It is configured to drive an external motor based on the voltage of the third output terminal.

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