Resistive random access memory and method of manufacturing the same

Abstract

This invention provides a resistive random access memory (RRAM) and its manufacturing method, which can effectively control the position and shape of conductive paths, thereby improving reliability and performance uniformity. The RRAM includes multiple bottom contact structures formed in a substrate, multiple memory cells formed on the substrate, and insulating structures formed between adjacent memory cells. Each memory cell includes a bottom electrode layer, two L-shaped resistive switching layers, multiple oxygen ion diffusion barrier layers, and a top electrode layer. The bottom electrode layer is formed on one of the bottom contact structures. The L-shaped resistive switching layer includes a horizontal portion and a vertical portion, and is formed on the bottom electrode layer. Oxygen ion diffusion barrier layers are formed on the inner and outer walls of the vertical portion of the L-shaped resistive switching layer. The L-shaped resistive switching layer is located between the top electrode layer and the bottom electrode layer.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a resistive random access memory and a method for manufacturing the same. Background Technology

[0002] In existing resistive random access memory (RRAM), an array region of a chip contains multiple memory cells, and each memory cell includes a patterned bottom electrode layer, a resistive switching layer, and a top electrode layer. When a formation voltage or a write voltage is applied to a memory cell, oxygen ions are driven away from the resistive switching layer. The equivalent positive valence oxygen vacancies remaining in the resistive switching layer form conductive pathways (or conductive filaments), thereby causing the resistive switching layer to transition from a high resistance state (HRS) to a low resistance state (LRS). When an erase voltage is applied, the oxygen ions return to the resistive switching layer and combine with the equivalent positive valence oxygen vacancies. Therefore, the conductive pathways disappear, and the resistive switching layer transitions from LRS to HRS.

[0003] When a write voltage is applied to convert the resistive transition layer to a low-resistance state (LRS), oxygen ions typically move to the oxygen ion storage layer above the resistive transition layer. However, in existing RRAMs, some oxygen ions may also move horizontally and remain in the resistive transition layer. If these oxygen ions remaining in the resistive transition layer gain energy from a high-temperature environment (e.g., the high-temperature environment of durability screening), they will recombine with oxygen vacancies in adjacent conductive paths. This will increase the resistance value of the low-resistance state, i.e., low-resistance state degrade (LRS degrade) will occur.

[0004] On the other hand, when the resistive switching layer is in HRS (High Resistance State), if oxygen ions in the resistive switching layer gain energy from a high-temperature environment (e.g., the high-temperature environment of durability screening), some oxygen ions may diffuse horizontally, leaving oxygen vacancies to form conductive paths. This will reduce the resistance value of the high-resistivity state, i.e., high-resistivity state degrade (HRS degrade) occurs. When low-resistivity state degrade or high-resistivity state degrade occurs, it will reduce the yield and reliability of the memory device.

[0005] Furthermore, in existing RRAMs, the conductive paths in the resistive switching layer are randomly formed and cannot be controlled each time a voltage is applied, and the resistance values ​​of the resistive switching layer at different memory cell locations are also different when the same voltage is applied. Therefore, the reliability and performance uniformity of the memory device are poor. Summary of the Invention

[0006] This invention provides an RRAM and a method for manufacturing the same, which can increase the yield and reliability of memory devices and improve the uniformity of reliability and performance.

[0007] An embodiment of the present invention discloses an RRAM comprising: a plurality of bottom contact structures formed in a substrate; a plurality of memory cells formed on the substrate, wherein each memory cell comprises: a bottom electrode layer formed on one of the bottom contact structures; two L-shaped resistive switching layers formed on the bottom electrode layer, wherein each of the L-shaped resistive switching layers comprises a horizontal portion and a vertical portion; a plurality of oxygen ion diffusion barrier layers formed on the inner and outer sidewalls of each of the vertical portions of the L-shaped resistive switching layers; and a top electrode layer, wherein the L-shaped resistive switching layers and the oxygen ion diffusion barrier layers are located between the top electrode layer and the bottom electrode layer; and an insulating structure formed between two adjacent memory cells.

[0008] An embodiment of the present invention discloses a method for manufacturing RRAM, comprising: forming a plurality of bottom contact structures in a substrate; forming a bottom electrode material on the substrate; forming a sacrificial pattern layer on the bottom electrode material, wherein the sacrificial pattern layer includes a plurality of first openings; conformally forming a resistive switching material on the sacrificial pattern layer; conformally forming a first oxygen ion diffusion barrier material on the resistive switching material; performing a first planarization process to make the top surface of the first oxygen ion diffusion barrier material, the top surface of the resistive switching material, and the top surface of the sacrificial pattern layer coplanar; removing the sacrificial pattern layer to form a plurality of second openings, wherein the second openings expose the sidewalls of the resistive switching material; forming a second oxygen ion diffusion barrier layer on the sidewalls of the resistive switching material; forming a top electrode material on the resistive switching material, the first oxygen ion diffusion barrier material, and the second oxygen ion diffusion barrier layer; performing a patterning process to form an insulating structure opening penetrating the bottom electrode material, the resistive switching material, the first oxygen ion diffusion barrier material, and the top electrode material, thereby defining a plurality of memory cells on the substrate; and forming an insulating structure in the insulating structure opening.

[0009] In the RRAM provided in this embodiment of the invention, a resistive switching layer with a specific shape (e.g., L-shaped and U-shaped) and size is formed. This effectively controls the position and shape of the conductive paths, thereby improving the uniformity of reliability and performance. Furthermore, in the RRAM provided in this embodiment of the invention, oxygen ion diffusion barrier layers are provided on the inner and outer walls of the vertical portion of the resistive switching layer. The oxygen ion diffusion barrier layers can restrict the horizontal movement of oxygen ions in the resistive switching layer, and also prevent oxygen ions from the insulating layer from entering the resistive switching layer and affecting the number and size of the conductive paths. In other words, low-resistance state degradation or high-resistance state degradation can be avoided, thereby improving yield and reliability. Attached Figure Description

[0010] Figures 1A to 1G This is a cross-sectional schematic diagram corresponding to each step in the manufacturing of RRAM according to some embodiments of the present invention.

[0011] Figure 2 This is a cross-sectional schematic diagram of the RRAM according to other embodiments of the present invention.

[0012] Figure 3A and Figure 3B This is a cross-sectional schematic diagram corresponding to the various steps in manufacturing RRAM according to other embodiments of the present invention.

[0013] Figure 4 This is a cross-sectional schematic diagram of the RRAM according to other embodiments of the present invention.

[0014] [Symbol Explanation]

[0015] 10: First Area

[0016] 20: Second Zone

[0017] 100, 200, 300, 400: RRAM

[0018] 102:Substrate

[0019] 101: Bottom contact structure

[0020] 104: Bottom Electrode Material

[0021] 104': Bottom electrode layer

[0022] 105: First Opening

[0023] 106: Sacrifice Pattern Layer

[0024] 108: Resistance conversion materials

[0025] 108': Resistor conversion layer

[0026] 108A, 108B, 108C: Resistor conversion layers

[0027] 110: First oxygen ion diffusion blocking material

[0028] 110A, 110B, 110C: First oxygen ion diffusion barrier layer

[0029] 112: First insulating layer

[0030] 114,114*: Second oxygen ion diffusion barrier layer

[0031] 115: Second opening

[0032] 116: Second insulating layer

[0033] 118: Third Oxygen Ion Diffusion Barrier Material

[0034] 118': Third oxygen ion diffusion barrier layer

[0035] 120: Oxygen ion storage material

[0036] 120': Oxygen ion storage layer

[0037] 122: Fourth Oxygen Ion Diffusion Barrier Material

[0038] 122': Fourth oxygen ion diffusion barrier layer

[0039] 124: Top electrode material

[0040] 124': Top electrode layer

[0041] 125: Third opening

[0042] 130: Insulation structure

[0043] 132: Fifth oxygen ion diffusion barrier layer

[0044] W1: First width

[0045] W2: Second width

[0046] W3: Third width

[0047] W4: Fourth Width

[0048] W5: Fifth Width

[0049] T1: First thickness

[0050] T2: Second thickness

[0051] θ1: included angle

[0052] θ2: included angle Detailed Implementation

[0053] To make the above and other objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Furthermore, repeated reference numerals and / or words may be used in different embodiments of the present invention. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures.

[0054] Here, the terms "about" or "approximately" generally mean within 20%, preferably within 10%, and even more preferably within 5%, of a given value or range. The quantities given here are approximate; that is, unless otherwise specified, the meaning of "about" or "approximately" may be implied. In this specification, "X equal to or close to Y" means that the absolute value of the difference between the two is within 5.0% of the larger one.

[0055] Figures 1A to 1GThis is a cross-sectional schematic diagram showing the steps involved in manufacturing a resistive random access memory (RRAM) 100 according to some embodiments of the present invention. Please refer to... Figure 1A A plurality of bottom contact structures 101 are formed in the substrate 102. The substrate 102 includes a first region 10 and a second region 20, and each of the first region 10 and the second region 20 has a bottom contact structure 101. Figures 1A to 1G In the middle, the boundary between the first region 10 and the second region 20 is marked with a dashed line.

[0056] The substrate 102 may be made of a bulk semiconductor substrate (e.g., a silicon substrate), a compound semiconductor substrate (e.g., a group IIIA-VA semiconductor substrate), a silicon-on-insulator (SOI) substrate, etc. The substrate 102 may be a doped or undoped semiconductor substrate. In some embodiments, the substrate 102 is a silicon substrate. In some embodiments, the bottom contact structure 101 is a single-layer structure formed of a conductive layer, and the conductive layer comprises tungsten, aluminum, copper, silver, other suitable metals, or combinations thereof. In other embodiments, the bottom contact structure 101 is a double-layer structure, comprising a liner and a conductive layer. The liner improves the adhesion between the conductive layer and the substrate 102 and prevents metal atoms from diffusing into the substrate 102. The liner may be made of titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or combinations thereof.

[0057] Next, a bottom electrode material 104 is formed on the substrate 102. The bottom electrode material 104 may comprise titanium, tantalum, titanium nitride, tantalum nitride, other suitable conductive materials, or combinations thereof. Next, a sacrificial pattern layer 106 is formed on the bottom electrode material 104. The sacrificial pattern layer 106 includes a plurality of first openings 105 and a plurality of second openings 115. The first openings 105 and second openings 115 expose the top surface of the bottom electrode material 104. In this embodiment, the first openings 105 have a first width W1, and the second openings 115 have a second width W2 greater than the first width W1. The sacrificial pattern layer 106 may comprise a suitable material, such as nitride, oxide, carbide, oxynitride, or polycrystalline silicon. In some embodiments, the sacrificial pattern layer 106 is silicon nitride.

[0058] Next, a resistivity switching material 108 is conformally formed on the sacrificial patterning layer 106. The resistivity switching material 108 determines the resistivity state of the memory cell. The resistivity switching material 108 may comprise a transition metal oxide, such as aluminum oxide (Al₂O₃). x O y ), titanium dioxide (Ti x O y Nickel oxide (Ni) x O y ), tantalum oxide (Tax O y ), hafnium oxide (Hf) x O y ) or zirconium oxide (Zr x O y The resistivity conversion material 108 can be formed using chemical vapor deposition, atomic layer deposition, or other suitable deposition processes. In some embodiments, the resistivity conversion material 108 is hafnium oxide (HfO2) formed by atomic layer deposition.

[0059] Next, a first oxygen ion diffusion barrier material 110 is compliantly formed on the resistivity conversion material 108. The first oxygen ion diffusion barrier material 110 can block oxygen ions, making their movement more difficult. Therefore, the horizontal movement of oxygen ions can be reduced or avoided. That is, oxygen ions can be prevented from diffusing from the resistivity conversion material 108 into the subsequently formed first insulating layer 112 (marked as shown in the diagram). Figure 1B This prevents oxygen ions from diffusing from the subsequently formed first insulating layer 112 into the resistivity conversion material 108. To block the horizontal movement of oxygen ions, the first oxygen ion diffusion barrier material 110 may differ from the resistivity conversion material 108. The first oxygen ion diffusion barrier material 110 may contain alumina (Al₂O₃). x O y ), titanium oxynitride (Ti x O y N z ), titanium dioxide (Ti x O y ), tantalum oxide (Ta x O y ), hafnium oxide (Hf) x O y Nickel oxide (Ni) x O y Zirconium oxide (Zr) x O y (or a combination thereof). In some embodiments, the first oxygen ion diffusion barrier material 110 is titanium oxynitride (TiON). The first oxygen ion diffusion barrier material 110 can be formed using chemical vapor deposition, atomic layer deposition, or other suitable deposition processes. In some embodiments, the first oxygen ion diffusion barrier material 110 is formed by atomic layer deposition of alumina (Al2O3).

[0060] Please refer to Figure 1BA first insulating layer 112 is formed in the first opening 105 and the second opening 115, and the resistivity conversion material 108 is divided into multiple discontinuous resistivity conversion layers 108A, 108B and 108C, and the first oxygen ion diffusion barrier material 110 is divided into multiple discontinuous first oxygen ion diffusion barrier layers 110A, 110B and 110C. The step of forming the first insulating layer 112 may include forming a first insulating material on the substrate 102 and filling the first opening 105 and the second opening 115. Next, a planarization process (e.g., chemical mechanical polishing) is performed, using the sacrificial pattern layer 106 as a stop layer, to partially remove the first insulating material, the first oxygen ion diffusion barrier material 110 and the resistivity conversion material 108 located on the sacrificial pattern layer 106. The first insulating layer 112 may contain a suitable insulating material, such as a nitride, oxide or oxynitride. In some embodiments, the first insulating layer 112 is black diamond. The first insulating layer 112 can be formed using chemical vapor deposition, atomic layer deposition, spin coating or other suitable deposition processes.

[0061] Please refer to Figure 1C A first etching process is performed to remove the sacrificial pattern layer 106 and form a plurality of third openings 125. The third openings 125 expose the sidewalls of the resistivity conversion layers 108A, 108B, and 108C. The first etching process may include a wet etching process, a dry etching process, or a combination thereof. In order to completely remove the sacrificial pattern layer 106 and avoid damage to the resistivity conversion material 108, the first oxygen ion diffusion barrier material 110, and the first insulating layer 112, the etching rate of the sacrificial pattern layer 106 during the first etching process may be greater than the etching rates of the resistivity conversion material 108, the first oxygen ion diffusion barrier material 110, and the first insulating layer 112. Furthermore, the material of the sacrificial pattern layer 106 may be different from the material of the first insulating layer 112. In some embodiments, in the first etching process, the ratio of the etching rate R1a of the sacrificial pattern layer 106 to the etching rate R1b of the resistivity conversion material 108, R1a / R1b, is 3.0-20.0, and the ratio of the etching rate R1a of the sacrificial pattern layer 106 to the etching rate R1c of the first oxygen ion diffusion barrier material 110, R1a / R1c, is 3.0-20.0.

[0062] Please refer to Figure 1DA second oxygen ion diffusion barrier layer 114 is compliantly formed in the third opening 125. In this embodiment, the second oxygen ion diffusion barrier layer 114 formed in the third opening 125 has a U-shaped cross-sectional profile. In this embodiment, each second oxygen ion diffusion barrier layer 114 is formed between adjacent resistor switching layers 108A, 108B, and 108C, such that the inner and outer walls of resistor switching layers 108A, 108B, and 108C can be covered by an oxygen ion diffusion barrier material (i.e., the first oxygen ion diffusion barrier layers 110A, 110B, and 110C or the second oxygen ion diffusion barrier layer 114), which is beneficial to increasing the yield and reliability of the RRAM 100. The material of the second oxygen ion diffusion barrier layer 114 may be the same as or similar to the first oxygen ion diffusion barrier material 110.

[0063] Please refer to Figure 1E A second insulating layer 116 is formed on the second oxygen ion diffusion barrier layer 114, filling the third opening 125. In this embodiment, the second oxygen ion diffusion barrier layer 114 and the second insulating layer 116 can be planarized independently or simultaneously, such that the top surface of the second insulating layer 116, the top surface of the second oxygen ion diffusion barrier layer 114, the top surface of the first insulating layer 112, the top surfaces of the first oxygen ion diffusion barrier layers 110A, 110B, and 110C, and the top surfaces of the resistive conversion layers 108A, 108B, and 108C are coplanar. The material of the second insulating layer 116 can be the same as or similar to the material of the first insulating layer 112.

[0064] Furthermore, to reduce stress between the resistivity conversion material 108 and the oxygen ion diffusion barrier material (e.g., the material of the first oxygen ion diffusion barrier layers 110A, 110B, 110C or the material of the second oxygen ion diffusion barrier layer 114), the material of the second insulating layer 116 may be different from the material of the sacrificial patterning layer 106. In this embodiment, the second insulating layer 116 is black diamond. In other embodiments, the second insulating layer 116 is an oxide and is made of a different material than the first insulating layer 112.

[0065] Please refer to Figure 1F A third oxygen ion diffusion barrier material 118, an oxygen ion storage material 120, a fourth oxygen ion diffusion barrier material 122, and a top electrode material 124 are sequentially formed on a substrate 102.

[0066] The third oxygen ion diffusion barrier material 118 can be used to reduce or prevent the vertical movement of oxygen ions. More specifically, in a high-resistivity state, the third oxygen ion diffusion barrier material 118 can prevent oxygen ions from diffusing from the resistance conversion layers 108A, 108B, and 108C into the oxygen ion storage material 120, thereby maintaining the stability of the high-resistivity state. On the other hand, in a low-resistivity state, the third oxygen ion diffusion barrier material 118 can prevent oxygen ions from diffusing from the oxygen ion storage material 120 into the resistance conversion layers 108A, 108B, and 108C, thereby maintaining the stability of the low-resistivity state. To block the vertical movement of oxygen ions, the third oxygen ion diffusion barrier material 118 may be different from the resistance conversion material 108. The third oxygen ion diffusion barrier material 118 may be the same as or similar to the first oxygen ion diffusion barrier material 110.

[0067] When a formation voltage or a write voltage is applied to the RRAM 100, the oxygen ion storage material 120 can be used to store oxygen ions from the resistive switching layers 108A, 108B, and 108C. When an erase voltage is applied to the RRAM 100, the oxygen ions stored in the oxygen ion storage material 120 can be driven back into the resistive switching layers 108A, 108B, and 108C. The oxygen ion storage material 120 may comprise titanium (Ti), tantalum (Ta), hafnium (Hf), or zirconium (Zr). In some embodiments, the material of the oxygen ion storage material 120 is titanium.

[0068] The fourth oxygen ion diffusion barrier material 122 can be used to reduce or prevent the vertical movement of oxygen ions. More specifically, in a low-resistance state, the fourth oxygen ion diffusion barrier material 122 can prevent oxygen ions from diffusing from the oxygen ion storage material 120 into the top electrode material 124. Therefore, oxidation of the top electrode material 124 can be prevented, thereby improving the performance and yield of the memory device. The fourth oxygen ion diffusion barrier material 122 may be the same as or similar to the first oxygen ion diffusion barrier material 110.

[0069] The top electrode material 124 may comprise titanium, tantalum, titanium nitride, tantalum nitride, other suitable conductive materials, or combinations thereof. In some embodiments, the bottom electrode material 104 is titanium, and the top electrode material 124 is titanium nitride. In other embodiments, the bottom electrode material 104 is titanium nitride, and the top electrode material 124 is titanium.

[0070] Please refer to Figure 1GA patterning process is performed to form multiple memory cells on the substrate 102. Next, an insulating structure 130 is formed between two adjacent memory cells. Specifically, a suitable dry etching process (e.g., plasma etching) can be performed to form openings (or trenches) at the junctions between different regions (e.g., the first region 10 and the second region 20) penetrating the bottom electrode material 104, the resistivity conversion material 108 (e.g., a portion of resistivity conversion layers 108A and 108C), the first oxygen ion diffusion barrier material 110 (e.g., a portion of the first oxygen ion diffusion barrier layers 110A and 110C), the first insulating layer 112, the third oxygen ion diffusion barrier material 118, the oxygen ion storage material 120, the fourth oxygen ion diffusion barrier material 122, and the top electrode material 124, and to form the bottom electrode layer 104', the third oxygen ion diffusion barrier layer 118', the oxygen ion storage layer 120', the fourth oxygen ion diffusion barrier layer 122', and the top electrode layer 124'. Next, insulating material is filled into the opening. Then, a planarization process is performed to remove excess insulating material on the top electrode layer 124' to form an insulating structure 130. The material and formation method of the insulating structure 130 may be the same as or similar to the material and formation method of the first insulating layer 112.

[0071] In this embodiment, the resistivity conversion material 108 located in the second opening 115 is patterned to form two mirror-symmetrical L-shaped structures (i.e., an L-shaped resistivity conversion layer 108C located in the first region 10 and an L-shaped resistivity conversion layer 108A located in the second region 20). Similarly, the first oxygen ion diffusion barrier material 110 located in the second opening 115 is also patterned to form two mirror-symmetrical L-shaped structures (i.e., an L-shaped first oxygen ion diffusion barrier layer 110C located in the first region 10 and an L-shaped first oxygen ion diffusion barrier layer 110A located in the second region 20).

[0072] Afterwards, other existing processes can be performed (e.g., a contact structure can be formed on the top electrode layer 124') to complete the RRAM 100, which will not be described in detail here.

[0073] Please refer to Figure 1GIn some embodiments, the RRAM 100 includes a plurality of bottom contact structures 101 formed in a substrate 102, a plurality of memory cells formed on the substrate 102, and an insulating structure 130 formed between two adjacent memory cells. Each memory cell is located in a first region 10 or a second region 20 and includes a bottom electrode layer 104', a resistive switching layer (e.g., 108A, 108B, and 108C), a first oxygen ion diffusion barrier layer (e.g., 110A, 110B, and 110C), a third oxygen ion diffusion barrier layer 118', an oxygen ion storage layer 120', a fourth oxygen ion diffusion barrier layer 122', and a top electrode layer 124' sequentially formed on the substrate 102. In addition, each memory cell also includes a U-shaped second oxygen ion diffusion barrier layer 114 located between adjacent resistive switching layers 108A, 108B, and 108C. By applying voltage to the bottom electrode layer 104' and the top electrode layer 124', the resistance switching layers 108A, 108B, and 108C can be converted into different resistance states.

[0074] In this embodiment, resistor conversion layers 108A and 108C are L-shaped, while resistor conversion layer 108B is U-shaped. The U-shaped resistor conversion layer 108B includes two vertical portions and one horizontal portion. The L-shaped resistor conversion layer 108A or 108C includes one vertical portion and one horizontal portion. In the first region 10, the horizontal portion of resistor conversion layer 108A extends from its vertical portion in a direction away from the center of the memory cell, and the horizontal portion of resistor conversion layer 108C also extends from its vertical portion in a direction away from the center of the memory cell. That is, the horizontal portions of resistor conversion layers 108A and 108C are located on opposite sides of their vertical portions. In other words, resistor conversion layers 108A and 108C in the same memory cell are arranged horizontally back-to-back.

[0075] In some embodiments, the length of the horizontal portion of resistive conversion layer 108A is different from the length of the horizontal portion of resistive conversion layer 108C. In other embodiments, the length of the horizontal portion of resistive conversion layer 108A is the same as the length of the horizontal portion of resistive conversion layer 108C, that is, resistive conversion layer 108A and resistive conversion layer 108C are mirror images of each other.

[0076] In this embodiment, the first oxygen ion diffusion barrier layers 110A and 110C are L-shaped, and the first oxygen ion diffusion barrier layer 110B is U-shaped. The first oxygen ion diffusion barrier layer 110A is formed on the groove formed by the resistive conversion layer 108A, the first oxygen ion diffusion barrier layer 110B is formed on the groove formed by the resistive conversion layer 108B, and the first oxygen ion diffusion barrier layer 110C is formed on the groove formed by the resistive conversion layer 108C. Each of the first oxygen ion diffusion barrier layers (110A, 110B, 110C) and the second oxygen ion diffusion barrier layer 114 are respectively formed on the inner and outer walls of the vertical portions of each resistive conversion layer 108A, 108B, 108C.

[0077] A bottom electrode layer 104' is formed on one of the bottom contact structures 101. In this embodiment, between the top electrode layer 124' and the bottom electrode layer 104', there is a resistor conversion layer 108A with an L-shaped cross-sectional profile, two resistor conversion layers 108B with U-shaped cross-sectional profiles, a resistor conversion layer 108C with an L-shaped cross-sectional profile, and a plurality of second oxygen ion diffusion barrier layers 114 with U-shaped cross-sectional profiles. More specifically, the resistor conversion layers 108A, 108B, 108C, the first oxygen ion diffusion barrier layers 110A, 110B, 110C, and the second oxygen ion diffusion barrier layers 114 are located in the overlapping region of the vertical projection of the top electrode layer 124' and the vertical projection of the bottom electrode layer 104'.

[0078] In the manufacturing method of RRAM 100 provided in this embodiment, by controlling the shape and size of the resistive switching layer, the position and shape of the conductive path can be effectively controlled, thereby improving the reliability and performance uniformity of the memory device.

[0079] For more details, please refer to Figure 1G Specifically, when a voltage is applied, compared to a conventional planar resistive switching layer, the resistive switching layers 108A, 108B, and 108C of this embodiment can confine the conductive path within the vertical portions of each resistive switching layer 108A, 108B, and 108C. In other words, by forming the resistive switching layers 108A, 108B, and 108C, the position and shape of the conductive path can be effectively controlled. This improves the reliability and performance uniformity of the RRAM 100. In some embodiments, the top surface of the vertical portion of each resistive switching layer 108A, 108B, and 108C has a surface area between... The third width W3 (drawn in) Figure 1E middle).

[0080] On the other hand, in this embodiment, the inner and outer walls of the vertical portions of each resistive switching layer 108A, 108B, and 108C are covered by an oxygen ion diffusion barrier layer. Therefore, when a voltage is applied, the horizontal movement of oxygen ions can be significantly reduced or avoided, and oxygen ions from the insulating layers (i.e., the first insulating layer 112 and the second insulating layer 116) can be prevented from entering the resistive switching layer and affecting the number and size of conductive paths. In other words, through the resistive switching layers 108A, 108B, and 108C, the first oxygen ion diffusion barrier layers 110A, 110B, and 110C, and the second oxygen ion diffusion barrier layer 114 of this embodiment, the resistance values ​​of the high-resistance state and the low-resistance state can be more easily predicted and controlled. In this way, low-resistance state degradation or high-resistance state degradation can be avoided, and the yield and reliability of the RRAM 100 can be improved.

[0081] To prevent oxygen ions from horizontally entering or leaving the vertical portions of resistive switching layers 108A, 108B, and 108C, please refer to... Figure 1E In some embodiments, the top surface of the vertical portion of each of the first oxygen ion diffusion barrier layers 110A, 110B, and 110C has a fourth width W4, which is 10-50 nm. The top surface of the vertical portion of the second oxygen ion diffusion barrier layer 114 has a fifth width W5, which is also 10-50 nm. In other embodiments, materials with strong oxygen ion blocking ability can be selected to form the first oxygen ion diffusion barrier layers 110A, 110B, and 110C and the second oxygen ion diffusion barrier layer 114, thereby reducing the fourth width W4 and the fifth width W5, which is beneficial for the miniaturization of the RRAM 100.

[0082] Please refer to Figure 1F In this embodiment, the third oxygen ion diffusion barrier material 118 and the fourth oxygen ion diffusion barrier material 122 may have a smaller thickness relative to the thickness of the vertical portions of the first oxygen ion diffusion barrier layers 110A, 110B, and 110C and the second oxygen ion diffusion barrier layer 114. This facilitates the movement (i.e., vertical movement) of oxygen ions between the oxygen ion storage layer 120' and the resistive switching layers 108A, 108B, and 108C. On the other hand, to further prevent oxygen ions from diffusing as expected, the third oxygen ion diffusion barrier material 118 may have a first thickness T1 between 1 and 5 nm, and the fourth oxygen ion diffusion barrier material 122 may have a second thickness T2 between 1 and 5 nm.

[0083] In other embodiments, more first openings 105 can be formed in the first region 10, allowing the memory cells located in the first region 10 to have more U-shaped resistive switching layers 108B. This increases the area available for forming conductive paths, thereby further improving the performance and yield of the RRAM 100.

[0084] Please refer to Figure 1G The top surfaces of resistive switching layers 108A, 108B, and 108C are coplanar, and their bottom surfaces are also coplanar. Each of the resistive switching layers 108A, 108B, and 108C contains a horizontal portion electrically connected to the bottom electrode layer 104' that can store oxygen ions. When an erase voltage is applied, some oxygen ions can move from the horizontal portions of the resistive switching layers 108A, 108B, and 108C into the vertical portions. Therefore, it is easier for all oxygen vacancies to recombine with oxygen ions. This improves reset efficiency and further enhances the performance of the RRAM 100.

[0085] Please refer to Figure 1A In this embodiment, since the second opening 115 has a second width W2 that is greater than the first width W1, after the insulating structure 130 is formed, the L-shaped resistive conversion layer 108C in the first region 10 and the L-shaped resistive conversion layer 108A in the second region 20 can still retain horizontal portions of appropriate length to store oxygen ions. It should be understood that... Figure 1A The number and size of the first opening 105 and the second opening 115 shown are for illustrative purposes only and are not intended to limit the invention.

[0086] Please refer to Figure 1A The bottom and sidewalls of the sacrificial pattern layer 106 have an angle θ1. Since the resistivity conversion material 108 and the first oxygen ion diffusion barrier material 110 are compliantly formed on the sacrificial pattern layer 106, the bottom and sidewalls of the first opening 105 and the second opening 115 have an angle θ2 that is substantially complementary to the angle θ1. To facilitate the filling of the first insulating layer 112 into the first opening 105 and the second opening 115, in some embodiments, the angle θ2 is 75 degrees to 105 degrees. Furthermore, please refer to... Figure 1C Since the position and shape of the third opening 125 correspond to the sacrificial pattern layer 106, there is an angle θ1 between the bottom and the sidewall of the third opening 125. This is to facilitate the filling of the second insulating layer 116, the second oxygen ion diffusion barrier layer 114, or the second oxygen ion diffusion barrier layer 114* (illustrated in...). Figure 3B and Figure 4 In the third opening 125, in some embodiments, the included angle θ2 is 75 degrees to 105 degrees. Please refer to... Figure 1AIn this embodiment, the sidewalls of the sacrificial pattern layer 106 are substantially perpendicular to the surface of the bottom electrode material 104. In other words, both the included angles θ1 and θ2 are approximately 90 degrees.

[0087] It should be noted that in this specification, the term "L-shaped" can include both "L-shaped" and "L-like", and the term "U-shaped" can include both "U-shaped" and "U-like". In other words, when the included angle θ1 is between 75 degrees and 105 degrees, the formed resistivity conversion layers 108A and 108C, the first oxygen ion diffusion barrier layers 110A and 110C can all be considered to have an "L-shaped" cross-sectional profile. Similarly, when the included angle θ2 is between 75 degrees and 105 degrees, the formed resistivity conversion layer 108B, the first oxygen ion diffusion barrier layer 110B, and the second oxygen ion diffusion barrier layer 114 can all be considered to have a "U-shaped" cross-sectional profile.

[0088] In this embodiment, instead of using an etching process (e.g., plasma etching), a planarization process is used to remove the second insulating layer 116 and expose the top surfaces of the resistive switching layers 108A, 108B, and 108C. This avoids damage to the top surfaces of the resistive switching layers 108A, 108B, and 108C during the etching process. Therefore, the performance and yield of the RRAM 100 can be further improved.

[0089] Figure 2 The RRAM 200 shown is... Figure 1G The RRAM 100 shown is similar, the difference being... Figure 2 The RRAM 200 further includes a fifth oxygen ion diffusion barrier layer 132. For simplicity, regarding the same... Figure 1G The devices and their manufacturing processes illustrated will not be described in detail here.

[0090] Please refer to Figure 2 The fifth oxygen ion diffusion barrier layer 132 has a U-shaped cross-sectional profile, and the insulating structure 130 fills the groove formed by the fifth oxygen ion diffusion barrier layer 132. In such a case... Figure 1G In the process, after forming openings or trenches at the boundaries between different regions (e.g., the first region 10 and the second region 20), an oxygen ion diffusion barrier material can be compliantly formed on the memory cell. Next, insulating material is filled into the openings or trenches. Then, a planarization process is performed to remove excess insulating material and oxygen ion diffusion barrier material located on the top electrode layer 124' to form an insulating structure 130 and a fifth oxygen ion diffusion barrier layer 132. The material and thickness of the fifth oxygen ion diffusion barrier layer 132 may be the same as or similar to the first oxygen ion diffusion barrier material 110 and its thickness.

[0091] In the first region 10, a fifth oxygen ion diffusion barrier layer 132 is formed between the horizontal portion of the resistive switching layer 108C and the insulating structure 130. In the second region 20, a fifth oxygen ion diffusion barrier layer 132 is formed between the horizontal portion of the resistive switching layer 108A and the insulating structure 130. The fifth oxygen ion diffusion barrier layer 132 prevents oxygen ions from diffusing from the insulating structure 130 into the resistive switching layer 108C in the first region 10 and the resistive switching layer 108A in the second region 20. Therefore, the performance and yield of the RRAM 200 can be further improved.

[0092] Figure 3A and Figure 3B Similar to Figure 1D and Figure 1G . Figure 3B The RRAM 300 shown is... Figure 1G The RRAM100 shown is similar, the difference being... Figure 3B The cross-sectional profile of the second oxygen ion diffusion barrier layer 114* is different from that of the second oxygen ion diffusion barrier layer 114*. Figure 1G The cross-sectional profile of the second oxygen ion diffusion barrier layer 114. For simplicity, regarding the same... Figure 1G The devices, process steps, and advantages illustrated will not be detailed here.

[0093] The position of the top surface of the second oxygen ion diffusion barrier layer 114* can be controlled by adjusting the duration of the planarization process. Figure 3A As shown, after this planarization process, the top surface of the second oxygen ion diffusion barrier layer 114* is higher than the top surfaces of the first insulating layer 112, the first oxygen ion diffusion barrier layers 110A, 110B, and 110C, and the top surfaces of the resistive conversion layers 108A, 108B, and 108C. The material of the second oxygen ion diffusion barrier layer 114* may be the same as or similar to the material of the second oxygen ion diffusion barrier layer 114.

[0094] In this embodiment, a second oxygen ion diffusion barrier layer 114* is formed to completely fill the third opening 125. The thermal conductivity of the second oxygen ion diffusion barrier layer 114* is better than that of the second insulating layer 116. Therefore, the heat dissipation capability of the memory cell can be improved, thereby enhancing the performance of the RRAM 300. Furthermore, the formation and planarization steps of the second insulating layer 116 can be omitted in this embodiment. Therefore, the manufacturing method provided by this embodiment simplifies the process and reduces the time and cost required for production.

[0095] Figure 4 The RRAM 400 shown is... Figure 3B The RRAM 300 shown is similar, the difference being... Figure 4 The RRAM 400 further includes a fifth oxygen ion diffusion barrier layer 132. For simplicity, regarding the same... Figure 3B The devices, process steps, and advantages illustrated will not be detailed here.

[0096] By forming a fifth oxygen ion diffusion barrier layer 132, oxygen ions can be prevented from diffusing from the insulating structure 130 into the L-type resistive switching layer 108C located in the first region 10 and the L-type resistive switching layer 108A located in the second region 20. Therefore, the performance and yield of the RRAM 400 can be further improved.

[0097] In summary, in the RRAM manufacturing method provided in this embodiment of the invention, by forming a sacrificial pattern layer, multiple L-shaped and U-shaped resistive switching layers can be formed between the top and bottom electrode layers of the same memory cell. The vertical portions of the L-shaped and U-shaped resistive switching layers can effectively control the position and shape of the conductive paths. This improves the reliability and performance uniformity of the RRAM.

[0098] Furthermore, the horizontal portions of the L-shaped and U-shaped resistive switching layers can store some oxygen ions. This improves reset efficiency and further enhances the performance of the RRAM. In the RRAM manufacturing method provided in this embodiment, the number and size of resistive switching layers with specific shapes can be controlled by adjusting the shape and size of the sacrificial pattern layer and the process conditions for depositing the resistive switching layers. Therefore, the process offers high flexibility.

[0099] Furthermore, in the RRAM provided in this embodiment of the invention, oxygen ion diffusion barrier layers are provided on the inner and outer walls of the vertical portion of the resistive switching layer. This restricts the horizontal movement of oxygen ions within the resistive switching layer. Therefore, degradation in low-resistivity or high-resistivity states can be avoided. This improves the yield and reliability of the RRAM. Moreover, the manufacturing method provided in this embodiment of the invention can be easily integrated into existing RRAM processes.

[0100] Although the present invention has been disclosed above with reference to several preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make any modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A resistive random access memory, characterized in that, include: Multiple bottom contact structures are formed in the substrate; A plurality of memory cells are formed on the substrate, wherein each of the memory cells includes: A bottom electrode layer is formed on one of the bottom contact structures; Two L-shaped resistive conversion layers are formed on the bottom electrode layer, wherein each of the L-shaped resistive conversion layers includes a horizontal portion and a vertical portion; Multiple oxygen ion diffusion blocking layers are formed on the inner and outer walls of each of the vertical portions of the L-shaped resistive conversion layer; and A top electrode layer, wherein the L-shaped resistive conversion layer and the oxygen ion diffusion blocking layer are located between the top electrode layer and the bottom electrode layer; and An insulating structure is formed between two adjacent memory cells.

2. The resistive random access memory as described in claim 1, characterized in that, In each of the memory cells, the horizontal portion of each of the L-shaped resistor conversion layers extends from the vertical portion toward a direction away from the center of the memory cell.

3. The resistive random access memory as described in claim 1, characterized in that, Each of the aforementioned memory units further includes: At least one U-shaped resistive conversion layer is formed on the bottom electrode layer and located between the L-shaped resistive conversion layers, wherein the U-shaped resistive conversion layer is located between the top electrode layer and the bottom electrode layer.

4. The resistive random access memory as described in claim 3, characterized in that, The top surface of the U-shaped resistor conversion layer is coplanar with the top surface of the L-shaped resistor conversion layer, and the bottom surface of the U-shaped resistor conversion layer is coplanar with the bottom surface of the L-shaped resistor conversion layer.

5. The resistive random access memory as described in claim 3, characterized in that, The U-shaped resistivity conversion layer includes two vertical portions and one horizontal portion, and the oxygen ion diffusion blocking layer is also formed on the inner and outer walls of each of the vertical portions of the U-shaped resistivity conversion layer.

6. The resistive random access memory as described in claim 3, characterized in that, In each of the memory cells, the oxygen ion diffusion barrier layer located between one of the L-shaped resistive conversion layers and the U-shaped resistive conversion layer has a U-shaped cross-sectional profile.

7. The resistive random access memory as described in claim 5, characterized in that, The space between one of the L-shaped resistive conversion layers and the U-shaped resistive conversion layer is completely filled by the oxygen ion diffusion barrier layer.

8. The resistive random access memory as described in claim 1, characterized in that, Including: U-shaped oxygen ion diffusion barrier layer, wherein the insulating structure fills the groove formed by the U-shaped oxygen ion diffusion barrier layer.

9. The resistive random access memory as described in claim 1, characterized in that, The top surface of the vertical portion of each of the L-shaped resistive conversion layers has a surface between The width.

10. The resistive random access memory as claimed in claim 1, characterized in that, The top surface of the oxygen ion diffusion barrier layer located on the sidewall of the vertical portion of the L-shaped resistive conversion layer has a first width, which is 10-50 nm.

11. The resistive random access memory as claimed in claim 1, characterized in that, include: A third oxygen ion diffusion barrier layer is formed on the oxygen ion diffusion barrier layer and the L-type resistive conversion layer; An oxygen ion storage layer is formed on the third oxygen ion diffusion barrier layer; and A fourth oxygen ion diffusion barrier layer is formed on the oxygen ion storage layer. The top electrode layer is formed on the fourth oxygen ion diffusion barrier layer.

12. A method for manufacturing a resistive random access memory, characterized in that, include: Multiple bottom contact structures are formed in the substrate; A bottom electrode material is formed on the substrate; A sacrificial pattern layer is formed on the bottom electrode material, wherein the sacrificial pattern layer includes a plurality of first openings; A resistivity-converting material is compliantly formed on the sacrificial pattern layer; A first oxygen ion diffusion barrier material is compliantly formed on the resistivity conversion material; A first planarization process is performed to make the top surface of the first oxygen ion diffusion barrier material, the top surface of the resistivity conversion material, and the top surface of the sacrificial pattern layer coplanar; Remove the sacrificial pattern layer to form a plurality of second openings, wherein the second openings expose the sidewalls of the resistivity conversion material; A second oxygen ion diffusion barrier layer is formed on the sidewall of the resistivity conversion material; A top electrode material is formed on the resistivity conversion material, the first oxygen ion diffusion barrier material, and the second oxygen ion diffusion barrier layer; A patterning process is performed to form an insulating structural opening that penetrates the bottom electrode material, the resistivity conversion material, the first oxygen ion diffusion barrier material, and the top electrode material, thereby defining a plurality of memory cells on the substrate; An insulating structure is formed in the opening of the insulating structure.

13. The method for manufacturing a resistive random access memory as described in claim 12, characterized in that, Each of the memory cells includes: A bottom electrode layer is formed on one of the bottom contact structures; Two L-shaped resistive conversion layers are formed on the bottom electrode layer, wherein each of the L-shaped resistive conversion layers includes a horizontal portion and a vertical portion; Multiple oxygen ion diffusion blocking layers are formed on the inner and outer walls of each of the vertical portions of the L-shaped resistive conversion layer; and A top electrode layer, wherein the L-shaped resistive conversion layer and the oxygen ion diffusion blocking layer are located between the top electrode layer and the bottom electrode layer.

14. The method for manufacturing a resistive random access memory as described in claim 12, characterized in that, Forming the second oxygen ion diffusion barrier layer includes: The second oxygen ion diffusion barrier layer is compliantly formed on the resistivity conversion material and in the second opening.

15. The method for manufacturing a resistive random access memory as described in claim 14, characterized in that, include: After the first oxygen ion diffusion barrier material is formed, a first insulating material is formed to fill the first opening; After the second oxygen ion diffusion barrier layer is formed, a second insulating material is formed to fill the second opening; as well as A second planarization process is performed to make the top surfaces of the first oxygen ion diffusion barrier material, the second oxygen ion diffusion barrier layer, the resistivity conversion material, the first insulating material, and the second insulating material coplanar.

16. The method for manufacturing a resistive random access memory as described in claim 15, characterized in that, The material of the sacrificial pattern layer is different from the first insulating material, and the material of the sacrificial pattern layer is different from the second insulating material.

17. The method for manufacturing a resistive random access memory as described in claim 12, characterized in that, Forming the second oxygen ion diffusion barrier layer includes: The second oxygen ion diffusion barrier layer is formed to completely fill the second opening.

18. The method for manufacturing a resistive random access memory as described in claim 17, characterized in that, include: After the first oxygen ion diffusion barrier material is formed, a first insulating material is formed to fill the first opening; as well as A second planarization process is performed to planarize the top surface of the second oxygen ion diffusion barrier layer, wherein after the second planarization process, the top surface of the second oxygen ion diffusion barrier layer is higher than the top surface of the first oxygen ion diffusion barrier material and the top surface of the resistive conversion material.

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