Periodic control method, device and medium based on feedback dynamic clock adjustment

Abstract

The application relates to a period control method, device and medium based on feedback dynamic clock adjustment, which is suitable for ATP systems and ATO systems under a two-by-two safety redundancy architecture, and the method is specifically as follows: in each period, the ATP system or the ATO system performs redundancy state mutual transmission in the respective system, each CPU in the system performs time system switching according to the received redundancy state messages of other CPUs, and whether to time out is judged according to the time system task execution condition and the time system control array. Compared with the prior art, the application has the advantages that the time system control array can be dynamically set through the redundancy state feedback of the CPU, the time system switching is used, and the fault tolerance and the operation stability of the system are improved.

Description

Technical Field

[0001] This invention relates to train signal control systems, and more particularly to a periodic control method, device, and medium based on feedback dynamic clock adjustment. Background Technology

[0002] With the rapid development of the rail transit industry, the on-board system platform is becoming increasingly complex in its business logic and requires more and more functions to adapt to the needs of multi-mode train control. Considering the system's response time, the operating cycle cannot be set too long, meaning more functions need to be executed in a shorter period of time. Within a cycle, different time slots are divided according to the functions to be executed. When the system enters the next time slot, the tasks in the previous time slot must be completed and cannot time out. This places higher demands on the platform software design, ensuring that this performance requirement is met.

[0003] Currently, the main task of the train control onboard system software is to run in a fixed cycle, with each cycle divided into several fixed time periods, running sequentially according to a set procedure. However, the existing design cannot adapt to the following situations:

[0004] 1. Due to different safety level requirements, ATP and ATO need to run on different boards. Under the two-out-of-two safety redundancy architecture, ATO runs with ATP. Since the clock frames sent by ATP will have a delay when transmitted on the bus, as the system runs, the system delay will reach a certain level under a fixed time system, causing the system to time out.

[0005] 2. Due to network congestion, there was a sudden increase in external input data, causing the periodic task to time out during processing.

[0006] CN111108711A discloses a method and apparatus for dynamic clock switching within a transmission time interval. It mainly describes determining the clock speed for processing data per unit time based on control information received from a base station. Specifically, the user equipment can determine the amount of time available for data processing based on the control information received from the base station and adjust its clock speed to complete data processing within the determined time. However, this method is applicable to wireless multiple access communication systems but not to train signal control systems. Furthermore, this method focuses on dynamically adjusting the CPU's input clock frequency and does not provide a solution for periodic task timeouts. Summary of the Invention

[0007] The purpose of this invention is to overcome the defects of the prior art by providing a cycle control method, device and medium based on feedback dynamic clock adjustment. Within a cycle, the length of the time system within the cycle is dynamically adjusted according to the data processing situation, and the cycle length is verified to ensure that the cycle will not exceed the time limit, thereby improving the fault tolerance and operational stability of the system.

[0008] The objective of this invention can be achieved through the following technical solutions:

[0009] According to a first aspect of the present invention, a cycle control method based on feedback dynamic clock adjustment is provided, which is applicable to ATP systems and ATO systems under a 2x2 redundancy architecture. In each cycle, the ATP system or ATO system performs redundancy state exchange within its respective system. Each CPU in the system switches the time system according to the redundancy state messages received from other CPUs, and determines whether a timeout has occurred based on the execution status of the time system task and the time system control array.

[0010] As a preferred technical solution, both the ATP system and the ATO system include an A series and a B series, which are redundant to each other, and a primary / backup switching is performed between the two series.

[0011] As a preferred technical solution, each system of the ATP system and ATO system includes two CPUs as intra-system execution units to perform the two-out-of-two function.

[0012] As a preferred technical solution, each CPU in the ATP system and ATO system interacts with other CPUs through a system bus.

[0013] As a preferred technical solution, the ATP system master controls the operating sequence of all boards, and the ATO system clock follows the ATP system clock.

[0014] As a preferred technical solution, the method includes an initialization phase and a normal operation phase. In the initialization phase, the primary / backup determination and clock synchronization are performed. In the normal operation phase, the timing is dynamically adjusted according to the CPU's redundancy status during the main task's operation.

[0015] As a preferred technical solution, the initialization stage includes the following steps:

[0016] S101. The system powers on, loads the configuration file, and initializes the hardware and software.

[0017] S102. Based on the configuration file and board slot identifier, the system performs master-slave negotiation and initializes the timing control array.

[0018] S103. After determining the primary and backup, the first CPU of the ATP primary system broadcasts a clock frame to other boards to synchronize the clocks of each board and the time when it enters the normal operation cycle.

[0019] As a preferred technical solution, the normal operation phase includes the following steps:

[0020] S201. The first CPU of the main system determines the start time of the cycle according to its own security clock, and broadcasts the clock frame to other CPUs at the beginning of the cycle to align the clocks between the CPUs.

[0021] S202. After entering the main cycle, time system switching and timeout judgment are performed in the clock interrupt;

[0022] S203. Before the start of the first time system, determine whether the clock number stored in the time system control array of the previous cycle is greater than the value in the historical time system control array. If it is greater, record the clock number of the previous cycle in the historical time system control array; otherwise, do not record it.

[0023] S204. Reset the time control array according to the preset clock number;

[0024] S205. Send the board redundancy status before the end of each time period in the main task;

[0025] S206. If the current clock count is less than or equal to the period clock count, and the first CPU of the main system has received the redundancy status messages of all other CPUs, then set the value in the time system control array to the current clock count plus 1, and perform time system switching when the next clock interrupt arrives. Otherwise, wait for the next time system and update the CPU redundancy status messages. If the current clock count is less than or equal to the period clock count and no redundancy status messages of all other CPUs are received, execute step S207.

[0026] S207. If the current clock count is greater than the value in the historical clock control array and the first CPU of the main system has only received the redundancy status message from another CPU in the same system, then set the value in the clock control array to the current clock count plus 1, and perform a clock system switch when the next clock interrupt arrives. If the current clock count is greater than the value in the historical clock control array and no redundancy status message has been received from another CPU in the same system, then continue to wait for the next clock system and update the CPU's redundancy status message until the current clock count is greater than the cycle clock count.

[0027] S208. If the current clock count is greater than the period clock count, set the value in the time control array to the current clock count, and perform time system switching during the current clock interrupt.

[0028] S209. After the time system switch, in the clock interrupt, it is determined whether the time system task in the main task of this channel has been completed. If it has not been completed, it indicates that the task execution of this channel has timed out, and a crash operation is performed to redirect to the safe side; if it has been completed, it indicates that the time system task has been successfully executed and it is ready to enter the next time system.

[0029] As a preferred technical solution, in step S206, if it is a single-system operation, the first CPU of the main system receives a redundancy status message flag from another CPU, indicating that the time system of the other CPU has been completed. The value in the time system control array is set to the current clock number plus 1, and the time system is switched when the next clock interrupt arrives. If it is a dual-system operation, the first CPU of the main system receives a redundancy status message flag from the other three CPUs, indicating that the time system of the other CPUs has been completed. The value in the time system control array is set to the current clock number plus 1, and the time system is switched when the next clock interrupt arrives.

[0030] As a preferred technical solution, the number of periodic clocks is a fixed value.

[0031] According to a second aspect of the present invention, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described thereon.

[0032] According to a third aspect of the present invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described thereon.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) This invention determines that other CPUs have completed the execution of time-based tasks by feedback of the redundancy status of other CPUs, and dynamically sets the time-based control array according to the feedback of the redundancy status for time-based switching, thereby improving the fault tolerance and operational stability of the system.

[0035] (2) For systems like ATP and ATO combinations, under a master-slave architecture, this invention ensures that multiple slave units can operate more smoothly under unexpected sudden conditions. Attached Figure Description

[0036] Figure 1 This is a system structure diagram of the present invention;

[0037] Figure 2 The flowchart for the initialization phase;

[0038] Figure 3 This is a flowchart for the normal operation phase. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] This embodiment provides a cycle control method based on feedback dynamic clock adjustment, which avoids timeouts and cycle timeouts by dynamically adjusting the time system during the main task operation.

[0041] This method is applicable to ATP systems and ATO systems with a 2x2 safety redundancy architecture, such as... Figure 1 As shown, both the ATP system and the ATO system include a series A and a series B, which are redundant and switch between each other. Each series includes two CPUs (CPU1 and CPU2) as internal execution units, performing a two-out-of-two function. Each CPU interacts with other CPUs through the system bus.

[0042] The ATP system master controls the runtime sequence of all boards, and the ATO system clock follows the ATP system clock. For example, if the ATP-A system is the master, then CPU1-A of the ATP-A system will send clock frames to all other CPUs to calibrate the clocks of each CPU.

[0043] In each cycle, the ATP system or ATO system exchanges redundant status messages within their respective systems. Each CPU in the system switches time based on the redundant status messages received from other CPUs and determines whether a timeout has occurred based on the execution status of the time system tasks and the time system control array.

[0044] In this embodiment, the cycle control method based on feedback dynamic clock adjustment includes an initialization phase and a normal operation phase. In the initialization phase, the primary / backup determination and clock synchronization are performed. In the normal operation phase, the clock is dynamically adjusted according to the CPU's redundancy status during the main task's operation.

[0045] like Figure 2 As shown, the initialization phase includes the following steps:

[0046] S101. The system powers on, loads the configuration file, and initializes the hardware and software.

[0047] S102. Based on the configuration file and board slot identifier, the system performs master-slave negotiation and initializes the timing control array.

[0048] S103. After determining the primary and backup, the CPU1 of the ATP primary system broadcasts a clock frame to other boards to synchronize the clocks of each board and the time when it enters the normal operation cycle.

[0049] Before describing the normal operation phase in detail, let's first clarify the following definitions: The number of clock cycles is fixed, that is, how many clocks are in each cycle, which determines the size of the cycle. Each cycle is divided into several time series, and the length of the time series is determined by the time series control array and the historical time series control array.

[0050] like Figure 3 As shown, the normal operation phase includes the following steps:

[0051] S201, the main CPU1 determines the start time of the cycle according to its own security clock, and broadcasts the clock frame to other CPUs at the start of the cycle to align the clocks between the CPUs;

[0052] S202. After entering the main cycle, time system switching and timeout judgment are performed in the clock interrupt;

[0053] S203. Before the start of the first time system, determine whether the clock number stored in the time system control array of the previous cycle is greater than the value in the historical time system control array. If it is greater, record the clock number of the previous cycle in the historical time system control array; otherwise, do not record it.

[0054] S204. Reset the time control array to a sufficiently large number of clocks to allow for sufficient margin for dynamic adjustment;

[0055] S205. Before the end of each time period in the main task, send the board redundancy status for main / backup negotiation and to notify other CPUs that the time period has been completed.

[0056] S206. If the current clock count is less than or equal to the period clock count, and the master CPU1 has received the redundancy status messages from all other CPUs, then set the value in the time control array to the current clock count plus 1, and perform time system switching when the next clock interrupt arrives. Otherwise, wait for the next time system and update the CPU redundancy status messages. If the current clock count is less than or equal to the period clock count and no redundancy status messages from all other CPUs are received, execute step S207.

[0057] S207. If the current clock count of the time system is greater than the value in the historical time system control array (indicating that the operation of a certain time system has taken too long), and the main CPU1 has only received the redundancy status message from another CPU in the same system, then the value in the time system control array is set to the current clock count plus 1, and the time system is switched when the next clock interrupt arrives. If the current clock count of the time system is greater than the value in the historical time system control array and no redundancy status message from another CPU in the same system is received, then the CPU continues to wait for the next time system and update the redundancy status message until the current clock count is greater than the cycle clock count. In this step, the execution status of the other system is no longer considered. This is because if no redundancy status message from the other system is received, it indicates that the other system may time out. The timeout of the other system should not cause the failure of the current system.

[0058] S208. If the time system times out, that is, the current clock number is greater than the cycle clock number, it means that the cycle time has expired and no redundant status message from other CPUs has been received. Set the value in the time system control array to the current clock number and switch the time system during the current clock interrupt.

[0059] S209. After the time system switch, in the clock interrupt, it is determined whether the time system task in the main task of this channel has been completed. If it has not been completed, it indicates that the task execution of this channel has timed out, and a crash operation is performed to redirect to the safe side; if it has been completed, it indicates that the time system task has been successfully executed and it is ready to enter the next time system.

[0060] In step S206, if it is a single-system operation, the main CPU1 receives a redundancy status message flag from another CPU, indicating that the time system of the other CPU has been completed. The value in the time system control array is set to the current clock number plus 1, and the time system is switched when the next clock interrupt arrives. If it is a dual-system operation, the main CPU1 receives a redundancy status message flag from the other three CPUs, indicating that the time system of the other CPUs has been completed. The value in the time system control array is set to the current clock number plus 1, and the time system is switched when the next clock interrupt arrives.

[0061] In steps S206 and S207, the clock count is incremented by 1 because within the current clock cycle, the local system may have just sent out the redundant status, and the other CPUs have not yet received it. They wait for one clock cycle to complete the time system switch after the other CPUs receive the redundant status in the next clock cycle.

[0062] The electronic device of this invention includes a central processing unit (CPU), which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) or loaded from a storage unit into random access memory (RAM). The RAM may also store various programs and data required for device operation. The CPU, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0063] Multiple components in the device are connected to the I / O interface, including: input units such as keyboards and mice; output units such as various types of displays and speakers; storage units such as disks and optical discs; and communication units such as network interface cards (NICs), modems, and wireless transceivers. The communication unit allows the device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0064] The processing unit executes the various methods and processes described above, such as methods S101-S103 and S201-S209. For example, in some embodiments, methods S101-S103 and S201-S209 may be implemented as computer software programs tangibly contained in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on the device via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by the CPU, one or more steps of methods S101-S103 and S201-S209 described above may be performed. Alternatively, in other embodiments, the CPU may be configured to execute methods S101-S103 and S201-S209 by any other suitable means (e.g., by means of firmware).

[0065] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0066] The program code used to implement the methods of the present invention can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0067] In the context of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0068] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A periodic control method based on feedback dynamic clock adjustment, applicable to ATP systems and ATO systems under a 2x2 redundancy architecture, characterized in that, In each cycle, the ATP system or ATO system exchanges redundant statuses within their respective systems. Each CPU in the system switches between time systems based on the redundant status messages received from other CPUs, and determines whether a timeout has occurred based on the execution status of the time system tasks and the time system control array. The method includes an initialization phase and a normal operation phase. In the initialization phase, the primary / backup determination and clock synchronization are performed. In the normal operation phase, the timing is dynamically adjusted according to the CPU redundancy status during the main task operation. The normal operation phase includes the following steps: S201. The first CPU of the main system determines the start time of the cycle according to its own security clock, and broadcasts the clock frame to other CPUs at the beginning of the cycle to align the clocks between the CPUs. S202. After entering the main cycle, time system switching and timeout judgment are performed in the clock interrupt; S203. Before the start of the first time system, determine whether the clock number stored in the time system control array of the previous cycle is greater than the value in the historical time system control array. If it is greater, record the clock number of the previous cycle in the historical time system control array; otherwise, do not record it. S204. Reset the time control array according to the preset clock number; S205. Send the board redundancy status before the end of each time period in the main task; S206. If the current clock count is less than or equal to the period clock count, and the first CPU of the main system has received the redundancy status messages of all other CPUs, then set the value in the time system control array to the current clock count plus 1, and perform time system switching when the next clock interrupt arrives. Otherwise, wait for the next time system and update the CPU redundancy status messages. If the current clock count is less than or equal to the period clock count and no redundancy status messages of all other CPUs are received, execute step S207. S207. If the current clock count is greater than the value in the historical clock control array and the first CPU of the main system has only received the redundancy status message from another CPU in the same system, then set the value in the clock control array to the current clock count plus 1, and perform a clock system switch when the next clock interrupt arrives. If the current clock count is greater than the value in the historical clock control array and no redundancy status message has been received from another CPU in the same system, then continue to wait for the next clock system and update the CPU's redundancy status message until the current clock count is greater than the cycle clock count. S208. If the current clock count is greater than the period clock count, set the value in the time control array to the current clock count, and perform time system switching during the current clock interrupt. S209. After the time system switch, in the clock interrupt, it is determined whether the time system task in the main task of this channel has been completed. If it has not been completed, it indicates that the task execution of this channel has timed out, and a crash operation is performed to redirect to the safe side; if it has been completed, it indicates that the time system task has been executed successfully and is ready to enter the next time system. In step S206, if it is a single-system operation, the first CPU of the main system receives a redundancy status message flag from another CPU, indicating that the time system of the other CPU has been completed. The value in the time system control array is set to the current clock number plus 1, and the time system is switched when the next clock interrupt arrives. If it is a dual-system operation, the first CPU of the main system receives a redundancy status message flag from the other three CPUs, indicating that the time system of the other CPUs has been completed. The value in the time system control array is set to the current clock number plus 1, and the time system is switched when the next clock interrupt arrives.

2. The periodic control method based on feedback dynamic clock adjustment according to claim 1, characterized in that, Both the ATP system and the ATO system include an A system and a B system, which are redundant to each other and can switch between primary and backup systems.

3. The periodic control method based on feedback dynamic clock adjustment according to claim 1, characterized in that, Each of the ATP and ATO systems includes two CPUs as intra-system execution units, performing a two-out-of-two function.

4. The periodic control method based on feedback dynamic clock adjustment according to claim 1, characterized in that, In the ATP system and ATO system, each CPU interacts with other CPUs via the system bus.

5. The periodic control method based on feedback dynamic clock adjustment according to claim 1, characterized in that, The ATP system master controls the operating sequence of all boards, and the ATO system clock follows the ATP system clock.

6. The periodic control method based on feedback dynamic clock adjustment according to claim 1, characterized in that, The initialization phase includes the following steps: S101. The system powers on, loads the configuration file, and initializes the hardware and software. S102. Based on the configuration file and board slot identifier, the system performs master-slave negotiation and initializes the timing control array. S103. After determining the primary and backup, the first CPU of the ATP primary system broadcasts a clock frame to other boards to synchronize the clocks of each board and the time when it enters the normal operation cycle.

7. The periodic control method based on feedback dynamic clock adjustment according to claim 1, characterized in that, The number of clock cycles is a fixed value.

8. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 7.

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