A method, system and platform for data delay control for boundary scan testing
By using a boundary scan delay control method, test data is acquired and corrected in real time, and a delay model is created. This solves the rate bottleneck and data instability caused by signal delay in boundary scan testing, and achieves more efficient testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN MICROTEST AUTOMATION CO LTD
- Filing Date
- 2023-12-20
- Publication Date
- 2026-07-14
Smart Images
Figure CN117741414B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of boundary scan test processing technology, specifically relating to a data delay control method, system, and platform for boundary scan testing. Background Technology
[0002] With the iterative updates of chips and boards, higher requirements have been placed on test speed and test stability. Existing hardware resources have a certain delay. Under the influence of the delay, on the one hand, the test speed reaches a bottleneck, and on the other hand, due to the unstable factors such as oscillation or jitter that often occur at the edges of the data waveform, if the data is collected at the edge of the waveform at the rising edge of TCK, it will lead to unstable test data.
[0003] When the delay is too large or the test frequency is too high, the TDO data reading on the rising edge of TCK will be misaligned. On the one hand, the TDO data needs to be read back from the boundary scan controller. When the TDO data is pushed out, if the delay is too large or the test frequency is too high, the rising edge of TCK clock will lead TDO by too much, resulting in the TCK rising edge not reading the corresponding TDO data, thus causing data misalignment.
[0004] When the rising edge of the clock operates at the critical edge of data change, it will cause unstable data acquisition. This critical edge is caused by signal delay. In addition, if the data at the critical edge has slight oscillation or jitter, it will cause data reading errors inside the boundary scan chip, which will lead to data shift errors or TDO returning to the FPGA reading error of the boundary scan driver circuit. When reading errors caused by unstable factors are intertwined with the test results of the external (Extest) board under test, it is difficult to determine whether the problem is caused by reading instability or by connection failure of the test board under test itself.
[0005] Existing methods fail to detect instability during offline debugging, but in the testing field, when faced with thousands of DUTs, signal instability becomes apparent. At this point, it is necessary to troubleshoot the root cause of the problem on-site, whether it is unstable reading or a connection failure of the DUT itself. Once the problem is found to be caused by instability, the only way to achieve stability is to reduce the test rate, which wastes a lot of manpower and resources and cannot increase the test rate. Therefore, it is necessary to solve these critical instability problems during offline testing.
[0006] Therefore, in order to address the technical problems and defects that lead to unstable test data and low test rate, there is an urgent need to design and develop a data delay control method, system and platform for boundary scan testing. Summary of the Invention
[0007] To overcome the shortcomings and difficulties of the existing technology, the present invention provides a data delay control method, system and platform for boundary scan testing. It combines a driving circuit to provide reliable signal driving capability and signal quality, overcomes signal delay problems through coarse adjustment, improves signal stability through fine adjustment, and thus improves the test rate.
[0008] The first objective of this invention is to provide a data delay control method for boundary scan testing; the second objective of this invention is to provide a data delay control system for boundary scan testing; and the third objective of this invention is to provide a data delay control platform for boundary scan testing.
[0009] The first objective of this invention is achieved as follows: the method comprises the following steps:
[0010] The system acquires first input data corresponding to the boundary scan test operation in real time and generates first waveform data corresponding to the first input data; wherein, the first input data is test operation input control signal data; and the first waveform data is waveform state data.
[0011] Based on the first waveform data, first delay data corresponding to the first waveform data is generated; wherein, the first delay data is the actual delay data of the waveform;
[0012] Create a boundary scan delay model, and based on the boundary scan delay model, combine the first waveform data and the first delay data to generate corresponding first amplitude modulation data;
[0013] Based on the first amplitude modulation data, the first waveform data is corrected and processed in real time, and a second waveform data corresponding to the first waveform data is generated; wherein, the second waveform data is the waveform state after correction and processing.
[0014] Furthermore, the step of generating first delay data corresponding to the first waveform data based on the first waveform data further includes:
[0015] Based on the first waveform data, generate delay parameter data corresponding to the first waveform data;
[0016] Obtain frequency data corresponding to the first waveform data, determine and generate real-time waveform status data corresponding to the frequency data.
[0017] Furthermore, the test operation input control signal data is presented in the form of a pin header; the signal data includes clock data, status signal data, and transmission signal data;
[0018] The first waveform data is the waveform state data before entering the boundary scan chain; the second waveform data is the waveform state data before entering the boundary scan chain and after correction processing.
[0019] The first amplitude modulation data includes clock cycle number amplitude modulation data and clock waveform phase amplitude modulation data.
[0020] Furthermore, the step of creating a boundary scan delay model and generating corresponding first amplitude modulation data based on the boundary scan delay model, combined with the first waveform data and the first delay data, further includes:
[0021] Acquire first delay data, determine a first numerical relationship between the first delay data and the clock cycle count data, and generate clock cycle count amplitude modulation data corresponding to the first numerical relationship;
[0022] Based on the clock cycle number amplitude modulation data, the clock cycle number data is processed in real time with lag phase fine adjustment.
[0023] Furthermore, the step of creating a boundary scan delay model and generating corresponding first amplitude modulation data based on the boundary scan delay model, combined with the first waveform data and the first delay data, further includes:
[0024] Acquire first delay data, determine a second numerical relationship between the first delay data and clock waveform phase data, and generate clock waveform phase amplitude modulation data corresponding to the second numerical relationship;
[0025] Based on the clock waveform phase amplitude modulation data, the clock waveform phase data is processed by real-time phase lag fine-tuning or phase lead fine-tuning.
[0026] Furthermore, the boundary scan delay model includes a boundary scan driving circuit; the circuit includes a first control chip; the PS terminal of the first control chip is connected to the input terminal of the first digital-to-analog converter; the output terminal of the first digital-to-analog converter is connected to the positive input terminal of the first comparator; the output terminal of the first comparator is connected to the negative input terminal of the first comparator and the Vref_A pin of the third control chip, respectively.
[0027] The PL terminal of the first control chip is sequentially connected to the B0, B1, and B2 pins of the second control chip; the A0, A1, and A2 pins of the second control chip are sequentially connected to the B1, B2, and B3 pins of the third control chip; the A1, A2, and A3 pins of the third control chip are sequentially connected to one side of the boundary scan test port signal terminal; the other side of the boundary scan test port signal terminal is connected to the boundary scan test chain.
[0028] The data output interface of the boundary scan test chain is connected to the data output interface of the boundary scan test port; the data output interface of the boundary scan test port is connected to the positive input terminal of the second comparator; the output terminal of the second comparator is connected to the signal receiving interface of the PL terminal in the first control chip.
[0029] Furthermore, the step of real-time correction and processing of the first waveform data based on the first amplitude modulation data, and generating second waveform data corresponding to the first waveform data, further includes:
[0030] Based on the first amplitude modulation data, a first control signal and a second control signal are generated respectively; wherein, the first control signal is a clock cycle number adjustment and correction processing control signal; and the second control signal is a clock cycle waveform phase adjustment and correction processing control signal.
[0031] The second objective of this invention is achieved as follows: the system is applied to the data delay control method, the system comprising:
[0032] The first data generation unit is used to acquire first input data corresponding to the boundary scan test operation in real time, and generate first waveform data corresponding to the first input data; wherein, the first input data is test operation input control signal data; and the first waveform data is waveform state data.
[0033] The second data generation unit is used to generate first delay data corresponding to the first waveform data based on the first waveform data; wherein, the first delay data is the actual delay data of the waveform;
[0034] A generation unit is created to create a boundary scan delay model and, based on the boundary scan delay model, the first waveform data and the first delay data, generate corresponding first amplitude modulation data.
[0035] The correction processing unit is used to correct the first waveform data in real time based on the first amplitude modulation data, and generate second waveform data corresponding to the first waveform data; wherein the second waveform data is the waveform state after correction processing.
[0036] Furthermore, the second data generation unit further includes: a first data generation module, used to generate delay parameter data corresponding to the first waveform data based on the first waveform data;
[0037] The first determination and generation module is used to acquire frequency data corresponding to the first waveform data, determine and generate real-time waveform status data corresponding to the frequency data; the test operation input control signal data is signal data presented in the form of a pin header; the signal data includes clock data, status signal data and transmission signal data; the first waveform data is waveform status data before entering the boundary scan chain; the second waveform data is waveform status data before entering the boundary scan chain and after correction processing; the first amplitude modulation data includes clock cycle number amplitude modulation data and clock waveform phase amplitude modulation data;
[0038] And / or, the creation and generation unit further includes: a second determination and generation module, configured to acquire first delay data, determine a first numerical relationship between the first delay data and clock cycle quantity data, and generate clock cycle quantity amplitude modulation data corresponding to the first numerical relationship; and a first fine-tuning processing module, configured to perform real-time lag phase fine-tuning processing on the clock cycle quantity data based on the clock cycle quantity amplitude modulation data.
[0039] And / or, the creation and generation unit further includes: a third determination and generation module, used to acquire first delay data, determine a second numerical relationship between the first delay data and clock waveform phase data, and generate clock waveform phase amplitude modulation data corresponding to the second numerical relationship;
[0040] The second fine-tuning processing module is used to perform real-time phase lag fine-tuning or phase lead fine-tuning of the clock waveform phase data based on the clock waveform phase amplitude modulation data.
[0041] The boundary scan delay model includes a boundary scan driving circuit; the circuit includes a first control chip; the PS terminal of the first control chip is connected to the input terminal of the first digital-to-analog converter.
[0042] The output terminal of the first digital-to-analog converter is connected to the positive input terminal of the first comparator; the output terminal of the first comparator is connected to the negative input terminal of the first comparator and the Vref_A pin of the third control chip; the PL terminal of the first control chip is sequentially connected to the B0, B1, and B2 pins of the second control chip; the A0, A1, and A2 pins of the second control chip are sequentially connected to the B1, B2, and B3 pins of the third control chip; the A1, A2, and A3 pins of the third control chip are sequentially connected to one side of the boundary scan test port signal terminal; the other side of the boundary scan test port signal terminal is connected to the boundary scan test chain; the data output interface of the boundary scan test chain is connected to the data output interface of the boundary scan test port; the data output interface of the boundary scan test port is connected to the positive input terminal of the second comparator; the output terminal of the second comparator is connected to the signal receiving interface of the PL terminal in the first control chip.
[0043] And / or, the correction processing unit further includes: a second data generation module, configured to generate a first control signal and a second control signal based on the first amplitude modulation data; wherein the first control signal is a clock cycle number adjustment correction processing control signal; and the second control signal is a clock cycle waveform phase adjustment correction processing control signal.
[0044] The third objective of this invention is achieved as follows: it includes a processor, a memory, and a data delay control platform control program for boundary scan testing; wherein the processor executes the data delay control platform control program for boundary scan testing, the data delay control platform control program for boundary scan testing is stored in the memory, and the data delay control platform control program for boundary scan testing implements the data delay control method for boundary scan testing.
[0045] This invention provides a method for real-time acquisition of first input data corresponding to a boundary scan test operation, and generation of first waveform data corresponding to the first input data. The first input data is test operation input control signal data; the first waveform data is waveform state data. Based on the first waveform data, first delay data corresponding to the first waveform data is generated; the first delay data is the actual delay data of the waveform. A boundary scan delay model is created, and based on the boundary scan delay model, combined with the first waveform data and the first delay data, corresponding first amplitude modulation data is generated. Based on the first amplitude modulation data, the first waveform data is corrected and processed in real-time, and second waveform data corresponding to the first waveform data is generated; the second waveform data is the corrected waveform state. A corresponding system and platform, combined with a driving circuit, provide reliable signal driving capability and signal quality. This overcomes signal delay problems through coarse adjustment and improves signal stability through fine adjustment, thereby increasing the test rate. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1 This is a schematic flowchart of a data delay control method for boundary scan testing according to the present invention;
[0048] Figure 2 This is a simplified schematic diagram of a boundary scan drive circuit, which is an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0049] Figure 3 This is a schematic diagram of a boundary scan delay model, which is an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0050] Figure 4 This is a schematic diagram of the ideal waveform of a boundary scan, representing an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0051] Figure 5 This is a schematic diagram of a boundary scan delay waveform, representing an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0052] Figure 6 This is a schematic diagram illustrating the adjustment of a certain delay in boundary scan to a normal test waveform, as an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0053] Figure 7 This is a schematic diagram of a waveform showing data misalignment caused by excessive delay during boundary scan, as an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0054] Figure 8 This is a schematic diagram of the waveform in the first step of the boundary scan misalignment problem solving method of the present invention for data delay control in boundary scan testing.
[0055] Figure 9 This is a schematic diagram of the waveform in the second step of solving the misalignment problem in a boundary scan test according to an embodiment of the data delay control method for boundary scan testing of the present invention.
[0056] Figure 10 This is a schematic diagram of a waveform showing data misalignment caused by excessive delay during boundary scan testing, as an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0057] Figure 11 This is a schematic diagram of waveform two, representing the first step of a data delay control method for boundary scan testing according to an embodiment of the present invention, which addresses the misalignment problem during boundary scan testing.
[0058] Figure 12 This is a schematic diagram of waveform two in the second step of solving the misalignment problem in boundary scan, as an embodiment of the data delay control method for boundary scan testing according to the present invention.
[0059] Figure 13 This is a schematic diagram of the communication implementation method for boundary scan testing, as an embodiment of the data delay control method for boundary scan testing according to the present invention.
[0060] Figure 14 This is a schematic diagram illustrating data passing through a boundary register, representing an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0061] Figure 15 This is a schematic diagram illustrating the passage of misaligned data through the boundary register, as an embodiment of a data delay control method for boundary scan testing according to the present invention.
[0062] Figure 16 This is a schematic diagram of a data delay control system architecture for boundary scan testing according to the present invention;
[0063] Figure 17 This is a schematic diagram of a data delay control platform architecture for boundary scan testing according to the present invention;
[0064] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0065] To facilitate a clearer understanding of the objectives, technical solutions, and advantages of this invention, the invention will be further described below in conjunction with the accompanying drawings and specific embodiments. Those skilled in the art can easily understand other advantages and effects of this invention from the content disclosed in this specification.
[0066] This invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of this invention.
[0067] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.
[0068] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Secondly, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.
[0069] Preferably, the data delay control method for boundary scan testing of the present invention is applied in one or more terminals or servers. The terminal is a device capable of automatically performing numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes, but is not limited to, microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.
[0070] The terminal can be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal can interact with the customer via a keyboard, mouse, remote control, touchpad, or voice control device.
[0071] This invention provides a data delay control method, system, and platform for boundary scan testing.
[0072] like Figure 1 The diagram shows a flowchart of a data delay control method for boundary scan testing provided in an embodiment of the present invention. In this embodiment, the data delay control method for boundary scan testing can be applied to a terminal or fixed terminal with display functionality. The terminal is not limited to personal computers, smartphones, tablets, desktop computers with cameras, or all-in-one computers.
[0073] The data delay control method for boundary scan testing can also be applied to a hardware environment consisting of a terminal and a server connected to the terminal via a network. The network includes, but is not limited to, a wide area network (WAN), a metropolitan area network (MAN), or a local area network (LAN). The data delay control method for boundary scan testing in this embodiment can be executed by the server, by the terminal, or by both the server and the terminal.
[0074] For example, for terminals requiring data delay control for boundary scan testing, the data delay control function for boundary scan testing provided by the method of this invention can be directly integrated into the terminal, or a client for implementing the method of this invention can be installed. Alternatively, the method provided by this invention can also run on servers or other devices in the form of a Software Development Kit (SDK), providing an interface for data delay control function for boundary scan testing in the form of an SDK. Terminals or other devices can then implement the data delay control function for boundary scan testing through the provided interface. The invention will be further described below with reference to the accompanying drawings.
[0075] like Figure 1 As shown, the present invention provides a data delay control method for boundary scan testing, the method comprising the following steps:
[0076] S1. Real-time acquisition of first input data corresponding to the boundary scan test operation, and generation of first waveform data corresponding to the first input data; wherein, the first input data is test operation input control signal data; the first waveform data is waveform state data;
[0077] S2. Based on the first waveform data, generate first delay data corresponding to the first waveform data; wherein, the first delay data is the actual delay data of the waveform;
[0078] S3. Create a boundary scan delay model, and generate corresponding first amplitude modulation data based on the boundary scan delay model, combined with the first waveform data and the first delay data.
[0079] S4. Based on the first amplitude modulation data, the first waveform data is corrected and processed in real time, and a second waveform data corresponding to the first waveform data is generated; wherein, the second waveform data is the waveform state after correction and processing.
[0080] The step of generating first delay data corresponding to the first waveform data based on the first waveform data further includes: S21, generating delay parameter data corresponding to the first waveform data based on the first waveform data; S22, acquiring frequency data corresponding to the first waveform data, determining and generating waveform real-time status data corresponding to the frequency data.
[0081] The test operation input control signal data is presented in the form of pin headers; the signal data includes clock data, status signal data, and transmission signal data; the first waveform data is the waveform status data before entering the boundary scan chain; the second waveform data is the waveform status data before entering the boundary scan chain and after correction processing; the first amplitude modulation data includes clock cycle number amplitude modulation data and clock waveform phase amplitude modulation data.
[0082] The step of creating a boundary scan delay model and generating corresponding first amplitude modulation data based on the boundary scan delay model, combined with the first waveform data and the first delay data, further includes:
[0083] S31. Obtain first delay data, determine a first numerical relationship between the first delay data and the clock cycle number data, and generate clock cycle number amplitude modulation data corresponding to the first numerical relationship.
[0084] S32. Based on the clock cycle number amplitude adjustment data, perform real-time lag phase fine-tuning on the clock cycle number data.
[0085] The step of creating a boundary scan delay model and generating corresponding first amplitude modulation data based on the boundary scan delay model, combined with the first waveform data and the first delay data, further includes:
[0086] S33. Obtain the first delay data, determine the second numerical relationship between the first delay data and the clock waveform phase data, and generate clock waveform phase amplitude modulation data corresponding to the second numerical relationship;
[0087] S34. Based on the clock waveform phase amplitude modulation data, perform real-time phase lag fine-tuning or phase lead fine-tuning on the clock waveform phase data.
[0088] The boundary scan delay model includes a boundary scan driving circuit; the circuit includes a first control chip; the PS terminal of the first control chip is connected to the input terminal of the first digital-to-analog converter.
[0089] The output terminal of the first digital-to-analog converter is connected to the positive input terminal of the first comparator; the output terminal of the first comparator is connected to the negative input terminal of the first comparator and the Vref_A pin of the third control chip; the PL terminal of the first control chip is connected to the B0, B1, and B2 pins of the second control chip in sequence; the A0, A1, and A2 pins of the second control chip are connected to the B1, B2, and B3 pins of the third control chip in sequence; the A1, A2, and A3 pins of the third control chip are connected to one side of the boundary scan test port signal terminal in sequence; the other side of the boundary scan test port signal terminal is connected to the boundary scan test chain.
[0090] The data output interface of the boundary scan test chain is connected to the data output interface of the boundary scan test port; the data output interface of the boundary scan test port is connected to the positive input terminal of the second comparator; the output terminal of the second comparator is connected to the signal receiving interface of the PL terminal in the first control chip.
[0091] The step of real-time correction and processing of the first waveform data based on the first amplitude modulation data, and generating second waveform data corresponding to the first waveform data, further includes:
[0092] S41. Based on the first amplitude modulation data, generate a first control signal and a second control signal respectively; wherein, the first control signal is a clock cycle number adjustment and correction processing control signal; and the second control signal is a clock cycle waveform phase adjustment and correction processing control signal.
[0093] Specifically, in this embodiment of the invention, existing testing methods do not systematically consider this issue. To overcome the testing rate bottleneck and solve the testing stability problem, it is necessary to start from three aspects: improving driving capability, improving signal quality, and overcoming the effects of delay. In-depth research on hardware and software is required to find solutions. Therefore, this invention proposes a boundary scan driving circuit, system, and method for improving testing rate, aiming to solve the above-mentioned technical deficiencies.
[0094] To address the issues of improving driving capability and signal quality, this invention provides a solution through a proposed driving circuit. The key focus is overcoming latency issues, considering two aspects: first, the inherent latency of the driving circuit itself; excessive delay in receiving the TDO at the FPGA end of the driving circuit may cause the first data bit, or even more bits, from the boundary scan chain to be missed on the rising edge of the TCK; second, the latency of the boundary scan chain itself, where data reading is completed on the rising edge of the TCK, therefore the rising edge of the TCK input to the link chip needs to maintain stable synchronization with the data input to the TDI of the link chip. To simultaneously address these two latency issues, this invention proposes a boundary scan driving circuit, a system, and a method for improving testing and speed.
[0095] like Figure 13 As shown, the host computer software includes a box for manually adjusting the number of TCK cycles. The minimum value for changing the number of TCK cycles is 0, and the maximum value is 5. When the number of TCK cycles is 0, the number of TCK cycles remains unchanged. When the number of TCK cycles is 1, the TCK is delayed by one cycle from the TDI and TDO data, and one clock cycle is added. When the number of TCK cycles is 2, the TCK is delayed by two cycles from the TDI and TDO data, and two clock cycles are added, and so on. The host computer software also includes a box for fine-tuning the TCK phase. If the FPGA's base frequency is set to 400MHz, the software... The TCK phase fine-tuning range is set to -2000ns to 2000ns. For JTAG-compatible TCK frequencies, fine-tuning is performed between 1MHz and 200MHz, with adjustment steps of 2.5ns. -2000ns to -2.5ns is set as lead fine-tuning, 0ns is the default state indicating no fine-tuning, and 2.5ns to 2000ns is set as lag fine-tuning. For test frequencies below 1MHz, the test rate is considered slow, and delay adjustment is not considered based on the drive circuit described in this invention. The data to be adjusted is input to the host computer. Before the boundary scan test, the host computer sends corresponding instructions to the FPGA to complete the configuration. These instructions are Instruction 1 and Instruction 2.
[0096] The specific implementation steps are as follows: From the moment the TCK signal is emitted until it enters the boundary scan chain, the delay between the TCK and TDI signals is basically synchronized. Based on this condition, the TCK, TDI, and TDO signals are brought out in the form of pin headers at the FPGA end of the driver circuit. After being brought out, they serve as measurement points for the waveform. By connecting an oscilloscope to this measurement point, the delay parameters of the waveform can be clearly observed, and the magnitude of the waveform delay can be obtained. Then, combined with the test frequency, the state of the waveform can be determined, and the values for changing the number of TCK cycles and fine-tuning the delay magnitude of the TCK phase can be extracted and input into the corresponding input box of the host computer. This allows the configuration to be completed before the boundary scan test. In other words, TCK and TMS are synchronous signals, so TMS is omitted. The delay can be considered as the delay between the initially issued TCK, TMS, or TDI and TDO. For simplicity, this invention omits the status signal TMS and uses only the clock signal TCK as a reference. The delay begins when TCK is issued by the FPGA. When TCK data is issued, it enters the boundary scan chain synchronously with TDI data. Since TCK and TDI enter the boundary scan chain synchronously, the acquisition of TDI data is normal under the action of the clock and the synchronous clock TCK. However, after the data is acquired, it shifts on the falling edge of the clock and returns to the TDO of the driver circuit. At this time, there is a certain delay between TDO and the initially issued TCK. If TDO is still read with reference to the initially issued TCK, the FPGA reading will be unstable or misaligned due to excessive delay or too high test frequency. This invention solves the reading problem of TDO return misalignment and reading stability problem, and improves the signal testing rate.
[0097] The delays of TDI and TDO are constant, which is an inherent characteristic of the drive circuit and boundary scan chain. In this invention, the relative positions of TDI and TDO remain unchanged, but TCK can be adjusted by lag according to the system clock at certain time intervals. Subsequent lead adjustment is a process of fine-tuning based on lag. The overall purpose of this invention is to lag TCK in order to find a stable position for TDO reading. As for misalignment, it can be correctly judged by the known number of misalignment bits, extract the correct reading data, and discard the data that is not of interest in order to achieve the purpose of correct high-speed testing.
[0098] For boundary scan chains, the rising edge of TCK needs to be positioned at a good point in the TDI data waveform, and not at the edge of the TDI data waveform, otherwise the boundary scan chain data acquisition will be unstable; the rising edge of TCK also needs to be positioned at a good point in the TDO data waveform, and not at the edge of the TDO data waveform, otherwise the data FPGA reading will also be unstable.
[0099] Always following the IEEE 1149 standard, data is acquired on the rising edge of the TCK clock and shifted on the falling edge. As long as the data acquisition on the rising edge is stable, the falling edge will correctly shift the data acquired in the previous acquisition into the boundary register.
[0100] By observing TCK and TDI, we can see that TCK and TDI are well synchronized at the initiating end. This synchronization also reflects the synchronization of entering the boundary scan chain.
[0101] By observing TCK and TDO, we can see the total delay between the sent and returned signals, which may cause the FPGA to read TDO incorrectly.
[0102] Specifically, the method for extracting the values of changing the number of TCK cycles and fine-tuning the delay of the TCK phase is as follows: Assuming the test frequency is f1, the clock cycle is 1 / f1. If the observed delay is t1, t1≤1 / (2*f1) (0.5 clock cycles), then the number of TCK cycles is set to 0. To achieve a more stable test state, the TCK phase lag is appropriately fine-tuned. The phase lag is fine-tuned to such a degree as... Figure 6 and Figure 9 The state shown indicates that the rising edge of TCK is adjusted to be in the middle of the interval formed by the TDI and TDO data ranges. Through derivation, the specific phase lag is t1 / 2. Specific examples are as follows: assuming the test frequency is 25MHz, its clock period is 40ns. If the observed delay is less than 20ns (half the clock period), then the TCK period count is set to 0. To achieve a more stable state, the TCK phase lag is fine-tuned appropriately. The phase lag is fine-tuned to... Figure 6 and Figure 9 The state shown is that the rising edge of TCK is adjusted to be in the middle of the interval formed by the TDI and TDO data intervals; specifically, if the observed delay is 13ns, 13ns < 20ns (half of the clock cycle), so the number of TCK cycles is changed to 0, and the hysteresis phase adjustment amount is: t1 / 2 = 6.5ns. Since the adjustment step is 2.5ns, the phase adjustment amount is set to 2.5*3 = 7.5ns, because it is closest to 6.5ns.
[0103] Assume the test frequency is f2, then the clock period is 1 / f2. If the observed delay is t2 and 1 / (2*f2) < t2 ≤ 3 / (2*f2), that is, t2 is greater than half a clock period and less than 1.5 clock periods, then set the number of changed TCK periods to 1. The TCK clock after changing the number of TCK periods to 1 lags behind the TCK clock with the number of changed TCK periods being 0 by one clock period, and an additional clock period is added based on the original. At this time, for the boundary scan chain, the first input data is a don't-care value, and this don't-care value is shifted out of the boundary register through the newly added last rising edge. Therefore, the data finally shifted into the boundary register is correct; since TCK lags behind TDI by one clock period based on the original, and the delay between TDI and TDO is fixed, the first bit of data of TDO can just be captured by the rising edge of the first TCK clock. Therefore, after the FPGA captures the data, removing the last don't-care value, the remaining values are all correct; as Figure 8 and Figure 9 、 Figure 11 and Figure 12 shown, by removing X1 and X2 through the above method, correct test data can be obtained, overcoming the influence of excessive delay or too high frequency on the test rate, and the test rate is significantly improved. After changing the number of TCK periods to 1 as above, it is only a rough adjustment result. Next, it is necessary to perform fine-tuning of the phase lead or lag of TCK on the waveform to improve the test stability.
[0104] The condition for phase lead fine-tuning is 1 / (2*f2) < t2 < 1 / f2, that is, between 0.5 and 1 TCK clock periods. The amount of phase lead fine-tuning is: 1 / 2*(t2 - 1 / f2). According to the above, the amount of phase lead fine-tuning is negative. When f2 = 1 / f2, in addition to changing the clock period of TCK, no fine-tuning is required, Figures 7 to 9 which shows the waveform diagrams before and after phase lead fine-tuning; the condition for phase lag fine-tuning is 1 / f2 < t2 < 3 / (2*f2), that is, between 1 and 1.5 TCK clock periods. The amount of phase lag fine-tuning is also: 1 / 2*(t2 - 1 / f2). According to the above, the amount of phase lag fine-tuning is positive. When f2 = 3 / (2*f2), in addition to changing the clock period of TCK, no fine-tuning is required, Figures 10 to 12 which shows the waveform diagrams before and after phase lag fine-tuning.
[0105] In addition, still assuming that the test frequency is 25 MHz, its clock period is 40 ns. If the observed delay is greater than 20 ns (0.5 clock cycles) and less than 40 ns (1 clock cycle), assuming the specific delay is 35 ns, first set the number of TCK cycle changes to 1 to complete a 1-cycle lag of TCK. To fine-tune to meet the condition of 1 / (2*f2) < t2 < 1 / f2, an advance fine-tuning is required. The fine-tuning amount is calculated by the formula 1 / 2*(t2 - 1 / f2), which is 2.5 ns, exactly one fine-tuning step as described above. Therefore, the host computer sets the lag fine-tuning to 2.5 ns. If the observed delay is greater than 40 ns (1 clock cycle) and less than 60 ns (1.5 clock cycles), assuming the specific delay is 48 ns, first set the number of TCK cycle changes to 1 to complete a 1-cycle lag of TCK. To fine-tune to meet the condition of 1 / f2 < t2 < 3 / (2*f2), a lag fine-tuning is required. The fine-tuning amount is calculated by the formula 1 / 2*(t2 - 1 / f2), which is -4 ns, closest to the two fine-tuning steps described above, i.e., -5 ns. Therefore, the host computer sets the lag fine-tuning to -5 ns. After setting the two parameters of changing the number of TCK cycles and fine-tuning the TCK phase through the host computer, the corresponding instructions will be sent to the FPGA to complete the corresponding TCK clock adjustment configuration and TCK cycle number configuration. The TDO data collected by the FPGA will be returned to the host computer. The host computer discards the values that are not concerned according to the instructions to be sent, and the remaining values are the correct ones.
[0106] The conditions of TCK and the status signal TMS of the present invention are synchronously adjusted. From a hardware perspective, their delays are the same. When adjusting TCK in the present invention, TMS is synchronously adjusted because the change of the JTAG state machine needs to be completed by combining TCK and TMS.
[0107] Combined with Figure 2As shown, the FPGA chip model is XC7Z020-2CLG484I. The chip's PL terminal has JTAG control signals, namely clock TCK, status signal TMS, transmit signal TDI, and receive signal TDO. The TCK, TMS, and TDI signals output at the PL terminal are at a 3.3V level. The GTL2014PW chip provides boost voltage, with a built-in comparator reference voltage of 0.8V and a power supply of 4.3V. The boosted signal levels of TCK_1, TMS_1, and TDI_1 are consistent with the GTL2014PW's power supply voltage of 4.3V. Since the signal quality after passing through the GTL2014PW is compared, a signal buck switch is introduced. The buck switch chip model is LSF0102DCUR, and the output high level depends on the voltage of Vref_A of the LSF0102DCUR. The voltage of _A is adjustable. Specifically, the I2C control DAC chip AD5667RBRMZ-1 at the PS end of the FPGA provides a voltage output from 1 to 3.3V. After the driving capability is boosted by an operational amplifier (OPA), it is given to Vref_A. The OPA model is LMV358A. The 4.3V level signal is stepped down by LSF0102DCUR to obtain TCK_2, TMS_2, and TDI_2 signals, which are at the level of Vref_A. After being output through the boundary scan test port, TCK_3, TMS_3, and TDI_3 are obtained and connected to the boundary scan chain. The TDO_2 output from the boundary scan test chain is connected to TDO_1 at the boundary scan test port. After being converted by a comparator, it returns to the PL end of the FPGA via TDO, which is compatible with voltage boosting from 1V to 3V. The comparator model is LTV3603.
[0108] The GTL2014PW boosts the standard 3.3V to 4.3V, then steps it down to 1V to 3.3V, flexibly meeting the 1V to 3.3V level requirements of the test chain. The signal drive current capability is primarily provided by the GTL2014PW chip; boosting to 4.3V and then stepping it down by the LSF0102DCUR chip can meet a minimum drive current requirement of 32mA. The AD5667RBRMZ-1 provides flexible output from 1V to 3.3V, allowing for flexible setting of the boundary scan test port level, compatible with test chains of different levels. The comparator TLV3603 converts the arbitrary 1V to 3.3V level of TDO_2 returned from the boundary scan chain into a standard 3.3V level before returning it to the FPGA's TDO. The LSF0102DCUR step-down signal chip improves signal quality; the combination of the GTL2014PW and LSF0102DCUR satisfies both drive capability requirements and significantly improves signal quality.
[0109] The chips related to the drive circuit and delay include GTL2014PW, LSF0102DCUR, and TLV3603. Among them, the delay of GTL2014PW chip is about 5.2ns, the delay of LSF0102DCUR is about 1ns, and the delay of TLV3603 is about 2.5ns. All of them are inexpensive chips with low delay.
[0110] Combination Figure 2 and Figure 3 As shown, Figure 3 It is by Figure 2 The boundary scan delay model extracted from the boundary scan driver circuit is as follows: delays T1.1, T2.1, and T3.1 represent the delays between TCK, TMS, and TDI signals and TCK_1, TMS_1, and TDI_1 signals, respectively; delays T1.2, T2.2, and T3.2 represent the delays between TCK_1, TMS_1, and TDI_1 signals and TCK_2, TMS_2, and TDI_2 signals, respectively; and delay T4.1 represents the delay between TDO_1 and TDO signals, respectively. In addition, before the boundary scan chains TCK_3, TMS_3, TDI_3, and TDO_2 are connected, they will pass through a certain length of leads and may be connected to signal driving chips, thus generating a certain delay. The delays of TCK_3, TMS_3, TDI_3, and TDO_2 when connected to the boundary scan chain are T1.3, T2.3, T3.3, and T4.2, respectively. The above delays include both chip delays and circuit path delays.
[0111] Combination Figure 3 and Figure 4 As shown, assuming Figure 3 With all delays set to 0, the waveform of the JTAG signal output by the FPGA will be an ideal waveform, such as... Figure 4 As shown, when the rising edge of TCK0 arrives, the rising edge is located in the middle of the TDI and TDO data waveforms. At this time, the data collected by the boundary scan chain register at the rising edge of the clock is the most stable. The data returned to the FPGA chip through TDO will also be collected through the rising edge of TCK0, and the collected data is also the most stable.
[0112] Combination Figure 4 and Figure 5 As shown, the delay of the driving circuit of this invention is fixed, and the delay of a specific boundary scan chain is also fixed. Therefore, the delay between TDI and TDO is fixed. Figure 4 and Figure 5 As shown, Figure 5 TDO and Figure 4 Compared to TDO, it introduces a certain delay. Figure 5 The rising edge of TCK1, the data of TDI and Figure 4 Similarly, in the middle of the TDI data waveform, the acquisition of TDI data at the rising edge of TCK1 in the boundary scan chain is stable. Then, the rising edge of TCK1 operates at the critical edge of TDO data change. The FPGA still acquires data through the rising edge of TCK1. Therefore, the TDO data removed from the boundary scan chain is unstable when received by the FPGA.
[0113] Combination Figure 5 and Figure 6 As shown, in order to solve Figure 5 The critical instability problem requires that... Figure 5 By sending the TCK1 waveform with a slight delay to obtain TCK2, the rising edge of TCK1 can be corrected to avoid it being at the critical edge of TDO data change, thus maintaining a relatively stable TDO data acquisition state for the FPGA. Furthermore, the correction magnitude should not be too large, as TDI data acquisition also needs to refer to TCK2. The stability of both the FPGA and the boundary scan chain acquisition must be considered. A compromise is made to ensure that both are in a relatively stable data acquisition state, and both can guarantee at least 1 / 4 of a clock cycle away from the critical edge, thereby ensuring the stability of test data acquisition and shifting.
[0114] Combination Figures 4 to 7 As shown, Figure 7 Excessive delay or excessively high test frequency caused a one-bit misalignment in the TDO data transmission. Specifically, the TDO data was collected at the rising edge of TCK3 with one bit of error.
[0115] Combination Figure 7 and Figure 8 As shown, in order to solve Figure 7 The misalignment problem Figure 8 The waveform in Figure 7 Based on this, the following steps were taken: relative to Figure 7TCK3 and TCK4 are sent with a one-cycle delay, and an additional cycle is added. The 9-bit data of the boundary scan chain is input from TDI. Under the action of clock TCK4, the first bit shifted in is X1, which is irrelevant data. After the last bit, the 9th bit, is shifted in, the first bit is irrelevant data and will be shifted out of the boundary scan register. Since the length of the boundary register cell is only 8, the result of data entering the boundary register is the same. Because TCK4 is sent with a one-cycle delay, and TDO is shifted out by one cycle due to the delay, the final TDO data can be acquired through the clock of TCK4. However, the last bit acquired, X2, is irrelevant data. The FPGA will send the acquired TDO data to the host computer, and the host computer will discard the X2 data to obtain the correct test data. This solves the problem of misalignment due to too much delay or too high frequency. The above is the case of handling a 1-bit misalignment. If the misalignment is 2 bits, the method described above is still the same, except that the irrelevant data of TDI and TDO increases by 1 bit, and so on.
[0116] Combination Figure 6 , Figure 8 and Figure 9 As shown, Figure 8 As can be seen, the data acquisition position is not at the optimal position of the TCK4 rising edge, so fine-tuning is required. The adjustment type is TCK4 phase lead fine-tuning. The stability of both FPGA and boundary scan chain acquisition must be considered, and a compromise is made to ensure that both are in a relatively stable data acquisition state. That is, the rising edge of TCK4 is adjusted to be in the middle of the interval formed by the TDI and TDO data intervals. Figure 9 TCK5, the interval is as follows Figure 9 In order to ensure the stability of data acquisition, all intervals in this invention are considered to be no less than 1 / 2 clock cycle, so the state of the rising edge acquisition is in a relatively stable state.
[0117] Combination Figures 4 to 7 and Figure 10 As shown, Figure 10 Excessive latency or excessively high testing frequency caused a one-bit misalignment in the TDO data transmission. Specifically, at the rising edge of TCK6, the TDO data was acquired with one bit off. Figure 7 The difference is that, Figure 7 The latency is between 0.5 and 1 TCK clock cycle, while Figure 10 The latency is even more severe, ranging from 1 to 1.5 TCK clock cycles.
[0118] Combination Figure 10 and Figure 11 As shown, in order to solve Figure 10 The misalignment problem Figure 11 The waveform in Figure 10 Based on this, the following steps were taken: relative to Figure 10 TCK6 and TCK7 are sent with a one-cycle delay, and an additional cycle is added. The 9-bit data of the boundary scan chain is input from TDI. Under the action of clock TCK7, the first bit shifted in is X1, which is irrelevant data. After the last bit, the 9th bit, is shifted in, the first bit is irrelevant data and will be shifted out of the boundary scan register. Since the length of the boundary register cell is only 8, the result of data entering the boundary register is the same. Because TCK7 is sent with a one-cycle delay, and TDO is shifted out by one cycle due to the delay, the final TDO data can be acquired through the clock of TCK7. However, the last bit acquired, X2, is irrelevant data. The FPGA will send the acquired TDO data to the host computer, and the host computer will discard the X2 data to obtain the correct test data. This solves the problem of misalignment due to too much delay or too high frequency. The above is the case of handling a 1-bit misalignment. If the misalignment is 2 bits, the method described above is still the same, except that the irrelevant data of TDI and TDO increases by 1 bit, and so on.
[0119] Combination Figure 11 and Figure 12 As shown, Figure 11 As can be seen, the data acquisition position is not at the optimal position of the TCK7 rising edge, so fine-tuning is required. The adjustment type is TCK7 phase lag fine-tuning. The stability of both FPGA and boundary scan chain acquisition must be considered, and a compromise is made to ensure that both are in a relatively stable data acquisition state. That is, the rising edge of TCK7 is adjusted to be in the middle of the interval formed by the TDI and TDO data intervals. Figure 12 TCK8, the interval is as follows Figure 12 In interval 2, to ensure the stability of data acquisition, all intervals in this invention are considered to be no less than 1 / 2 clock cycle, so the state of the rising edge acquisition is in a relatively stable state.
[0120] The imported data corresponds one-to-one with the waveforms of this invention. Figure 14 The order of data shifting into and out of the boundary register is clearly visible. This embodiment only lists an 8-bit length to clearly demonstrate the entire process of the invention; however, the actual length of the boundary register in a boundary scan chip is far greater than 8 bits.
[0121] Figure 15This demonstrates the case where data with a one-bit misalignment passes through the boundary register. X1 enters the boundary register unit first, followed by the next 8 bits. After a data segment is sent, the unimportant data X1 is shifted out, ensuring that the configuration remains the same and guaranteeing the correctness of the TDI input boundary scan chain data. After the shifted-out data is acquired by the host computer, the unimportant data X2 is discarded, leaving only the correct data, thus ensuring the correctness of the boundary scan chain output TDO data acquisition.
[0122] To achieve the above objectives, the present invention also provides a data delay control system for boundary scan testing, wherein the system is applied to the aforementioned data delay control method, such as... Figure 16 As shown, the system includes:
[0123] A first data generation unit is used to acquire first input data corresponding to the boundary scan test operation in real time, and generate first waveform data corresponding to the first input data; wherein, the first input data is test operation input control signal data; the first waveform data is waveform state data; a second data generation unit is used to generate first delay data corresponding to the first waveform data based on the first waveform data; wherein, the first delay data is the actual delay data of the waveform; a creation generation unit is used to create a boundary scan delay model, and generate corresponding first amplitude modulation data based on the boundary scan delay model, combined with the first waveform data and the first delay data; a correction processing unit is used to correct and process the first waveform data in real time based on the first amplitude modulation data, and generate second waveform data corresponding to the first waveform data; wherein, the second waveform data is the waveform state after correction processing.
[0124] The second data generation unit further includes: a first data generation module, used to generate delay parameter data corresponding to the first waveform data based on the first waveform data; and a first determination generation module, used to acquire frequency data corresponding to the first waveform data, determine and generate real-time waveform status data corresponding to the frequency data.
[0125] The test operation input control signal data is presented in the form of a pin header; the signal data includes clock data, status signal data, and transmission signal data; the first waveform data is the waveform status data before entering the boundary scan chain; the second waveform data is the waveform status data before entering the boundary scan chain and after correction processing; the first amplitude modulation data includes clock cycle number amplitude modulation data and clock waveform phase amplitude modulation data;
[0126] And / or, the creation and generation unit further includes: a second determination and generation module, configured to acquire first delay data, determine a first numerical relationship between the first delay data and clock cycle quantity data, and generate clock cycle quantity amplitude modulation data corresponding to the first numerical relationship; and a first fine-tuning processing module, configured to perform real-time lag phase fine-tuning processing on the clock cycle quantity data based on the clock cycle quantity amplitude modulation data.
[0127] And / or, the creation and generation unit further includes: a third determination and generation module, used to acquire first delay data, determine a second numerical relationship between the first delay data and clock waveform phase data, and generate clock waveform phase amplitude modulation data corresponding to the second numerical relationship; and a second fine-tuning processing module, used to perform real-time phase lag fine-tuning processing or phase lead fine-tuning processing of the clock waveform phase data according to the clock waveform phase amplitude modulation data.
[0128] The boundary scan delay model includes a boundary scan driving circuit; the circuit includes a first control chip; the PS terminal of the first control chip is connected to the input terminal of the first digital-to-analog converter.
[0129] The output terminal of the first digital-to-analog converter is connected to the positive input terminal of the first comparator; the output terminal of the first comparator is connected to the negative input terminal of the first comparator and the Vref_A pin of the third control chip; the PL terminal of the first control chip is connected to the B0, B1, and B2 pins of the second control chip in sequence; the A0, A1, and A2 pins of the second control chip are connected to the B1, B2, and B3 pins of the third control chip in sequence; the A1, A2, and A3 pins of the third control chip are connected to one side of the boundary scan test port signal terminal in sequence; the other side of the boundary scan test port signal terminal is connected to the boundary scan test chain.
[0130] The data output interface of the boundary scan test chain is connected to the data output interface of the boundary scan test port; the data output interface of the boundary scan test port is connected to the positive input terminal of the second comparator; the output terminal of the second comparator is connected to the signal receiving interface of the PL terminal in the first control chip.
[0131] And / or, the correction processing unit further includes: a second data generation module, configured to generate a first control signal and a second control signal based on the first amplitude modulation data; wherein the first control signal is a clock cycle number adjustment correction processing control signal; and the second control signal is a clock cycle waveform phase adjustment correction processing control signal.
[0132] In the system embodiment of the present invention, the specific details of the method steps involved in the data delay control for boundary scan testing have been described above. That is to say, the functional modules in the system are used to implement the steps or sub-steps in the above method embodiment, which will not be repeated here.
[0133] To achieve the above objectives, the present invention also provides a data delay control platform for boundary scan testing, such as... Figure 17 As shown, it includes a processor, a memory, and a data delay control platform control program for boundary scan testing; wherein, the processor executes the data delay control platform control program for boundary scan testing, and the data delay control platform control program for boundary scan testing is stored in the memory; the data delay control platform control program for boundary scan testing implements the steps of the data delay control method for boundary scan testing. For example:
[0134] S1. Acquire first input data corresponding to the boundary scan test operation in real time, and generate first waveform data corresponding to the first input data; wherein, the first input data is test operation input control signal data; the first waveform data is waveform state data; S2. Generate first delay data corresponding to the first waveform data based on the first waveform data; wherein, the first delay data is the actual delay data of the waveform; S3. Create a boundary scan delay model, and generate corresponding first amplitude modulation data based on the boundary scan delay model, combined with the first waveform data and the first delay data; S4. Correct and process the first waveform data in real time based on the first amplitude modulation data, and generate second waveform data corresponding to the first waveform data; wherein, the second waveform data is the corrected waveform state. The specific details of these steps have been described above and will not be repeated here.
[0135] In this embodiment of the invention, the data delay control platform for boundary scan testing has a built-in processor that can be composed of integrated circuits. For example, it can be composed of a single packaged integrated circuit, or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor connects to various components using various interfaces and lines, and executes programs or units stored in memory, as well as calling data stored in memory, to perform various functions for data delay control and data processing for boundary scan testing.
[0136] The memory is used to store program code and various data. It is installed in the data delay control platform used for boundary scan testing and enables high-speed and automatic access to programs or data during operation.
[0137] The memory includes read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.
[0138] This invention provides a method for real-time acquisition of first input data corresponding to a boundary scan test operation, and generation of first waveform data corresponding to the first input data. The first input data is test operation input control signal data; the first waveform data is waveform state data. Based on the first waveform data, first delay data corresponding to the first waveform data is generated; the first delay data is the actual delay data of the waveform. A boundary scan delay model is created, and based on the boundary scan delay model, combined with the first waveform data and the first delay data, corresponding first amplitude modulation data is generated. Based on the first amplitude modulation data, the first waveform data is corrected and processed in real-time, and second waveform data corresponding to the first waveform data is generated; the second waveform data is the corrected waveform state. A corresponding system and platform, combined with a driving circuit, provide reliable signal driving capability and signal quality. This overcomes signal delay problems through coarse adjustment and improves signal stability through fine adjustment, thereby increasing the test rate.
[0139] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A data delay control method for boundary scan testing, characterized in that, The method includes the following steps: The system acquires first input data corresponding to the boundary scan test operation in real time and generates first waveform data corresponding to the first input data; wherein, the first input data is test operation input control signal data; and the first waveform data is waveform state data. Based on the first waveform data, first delay data corresponding to the first waveform data is generated; wherein, the first delay data is the actual delay data of the waveform; A boundary scan delay model is created, and based on the boundary scan delay model, combined with the first waveform data and the first delay data, corresponding first amplitude modulation data is generated; this further includes: acquiring the first delay data, determining a first numerical relationship between the first delay data and clock cycle quantity data, and generating clock cycle quantity amplitude modulation data corresponding to the first numerical relationship; performing real-time lag phase fine-tuning processing on the clock cycle quantity data based on the clock cycle quantity amplitude modulation data; acquiring the first delay data, determining a second numerical relationship between the first delay data and clock waveform phase data, and generating clock waveform phase amplitude modulation data corresponding to the second numerical relationship; performing real-time phase lag fine-tuning processing or phase lead fine-tuning processing on the clock waveform phase data based on the clock waveform phase amplitude modulation data; Based on the first amplitude modulation data, the first waveform data is corrected and processed in real time, and a second waveform data corresponding to the first waveform data is generated; wherein, the second waveform data is the waveform state after correction and processing.
2. The data delay control method for boundary scan testing according to claim 1, characterized in that, The step of generating first delay data corresponding to the first waveform data based on the first waveform data further includes: Based on the first waveform data, generate delay parameter data corresponding to the first waveform data; Obtain frequency data corresponding to the first waveform data, determine and generate real-time waveform status data corresponding to the frequency data.
3. A data delay control method for boundary scan testing according to claim 1 or 2, characterized in that, The test operation input control signal data is presented in the form of a pin header; the signal data includes clock data, status signal data, and transmission signal data. The first waveform data is the waveform state data before entering the boundary scan chain; the second waveform data is the waveform state data before entering the boundary scan chain and after correction processing. The first amplitude modulation data includes clock cycle number amplitude modulation data and clock waveform phase amplitude modulation data.
4. The data delay control method for boundary scan testing according to claim 1, characterized in that, The boundary scan delay model includes a boundary scan drive circuit. The circuit includes a first control chip; the PS terminal of the first control chip is connected to the input terminal of the first digital-to-analog converter. The output terminal of the first digital-to-analog converter is connected to the positive input terminal of the first comparator; the output terminal of the first comparator is connected to the negative input terminal of the first comparator and the Vref_A pin of the third control chip, respectively. The PL terminal of the first control chip is sequentially connected to the B0, B1, and B2 pins of the second control chip; the A0, A1, and A2 pins of the second control chip are sequentially connected to the B1, B2, and B3 pins of the third control chip; the A1, A2, and A3 pins of the third control chip are sequentially connected to one side of the boundary scan test port signal terminal; the other side of the boundary scan test port signal terminal is connected to the boundary scan test chain. The data output interface of the boundary scan test chain is connected to the data output interface of the boundary scan test port; the data output interface of the boundary scan test port is connected to the positive input terminal of the second comparator; the output terminal of the second comparator is connected to the signal receiving interface of the PL terminal in the first control chip.
5. The data delay control method for boundary scan testing according to claim 1, characterized in that, The step of real-time correction and processing of the first waveform data based on the first amplitude modulation data, and generating second waveform data corresponding to the first waveform data, further includes: Based on the first amplitude modulation data, a first control signal and a second control signal are generated respectively; wherein, the first control signal is a clock cycle number adjustment and correction processing control signal; and the second control signal is a clock cycle waveform phase adjustment and correction processing control signal.
6. A data delay control system for boundary scan testing, characterized in that, The system is applied to the data delay control method according to any one of claims 1-5, and the system comprises: The first data generation unit is used to acquire first input data corresponding to the boundary scan test operation in real time, and generate first waveform data corresponding to the first input data; wherein, the first input data is test operation input control signal data; and the first waveform data is waveform state data. The second data generation unit is used to generate first delay data corresponding to the first waveform data based on the first waveform data; wherein, the first delay data is the actual delay data of the waveform; A generation unit is created to create a boundary scan delay model and, based on the boundary scan delay model, the first waveform data and the first delay data, generate corresponding first amplitude modulation data. The correction processing unit is used to correct the first waveform data in real time based on the first amplitude modulation data, and generate second waveform data corresponding to the first waveform data; wherein the second waveform data is the waveform state after correction processing.
7. A data delay control system for boundary scan testing according to claim 6, characterized in that, The second data generation unit further includes: The first data generation module is used to generate delay parameter data corresponding to the first waveform data based on the first waveform data. The first determination and generation module is used to acquire frequency data corresponding to the first waveform data, determine and generate real-time waveform status data corresponding to the frequency data; The test operation input control signal data is presented in the form of a pin header; the signal data includes clock data, status signal data, and transmission signal data. The first waveform data is the waveform state data before entering the boundary scan chain; the second waveform data is the waveform state data before entering the boundary scan chain and after correction processing. The first amplitude modulation data includes clock cycle number amplitude modulation data and clock waveform phase amplitude modulation data; And / or, the creation and generation unit further includes: The second determination and generation module is used to acquire the first delay data, determine the first numerical relationship between the first delay data and the clock cycle number data, and generate clock cycle number amplitude modulation data corresponding to the first numerical relationship. The first fine-tuning processing module is used to perform real-time hysteresis phase fine-tuning processing on the clock cycle number data based on the clock cycle number amplitude modulation data. And / or, the creation and generation unit further includes: The third determination and generation module is used to acquire the first delay data, determine the second numerical relationship between the first delay data and the clock waveform phase data, and generate clock waveform phase amplitude modulation data corresponding to the second numerical relationship. The second fine-tuning processing module is used to perform real-time phase lag fine-tuning or phase lead fine-tuning of the clock waveform phase data based on the clock waveform phase amplitude modulation data. The boundary scan delay model includes a boundary scan drive circuit. The circuit includes a first control chip; the PS terminal of the first control chip is connected to the input terminal of the first digital-to-analog converter. The output terminal of the first digital-to-analog converter is connected to the positive input terminal of the first comparator; the output terminal of the first comparator is connected to the negative input terminal of the first comparator and the Vref_A pin of the third control chip, respectively. The PL terminal of the first control chip is sequentially connected to the B0, B1, and B2 pins of the second control chip; the A0, A1, and A2 pins of the second control chip are sequentially connected to the B1, B2, and B3 pins of the third control chip; the A1, A2, and A3 pins of the third control chip are sequentially connected to one side of the boundary scan test port signal terminal; the other side of the boundary scan test port signal terminal is connected to the boundary scan test chain. The data output interface of the boundary scan test chain is connected to the data output interface of the boundary scan test port; the data output interface of the boundary scan test port is connected to the positive input terminal of the second comparator; the output terminal of the second comparator is connected to the signal receiving interface of the PL terminal in the first control chip. And / or, the correction processing unit further includes: The second data generation module is used to generate a first control signal and a second control signal based on the first amplitude modulation data; wherein the first control signal is a clock cycle number adjustment correction processing control signal; and the second control signal is a clock cycle waveform phase adjustment correction processing control signal.
8. A data delay control platform for boundary scan testing, characterized in that, The system includes a processor, a memory, and a data delay control platform control program for boundary scan testing; wherein the processor executes the data delay control platform control program for boundary scan testing, the data delay control platform control program for boundary scan testing is stored in the memory, and the data delay control platform control program for boundary scan testing implements the data delay control method for boundary scan testing as described in any one of claims 1 to 5.