An op-amp-free low-power reference circuit

Abstract

This invention belongs to the field of electronic circuit technology, specifically disclosing a low-power reference circuit without an operational amplifier. It includes: MOSFETs MN1, MN2, MN3, MN4, MN5, and MN6; MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, and MP9; resistors R1, R2, R3, R4, R5, R6, R7, and R8; and transistors Q1 and Q2 and their connections. This invention utilizes the current-voltage relationship of the MOSFETs, using a current mirror to make the currents of the two NMOS transistors in the circuit equal, thereby obtaining two equal source voltages. That is, it can obtain ΔV without an operational amplifier. BE This generates an accurate reference voltage, greatly reducing circuit power consumption.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a low-power reference circuit without operational amplifiers. Background Technology

[0002] Reference voltage generation circuits are present in almost every analog and mixed-signal chip, providing a precise and reliable reference voltage for the system. Therefore, the performance of the reference circuit largely determines the system's performance. The system needs a precise reference voltage over a wide temperature range, which requires the reference voltage generated by the reference circuit to be temperature-insensitive; that is, the magnitude of the reference voltage should remain constant or change very little as the temperature changes. Most reference circuits use BJT-based bandgap references, where the voltage between the base and emitter of the BJT transistor... BE Voltage has a negative temperature coefficient characteristic. According to the collector current formula of a BJT transistor:

[0003]

[0004] Among them, I S It is the saturation current of the BJT transistor, V T =k B T / q is the thermal voltage, k B This is Boltzmann's constant. From the above equation, we can see that if the currents of the two BJTs are different, then their V... BE The difference, i.e., ΔV BE It has a positive temperature coefficient.

[0005] like Figure 1 As shown, the two transistors are the same size but have different collector currents. From this, we can derive the following equation:

[0006]

[0007] From the above equation, we can know that △V BE It is a value that is directly proportional to temperature.

[0008] Using V BE and △V BE Theoretically, by adding these two voltages with opposite temperature coefficients in proportion, a zero-temperature coefficient reference voltage can be obtained.

[0009] Traditional bandgap reference circuits, such as Figure 2 As shown, M1 to M3 have the same width-to-length ratio, forming a current mirror structure that ensures the current flowing through M1 to M3 is equal, which in turn means the current flowing through Q1 to Q3 is equal. The feedback effect of the operational amplifier makes the voltages at points A and B equal. The number of transistors Q2 and Q3 is the same, both being n times the number of Q1. The voltage across resistor R1 is V1 of Q1 and Q2. BE The difference, from which the current of M2 can be obtained:

[0010] I = ΔV BE / R1=(V T ln n) / R1

[0011] Therefore, the reference voltage V can be obtained. REF The expression:

[0012] V REF =V BE3 +(V T ln n)(R2 / R1)

[0013] V BE and V T They have negative and positive temperature coefficients, respectively. By choosing appropriate values ​​for R1, R2, and n, V can be made... REF It becomes independent of temperature, resulting in a reference voltage with a near-zero temperature coefficient.

[0014] In traditional bandgap reference circuits, operational amplifiers (op-amps) are used to ensure that the voltages at points A and B are equal. However, high-gain op-amps inevitably increase circuit power consumption. For advanced electronic devices, miniaturization and low power consumption are development trends. Therefore, reference circuits using op-amps have relatively high power consumption, which is inconsistent with the trend of low power consumption.

[0015] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0016] The purpose of this invention is to solve the technical problems existing in the background art. To this end, an op-amp-free low-power reference circuit is provided.

[0017] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0018] An op-amp-free low-power reference circuit includes:

[0019] MOS tubes MN1, MN2, MN3, MN4, MN5 and MN6;

[0020] MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, and MP9;

[0021] Resistors R1, R2, R3, R4, R5, R6, R7, R8;

[0022] Transistors Q1 and Q2;

[0023] The gates of MOSFETs MN1 and MN2 are electrically connected, and the sources of MOSFETs MN1 and MN2 are both grounded.

[0024] One end of resistor R1 is connected to power supply VDDA, and the other end is electrically connected to the drain of MOSFET MN1 and connected to the line between the gates of MOSFETs MN1 and MN2.

[0025] The source of MOSFET MP1 is connected to power supply VDDA, and MOSFETs MP5 and MP6 are connected between the drain of MOSFET MP1 and the drain of MOSFET MN2.

[0026] The source of MOSFET MP2 is connected to power supply VDDA. The drain of MOSFET MP2 and the emitter of transistor Q1 are connected in sequence by MOSFET MP7, resistor R5, MOSFET MN5, MOSFET MN3, and resistor R2. The collector and base of transistor Q1 are grounded. One end of resistor R3 is connected to the line between MOSFET MN3 and resistor R2, and the other end is grounded.

[0027] The source of MOSFET MP3 is connected to power supply VDDA. MOSFET MP8, resistor R6, MOSFET MN6, and MOSFET MN4 are connected in sequence between the drain of MOSFET MP3 and the emitter of transistor Q2. The collector and base of transistor Q2 are grounded. One end of resistor R4 is connected to the line between MOSFET MN4 and the emitter of transistor Q2, and the other end is grounded.

[0028] The gates of MOSFET MN3, MOSFET MN4, and MOSFET MN6 are electrically connected; the gates of MOSFET MN5, MOSFET MN6, and MOSFET MN8 are electrically connected; the gates of MOSFET MN7, MOSFET MN8, and MOSFET MN5 are electrically connected; the drain of MOSFET MN7 is connected to the power supply VDDA.

[0029] The source of MOSFET MP4 is connected to power supply VDDA. MOSFET MP9 and resistor R7 are connected in sequence between the drain of MOSFET MP4 and one end of resistor R8. The other end of resistor R8 is grounded. The gate of MOSFET MP9 is electrically connected to the gate of MOSFET MN8.

[0030] The gates of MOSFETs MP1, MP2, MP3, and MP4 are electrically connected, and a reference voltage output point is provided in the line between resistors R7 and R8.

[0031] The following is a further defined technical solution of the present invention: MOS transistors MP2, MP3, and MP4 are Cascode current mirrors of the same size, and MOS transistors MP7, MP8, and MP9 are Cascode current mirrors of the same size.

[0032] The following is a further defined technical solution of the present invention, wherein resistors R5 and R6 have the same resistance value.

[0033] The following is a further defined technical solution of the present invention: MOS transistors MN3 and MN4 have the same size, and MOS transistors MN5 and MN6 have the same size.

[0034] The following is a further defined technical solution of the present invention, wherein the amplification factor between transistors Q1 and Q2 is n.

[0035] Compared with the prior art, the present invention has the following technical effects:

[0036] This invention utilizes the current-voltage relationship of MOS transistors and uses a current mirror to make the currents of the two NMOS transistors in the circuit equal, thereby obtaining two equal source voltages. This eliminates the need for an operational amplifier and allows for the generation of ΔV. BE This generates an accurate reference voltage, greatly reducing circuit power consumption.

[0037] The present invention will be further described below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a circuit diagram of a PTAT voltage generation circuit based on BJT in the existing technology;

[0040] Figure 2 This is a diagram of a bandgap reference circuit in the existing technology.

[0041] Figure 3 This is a circuit connection diagram of the present invention. Detailed Implementation

[0042] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0043] like Figure 3As shown, a low-power reference circuit without operational amplifiers is provided, which includes: MOSFETs MN1, MN2, MN3, MN4, MN5 and MN6; MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8 and MP9; resistors R1, R2, R3, R4, R5, R6, R7 and R8; and transistors Q1 and Q2.

[0044] The gates of MOSFETs MN1 and MN2 are electrically connected, and the sources of both MOSFETs MN1 and MN2 are grounded.

[0045] One end of resistor R1 is connected to power supply VDDA, and the other end is electrically connected to the drain of MOSFET MN1 and connected to the line between the gates of MOSFETs MN1 and MN2.

[0046] The source of MOSFET MP1 is connected to power supply VDDA, and MOSFETs MP5 and MP6 are connected between the drain of MOSFET MP1 and the drain of MOSFET MN2.

[0047] The source of MOSFET MP2 is connected to power supply VDDA. The drain of MOSFET MP2 and the emitter of transistor Q1 are connected in sequence by MOSFET MP7, resistor R5, MOSFET MN5, MOSFET MN3, and resistor R2. The collector and base of transistor Q1 are grounded. One end of resistor R3 is connected to the line between MOSFET MN3 and resistor R2, and the other end is grounded.

[0048] The source of MOSFET MP3 is connected to power supply VDDA. MOSFET MP8, resistor R6, MOSFET MN6, and MOSFET MN4 are connected in sequence between the drain of MOSFET MP3 and the emitter of transistor Q2. The collector and base of transistor Q2 are grounded. One end of resistor R4 is connected to the line between MOSFET MN4 and the emitter of transistor Q2, and the other end is grounded.

[0049] The gates of MOSFET MN3, MOSFET MN4, and MOSFET MN6 are electrically connected; the gates of MOSFET MN5, MOSFET MN6, and MOSFET MN8 are electrically connected; the gates of MOSFET MN7, MOSFET MN8, and MOSFET MN5 are electrically connected; the drain of MOSFET MN7 is connected to the power supply VDDA.

[0050] The source of MOSFET MP4 is connected to power supply VDDA. MOSFET MP9 and resistor R7 are connected in sequence between the drain of MOSFET MP4 and one end of resistor R8. The other end of resistor R8 is grounded. The gate of MOSFET MP9 is electrically connected to the gate of MOSFET MN8.

[0051] The gates of MOSFETs MP1, MP2, MP3, and MP4 are electrically connected, and a reference voltage output point is provided in the line between resistors R7 and R8.

[0052] MOSFETs MP2, MP3, and MP4 are Cascode current mirrors of the same size. MOSFETs MP7, MP8, and MP9 are also Cascode current mirrors of the same size. Resistors R5 and R6 have the same resistance value. MOSFETs MN3 and MN4 are the same size, and MOSFETs MN5 and MN6 are the same size. The ratio between transistors Q1 and Q2 is n.

[0053] When the power supply VDDA starts to rise from 0V, the voltage at the connection point between resistor R1 and MOSFET MN1 also begins to rise. When this voltage rises to near the threshold voltage of MOSFET MN1, MOSFET MN1 turns on, and current is generated in this branch. MOSFET MN2 acts as a current mirror, replicating the current on MOSFET MN1. Then, through current mirrors MOSFETs MP1, MP2, MP3, and MP4, each branch circuit starts to operate, generating a reference voltage.

[0054] Since current mirrors MP2, MP3, and MP4 are the same size, the current in the branch containing these three transistors is the same. Therefore, the current flowing through MOSFETs MN3 and MN4 is the same. If these two transistors operate in the saturation region, then according to the saturation region current formula:

[0055]

[0056] Where, μ n C is the carrier mobility of the NMOS transistor. ox W / L is the gate oxide thickness of the MOSFET, and W / L is the width-to-length ratio of the MOSFET. GS It is the gate-source voltage, V TH It is the threshold voltage.

[0057] MOSFETs MN3 and MN4 are identical in size, connected at their gates, and carry the same current; therefore, their source-terminal voltages are the same. From this, we can conclude that:

[0058] V BE2 =V BE1 +I 01 R2

[0059] Among them, I 01 This represents the current flowing through resistor R2 and transistor Q1.

[0060] From the above formula, we can obtain the current I in the branch containing transistor Q1. 01 =ΔV BE / R2.

[0061] The current in the branch containing MOSFETs MP2, MP3, and MP4, i.e., the current flowing through MOSFET MN3, is: I = I 01 +V BE / R3.

[0062] In summary, the reference voltage can be obtained:

[0063] V REF =I*R8=(ΔV BE / R2+V BE2 / R3)R8

[0064] V BE It has a negative temperature coefficient, ΔV BE It has a positive temperature coefficient. By adjusting the multiple n between transistors Q1 and Q2, as well as the resistance values ​​of R2, R3, and R4, a reference voltage with a near-zero temperature coefficient can be obtained.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present invention, or modify it into equivalent embodiments, without departing from the scope of the present invention's technical solution. Therefore, all equivalent changes made based on the shape, structure, and principle of the present invention without departing from the scope of the present invention's technical solution should be covered within the protection scope of the present invention.

Claims

1. A low-power reference circuit without operational amplifiers, characterized in that, include: MOS tubes MN1, MN2, MN3, MN4, MN5 and MN6; MOSFETs MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, and MP9; Resistors R1, R2, R3, R4, R5, R6, R7, R8; Transistors Q1 and Q2; The gates of MOSFETs MN1 and MN2 are electrically connected, and the sources of MOSFETs MN1 and MN2 are both grounded. One end of resistor R1 is connected to power supply VDDA, and the other end is electrically connected to the drain of MOSFET MN1 and connected to the line between the gates of MOSFETs MN1 and MN2. The source of MOSFET MP1 is connected to power supply VDDA, and MOSFETs MP5 and MP6 are connected between the drain of MOSFET MP1 and the drain of MOSFET MN2. The source of MOSFET MP2 is connected to power supply VDDA. The drain of MOSFET MP2 and the emitter of transistor Q1 are connected in sequence by MOSFET MP7, resistor R5, MOSFET MN5, MOSFET MN3, and resistor R2. The collector and base of transistor Q1 are grounded. One end of resistor R3 is connected to the line between MOSFET MN3 and resistor R2, and the other end is grounded. The source of MOSFET MP3 is connected to power supply VDDA. MOSFET MP8, resistor R6, MOSFET MN6, and MOSFET MN4 are connected in sequence between the drain of MOSFET MP3 and the emitter of transistor Q2. The collector and base of transistor Q2 are grounded. One end of resistor R4 is connected to the line between MOSFET MN4 and the emitter of transistor Q2, and the other end is grounded. The gates of MOSFET MN3, MOSFET MN4, and MOSFET MN6 are electrically connected; the gates of MOSFET MN5, MOSFET MN6, and MOSFET MP8 are electrically connected; the gates of MOSFET MP7, MOSFET MP8, and MOSFET MN5 are electrically connected; the drain of MOSFET MP7 is connected to power supply VDDA. The source of MOSFET MP4 is connected to power supply VDDA. MOSFET MP9 and resistor R7 are connected in sequence between the drain of MOSFET MP4 and one end of resistor R8. The other end of resistor R8 is grounded. The gate of MOSFET MP9 is electrically connected to the gate of MOSFET MP8. The gates of MOSFETs MP1, MP2, MP3, and MP4 are all electrically connected, and a reference voltage output point is provided in the line between resistors R7 and R8. When the power supply VDDA starts to rise from 0V, the voltage at the connection point between resistor R1 and MOSFET MN1 also starts to rise. When the voltage at this point rises to near the threshold voltage of MOSFET MN1, MOSFET MN1 turns on, and current is generated in the branch where MOSFET MN1 is located. MOSFET MN2 acts as a current mirror to replicate the current on MOSFET MN1, and then through MOSFETs MP1, MP2, MP3, and MP4, each branch circuit starts to work and generates a reference voltage; The current mirrors MP2, MP3, and MP4 are the same size, and the current in the branch containing the current mirrors MP2, MP3, and MP4 is the same. Since the current flowing through MOSFETs MN3 and MN4 is the same, and MOSFETs MN3 and MN4 are to operate in the saturation region, according to the current formula for the saturation region: ； in, It is the carrier mobility of the NMOS transistor. It refers to the gate oxide thickness of the MOSFET. It is the width-to-length ratio of the MOSFET. It is the gate-source voltage. It is the threshold voltage; MOSFETs MN3 and MN4 have the same dimensions, their gates are connected, and the current flowing through them is the same. Therefore, the source voltages of MOSFETs MN3 and MN4 are the same. ； in, This represents the current flowing through resistor R2 and transistor Q1; Obtain the current in the branch containing transistor Q1 ; The current in the branch containing MOSFETs MP2, MP3, and MP4, i.e., the current flowing through MOSFET MN3, is: ; Obtain the reference voltage: ； V BE2 It has a negative temperature coefficient, ΔV BE It has a positive temperature coefficient. By adjusting the multiple n between transistors Q1 and Q2, and the resistance values ​​of R2, R3, and R8, a reference voltage with a near-zero temperature coefficient can be obtained.

2. The op-amp-free low-power reference circuit according to claim 1, characterized in that, MOSFETs MP2, MP3, and MP4 are Cascode current mirrors of the same size, as are MOSFETs MP7, MP8, and MP9.

3. The op-amp-free low-power reference circuit according to claim 1, characterized in that, Resistors R5 and R6 have the same resistance value.

4. The op-amp-free low-power reference circuit according to claim 1, characterized in that, MOSFETs MN3 and MN4 have the same dimensions, and MOSFETs MN5 and MN6 have the same dimensions.

5. The op-amp-free low-power reference circuit according to claim 1, characterized in that, The amplification factor between transistors Q1 and Q2 is n.

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