A low-power LDO circuit applied to high power voltage

Abstract

The application relates to a low-power-consumption LDO circuit applied to a high power voltage, which comprises a zero-temperature-drift voltage generation module, a voltage conversion module, a reference voltage selection module and an LDO output module, wherein one end of the zero-temperature-drift voltage generation module is provided with a power supply VDD2, meanwhile, an output voltage signal VREF1 generated by the zero-temperature-drift voltage generation module is used as an input signal of the voltage conversion module; the power supply VDD2 output signal is also arranged at one end of the reference voltage selection module, meanwhile, a D1 adjusting resistor string RA is arranged in the reference voltage selection module; and output signals VREF2 and VREF3 generated by the reference voltage selection module are used as input signals of the voltage conversion module and the LDO output module respectively. The low-power-consumption LDO circuit can convert a high-voltage high-noise power supply into a low-noise power supply with an LDO output voltage as a chip global power supply voltage, thereby improving the stability of the overall structure work.

Description

Technical Field

[0001] This invention relates to integrated chip technology, and in particular to a low-power LDO circuit for use at high power supply voltages. Background Technology

[0002] In structures that use high-voltage, high-ripple power supplies such as batteries as chip power sources, in order to reduce the impact of noise from such power supplies on the chip, improve the stability of chip operation, and reduce the overall power consumption of the chip, it is necessary to design a way to convert such power supplies into a voltage output by an LDO structure as a global power supply. Summary of the Invention

[0003] To solve the above-mentioned technical problems, the present invention provides a low-power LDO circuit for high power supply voltage. The LDO circuit includes a zero-temperature drift voltage generation module, a voltage conversion module, a reference voltage selection module, and an LDO output module. The zero-temperature drift voltage generation module is provided with a power supply VDD2 at one end, which is generated and output by the voltage conversion module. At the same time, the output voltage signal VREF1 generated by the zero-temperature drift voltage generation module serves as the input signal of the voltage conversion module. Furthermore, the power supply VDD2 output signal is also located at one end of the reference voltage selection module. The reference voltage selection module has a control signal D1 to adjust the proportional coefficient of the resistor series RA, which is controlled by the chip's digital module. The output signals VREF2 and VREF3 generated by the reference voltage selection module serve as the input signals of the voltage conversion module and the LDO output module, respectively. The LDO output module has a power transistor stage with an input signal terminal VDD1, which is an externally supplied power supply voltage signal. It also generates an output voltage VLDO connected to the input signal of the voltage conversion module. The control module in the LDO output module generates a first, a second, and a third control signal. The first and third control signals serve as input control signals for the voltage conversion module, while the second control signal serves as the control signal for the reference voltage selection module.

[0004] In one embodiment of the present invention, the zero-temperature drift voltage generation module generates a zero-temperature drift current I0, and the current I0 is converted to generate an output voltage VREF1; the zero-temperature drift voltage generation module also includes transistors MP1, MP2, and MP3; their size ratio is 1:1:1, so the saturation currents flowing through transistors MN1, MN2, and MN3 are equal. .

[0005] In one embodiment of the present invention, the voltage conversion module includes transistor M1, transistor M2, operational amplifier AMP1, and operational amplifier AMP2; the source terminal of transistor M1 is connected to VDD1, and the gate terminal of transistor M1 is controlled by a first control signal, which determines the on / off state of the output of operational amplifier AMP1 and the gate terminal of transistor M1. At the same time, one end of the drain terminal of transistor M1 is connected to a resistor string composed of R3, R4, and R5, and serves as the output terminal of VDD2, while the other end of the resistor string composed of R3, R4, and R5 is grounded. The negative terminal of op-amp AMP1 is connected to the input signal VREF1, which is provided by the zero temperature drift voltage generation module. Under the control of the first control signal, the branch of VDD1 turns on transistor M1. The source terminal of transistor M2 is connected to VLDO. The gate terminal of transistor M2 is connected to the output of op-amp AMP2. The third control signal controls the on / off state of op-amp output and transistor M2. The drain terminal of M2 is connected to one end of resistor R5, and the other end of resistor R5 is grounded.

[0006] In one embodiment of the present invention, the negative terminal of operational amplifier AMP2 is connected to the input signal VREF2, while the positive terminal is connected to resistor R5 and the drain terminal of transistor M2; the negative feedback structure formed by power supply VDD1, transistor M1, the first control signal, AMP1, R3, R4, and R5 generates an output voltage. VREF1 is the output voltage generated by the zero-temperature drift voltage generation module; Similarly, the negative feedback structure formed by the power supply VLDO, transistor M2, the third control signal, AMP2, R4, and R5 generates the output voltage: VREF2 is the bandgap reference voltage generated by the reference voltage selection module.

[0007] In one embodiment of the present invention, the second control signal connected to the input terminal of the reference voltage selection module controls the output of the bandgap reference module voltage VREF2, and the resistor string RA generates the output voltage VREF3 under the control of the selection control signal D1. VREF2 is the zero-temperature-drift reference voltage generated by the bandgap reference module, RA is the total resistance of the resistor string, and DN1 is the scaling factor for voltage division of the resistor string.

[0008] In one embodiment of the present invention, the LDO output module includes a power transistor M3, an operational amplifier AMP3, and a control module; the source terminal of the power transistor M3 is connected to VDD1, and the gate terminal is connected to the output of the operational amplifier AMP3; the drain terminal of the power transistor M3 is connected to a resistor string composed of R6 and R7, and the other end of the resistor string composed of R6 and R7 is grounded; the negative polarity signal of the operational amplifier AMP3 is provided by VREF3 of the reference voltage selection module; the positive polarity terminal of the operational amplifier AMP3 is connected to one end of the resistor R7, and the other end of R7 is grounded; The input terminal of the control module is connected to a VLDO signal, and by sampling the VLDO signal, a first control signal, a second control signal, and a third control signal are obtained. These three control signals ensure the implementation of a low-power LDO structure applicable to high power supply voltage.

[0009] In one embodiment of the present invention, the negative feedback loop formed by voltage VDD1, transistor M3, operational amplifier AMP3, resistors R5 and R6 produces the output voltage: VREF2 is the zero-temperature-drift output voltage generated by the bandgap reference module. The proportional coefficient DN1 is a constant. The resistors RA, R6, and R7 are of the same type. The output voltage VLDO of all LDO output module structures is the zero-temperature-drift output voltage.

[0010] Compared with the prior art, the above-mentioned technical solution of the present invention has the following advantages: The low-power LDO circuit of the present invention realizes the conversion of high-voltage and high-noise power supply into low-noise LDO output voltage as the global power supply voltage of the chip, thereby improving the stability of the overall structure and reducing the overall power consumption. Attached Figure Description

[0011] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0012] Figure 1 This is a schematic diagram of the overall structure of the low-power LDO circuit applied to high power supply voltage according to the present invention.

[0013] Figure 2 This is a schematic diagram of the zero-temperature-drift voltage generation module described in this invention.

[0014] Figure 3 This is a schematic diagram of the voltage conversion module structure described in this invention.

[0015] Figure 4 This is a schematic diagram of the reference voltage selection module structure described in this invention.

[0016] Figure 5This is a schematic diagram of the LDO output module structure described in this invention. Detailed Implementation

[0017] like Figure 1 As shown, this embodiment provides a low-power LDO circuit for high power supply voltages, comprising four parts: a zero-temperature drift voltage generation module, a voltage conversion module, a reference voltage selection module, and an LDO output module. In the overall structure, the power supply voltage VDD1 can be a battery, button cell, etc., provided externally, serving as the power signal for high voltage and high ripple noise in the circuit structure. The zero-temperature drift voltage generation module's power supply VDD2 is provided by the voltage conversion module, and the generated output voltage signal VREF1 serves as the input signal to the voltage conversion module. VDD1 and VLDO serve as the power supply voltages for the voltage conversion module, with VREF1 and VREF2 provided by the zero-temperature drift voltage generation module and the reference voltage selection module, respectively. The first and second control signals are provided by the LDO output module, and the VDD2 output signal is provided to both the zero-temperature drift voltage generation module and the reference voltage selection module. In the reference voltage selection module, the VDD2 voltage is provided by the voltage conversion module, and the second control signal is provided by the LDO output module. The control signal D1 adjusts the proportional coefficient of the resistor series RA, controlled by the chip's digital module, generating output signals VREF2 and VREF3, which serve as the input signals to the voltage conversion module and the LDO output module, respectively. VDD1 serves as the input signal for the power transistor stage of the LDO output module. The VREF3 input signal is provided by the reference voltage selection module, generating the output voltage VLDO, which serves as the input signal for the voltage conversion module. The first and third control signals generated by the control module serve as the input control signals for the voltage conversion module, and the second control signal serves as the control signal for the reference voltage selection module. The overall structure converts the VDD1 power supply into a VLDO power supply through the voltage conversion module. VLDO is a low-noise, high-precision voltage generated by the LDO, thus realizing a low-power, low-noise LDO circuit structure applicable to high power supply voltages.

[0018] Figure 2 The schematic diagram of the zero-temperature-drift voltage generation module shows that the power supply voltage VDD2 is provided by the voltage conversion module. This module generates a zero-temperature-drift current I0, which is independent of the power supply voltage. This current I0 is then converted to produce the output voltage VREF1. Since the size ratio of transistors MP1, MP2, and MP3 is 1:1:1, the saturation currents flowing through transistors MN1, MN2, and MN3 are equal.

[0019] The magnitude of the current in the saturation region can be expressed as Transistors MN1 and MN2 have a size ratio of M:1. One end of the resistor string R1 and R2 is connected to the source terminal of transistor MN1, and the other end is grounded. The current flowing through the resistor string is... , The resistors R1 and R2 are selected with positive and negative temperature coefficients, respectively. By adjusting the values ​​of the number of resistors K1 and K2, R1 and R2 form a resistor string with zero temperature coefficient. Therefore, the first branch current I0 is the zero-temperature drift current. The size ratio of transistor MP4 to transistor MP1 is N:1, so the ratio of the current flowing through transistor MN4 to the current flowing through MN1 is... , The output of the zero-temperature drift voltage generation module is obtained. Where I0 is the zero-temperature drift current in the first branch of the zero-temperature drift voltage generation module. Here, the influence of temperature on the threshold voltage determined by the process is not considered. Therefore, the output voltage VREF1 of the zero-temperature drift voltage generation module is the zero-temperature drift voltage.

[0020] Figure 3 This is a schematic diagram of the voltage conversion module. VDD1 is an externally supplied high-ripple, high-noise high-voltage power supply, such as a lead-acid battery or button cell battery. The VDD1 power supply is connected to the source terminal of transistor M1 in the voltage conversion module. The gate terminal of transistor M1 is controlled by a first control signal, which determines the on / off state of the output of operational amplifier AMP1 and the gate terminal of transistor M1. The drain terminal of transistor M1 is connected to one end of a resistor string composed of R3, R4, and R5; this end also serves as the output terminal of VDD2. The other end of the resistor string is grounded. The negative input signal VREF1 of operational amplifier AMP1 is provided by a zero-temperature drift voltage generation module. Under the control of the first control signal, transistor M1 is turned on in the VDD1 branch. VLDO is the power supply voltage provided by the LDO output module. The VLDO signal is a stable power supply with low ripple and low noise. VLDO is connected to the source terminal of transistor M2, and the gate terminal of transistor M2 is connected to the output of operational amplifier AMP2. The third control signal controls the switching of the operational amplifier output and transistor M2. The drain terminal of the transistor is connected to one end of resistor R5, and the other end of resistor R5 is grounded. The negative input signal VREF2 of operational amplifier AMP2 is provided by the reference voltage selection module, and its positive terminal is connected to resistor R5 and the drain terminal of transistor M2. The negative feedback structure formed by power supply VDD1, transistor M1, the first control signal, AMP1, R3, R4, and R5 generates the output voltage. VREF1 is the output voltage generated by the zero-temperature drift voltage generation module. The negative feedback structure formed by the power supply VLDO, transistor M2, the third control signal, AMP2, R4, and R5 generates the output voltage. VREF2 is a bandgap reference voltage generated by the reference voltage selection module. VLDO is a low-ripple, low-noise voltage generated by the LDO. In the voltage conversion module, the first branch consists of the power supply voltage VDD1, transistor M1, the first control signal, operational amplifier AMP1, resistors R3, R4, and R5. The second branch consists of VLDO, transistor M2, the third control signal, operational amplifier AMP2, and resistor R5. These two branches are switched by the first and third control signals to obtain the output VDD2. The output VDD2 obtained by the loop formed by the second branch serves as the power supply voltage for other modules of the chip, featuring low ripple and low noise characteristics.

[0021] Figure 4 This is a schematic diagram of the reference voltage selection module, showing the power supply voltage VDD2, and a schematic diagram of the bandgap reference module used to generate the bandgap reference voltage. The second control signal controls the output of the bandgap reference module voltage VREF2. The resistor string RA, under the control of the selection control signal D1, generates the output voltage VREF3. VREF2 is the zero-temperature-drift reference voltage generated by the bandgap reference module, RA is the total resistance of the resistor string, and DN1 is the scaling factor for voltage division of the resistor string.

[0022] Figure 5 This is a schematic diagram of the LDO output module. The power supply voltage VDD1 is an externally provided high-voltage, high-noise signal, connected to the source terminal of power transistor M3. The gate terminal of power transistor M3 is connected to the output of operational amplifier AMP3. The drain terminal of power transistor M3 is connected to one end of a resistor string composed of R6 and R7, and the other end of the resistor string is grounded. The negative polarity signal of operational amplifier AMP3 is provided by VREF3 of the reference voltage selection module. The positive polarity terminal of operational amplifier AMP3 is connected to one end of resistor R7, and the other end of R7 is grounded. The negative feedback loop formed by voltage VDD1, transistor M3, operational amplifier AMP3, and resistors R5 and R6 produces the output voltage. , VREF2 is a zero-temperature-drift output voltage generated by the bandgap reference module, and the proportional coefficient DN1 is constant. Resistors RA, R6, and R7 are of the same type. Therefore, the output voltage VLDO of the entire LDO output module structure is a zero-temperature-drift output voltage. The VLDO voltage is provided to the voltage conversion module and other modules as a highly stable, low-noise power supply. Simultaneously, in the LDO output module, the VLDO signal also serves as the input to the control module. By sampling the VLDO signal, a first control signal, a second control signal, and a third control signal are obtained. These three control signals ensure the implementation of this low-power LDO structure applied to high power supply voltages. For example, when the VLDO voltage is very low, the three control signals can be implemented as follows: the first control signal turns on transistor M1, the second control signal turns on the VREF2 output, and the third control signal turns off transistor M2. Conversely, when the VLDO voltage reaches a set value, the three control signals can be implemented as follows: the first control signal turns off transistor M1, the second control signal turns on the VREF2 output, and the third control signal turns on transistor M2, thus realizing the operation of the entire loop.

[0023] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A low-power LDO circuit for use with high power supply voltage, characterized in that, The LDO circuit includes a zero-temperature drift voltage generation module, a voltage conversion module, a reference voltage selection module, and an LDO output module. The zero-temperature drift voltage generation module has a power supply VDD2 at one end, which is generated and output by the voltage conversion module. At the same time, the output voltage signal VREF1 generated by the zero-temperature drift voltage generation module serves as the input signal of the voltage conversion module. Furthermore, the power supply VDD2 output signal is also located at one end of the reference voltage selection module. The reference voltage selection module has a control signal D1 to adjust the proportional coefficient of the resistor series RA, which is controlled by the chip's digital module. The output signals VREF2 and VREF3 generated by the reference voltage selection module serve as the input signals of the voltage conversion module and the LDO output module, respectively. The LDO output module has a power transistor stage with an input signal terminal VDD1, which is an externally supplied power supply voltage signal; at the same time, it generates an output voltage VLDO connected to the input signal of the voltage conversion module. The control module in the LDO output module generates a first, a second, and a third control signal. The first and third control signals serve as input control signals for the voltage conversion module, and the second control signal serves as a control signal for the reference voltage selection module. The voltage conversion module includes transistor M1, transistor M2, operational amplifier AMP1, and operational amplifier AMP2. The source terminal of transistor M1 is connected to VDD1, and the gate terminal of transistor M1 is controlled by a first control signal. The first control signal determines the on / off state of the output of operational amplifier AMP1 and the gate terminal of transistor M1. At the same time, one end of the drain terminal of transistor M1 is connected to a resistor string composed of R3, R4, and R5, and serves as the output terminal of VDD2. The other end of the resistor string composed of R3, R4, and R5 is grounded. The negative terminal of operational amplifier AMP1 is connected to the input signal VREF1, which is provided by the zero temperature drift voltage generation module. Under the control of the first control signal, the branch of VDD1 turns on transistor M1. The source terminal of transistor M2 is connected to VLDO, and the gate terminal of transistor M2 is connected to the output of operational amplifier AMP2. The third control signal controls the switching of the operational amplifier output and transistor M2. The drain terminal of M2 is connected to one end of resistor R5, and the other end of resistor R5 is grounded. The input terminal of the control module is connected to a VLDO signal, and a first control signal, a second control signal, and a third control signal are obtained by sampling the VLDO signal. When the VLDO voltage is very low, the first control signal turns on transistor M1, the second control signal turns on the output of VREF2, and the third control signal turns off transistor M2. When the VLDO voltage reaches a set value, the first control signal turns off transistor M1, the second control signal turns on the output of VREF2, and the third control signal turns on transistor M2.

2. The low-power LDO circuit according to claim 1, characterized in that: The zero-temperature drift voltage generation module generates a zero-temperature drift current I0, and the current I0 is converted to generate an output voltage VREF1; the zero-temperature drift voltage generation module also includes transistors MP1, MP2 and MP3. If their size ratio is 1:1:1, then the saturation currents flowing through transistors MN1, MN2, and MN3 are equal. .

3. The low-power LDO circuit according to claim 1, characterized in that: The negative terminal of operational amplifier AMP2 is connected to the input signal VREF2, while its positive terminal is connected to resistor R5 and the drain terminal of transistor M2. The negative feedback structure formed by power supply VDD1, transistor M1, the first control signal, AMP1, R3, R4, and R5 generates the output voltage. ， VREF1 is the output voltage generated by the zero-temperature drift voltage generation module; Similarly, the negative feedback structure formed by the power supply VLDO, transistor M2, the third control signal, AMP2, R4, and R5 generates the output voltage: ， VREF2 is the bandgap reference voltage generated by the reference voltage selection module.

4. The low-power LDO circuit according to claim 1, characterized in that: The second control signal connected to the input terminal of the reference voltage selection module controls the output of the bandgap reference module voltage VREF2. Under the control of the selection control signal D1, the resistor string RA generates the output voltage VREF3. ， VREF2 is the zero-temperature-drift reference voltage generated by the bandgap reference module, RA is the total resistance of the resistor string, and DN1 is the scaling factor for voltage division of the resistor string.

5. The low-power LDO circuit according to claim 1, characterized in that: The LDO output module includes a power transistor M3, an operational amplifier AMP3, and a control module. The source terminal of the power transistor M3 is connected to VDD1, and its gate terminal is connected to the output of the operational amplifier AMP3. The drain terminal of the power transistor M3 is connected to a resistor string composed of R6 and R7, and the other end of the resistor string composed of R6 and R7 is grounded. The negative polarity signal of the operational amplifier AMP3 is provided by VREF3 of the reference voltage selection module. The positive polarity terminal of the operational amplifier AMP3 is connected to one end of the resistor R7, and the other end of R7 is grounded. The input terminal of the control module is connected to a VLDO signal, and by sampling the VLDO signal, a first control signal, a second control signal, and a third control signal are obtained. These three control signals ensure the implementation of a low-power LDO structure applicable to high power supply voltage.

6. The low-power LDO circuit according to claim 5, characterized in that: The negative feedback loop consisting of voltage VDD1, transistor M3, operational amplifier AMP3, resistors R5 and R6 produces the output voltage: ， VREF2 is the zero-temperature-drift output voltage generated by the bandgap reference module. The proportional coefficient DN1 is a constant. The resistors RA, R6, and R7 are of the same type. The output voltage VLDO of all LDO output module structures is the zero-temperature-drift output voltage.

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