Reference voltage generating circuit and radio frequency module comprising the same

Abstract

The application relates to a reference voltage generating circuit and a radio frequency module comprising the same. The reference voltage generating circuit comprises a bandgap reference module, the bandgap reference module being configured to generate a reference voltage; and a compensation current module, configured to output a compensation current to the bandgap reference core circuit according to a second positive temperature coefficient current and a second negative temperature coefficient current when a temperature is greater than a temperature threshold, wherein the compensation current is configured to compensate an influence of the temperature on the reference voltage output by the bandgap reference core circuit.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a reference voltage generating circuit and a radio frequency module including the same. Background Technology

[0002] The bandgap reference (BGR) is a fundamental module in very large-scale integrated circuits (VLSI) and many electronic systems. It is widely used in many analog, digital, or mixed-signal integrated circuits (ICs), such as analog-to-digital (A / D) converters, dynamic random access memory (DRAM), and flash memory control modules.

[0003] The principle of a bandgap reference is: the base-emitter voltage difference ΔV of a bipolar junction transistor (BJT). BE It has a positive temperature coefficient, and the base-emitter voltage V of the bipolar transistor BE Having a negative temperature coefficient, by adding two voltages, a voltage with a near-zero temperature coefficient can be achieved through appropriate parameter design. This reduces the influence of temperature on the reference voltage. The base-emitter voltage V of a bipolar transistor... BE The temperature-dependent variation of the BJT exhibits a certain nonlinearity, resulting in a curvature in the generated reference voltage. The first-order temperature-compensated BGR typically displays a temperature coefficient (TC) between 20 and 100 ppm / ℃. Since the BGR utilizes the nonlinearity of the TC in the base-emitter voltage of the BJT, its ability to further improve the TC is limited. Therefore, improving the TC of the BGR is a pressing issue that needs to be addressed. Summary of the Invention

[0004] In view of this, the present application provides a reference voltage generating circuit and an RF module including the present application to solve at least one problem existing in the prior art.

[0005] A first aspect of this application provides a reference voltage generating circuit, the reference voltage generating circuit comprising:

[0006] A bandgap reference module includes: a bandgap reference core circuit; the bandgap reference core circuit includes: a positive temperature coefficient voltage unit for generating a positive temperature coefficient voltage, and a negative temperature coefficient voltage unit for generating a negative temperature coefficient voltage, wherein the positive temperature coefficient voltage and the negative temperature coefficient voltage are used to generate a reference voltage; wherein the positive temperature coefficient voltage unit is used to directly generate the positive temperature coefficient voltage, or to generate the positive temperature coefficient voltage based on a first positive temperature coefficient current within the bandgap reference core circuit; the negative temperature coefficient voltage unit is used to directly generate the negative temperature coefficient voltage, or to generate the negative temperature coefficient voltage based on a first negative temperature coefficient current within the bandgap reference core circuit;

[0007] A compensation current module is used to output a compensation current to the bandgap reference core circuit when the temperature is greater than a temperature threshold, based on a second positive temperature coefficient current and a second negative temperature coefficient current. The compensation current is used to compensate for the effect of temperature on the reference voltage output by the bandgap reference core circuit. The second positive temperature coefficient current is associated with the first positive temperature coefficient current, or the second negative temperature coefficient current is associated with the first negative temperature coefficient current.

[0008] In some embodiments, the compensation current module includes:

[0009] The first current mirror unit is used to obtain the second positive temperature coefficient current;

[0010] The second current mirror unit is used to obtain the second negative temperature coefficient current; wherein, when the temperature is greater than the temperature threshold, the second positive temperature coefficient current is greater than the second negative temperature coefficient current.

[0011] A compensation current generation unit is used to output a compensation current, wherein the compensation current is the difference between the second positive temperature coefficient current and the second negative temperature coefficient current mirrored by the compensation current generation unit at a third ratio when the temperature is greater than the temperature threshold.

[0012] In some embodiments, the first current mirroring unit is used to mirror the first positive temperature coefficient current in the bandgap reference core circuit at a first ratio to obtain the second positive temperature coefficient current.

[0013] The second current mirroring unit is used to mirror the third negative temperature coefficient current according to the second ratio to obtain the second negative temperature coefficient current, wherein the third negative temperature coefficient current is generated by the current generation module in the reference voltage generation circuit, and the current generation module is different from the bandgap reference module.

[0014] In some embodiments, the first current mirror unit includes: a first PMOS transistor for replicating the first positive temperature coefficient current, and a current mirror composed of a first NMOS transistor and a second NMOS transistor for mirroring the replicated first positive temperature coefficient current according to the first ratio to obtain the second positive temperature coefficient current.

[0015] The second current mirror unit includes: a second PMOS transistor, used to mirror the third negative temperature coefficient current according to the second ratio to obtain the second negative temperature coefficient current;

[0016] The compensation current generation unit includes: a third PMOS transistor and a fourth PMOS transistor;

[0017] The third PMOS transistor and the second PMOS transistor are connected in parallel and then connected in series with the second NMOS transistor. The fourth PMOS transistor and the third PMOS transistor form a current mirror, which is used to mirror the difference between the second positive temperature coefficient current and the second negative temperature system current output by the third PMOS transistor according to the third ratio, and output the compensation current.

[0018] The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to a simulated positive voltage, while the sources of the first NMOS transistor and the second NMOS transistor are connected to a simulated negative voltage.

[0019] In some embodiments, the compensation current is expressed by the following expression:

[0020]

[0021] Wherein, β1 represents the first proportion, β2 represents the second proportion, and I PTAT I represents the first positive temperature coefficient current. CTAT The third negative temperature coefficient current is represented by T0, the temperature threshold is represented by N, and the third ratio is represented by N.

[0022] In some embodiments, the current generation module includes a negative temperature coefficient current generation unit, wherein the negative temperature coefficient current generation unit includes a first current mirror, a common source cascode current mirror, a first PNP bipolar junction transistor (BJT), and a first resistor.

[0023] The two current input terminals of the first current mirror are connected to simulated positive voltage, and the two current output terminals of the first current mirror are respectively connected to the two current input terminals of the common source cascode current mirror. The two current output terminals of the common source cascode current mirror are respectively connected to the first terminal of the first resistor and the emitter of the first PNP BJT. The second terminal of the first resistor, the base of the first PNP BJT, and the collector of the first PNP BJT are connected to simulated negative voltage. The second current mirror unit is used to mirror the third negative temperature coefficient current generated by the first current mirror.

[0024] In some embodiments, the first current mirror includes a fifth PMOS transistor and a sixth PMOS transistor; the common-source common-gate current mirror includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor.

[0025] The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the simulated positive voltage connection are connected.

[0026] The gate of the fifth PMOS transistor, the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor, and the gate of the second PMOS transistor are connected.

[0027] The drain of the third NMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the sixth PMOS transistor, and the gate of the third NMOS transistor, the gate of the fourth NMOS transistor, and the drain of the fifth PMOS transistor are connected.

[0028] The drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor, and the gates of the fifth NMOS transistor, the sixth NMOS transistor, and the third NMOS transistor are connected.

[0029] The source of the fifth NMOS transistor is connected to the emitter of the first PNP BJT, and the source of the sixth NMOS transistor is connected to the first end of the first resistor.

[0030] In some embodiments, the current generating module further includes: a first startup circuit for activating the negative temperature coefficient current generating unit.

[0031] The first startup circuit includes: a second resistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor;

[0032] The first terminal of the second resistor and the drain of the seventh NMOS transistor are connected to an analog positive voltage. The second terminal of the second resistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the drain of the eighth NMOS transistor, and the gate of the ninth NMOS transistor are connected. The source of the seventh NMOS transistor is connected to the drain of the fifth PMOS transistor.

[0033] The source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor;

[0034] The source of the ninth NMOS transistor is connected to a simulated negative voltage.

[0035] In some embodiments, the bandgap reference core circuit includes: a first operational amplifier, a first amplification unit, a positive temperature coefficient current generation unit, a positive temperature coefficient voltage unit, a negative temperature coefficient voltage unit, and a current biasing unit, wherein...

[0036] The positive temperature coefficient current generating unit includes a seventh PMOS transistor, an eighth PMOS transistor, a second PNP BJT, a third PNP BJT, and a third resistor;

[0037] The positive temperature coefficient voltage unit includes: a ninth PMOS transistor and a fourth resistor;

[0038] The negative temperature coefficient voltage unit includes: the fourth PNP BJT;

[0039] The current bias unit includes: the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, and the fourteenth NMOS transistor;

[0040] The first amplification unit includes: a thirteenth PMOS transistor, a fifteenth NMOS transistor, and a first capacitor;

[0041] The source of the seventh PMOS transistor, the source of the eighth PMOS transistor, the source of the ninth PMOS transistor, the source of the tenth PMOS transistor, the source of the eleventh PMOS transistor, the source of the twelfth PMOS transistor, and the simulated positive voltage connection are connected.

[0042] The source of the tenth NMOS transistor, the source of the eleventh NMOS transistor, the source of the fourteenth NMOS transistor, the source of the fifteenth NMOS transistor, the collector of the second PNP BJT, the base of the second PNP BJT, the collector of the third PNP BJT, the base of the third PNP BJT, the collector of the fourth PNP BJT, the base of the fourth PNP BJT, and the simulated negative voltage connection are connected.

[0043] The drain of the seventh PMOS transistor, the emitter of the second PNP BJT, and the negative input terminal of the first operational amplifier are connected.

[0044] The drain of the eighth PMOS transistor, the first end of the third resistor, and the positive input terminal of the first operational amplifier are connected. The second end of the third resistor is connected to the emitter of the third PNP BJT. A positive temperature coefficient current is generated between the drain and the source of the eighth PMOS transistor in the bandgap reference core circuit.

[0045] The drain of the tenth PMOS transistor, the drain of the tenth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected, and the drain of the eleventh NMOS transistor generates a bias current.

[0046] The drain of the eleventh NMOS transistor, the drain of the eleventh PMOS transistor, the gate of the eleventh PMOS transistor, and the gate of the twelfth PMOS transistor are connected.

[0047] The drain of the twelfth PMOS transistor, the drain of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor are connected. The source of the twelfth NMOS transistor and the drain of the thirteenth NMOS transistor are connected. The source of the thirteenth NMOS transistor and the drain of the fourteenth NMOS transistor are connected.

[0048] The gate of the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the first PMOS transistor, the drain of the fifteenth NMOS transistor, and the first terminal of the first capacitor are connected and used to input the startup voltage.

[0049] The output terminal of the first operational amplifier, the second terminal of the first capacitor, and the gate of the fifteenth NMOS transistor are connected.

[0050] The drain of the ninth PMOS transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the emitter of the fourth PNP BJT, and the first end of the fourth resistor is used to output the reference voltage.

[0051] In some embodiments, the first operational amplifier includes: a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor;

[0052] The source of the fourteenth PMOS transistor is connected to the simulated positive voltage.

[0053] The source of the eighteenth NMOS transistor and the source of the nineteenth NMOS transistor are connected to the simulated negative voltage.

[0054] The gate of the fourteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor to replicate the bias current;

[0055] The drain of the fourteenth PMOS transistor, the source of the fifteenth PMOS transistor, and the source of the sixteenth PMOS transistor are connected.

[0056] The gate of the fifteenth PMOS transistor is the positive input terminal of the first operational amplifier, and the gate of the sixteenth PMOS transistor is the negative input terminal of the first operational amplifier.

[0057] The drain of the fifteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor, the drain of the sixteenth PMOS transistor is connected to the source of the eighteenth PMOS transistor, and the gate of the seventeenth PMOS transistor is connected to the gate of the eighteenth PMOS transistor.

[0058] The drain of the seventeenth PMOS transistor, the drain of the sixteenth NMOS transistor, the gate of the eighteenth NMOS transistor, and the gate of the nineteenth NMOS transistor are connected.

[0059] The drain of the eighteenth PMOS transistor is connected to the drain of the seventeenth NMOS transistor and is used as the output terminal of the first operational amplifier.

[0060] The source of the sixteenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor, and the source of the seventeenth NMOS transistor is connected to the drain of the nineteenth NMOS transistor.

[0061] The gates of the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the twelfth NMOS transistor are connected.

[0062] In some embodiments, the first PNP BJT and the second PNP BJT have at least the same base-emitter voltage difference.

[0063] In some embodiments, the bandgap reference module includes: a second startup circuit for starting the bandgap reference core circuit, the second startup circuit including: a first inverter, a second inverter, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, and at least one of a twenty-fifth PMOS transistor and a twenty-third NMOS transistor;

[0064] The input terminal of the first inverter is used to input the first start-stop control signal; the output terminal of the first inverter is connected to the input terminal of the second inverter and is used to output the second start-stop control signal; the output terminal of the second inverter is used to output the third start-stop control signal.

[0065] The source of the nineteenth PMOS transistor, the source of the twenty-fourth PMOS transistor, the source of the twenty-fifth PMOS transistor, and the simulated positive voltage connection are connected.

[0066] The source of the twentieth NMOS transistor, the source of the twentieth NMOS transistor, the source of the twentieth NMOS transistor, and the simulated negative voltage connection are connected;

[0067] The gate and drain of the nineteenth PMOS transistor are connected to the source of the twentieth PMOS transistor; the gate and drain of the twentieth PMOS transistor are connected to the source of the twenty-first PMOS transistor; the gate and drain of the twenty-first PMOS transistor are connected to the source of the twenty-second PMOS transistor; the gate and drain of the twenty-second PMOS transistor are connected to the source of the twenty-third PMOS transistor.

[0068] The gate of the 23rd PMOS transistor is connected to the gate of the 20th NMOS transistor for inputting the reference voltage;

[0069] The drain of the 23rd PMOS transistor, the drain of the 20th NMOS transistor, and the gate of the 22nd NMOS transistor;

[0070] The gate of the 24th PMOS transistor is connected to the gate of the 21st NMOS transistor for inputting the second start / stop control signal;

[0071] The source of the 21st NMOS transistor and the drain of the 22nd NMOS transistor are connected; the drain of the 24th PMOS transistor and the drain of the 21st NMOS transistor are connected to output the startup voltage.

[0072] The gate of the 25th PMOS transistor is used to input the second start / stop control signal, and the drain of the 25th PMOS transistor is connected to the gate of the 11th PMOS transistor.

[0073] The gate of the 23rd NMOS transistor is used to input the third start / stop control signal, the drain of the 23rd NMOS transistor is connected to the reference voltage, and the source of the 23rd NMOS transistor is connected to the analog negative voltage.

[0074] The gate of the seventeenth PMOS transistor is used to input the third start / stop control signal.

[0075] In some embodiments, the compensation current is used to generate a compensated positive temperature coefficient voltage across a fourth resistor in conjunction with the first positive temperature coefficient current, and the compensated reference voltage includes the sum of the negative temperature coefficient voltage and the compensated positive temperature coefficient voltage.

[0076] A second aspect of this application provides a radio frequency module, the radio frequency module including the reference voltage generating circuit described in the first aspect.

[0077] According to an embodiment of this disclosure, the reference voltage generating circuit includes: a bandgap reference module, comprising: a bandgap reference core circuit; the bandgap reference core circuit includes: a positive temperature coefficient voltage unit for generating a positive temperature coefficient voltage, and a negative temperature coefficient voltage unit for generating a negative temperature coefficient voltage, wherein the positive temperature coefficient voltage and the negative temperature coefficient voltage are used to generate a reference voltage; wherein the positive temperature coefficient voltage unit is used to directly generate the positive temperature coefficient voltage, or to generate the positive temperature coefficient voltage based on a first positive temperature coefficient current within the bandgap reference core circuit; the negative temperature coefficient voltage unit is used to directly generate the negative temperature coefficient voltage, or to generate the negative temperature coefficient voltage based on a first negative temperature coefficient current within the bandgap reference core circuit; a compensation current module is used to output a compensation current to the bandgap reference core circuit when the temperature is greater than a temperature threshold, based on a second positive temperature coefficient current and a second negative temperature coefficient current, wherein the compensation current is used to compensate for the influence of temperature on the reference voltage output by the bandgap reference core circuit; wherein the second positive temperature coefficient current is associated with the first positive temperature coefficient current, or the second negative temperature coefficient current is associated with the first negative temperature coefficient current. In this way, by determining the compensation current through the second positive temperature coefficient current and the second negative temperature coefficient current, the reference voltage is compensated, thus realizing nonlinear compensation of the reference voltage and improving the accuracy of the output reference voltage of the bandgap reference module.

[0078] Additional aspects and advantages of the embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of this application. Attached Figure Description

[0079] The accompanying drawings, incorporated in and forming part of this specification, illustrate embodiments conforming to this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but rather to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. In the drawings:

[0080] Figure 1 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0081] Figure 2 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0082] Figure 3 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0083] Figure 4 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0084] Figure 5 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0085] Figure 6 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0086] Figure 7 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0087] Figure 8 This is a schematic diagram illustrating the composition of a reference voltage generating circuit according to an exemplary embodiment;

[0088] Figure 9 This is a schematic diagram of a reference voltage according to an exemplary embodiment;

[0089] Figure 10 This is a schematic diagram of a reference voltage according to an exemplary embodiment;

[0090] Figure 11This is a schematic diagram illustrating the composition structure of a radio frequency module according to an exemplary embodiment. Detailed Implementation

[0091] To make the technical solution and beneficial effects of the present invention more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application pertains.

[0092] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step in a particular embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, a solution after removing some steps in a particular embodiment can also be implemented as an independent embodiment, and the order of the steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined, for example, some or all steps of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments.

[0093] In each of the disclosed embodiments, unless otherwise specified or in case of logical conflict, the terminology and / or descriptions of the embodiments are consistent and can be referenced by each other. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0094] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0095] In this embodiment of the disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular expression or a plural expression.

[0096] In the embodiments disclosed herein, "multiple" refers to two or more.

[0097] In some embodiments, the terms “at least one of”, “one or more”, “a plurality of”, “multiple”, etc., may be used interchangeably.

[0098] In some embodiments, the notation "at least one of A and B", "A and / or B", "A in one case, B in another", "A in one case, B in another", etc., may include the following technical solutions depending on the situation: in some embodiments, A (A is executed regardless of B); in some embodiments, B (B is executed regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed); in some embodiments, A and B (both A and B are executed). The same applies when there are more branches such as A, B, C, etc.

[0099] In some embodiments, the notation "A or B" may include the following technical solutions, depending on the situation: in some embodiments, A (execution of A regardless of B); in some embodiments, B (execution of B regardless of A); in some embodiments, execution is selected from A and B (A and B are selectively executed). The same applies when there are more branches such as A, B, C, etc.

[0100] The prefixes "first," "second," etc., used in the embodiments of this disclosure are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, value, or content of the descriptive objects. The description of the descriptive objects should be found in the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, if the descriptive object is a "field," the ordinal numbers preceding "field" in "first field" and "second field" do not restrict the position or order of the "fields." "First" and "second" do not restrict whether the "fields" they modify are in the same message, nor do they restrict the order of "first field" and "second field." Similarly, if the descriptive object is a "level," the ordinal numbers preceding "level" in "first level" and "second level" do not restrict the priority between "levels." Furthermore, the value of the descriptive object is not limited by ordinal numbers and can be one or more. For example, in "first device," the value of "device" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the object being described is "device", then "first device" and "second device" can be the same device or different devices, and their types can be the same or different. Similarly, if the object being described is "information", then "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0101] In some embodiments, “including A,” “containing A,” “for indicating A,” and “carrying A” can be interpreted as directly carrying A or indirectly indicating A.

[0102] In some embodiments, terms such as “…”, “determine…”, “in the case of…”, “when…”, “when…”, “if…”, etc. can be used interchangeably.

[0103] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0104] In some embodiments, devices, etc., can be interpreted as physical or virtual, and their names are not limited to the names recorded in the embodiments. Terms such as “device”, “equipment”, “circuit”, “network element”, “node”, “function”, “unit”, “section”, “system”, “network”, “chip”, “chip system”, “entity”, and “subject” can be used interchangeably.

[0105] Furthermore, each element, each row, or each column in the table of this disclosure can be implemented as an independent embodiment, and any combination of any element, any row, or any column can also be implemented as an independent embodiment.

[0106] This application provides a reference voltage generating circuit 10, such as... Figure 1 As shown, the reference voltage generating circuit 10 includes:

[0107] The bandgap reference module 11 includes: a bandgap reference core circuit 111; the bandgap reference core circuit 111 includes: a positive temperature coefficient voltage unit for generating a positive temperature coefficient voltage, and a negative temperature coefficient voltage unit for generating a negative temperature coefficient voltage, wherein the positive temperature coefficient voltage and the negative temperature coefficient voltage are used to generate a reference voltage; wherein the positive temperature coefficient voltage unit is used to directly generate the positive temperature coefficient voltage, or to generate the positive temperature coefficient voltage based on a first positive temperature coefficient current within the bandgap reference module; the negative temperature coefficient voltage unit is used to directly generate the negative temperature coefficient voltage, or to generate the negative temperature coefficient voltage based on a first negative temperature coefficient current within the bandgap reference module;

[0108] The compensation current module 12 is used to output a compensation current to the bandgap reference module when the temperature is greater than a temperature threshold, based on a second positive temperature coefficient current and a second negative temperature coefficient current. The compensation current is used to compensate for the influence of temperature on the reference voltage output by the bandgap reference module. The second positive temperature coefficient current is associated with the first positive temperature coefficient current, or the second negative temperature coefficient current is associated with the first negative temperature coefficient current.

[0109] In one possible implementation, the reference voltage generating circuit 10 can be composed of multiple independent electronic components.

[0110] In one possible implementation, the reference voltage generating circuit 10 can be implemented using an integrated circuit.

[0111] In one possible implementation, the reference voltage generating circuit 10 can be applied to the radio frequency module, but is not limited thereto.

[0112] The compensation current is used to compensate for the effect of temperature on the reference voltage output by the bandgap reference module 11, including: compensating the reference voltage according to the compensation current.

[0113] In one possible implementation, the reference voltage generating circuit 10 is as follows: Figure 2 As shown. The reference voltage generating circuit 10 includes at least a bandgap reference module 11 and a compensation current module 12. In some embodiments, the specific circuit structure of the bandgap reference (BGR) core circuit 111 is as follows. Figure 3 As shown, the bandgap reference core circuit 111 includes: a first operational amplifier, a first amplification unit, a positive temperature coefficient current generation unit, a positive temperature coefficient voltage unit, a negative temperature coefficient voltage unit, and a current bias unit, wherein...

[0114] The positive temperature coefficient current generating unit includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a second PNP BJT Q2, a third PNP BJT Q3, and a third resistor R3;

[0115] The positive temperature coefficient voltage unit includes: a ninth PMOS transistor MP9 and a fourth resistor R4;

[0116] The negative temperature coefficient voltage unit includes: the fourth PNP BJT Q4;

[0117] The current bias unit includes: the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, and the fourteenth NMOS transistor MN14;

[0118] The first amplification unit includes: the thirteenth PMOS transistor MP13, the fifteenth NMOS transistor MN15, and the first capacitor C1;

[0119] The sources of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the eleventh PMOS transistor MP11, and the twelfth PMOS transistor MP12 are connected to a simulated positive voltage connection (e.g., Figure 2 (vdda in the text);

[0120] The source of the tenth NMOS transistor MN10, the source of the eleventh NMOS transistor MN11, the source of the fourteenth NMOS transistor MN14, the source of the fifteenth NMOS transistor MN15, the collector of the second PNP BJT Q2, the base of the second PNP BJT Q2, the collector of the third PNP BJT Q3, the base of the third PNP BJT Q3, the collector of the fourth PNP BJT Q4, the base of the fourth PNP BJT Q4, and the simulated negative voltage connection are connected.

[0121] The drain of the seventh PMOS transistor MP7, the emitter of the second PNP BJT Q2, and the negative input terminal of the first operational amplifier are connected.

[0122] The drain of the eighth PMOS transistor MP8, the first end of the third resistor R3, and the positive input terminal of the first operational amplifier are connected. The second end of the third resistor R3 is connected to the emitter of the third PNP BJT Q3. A positive temperature coefficient current is generated between the drain and the source of the eighth PMOS transistor MP8 in the bandgap reference core circuit 111.

[0123] The drain of the tenth PMOS transistor MP10, the drain of the tenth NMOS transistor MN10, the gate of the tenth NMOS transistor MN10, and the gate of the eleventh NMOS transistor MN11 are connected, and a bias current is generated at the drain of the eleventh NMOS transistor MN11 (e.g., Figure 2 (ibias);

[0124] The drain of the eleventh NMOS transistor MN11, the drain of the eleventh PMOS transistor MP11, the gate of the eleventh PMOS transistor MP11, and the gate of the twelfth PMOS transistor MP12 are connected.

[0125] The drain of the twelfth PMOS transistor MP12, the drain of the twelfth NMOS transistor MN12, the gate of the twelfth NMOS transistor MN12, the gate of the thirteenth NMOS transistor MN13, and the gate of the fourteenth NMOS transistor MN14 are connected. The source of the twelfth NMOS transistor MN12 and the drain of the thirteenth NMOS transistor MN13 are connected. The source of the thirteenth NMOS transistor MN13 and the drain of the fourteenth NMOS transistor MN14 are connected.

[0126] The gate and drain of the thirteenth PMOS transistor MP13, the gate of the seventh PMOS transistor MP7, the gate of the eighth PMOS transistor MP8, the gate of the ninth PMOS transistor MP9, the gate of the tenth PMOS transistor MP10, the gate of the first PMOS transistor MP1, the drain of the fifteenth NMOS transistor MN15, and the first terminal of the first capacitor C1 are connected and used to input the startup voltage (e.g. Figure 2 (v1);

[0127] The output terminal of the first operational amplifier, the second terminal of the first capacitor C1, and the gate of the fifteenth NMOS transistor MN15 are connected.

[0128] The drain of the ninth PMOS transistor MP9 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the emitter of the fourth PNP BJT Q4, and the first end of the fourth resistor R4 is used to output the reference voltage.

[0129] In some embodiments, the first operational amplifier includes: a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, and a nineteenth NMOS transistor MN19.

[0130] The source of the fourteenth PMOS transistor MP14 is connected to the simulated positive voltage.

[0131] The source of the eighteenth NMOS transistor MN18 and the source of the nineteenth NMOS transistor MN19 are connected to the simulated negative voltage.

[0132] The gate of the fourteenth PMOS transistor MP14 is connected to the gate of the twelfth PMOS transistor MP12 to replicate the bias current;

[0133] The drain of the fourteenth PMOS transistor MP14, the source of the fifteenth PMOS transistor MP15, and the source of the sixteenth PMOS transistor MP16 are connected.

[0134] The gate of the fifteenth PMOS transistor MP15 is the positive input terminal of the first operational amplifier, and the gate of the sixteenth PMOS transistor MP16 is the negative input terminal of the first operational amplifier.

[0135] The drain of the fifteenth PMOS transistor MP15 is connected to the source of the seventeenth PMOS transistor MP17, the drain of the sixteenth PMOS transistor MP16 is connected to the source of the eighteenth PMOS transistor MP18, and the gate of the seventeenth PMOS transistor MP17 is connected to the gate of the eighteenth PMOS transistor MP18.

[0136] The drain of the seventeenth PMOS transistor MP17, the drain of the sixteenth NMOS transistor MN16, the gate of the eighteenth NMOS transistor MN18, and the gate of the nineteenth NMOS transistor MN19 are connected.

[0137] The drain of the eighteenth PMOS transistor MP18 is connected to the drain of the seventeenth NMOS transistor MN17 and is used as the output terminal of the first operational amplifier.

[0138] The source of the sixteenth NMOS transistor MN16 is connected to the drain of the eighteenth NMOS transistor MN18, and the source of the seventeenth NMOS transistor MN17 is connected to the drain of the nineteenth NMOS transistor MN19.

[0139] The gates of the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, and the twelfth NMOS transistor MN12 are connected.

[0140] The bandgap reference core circuit 111 utilizes the virtual short characteristic of the first operational amplifier to keep Vn and Vp equal, thereby generating the base-emitter voltage V of Q2 across R3. BE2 and the base-emitter voltage V of Q3 BE3 The base-emitter voltage difference ΔV between BE1 (Voltage with a positive temperature coefficient), ΔV BE1 The first positive temperature coefficient current I is generated on R3. PTAT It can be represented by expression (1).

[0141]

[0142] The core circuit of the bandgap reference 111 replicates the first positive temperature coefficient current I. PThT ,like Figure 3 As shown, the first positive temperature coefficient current I on MP8 can be replicated using MP9 through the current mirror principle. PTATThis leads to R4, which generates a positive temperature coefficient voltage. This positive temperature coefficient voltage across R4 is then compared with the base-emitter voltage V of Q4. BE4 That is, the negative temperature coefficient voltages are added together to obtain the reference voltage, which is the first-order compensated zero temperature coefficient voltage vbgr. Since the bandgap reference core circuit 111 utilizes the nonlinear temperature coefficient in the base-emitter voltage of the BJT, it limits the ability of BGR to further improve the temperature coefficient.

[0143] In one possible implementation, the positive temperature coefficient voltage and the negative temperature coefficient voltage can be weighted to obtain a reference voltage to cancel out the positive and negative temperature coefficients.

[0144] In one possible implementation, such as Figure 3 As shown, the bandgap reference core circuit 111 employs a two-stage amplification. The first stage is a sleeve-type common-source cascode amplifier (implemented by the first operational amplifier), and the second stage is a common-source amplifier (the first amplification unit), thereby improving the loop gain.

[0145] Figure 3 This is just one implementation of the bandgap reference core circuit 111 in this embodiment, and the implementation of the bandgap reference core circuit 111 in this embodiment is not limited to this.

[0146] In one possible implementation, the bandgap reference core circuit 111 generates a first positive temperature coefficient current, but does not generate a first negative temperature coefficient current.

[0147] In one possible implementation, the bandgap reference core circuit 111 generates a first negative temperature coefficient current, but does not generate a first positive temperature coefficient current.

[0148] In one possible implementation, the association of the second positive temperature coefficient current with the first positive temperature coefficient current can include: the second positive temperature coefficient current being generated based on the first positive temperature coefficient current. For example, the second positive temperature coefficient current is obtained by proportionally replicating the first positive temperature coefficient current. This could be achieved by using a current mirror to replicate the first positive temperature coefficient current to obtain the second positive temperature coefficient current.

[0149] In one possible implementation, the association of the second negative temperature coefficient current with the first negative temperature coefficient current can include: the second negative temperature coefficient current being generated based on the first negative temperature coefficient current. For example, the second negative temperature coefficient current is obtained by proportionally replicating the first negative temperature coefficient current. This could be achieved by using a current mirror to replicate the first negative temperature coefficient current to obtain the second negative temperature coefficient current.

[0150] In one possible implementation, the second positive temperature coefficient current is generated based on the first positive temperature coefficient current, and the second negative temperature coefficient current is generated by other circuitry outside the bandgap reference module 11. In another possible implementation, the second negative temperature coefficient current is generated based on the first negative temperature coefficient current, and the second negative positive temperature coefficient current is generated by other circuitry outside the bandgap reference module 11.

[0151] The temperature threshold can be determined based on the reference voltage offset value generated by the bandgap reference module 11. For example, the temperature at which the offset between the reference voltage and the zero temperature coefficient voltage is greater than the offset threshold can be determined as the temperature threshold.

[0152] In one possible implementation, the temperature threshold could be the temperature corresponding to a zero temperature coefficient voltage. For example, the temperature threshold could be 40°C.

[0153] The second positive temperature coefficient current and the second negative temperature coefficient current are related to the nonlinear temperature coefficient in the base-emitter voltage of the BJT. Therefore, the compensation current module 12 can generate a compensation current based on the second positive temperature coefficient current and the second negative temperature coefficient current when the temperature is greater than the temperature threshold, in order to compensate the reference voltage.

[0154] For example, if the temperature is less than or equal to a temperature threshold, and the difference between the second positive temperature coefficient current and the second negative temperature coefficient current is within the current difference range, then the compensation current module 12 does not generate a compensation current. If the temperature is greater than the temperature threshold, and the difference between the second positive temperature coefficient current and the second negative temperature coefficient current exceeds the current difference range, then the compensation current module 12 can generate a compensation current, which can be determined based on the portion of the difference between the second positive temperature coefficient current and the second negative temperature coefficient current that exceeds the current difference range.

[0155] In one possible implementation, the compensation current can be superimposed on the first positive temperature coefficient current I. PTAT The above is used to compensate for the reference voltage generated by the bandgap reference core circuit 111.

[0156] For example, a compensation current can be applied to Figure 3 The reference voltage is compensated on R4 as shown.

[0157] In this way, by determining the compensation current through the second positive temperature coefficient current and the second negative temperature coefficient current, the reference voltage is compensated, thus realizing nonlinear compensation of the reference voltage and improving the accuracy of the output reference voltage of the bandgap reference module 11.

[0158] In some embodiments, such as Figure 2As shown, the bandgap reference module 11 includes: a second startup circuit 112, used to start the bandgap reference core circuit 111. The second startup circuit 112 includes: a first directional controller U1, a second directional controller U2, a nineteenth PMOS transistor MP19, a twentieth PMOS transistor MP20, a twenty-first PMOS transistor MP21, a twenty-second PMOS transistor MP22, a twenty-third PMOS transistor MP23, a twenty-fourth PMOS transistor MP24, a twentieth NMOS transistor MN20, a twenty-first NMOS transistor MN21, a twenty-second NMOS transistor MN22, and a twenty-fifth PMOS transistor MP25 and a twenty-third NMOS transistor MN23.

[0159] The input terminal of the first directional controller U1 is used to input the first start / stop control signal (such as...). Figure 2 In the pd_bg), the output of the first directional controller U1 is connected to the input of the second directional controller U2 and is used to output the second start / stop control signal (e.g., pd_bg). Figure 2 (pdp); the output of the second directional controller U2 is used to output the third start / stop control signal (e.g., pdp); Figure 2 (pd);

[0160] The source of the nineteenth PMOS transistor MP19, the source of the twenty-fourth PMOS transistor MP24, the source of the twenty-fifth PMOS transistor MP25, and the simulated positive voltage connection are connected.

[0161] The source of the twentieth NMOS transistor MN20, the source of the twenty-second NMOS transistor MN22, and the source of the twenty-third NMOS transistor MN23 are connected to the simulated negative voltage.

[0162] The gate and drain of the nineteenth PMOS transistor MP19 are connected to the source of the twentieth PMOS transistor MP20; the gate and drain of the twentieth PMOS transistor MP20 are connected to the source of the twenty-first PMOS transistor MP21; the gate and drain of the twenty-first PMOS transistor MP21 are connected to the source of the twenty-second PMOS transistor MP22; the gate and drain of the twenty-second PMOS transistor MP22 are connected to the source of the twenty-third PMOS transistor MP23.

[0163] The gate of the 23rd PMOS transistor MP23 is connected to the gate of the 20th NMOS transistor MN20 for inputting the reference voltage;

[0164] The drain of the 23rd PMOS transistor MP23, the drain of the 20th NMOS transistor MN20, and the gate of the 22nd NMOS transistor MN22;

[0165] The gate of the 24th PMOS transistor MP24 is connected to the gate of the 21st NMOS transistor MN21, and is used to input the second start / stop control signal;

[0166] The source of the 21st NMOS transistor MN21 and the drain of the 22nd NMOS transistor MN22 are connected; the drain of the 24th PMOS transistor MP24 and the drain of the 21st NMOS transistor MN21 are connected to output the startup voltage.

[0167] The gate of the 25th PMOS transistor MP25 is used to input the second start / stop control signal, and the drain of the 25th PMOS transistor MP25 is connected to the gate of the 11th PMOS transistor MP11.

[0168] The gate of the 23rd NMOS transistor MN23 is used to input the third start / stop control signal, the drain of the 23rd NMOS transistor MN23 is connected to the reference voltage, and the source of the 23rd NMOS transistor MN23 is connected to the analog negative voltage.

[0169] The gate of the seventeenth PMOS transistor MP17 is used to input the third start / stop control signal.

[0170] The second startup circuit 112 can also be called the startup circuit of the bandgap reference core circuit 111.

[0171] Due to its operating principle, the bandgap reference core circuit 111 has a zero-balance point (the bandgap reference core circuit 111 is in a zero-balance state), and the currents of MP7 and MP8 are 0 in the zero-balance state. The second startup circuit 112 can allow the bandgap reference core circuit 111 to escape the zero-balance point. For example... Figure 2 As shown, the moment the bandgap reference core circuit 111 is powered on, the bandgap output vbgr is 0, at which point MP23 and MN22 are turned on. The input to the PD port is low, and the output of the PDP port is high, causing MP24 to be turned off and MN21 to be turned on. This pulls down the startup voltage V1, that is, the voltage at point C, causing MP7 and MP8 to be turned on. Then, current is injected into the bandgap reference core circuit 111, causing Q2 and Q3 to be turned on, and generating a positive coefficient first positive temperature coefficient current across R3. This voltage is then copied to MP9 and MP10, generating a positive temperature coefficient voltage across R4. Q4 is a negative temperature coefficient voltage. The positive and negative temperature coefficient voltages are superimposed to produce a first-order compensated zero temperature coefficient voltage vbgr. The first positive temperature coefficient current is copied to the first operational amplifier through current mirrors MN10 and MN11. The first operational amplifier operates normally, the entire circuit escapes the zero-parallel point, and outputs a reference voltage, causing MP23 and MN22 to turn off, i.e., the startup circuit module is shut down. A two-stage amplification is used here: the first stage is a cascaded common-source amplifier, and the second stage is a common-source amplifier to improve loop gain. Thus, the second startup circuit 112 causes the bandgap reference core circuit 111 to escape the zero-balance state and generate a reference voltage.

[0172] In some embodiments, such as Figure 4 As shown, the compensation current module 12 includes:

[0173] The first current mirror unit 121 is used to obtain the second positive temperature coefficient current;

[0174] The second current mirror unit 122 is used to obtain the second negative temperature coefficient current; wherein, when the temperature is greater than the temperature threshold, the second positive temperature coefficient current is greater than the second negative temperature coefficient current.

[0175] The compensation current generating unit 123 is used to output a compensation current, wherein the compensation current is the difference between the second positive temperature coefficient current and the second negative temperature coefficient current mirrored by the compensation current generating unit at a third ratio when the temperature is greater than the temperature threshold.

[0176] In one possible implementation, the first current mirror unit 121 and the second current mirror unit 122 can be implemented using a current mirror.

[0177] In one possible implementation, the compensation current generation unit can also be implemented using a current mirror to output the compensation current based on the third proportional mirror difference.

[0178] In one possible implementation, the first current mirror unit can proportionally replicate the first positive temperature coefficient current to obtain the second positive temperature coefficient current, and the second current mirror unit can obtain the second negative temperature coefficient current from outside the bandgap reference module 11.

[0179] In one possible implementation, the second current mirror unit can proportionally replicate the first negative temperature coefficient current to obtain the second negative temperature coefficient current, and the second current mirror unit can obtain the second positive temperature coefficient current from outside the bandgap reference module 11.

[0180] The compensation current generation unit can generate a compensation current based on the difference between the second positive temperature coefficient current and the second negative temperature coefficient current when the temperature is greater than the temperature threshold.

[0181] In one possible implementation, the third ratio can be determined based on the amplitude of the required compensation current output. The third ratio is positively correlated with the amplitude of the required compensation current.

[0182] In this way, by determining the compensation current through the second positive temperature coefficient current and the second negative temperature coefficient current, the reference voltage is compensated, thus realizing nonlinear compensation of the reference voltage and improving the accuracy of the output reference voltage of the core circuit 111.

[0183] In some embodiments, the first current mirroring unit is used to mirror the first positive temperature coefficient current in the bandgap reference core circuit 111 at a first ratio to obtain the second positive temperature coefficient current.

[0184] The second current mirroring unit is used to mirror the third negative temperature coefficient current according to the second ratio to obtain the second negative temperature coefficient current, wherein the third negative temperature coefficient current is generated by the current generation module 13 in the reference voltage generation circuit, wherein the current generation module 13 is different from the bandgap reference module.

[0185] In one possible implementation, the current generation module generates a third negative temperature coefficient current based on the negative temperature coefficient of the bandgap reference core circuit 111.

[0186] In one possible implementation, the first negative temperature coefficient current and the third negative temperature coefficient current have the same negative temperature coefficient.

[0187] In one possible implementation, the first negative temperature coefficient current and the third negative temperature coefficient current have the same proportional relationship.

[0188] In some embodiments, such as Figure 5 As shown, the first current mirror unit includes: a first PMOS transistor MP1, used to replicate the first positive temperature coefficient current; and a current mirror composed of a first NMOS transistor MN1 and a second NMOS transistor MN2, used to mirror the replicated first positive temperature coefficient current according to the first ratio to obtain the second positive temperature coefficient current.

[0189] The second current mirror unit includes: a second PMOS transistor MP2, used to mirror the third negative temperature coefficient current according to the second ratio to obtain the second negative temperature coefficient current;

[0190] The compensation current generation unit includes: a third PMOS transistor MP3 and a fourth PMOS transistor MP4;

[0191] The third PMOS transistor MP3 and the second PMOS transistor MP2 are connected in parallel and then connected in series with the second NMOS transistor MN2. The fourth PMOS transistor MP4 and the third PMOS transistor MP3 form a current mirror, which is used to mirror the difference between the second positive temperature coefficient current and the second negative temperature system current output by the third PMOS transistor MP3 according to the third ratio, and output the compensation current.

[0192] In this configuration, the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are connected to a simulated positive voltage, while the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to a simulated negative voltage. In one possible implementation, the first PMOS transistor MP1 can form a current mirror with the PMOS transistor that generates the positive temperature coefficient current to replicate the first positive temperature coefficient current.

[0193] Specifically, such as Figure 2 and Figure 5 As shown, the first PMOS transistor MP1 can replicate the positive temperature coefficient current flowing through MP8, and the current mirror composed of the first NMOS transistor MN1 and the second NMOS transistor MN2 is used to mirror the positive temperature coefficient current replicated by the first PMOS transistor MP1 according to the first ratio to obtain the second positive temperature coefficient current.

[0194] The current mirror formed by the first NMOS transistor MN1 and the second NMOS transistor MN2 can adjust the first ratio by adjusting the channel width-to-length ratio of the first NMOS transistor MN1 and / or the second NMOS transistor MN2.

[0195] In one possible implementation, the first ratio can be adjusted by changing the channel width-to-length ratio of the first PMOS transistor MP1. The current mirror formed by the first NMOS transistor MN1 and the second NMOS transistor MN2 mirrors the current in the first PMOS transistor MP1 in a 1:1 ratio, thus obtaining the second positive temperature coefficient current.

[0196] In one possible implementation, the first positive temperature coefficient current can be mirrored by adjusting the channel width-to-length ratio of the first PMOS transistor MP1 at a fourth ratio. Then, by adjusting the channel width-to-length ratio of the first NMOS transistor MN1 and / or the second NMOS transistor MN2, the current in the first PMOS transistor MP1 can be mirrored at a fifth ratio, thereby mirroring the first positive temperature coefficient current at a first ratio and obtaining the second positive temperature coefficient current.

[0197] In one possible implementation, the second PMOS transistor MP2 can form a current mirror with the PMOS transistor that generates the third negative temperature coefficient current, and the second ratio can be adjusted by adjusting the channel width-to-length ratio of the second PMOS transistor MP2.

[0198] In one possible implementation, the first and second proportions satisfy the condition that, when the temperature is at a temperature threshold, the second positive temperature coefficient current is the same as the second negative temperature coefficient current. That is, the first and second proportions satisfy the second expression (1):

[0199] β1I PTAT -β2I CTAT =0, T=T0 (1)

[0200] Where β1 represents the first proportion, β2 represents the second proportion, and I PTAT I represents the first positive temperature coefficient current. CTAT β1I represents the third negative temperature coefficient current, and T0 represents the temperature threshold. PTAT β²I represents the second positive temperature coefficient current. CTAT This represents the second negative temperature coefficient current.

[0201] When the temperature is above the temperature threshold, the second positive temperature coefficient current is greater than the second negative temperature coefficient current. The relationship between the second positive temperature coefficient current and the second negative temperature coefficient current is shown in expression (2):

[0202] β1I PTAT -β2I CTAT >0, T>T0 (2)

[0203] Where β1 represents the first proportion, β2 represents the second proportion, and I PTAT I represents the first positive temperature coefficient current. CTAT β1I represents the third negative temperature coefficient current, and T0 represents the temperature threshold. PTAT β²I represents the second positive temperature coefficient current. CTAT This represents the second negative temperature coefficient current.

[0204] In one possible implementation, the third ratio can be adjusted by adjusting the channel width-to-length ratio of the fourth PMOS transistor MP4 and / or the third PMOS transistor MP3.

[0205] Specifically, such as Figure 5As shown, the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are connected to the simulated positive voltage, and the drain of the second PMOS transistor MP2 and the drain of the third PMOS transistor MP3 are connected to the drain of the second NMOS transistor MN2, respectively. The current flowing through the second PMOS transistor MP2 and the third PMOS transistor MP3 flows out to the simulated negative voltage through the second NMOS transistor MN2.

[0206] The second PMOS transistor MP2 mirrors the third negative temperature coefficient current according to the second ratio, obtaining the second negative temperature coefficient current; the second NMOS transistor MN2 mirrors the first positive temperature coefficient current according to the first ratio, obtaining the second positive temperature coefficient current. At a certain temperature (T0), the two currents are equal. When the temperature is greater than T0, the second positive temperature coefficient current of the second NMOS transistor MN2 is greater than the second negative temperature coefficient current flowing through the second PMOS transistor MP2. The third PMOS transistor MP3 will then generate a differential current to compensate for the difference between the second positive temperature coefficient current and the second negative temperature coefficient current. Then, through the current mirror formed by the third PMOS transistor MP3 and the fourth PMOS transistor MP4, the differential current is converted into a compensation current and transmitted. The current ratio of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 is the third ratio, i.e., 1:N, where N is a positive number. For example, N is a positive integer. At this time, the second PMOS transistor MP2 is in the linear region, and the third PMOS transistor MP3 is in the on state.

[0207] When the temperature is less than T0, the second negative temperature coefficient current flowing through the second PMOS transistor MP2 is equal to the second positive temperature coefficient current flowing through the second NMOS transistor MN2, and the current in the third PMOS transistor MP3 is 0. At this time, the second PMOS transistor MP2 is in the saturation region, and the third PMOS transistor MP3 is in the off state.

[0208] In some embodiments, the compensation current is represented by expression (2):

[0209]

[0210] Wherein, β1 represents the first proportion, β2 represents the second proportion, and I PTAT I represents the first positive temperature coefficient current. CTAT The third negative temperature coefficient current is represented by T0, the temperature threshold is represented by N, and the third ratio is represented by N.

[0211] like Figure 5 As shown, the compensation current I output from the drain of the fourth PMOS transistor MP4 NL β1I can be represented by expression (2). PTAT This can represent the second positive temperature coefficient current, β2I, obtained by mirroring the second NMOS transistor MN2 according to the first ratio. CTATThis can represent the second negative temperature coefficient current obtained by mirroring the second PMOS transistor in a second ratio.

[0212] In some embodiments, the compensation current is used to generate a compensated positive temperature coefficient voltage across the fourth resistor R4 in conjunction with the first positive temperature coefficient current in the bandgap reference module 11. The compensated reference voltage includes the sum of the negative temperature coefficient voltage and the compensated positive temperature coefficient voltage.

[0213] Here, the third resistor R3 is used to generate the first positive temperature coefficient voltage, such as Figure 2 and Figure 5 As shown, the compensation current I output by the fourth PMOS transistor MP4 NL Both the first positive temperature coefficient current replicated by MP9 and the current from the fourth resistor R4 flow through it, thus generating a compensated positive temperature coefficient voltage, which is related to the base-emitter voltage V of Q4. BE3 That is, the negative temperature coefficient voltages are added together to obtain the compensated reference voltage.

[0214] In some embodiments, such as Figure 6 As shown, the reference voltage generating circuit 10 also includes a current generating module 13. For example... Figure 6 As shown, the current generating module 13 includes a negative temperature coefficient current generating unit 131, wherein, as Figure 7 As shown, the negative temperature coefficient current generating unit 131 includes a first current mirror 1311, a common source cascode current mirror 1312, a first PNP bipolar junction transistor (BJT) Q1, and a first resistor R1.

[0215] The two current input terminals of the first current mirror 1311 are connected to the simulated positive voltage. The two current output terminals of the first current mirror 1311 are respectively connected to the two current input terminals of the common source cascode current mirror 1312. The two current output terminals of the common source cascode current mirror 1312 are respectively connected to the first terminal of the first resistor R1 and the emitter of the first PNP BJT Q1. The second terminal of the first resistor R1, the base of the first PNP BJT Q1, and the collector of the first PNP BJT Q1 are connected to the simulated negative voltage connection. The second current mirror unit is used to mirror the third negative temperature coefficient current generated by the first current mirror 1311. The negative temperature coefficient current generating unit 131 can generate a negative temperature coefficient voltage based on a principle similar to that of the bandgap reference module 11 outside the bandgap reference module 11, and generate a third negative temperature coefficient current based on the negative temperature coefficient voltage.

[0216] The second current mirroring unit 122 can mirror the third negative temperature coefficient current generated by the negative temperature coefficient current generating unit 131. In this way, the negative temperature coefficient current is generated outside the bandgap reference module 11, which can reduce the design complexity of the bandgap reference module 11.

[0217] In some embodiments, such as Figure 8 As shown, the first current mirror 1311 includes a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6; the common-source common-gate current mirror 1312 includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a sixth NMOS transistor MN6.

[0218] The source of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, and the simulated positive voltage connection are connected.

[0219] The gate of the fifth PMOS transistor MP5, the gate of the sixth PMOS transistor MP6, the drain of the sixth PMOS transistor MP6, and the gate of the second PMOS transistor MP2 are connected.

[0220] The drain of the third NMOS transistor MN3 is connected to the drain of the fifth PMOS transistor MP5, the drain of the fourth NMOS transistor MN4 is connected to the drain of the sixth PMOS transistor MP6, and the gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, and the drain of the fifth PMOS transistor MP5 are connected.

[0221] The drain of the fifth NMOS transistor MN5 is connected to the source of the third NMOS transistor MN3, the drain of the sixth NMOS transistor MN6 is connected to the source of the fourth NMOS transistor MN4, and the gates of the fifth NMOS transistor MN5, the sixth NMOS transistor MN6, and the source of the third NMOS transistor MN3 are connected.

[0222] The source of the fifth NMOS transistor MN5 is connected to the emitter of the first PNP BJT Q1, and the source of the sixth NMOS transistor MN6 is connected to the first end of the first resistor R1.

[0223] Specifically, such as Figure 8 As shown, two PMOS transistors, MP5 and MP6, form the first current mirror 1311, and four NMOS transistors, MN3, MN4, MN6, and MN7, form the common-source cascode current mirror 1312. The negative temperature coefficient current generation unit 131 utilizes the PN junction voltage drop, i.e., the V1 of the first PNP BJT Q1. BE1To determine the current, when MP5 and MP6 use the same transistor, and MN3, MN4, MN5 and MN6 all use the same transistor, the third negative temperature coefficient current generated on R1 can be expressed by expression (3):

[0224]

[0225] In some embodiments, such as Figure 8 As shown, the current generating module 13 further includes: a first start-up circuit 132, used to start the negative temperature coefficient current generating unit 131.

[0226] The first startup circuit 132 includes: a second resistor R2, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a ninth NMOS transistor MN9;

[0227] The first terminal of the second resistor R2 and the drain of the seventh NMOS transistor MN7 are connected to an analog positive voltage. The second terminal of the second resistor R2, the gate of the seventh NMOS transistor MN7, the gate of the eighth NMOS transistor MN8, the drain of the eighth NMOS transistor MN8, and the gate of the ninth NMOS transistor MN9 are connected. The source of the seventh NMOS transistor MN7 is connected to the drain of the fifth PMOS transistor MP5.

[0228] The source of the eighth NMOS transistor MN8 is connected to the drain of the ninth NMOS transistor MN9;

[0229] The source of the ninth NMOS transistor MN9 is connected to a simulated negative voltage.

[0230] In one possible implementation, the negative temperature coefficient current generating unit 131 has two steady-state points: one is the equilibrium point when generating a stable negative temperature coefficient current, and the other is the zero equilibrium point when the current mirror current is 0. Therefore, the negative temperature coefficient current generating unit 131 also includes a startup circuit to trigger the negative temperature coefficient current generating unit 131 to switch from the zero equilibrium point to the equilibrium point when generating a stable third negative temperature coefficient current.

[0231] like Figure 8 As shown, R3, MN7, MN8, and MN9 form the first startup circuit 132. During the charging process, when the reference current is at the zero equilibrium point, MN7 will provide current to the MN3 branch to make the circuit leave the zero current state. As the circuit gradually enters the normal bias state, the source potential of MN7 rises and eventually turns off MN7, completing the startup process. The first startup circuit 132 no longer affects the third negative temperature coefficient current generating circuit. When designing the circuit, it is necessary to note that the current flowing through the branch composed of R2, MN8, and MN9 is relatively small after the reference circuit is started, which can save circuit power consumption.

[0232] In some embodiments, the first PNP BJT Q1 and the fourth PNP BJT Q4 have at least the same base-emitter voltage difference.

[0233] Within the bandgap reference module 11, the fourth PNP BJT Q4 is used to generate a negative temperature system voltage. Specifically, the bandgap reference module 11 uses the base-emitter voltage of the fourth PNP BJT Q4 as the negative temperature system voltage, and the sum of the negative temperature system voltage and the positive temperature system voltage as the zero temperature coefficient voltage vbgr. The negative temperature coefficient current generation unit 131 generates a negative temperature coefficient voltage outside the bandgap reference module 11, thereby generating a negative temperature coefficient current. The negative temperature coefficient voltage generated outside the bandgap reference module 11 needs to have a corresponding relationship (e.g., proportional relationship, same) with the negative temperature system voltage inside the bandgap reference module 11 to achieve accurate compensation current. Therefore, the first PNP BJT Q1 in the negative temperature coefficient current generation unit 131 can be implemented using the same PNP BJT as the fourth PNP BJT Q4. Essentially, the negative temperature coefficient current generated outside the bandgap reference module 11 is based on the negative temperature system voltage inside the bandgap reference module 11, thus making the generated negative temperature coefficient current more accurate and improving compensation precision.

[0234] like Figure 2 and Figure 8 As shown, the bandgap reference module 11 uses Q4 to generate the negative temperature system voltage; the negative temperature coefficient current generation unit 131 uses Q1 to generate the negative temperature system voltage. Q1 and Q4 can use the same PNP BJT, so that the negative temperature system voltage generated by Q4 and the negative temperature system voltage generated by Q1 have a strong correlation (such as proportional correlation or the same), thereby making the generated negative temperature coefficient current more accurate and improving the compensation accuracy.

[0235] Figure 9 The curve of the reference voltage (vbgr) output of the bandgap reference module 11 (which does not have a current compensation module 12) versus temperature is shown. After first-order temperature compensation, it exhibits zero temperature coefficient around room temperature. Below or above this temperature, the output shows a decreasing trend. Overall, the temperature coefficient (TC) is 11.23 ppm / ℃.

[0236] Figure 10 The curve showing the output of the reference voltage (vbgr) of the bandgap reference module 11 with compensation current module 12 as a function of temperature is shown. After nonlinear current compensation by compensation current module 12, a nonlinear current (compensation current) is added after the voltage exceeds the zero temperature coefficient to suppress its decreasing trend. The overall temperature coefficient (TC) is 4.27 ppm / ℃.

[0237] The method of this embodiment will be described below with reference to a specific example.

[0238] A complete reference voltage generation circuit, such as Figure 2 As shown, it includes a BGR start-up circuit (second start-up circuit), a BGR core circuit (i.e., bandgap reference module), a nonlinear compensation current generator (i.e., compensation current module), and a negative temperature coefficient current generator (i.e., current generation module 13). Among them, the BGR core circuit includes a positive temperature coefficient current generator.

[0239] The Pd_bg input port is the power-down port for the entire circuit structure. When it is set to a high potential (power supply voltage), the pdp signal is at a low potential (zero potential), the pd signal is at a high potential, and the entire BGR circuit is turned off; conversely, when the pd_bg input port is at a zero potential, the BGR circuit is turned on.

[0240] The BGR startup circuit is designed to bring the bandgap reference core circuit and the independent bias circuit out of the zero-current state.

[0241] The core circuit of the BGR is a first-order temperature-compensated voltage-mode BGR structure, which uses a common-source common-gate amplifier. The bias current of the amplifier is provided by the bandgap reference core circuit.

[0242] The positive temperature coefficient current generator is based on the positive temperature coefficient current in the core circuit of the bandgap reference.

[0243] The negative temperature coefficient current generator is based on the base-emitter voltage of a BJT.

[0244] The nonlinear compensation current generator compares the positive and negative coefficients of temperature and current, and then finally generates a nonlinear compensation current.

[0245] The band gap of the BGR starter circuit and the BGR core circuit is as follows: Figure 2 As shown:

[0246] The BGR startup circuit is designed to eliminate the zero-coupling point of the BGR circuit. At the instant the entire circuit powers on, the bandgap output VBGR is 0, at which point MP23 and MN22 are turned on. The input to the PD port is low, and the output of PDP is high, causing MP24 to be cut off and MN21 to conduct. This pulls the voltage at point V1 low, i.e., the voltage at point C low, causing MP7 and MP8 to conduct. Current then flows into the core bandgap reference circuit, causing Q1 and Q3 to conduct, and generating a positive temperature coefficient current across R3. This voltage is then copied to MP9 and MP10, generating a positive temperature coefficient voltage across R4. Q4 then generates a negative temperature coefficient voltage, ultimately resulting in a first-order compensated zero temperature coefficient voltage from vbgr. The current (i.e., the bias current ibias) is copied to the op-amp (first operational amplifier) ​​via current mirrors MN10 and MN11. With the op-amp operating normally, the entire circuit escapes the zero-coupling point, outputting a reference voltage that shuts down MP23 and MN22, effectively turning off the startup circuit module. The op-amp uses a two-stage design: the first stage is a cascode common-source amplifier, and the second stage is a common-source amplifier to enhance loop gain.

[0247] Negative temperature coefficient current generating circuit, such as Figure 2 and Figure 8 As shown:

[0248] The negative temperature coefficient current generating circuit uses the PN junction voltage drop to determine the current. When MP6, MP6, MN3, MN4, MN5, and MN6 all use the same transistors, a negative temperature coefficient current is generated across R1. The first startup circuit consists of MN7, MN8, and MN9. During the charging process, when the reference current is at the zero equilibrium point, MN7 will provide current to the MN3 branch to make the circuit leave the zero current state. As the circuit gradually enters the normal bias state, the source potential of MN7 rises and eventually turns off MN7, completing the startup process. The first startup circuit no longer affects the negative temperature coefficient current generation circuit. When designing the circuit, it is necessary to note that the branch composed of R2 and MN8 and MN9 will have a very small current flowing through it after the reference circuit is started, so as to save circuit power consumption.

[0249] Nonlinear compensation current generation circuit, such as Figure 5 As shown:

[0250] Figure 2 This demonstrates the basic principle of nonlinear current generation. MP2 replicates a negative temperature coefficient current, and MN2 replicates a positive temperature coefficient current. At a certain temperature (T0), the two currents are equal. When the temperature exceeds T0, the current in MN2 exceeds the current flowing through MP2. MP3 then generates a current to compensate for the excess current in MN2. This excess current is then transmitted through a current mirror composed of MP3 and MP4, with a current ratio of 1:N between MP3 and MP4. At this point, MP2 is in the linear region, and MP3 is in the on state.

[0251] When the temperature is below T0, the current flowing through MP2 is equal to the current through MN2, and the current in MP3 is 0. At this time, MP2 is in the saturation region, and MP3 is in the off state.

[0252] The above description is presented using mathematical expressions, as shown in expression (2) below.

[0253] MP1 replicates the positive temperature coefficient current and then transmits it to MN2 through the current mirror MN1. MP2 replicates the negative temperature coefficient current mentioned above. The currents of MP2 and MN2 are compared. At a certain temperature (T0), MM4 generates a nonlinear compensation current to the output terminal, giving the entire BGR better temperature characteristics.

[0254] Figure 9 The curve of the reference voltage (vbgr) output of a bandgap reference module without a current compensation module as a function of temperature is shown. After first-order temperature compensation, it exhibits zero temperature coefficient around room temperature. Below or above this temperature, the output shows a decreasing trend. The overall temperature coefficient (TC) is 11.23 ppm / ℃.

[0255] Figure 10 The curve shows the output reference voltage (vbgr) of the bandgap reference module with a compensation current module as a function of temperature. After nonlinear current compensation, an additional nonlinear current (compensation current) is added above the zero temperature coefficient voltage to suppress its decreasing trend. The overall temperature coefficient (TC) is 4.27 ppm / ℃.

[0256] This application provides an embodiment of a radio frequency module, such as... Figure 11 As shown, the radio frequency module 1 includes a reference voltage generating circuit 10.

[0257] The specific implementation method of the reference voltage generating circuit 10 is as follows: Figures 1 to 10 As shown in any of the embodiments, it will not be described again here.

[0258] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0259] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A reference voltage generating circuit, characterized in that, The reference voltage generating circuit includes: A bandgap reference module includes: a bandgap reference core circuit; the bandgap reference core circuit includes: a positive temperature coefficient voltage unit for generating a positive temperature coefficient voltage, and a negative temperature coefficient voltage unit for generating a negative temperature coefficient voltage, wherein the positive temperature coefficient voltage and the negative temperature coefficient voltage are used to generate a reference voltage; wherein the positive temperature coefficient voltage unit is used to directly generate the positive temperature coefficient voltage, or to generate the positive temperature coefficient voltage based on a first positive temperature coefficient current within the bandgap reference core circuit; the negative temperature coefficient voltage unit is used to directly generate the negative temperature coefficient voltage, or to generate the negative temperature coefficient voltage based on a first negative temperature coefficient current within the bandgap reference core circuit; A compensation current module is used to output a compensation current to the bandgap reference core circuit when the temperature is greater than a temperature threshold, based on a second positive temperature coefficient current and a second negative temperature coefficient current. The compensation current is used to compensate for the effect of temperature on the reference voltage output by the bandgap reference core circuit. The second positive temperature coefficient current is associated with the first positive temperature coefficient current, or the second negative temperature coefficient current is associated with the first negative temperature coefficient current. The compensation current module includes: The first current mirror unit is used to obtain the second positive temperature coefficient current; The second current mirror unit is used to obtain the second negative temperature coefficient current; wherein, when the temperature is greater than the temperature threshold, the second positive temperature coefficient current is greater than the second negative temperature coefficient current. A compensation current generating unit is used to output a compensation current, wherein the compensation current is the difference between the second positive temperature coefficient current and the second negative temperature coefficient current mirrored by the compensation current generating unit at a third ratio when the temperature is greater than the temperature threshold. The first current mirroring unit is used to mirror the first positive temperature coefficient current in the bandgap reference core circuit according to a first ratio to obtain the second positive temperature coefficient current. The second current mirroring unit is used to mirror the third negative temperature coefficient current according to the second ratio to obtain the second negative temperature coefficient current, wherein the third negative temperature coefficient current is generated by the current generation module in the reference voltage generation circuit, and the current generation module is different from the bandgap reference module.

2. The reference voltage generating circuit according to claim 1, characterized in that, The first current mirror unit includes: a first PMOS transistor for replicating the first positive temperature coefficient current, and a current mirror composed of a first NMOS transistor and a second NMOS transistor for mirroring the replicated first positive temperature coefficient current according to the first ratio to obtain the second positive temperature coefficient current. The second current mirror unit includes: a second PMOS transistor, used to mirror the third negative temperature coefficient current according to the second ratio to obtain the second negative temperature coefficient current; The compensation current generation unit includes: a third PMOS transistor and a fourth PMOS transistor; The third PMOS transistor and the second PMOS transistor are connected in parallel and then connected in series with the second NMOS transistor. The fourth PMOS transistor and the third PMOS transistor form a current mirror, which is used to mirror the difference between the second positive temperature coefficient current and the second negative temperature system current output by the third PMOS transistor according to the third ratio, and output the compensation current. The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to a simulated positive voltage, while the sources of the first NMOS transistor and the second NMOS transistor are connected to a simulated negative voltage.

3. The reference voltage generating circuit according to claim 2, characterized in that, The compensation current is expressed by the following expression: ； in, Indicates the first proportion. Indicates the second proportion. This represents the first positive temperature coefficient current. This represents the third negative temperature coefficient current. Indicates the temperature threshold. This indicates the third ratio.

4. The reference voltage generating circuit according to claim 2, characterized in that, The current generation module includes a negative temperature coefficient current generation unit. The negative temperature coefficient current generating unit includes a first current mirror, a common-source cascode current mirror, a first PNP BJT, and a first resistor. The two current input terminals of the first current mirror are connected to simulated positive voltage, and the two current output terminals of the first current mirror are respectively connected to the two current input terminals of the common source cascode current mirror. The two current output terminals of the common source cascode current mirror are respectively connected to the first terminal of the first resistor and the emitter of the first PNP BJT. The second terminal of the first resistor, the base of the first PNP BJT, and the collector of the first PNP BJT are connected to simulated negative voltage. The second current mirror unit is used to mirror the third negative temperature coefficient current generated by the first current mirror.

5. The reference voltage generating circuit according to claim 4, characterized in that, The first current mirror includes a fifth PMOS transistor and a sixth PMOS transistor; the common-source cascode current mirror includes a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the simulated positive voltage connection are connected. The gate of the fifth PMOS transistor, the gate of the sixth PMOS transistor, the drain of the sixth PMOS transistor, and the gate of the second PMOS transistor are connected. The drain of the third NMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the sixth PMOS transistor, and the gate of the third NMOS transistor, the gate of the fourth NMOS transistor, and the drain of the fifth PMOS transistor are connected. The drain of the fifth NMOS transistor is connected to the source of the third NMOS transistor, the drain of the sixth NMOS transistor is connected to the source of the fourth NMOS transistor, and the gates of the fifth NMOS transistor, the sixth NMOS transistor, and the third NMOS transistor are connected. The source of the fifth NMOS transistor is connected to the emitter of the first PNP BJT, and the source of the sixth NMOS transistor is connected to the first end of the first resistor.

6. The reference voltage generating circuit according to claim 5, characterized in that, The current generating module further includes: a first start-up circuit for starting the negative temperature coefficient current generating unit. The first startup circuit includes: a second resistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; The first terminal of the second resistor and the drain of the seventh NMOS transistor are connected to an analog positive voltage. The second terminal of the second resistor, the gate of the seventh NMOS transistor, the gate of the eighth NMOS transistor, the drain of the eighth NMOS transistor, and the gate of the ninth NMOS transistor are connected. The source of the seventh NMOS transistor is connected to the drain of the fifth PMOS transistor. The source of the eighth NMOS transistor is connected to the drain of the ninth NMOS transistor; The source of the ninth NMOS transistor is connected to a simulated negative voltage.

7. The reference voltage generating circuit according to claim 4, characterized in that, The core circuit of the bandgap reference includes: a first operational amplifier, a first amplification unit, a positive temperature coefficient current generation unit, a positive temperature coefficient voltage unit, a negative temperature coefficient voltage unit, and a current biasing unit, wherein... The positive temperature coefficient current generating unit includes a seventh PMOS transistor, an eighth PMOS transistor, a second PNP BJT, a third PNP BJT, and a third resistor; The positive temperature coefficient voltage unit includes: a ninth PMOS transistor and a fourth resistor; The negative temperature coefficient voltage unit includes: the fourth PNP BJT; The current bias unit includes: the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, and the fourteenth NMOS transistor; The first amplification unit includes: a thirteenth PMOS transistor, a fifteenth NMOS transistor, and a first capacitor; The source of the seventh PMOS transistor, the source of the eighth PMOS transistor, the source of the ninth PMOS transistor, the source of the tenth PMOS transistor, the source of the eleventh PMOS transistor, the source of the twelfth PMOS transistor, and the simulated positive voltage connection are connected. The source of the tenth NMOS transistor, the source of the eleventh NMOS transistor, the source of the fourteenth NMOS transistor, the source of the fifteenth NMOS transistor, the collector of the second PNP BJT, the base of the second PNP BJT, the collector of the third PNP BJT, the base of the third PNP BJT, the collector of the fourth PNP BJT, the base of the fourth PNP BJT, and the simulated negative voltage connection are connected. The drain of the seventh PMOS transistor, the emitter of the second PNP BJT, and the negative input terminal of the first operational amplifier are connected. The drain of the eighth PMOS transistor, the first end of the third resistor, and the positive input terminal of the first operational amplifier are connected. The second end of the third resistor is connected to the emitter of the third PNP BJT. A positive temperature coefficient current is generated between the drain and the source of the eighth PMOS transistor in the bandgap reference core circuit. The drain of the tenth PMOS transistor, the drain of the tenth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor are connected, and the drain of the eleventh NMOS transistor generates a bias current. The drain of the eleventh NMOS transistor, the drain of the eleventh PMOS transistor, the gate of the eleventh PMOS transistor, and the gate of the twelfth PMOS transistor are connected. The drain of the twelfth PMOS transistor, the drain of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor are connected. The source of the twelfth NMOS transistor and the drain of the thirteenth NMOS transistor are connected. The source of the thirteenth NMOS transistor and the drain of the fourteenth NMOS transistor are connected. The gate of the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor, the gate of the seventh PMOS transistor, the gate of the eighth PMOS transistor, the gate of the ninth PMOS transistor, the gate of the tenth PMOS transistor, the gate of the first PMOS transistor, the drain of the fifteenth NMOS transistor, and the first terminal of the first capacitor are connected and used to input the startup voltage. The output terminal of the first operational amplifier, the second terminal of the first capacitor, and the gate of the fifteenth NMOS transistor are connected. The drain of the ninth PMOS transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the emitter of the fourth PNP BJT, and the first end of the fourth resistor is used to output the reference voltage.

8. The reference voltage generating circuit according to claim 7, characterized in that, The first operational amplifier includes: a fourteenth PMOS transistor, a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth NMOS transistor; The source of the fourteenth PMOS transistor is connected to the simulated positive voltage. The source of the eighteenth NMOS transistor and the source of the nineteenth NMOS transistor are connected to the simulated negative voltage. The gate of the fourteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor to replicate the bias current; The drain of the fourteenth PMOS transistor, the source of the fifteenth PMOS transistor, and the source of the sixteenth PMOS transistor are connected. The gate of the fifteenth PMOS transistor is the positive input terminal of the first operational amplifier, and the gate of the sixteenth PMOS transistor is the negative input terminal of the first operational amplifier. The drain of the fifteenth PMOS transistor is connected to the source of the seventeenth PMOS transistor, the drain of the sixteenth PMOS transistor is connected to the source of the eighteenth PMOS transistor, and the gate of the seventeenth PMOS transistor is connected to the gate of the eighteenth PMOS transistor. The drain of the seventeenth PMOS transistor, the drain of the sixteenth NMOS transistor, the gate of the eighteenth NMOS transistor, and the gate of the nineteenth NMOS transistor are connected. The drain of the eighteenth PMOS transistor is connected to the drain of the seventeenth NMOS transistor and is used as the output terminal of the first operational amplifier. The source of the sixteenth NMOS transistor is connected to the drain of the eighteenth NMOS transistor, and the source of the seventeenth NMOS transistor is connected to the drain of the nineteenth NMOS transistor. The gates of the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the twelfth NMOS transistor are connected.

9. The reference voltage generating circuit according to claim 7, characterized in that, The first PNP BJT and the second PNP BJT have at least the same base-emitter voltage difference.

10. The reference voltage generating circuit according to claim 8, characterized in that, The bandgap reference module includes: a second startup circuit for starting the bandgap reference core circuit, the second startup circuit including: a first inverter, a second inverter, a nineteenth PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, and at least one of a twenty-fifth PMOS transistor and a twenty-third NMOS transistor; The input terminal of the first inverter is used to input the first start-stop control signal; the output terminal of the first inverter is connected to the input terminal of the second inverter and is used to output the second start-stop control signal; the output terminal of the second inverter is used to output the third start-stop control signal. The source of the nineteenth PMOS transistor, the source of the twenty-fourth PMOS transistor, the source of the twenty-fifth PMOS transistor, and the simulated positive voltage connection are connected. The source of the twentieth NMOS transistor, the source of the twentieth NMOS transistor, the source of the twentieth NMOS transistor, and the simulated negative voltage connection are connected; The gate and drain of the nineteenth PMOS transistor are connected to the source of the twentieth PMOS transistor; the gate and drain of the twentieth PMOS transistor are connected to the source of the twenty-first PMOS transistor; the gate and drain of the twenty-first PMOS transistor are connected to the source of the twenty-second PMOS transistor; the gate and drain of the twenty-second PMOS transistor are connected to the source of the twenty-third PMOS transistor. The gate of the 23rd PMOS transistor is connected to the gate of the 20th NMOS transistor for inputting the reference voltage; The drain of the 23rd PMOS transistor, the drain of the 20th NMOS transistor, and the gate of the 22nd NMOS transistor; The gate of the 24th PMOS transistor is connected to the gate of the 21st NMOS transistor for inputting the second start / stop control signal; The source of the 21st NMOS transistor and the drain of the 22nd NMOS transistor are connected; the drain of the 24th PMOS transistor and the drain of the 21st NMOS transistor are connected to output the startup voltage. The gate of the 25th PMOS transistor is used to input the second start / stop control signal, and the drain of the 25th PMOS transistor is connected to the gate of the 11th PMOS transistor. The gate of the 23rd NMOS transistor is used to input the third start / stop control signal, the drain of the 23rd NMOS transistor is connected to the reference voltage, and the source of the 23rd NMOS transistor is connected to the analog negative voltage. The gate of the seventeenth PMOS transistor is used to input the third start / stop control signal.

11. The reference voltage generating circuit according to claim 7, characterized in that, The compensation current is used to generate a compensated positive temperature coefficient voltage across the fourth resistor in conjunction with the first positive temperature coefficient current. The compensated reference voltage includes the sum of the negative temperature coefficient voltage and the compensated positive temperature coefficient voltage.

12. A radio frequency module, characterized in that, The radio frequency module includes the reference voltage generating circuit according to any one of claims 1 to 11.

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