Non-volatile memory device and data erase method

Abstract

A method for data erasure for a non-volatile memory device is disclosed. The memory includes a plurality of strings of memory cells, each string including a select gate transistor and a plurality of memory cells connected in series. The method includes applying a step erase voltage to one string of memory cells for an erase operation, the step erase voltage having a voltage waveform with a step-up shape. The method also includes raising a voltage of the select gate transistor from a starting level to a peak level and raising a voltage of a predetermined region from a starting level to a peak level during a time period in which the step erase voltage is raised from an intermediate level to the peak level, thereby generating gate-induced drain leakage current in the one string of memory cells. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Description

Technical Field

[0001] This disclosure relates generally to the field of semiconductor technology, and more specifically to non-volatile memory devices and data erasure methods for said non-volatile memory devices. Background Technology

[0002] Recently, non-volatile memory with vertically stacked (i.e., in three dimensions (3D)) memory cells has become widely used in electronic devices. Non-volatile memory devices typically include multiple vertically stacked levels, such as a top level and a bottom level formed by a double-stack process. Each level can include multiple vertically stacked memory cells. For efficient read, write, and erase operations to be implemented in a non-volatile memory device with multiple levels, each level must be able to perform an erase operation independently.

[0003] Furthermore, as the number of stacked layers in non-volatile memory devices increases, the interconnection mode of the bottom structure of the channel layer has evolved from the traditional selective epitaxial structure to a lateral interconnection mode or a bottom interconnection mode. By forming a highly doped semiconductor layer (typically with the same type of doping as the channel layer) at the bottom of the channel layer as the interconnection structure, non-volatile memory devices fabricated using existing methods are unsuitable for a large number of erase operations. Therefore, gate-induced drain leakage (GIDL) is introduced to generate an auxiliary host bias to assist the erase operation at each stage, thereby enabling data erasure in non-volatile memory devices.

[0004] Therefore, it is desirable to improve the efficiency of level erase and GIDL erase operations in non-volatile memory devices. Summary of the Invention

[0005] This disclosure describes embodiments of a three-dimensional (3D) memory device.

[0006] One aspect of this disclosure provides a method for erasing data in a non-volatile memory device. The memory includes a plurality of memory cell strings, each string including at least one select gate transistor and a plurality of memory cells connected in series. The method includes applying a stepped erase voltage to one memory cell string to perform an erase operation, the stepped erase voltage having a voltage waveform with a stepped-up shape. The method further includes: during a time period in which the stepped erase voltage rises from an intermediate level to a peak level, increasing the voltage of the at least one select gate transistor from a starting level to a peak level, and increasing the voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one of the plurality of memory cells.

[0007] In some embodiments, the at least one select gate transistor includes a top select gate (TSG) transistor connected to a bit line and / or a bottom select gate (BSG) transistor connected to a well-doped region in the substrate, and the predetermined region includes a first predetermined region and a second predetermined region, wherein the first predetermined region is adjacent to the BSG transistor and includes at least one of the plurality of memory cells, and the second predetermined region is adjacent to the TSG transistor and includes at least one of the plurality of memory cells.

[0008] In some embodiments, raising the voltage of the at least one select gate transistor and raising the voltage of the predetermined region includes raising the voltage of the predetermined region from the initial level of the predetermined region to the peak level of the predetermined region during a time period in which the voltage of the at least one select gate transistor is raised from the initial level of the at least one select gate transistor to the peak level of the at least one select gate transistor.

[0009] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: simultaneously increasing the voltage of the at least one select gate transistor from its initial level to its peak level and increasing the voltage of the predetermined region from its initial level to its peak level, wherein the peak level of the at least one select gate transistor is equal to the peak level of the predetermined region.

[0010] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the predetermined region from the initial level of the at least one select gate transistor after increasing the voltage of the at least one select gate transistor from the initial level of the at least one select gate transistor.

[0011] In some embodiments, the plurality of memory cells includes at least one dummy memory cell; the at least one dummy memory cell further includes at least one first dummy memory cell located between the BSG transistor and the well-doped region; and the first predetermined region is adjacent to the BSG transistor and includes the at least one dummy memory cell, and is separated from the substrate by the at least one first dummy memory cell.

[0012] In some embodiments, the method further includes setting at least one of the first dummy memory cells to a floating state during the erase operation.

[0013] In some embodiments, the method further includes applying another step erase voltage to at least one of the first dummy memory cells.

[0014] In some embodiments, the at least one dummy memory cell further includes at least one select-level dummy memory cell adjacent to the at least one select-gate transistor.

[0015] In some embodiments, the method further includes: during the time period during which the step erase voltage rises from the intermediate level to the peak level, increasing the voltage of the at least one select-level dummy memory cell from the starting level of the at least one select-level dummy memory cell to the peak level of the at least one select-level dummy memory cell.

[0016] In some embodiments, the method further includes: during a time period in which the voltage of the at least one select-gate transistor is increased from the initial level of the at least one select-gate transistor to the peak level of the at least one select-gate transistor, the voltage of the at least one select-level dummy memory cell is increased from the initial level of the at least one select-gate transistor to the peak level of the at least one select-gate transistor.

[0017] In some embodiments, the method further includes: simultaneously increasing the voltage of the at least one select gate transistor from the start level of the at least one select gate transistor to the peak level of the at least one select gate transistor and increasing the voltage of the at least one select level dummy memory cell from the start level of the at least one select level dummy memory cell to the peak level of the at least one select level dummy memory cell.

[0018] In some embodiments, the method further includes: after increasing the voltage of the at least one select gate transistor from the start level of the at least one select gate transistor, increasing the voltage of the at least one select level dummy memory cell from the start level of the at least one select level dummy memory cell.

[0019] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the first predetermined region from the initial level of the first predetermined region to the peak level of the first predetermined region during a time period in which the voltage of the BSG transistor is increased from the initial level of the BSG transistor to the peak level of the BSG transistor; and increasing the voltage of the second predetermined region from the initial level of the second predetermined region to the peak level of the second predetermined region during a time period in which the voltage of the TSG transistor is increased from the initial level of the TSG transistor to the peak level of the TSG transistor.

[0020] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the first predetermined region from the starting level of the first predetermined region after increasing the voltage of the BSG transistor from the starting level of the BSG transistor; and simultaneously increasing the voltage of the TSG transistor from the starting level of the TSG transistor to the peak level of the TSG transistor and increasing the voltage of the second predetermined region from the starting level of the second predetermined region to the peak level of the second predetermined region.

[0021] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: simultaneously increasing the voltage of the BSG transistor from the start level of the BSG transistor to the peak level of the BSG transistor and increasing the voltage of the first predetermined region from the start level of the first predetermined region to the peak level of the first predetermined region; and after increasing the voltage of the TSG transistor from the start level of the TSG transistor, increasing the voltage of the second predetermined region from the start level of the second predetermined region.

[0022] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: simultaneously increasing the voltage of the BSG transistor from the start level of the BSG transistor to the peak level of the BSG transistor and increasing the voltage of the first predetermined region from the start level of the first predetermined region to the peak level of the first predetermined region; and simultaneously increasing the voltage of the TSG transistor from the start level of the TSG transistor to the peak level of the TSG transistor and increasing the voltage of the second predetermined region from the start level of the second predetermined region to the peak level of the second predetermined region.

[0023] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the first predetermined region from the starting level of the first predetermined region after increasing the voltage of the BSG transistor from the starting level of the BSG transistor; and increasing the voltage of the second predetermined region from the starting level of the second predetermined region after increasing the voltage of the TSG transistor from the starting level of the TSG transistor.

[0024] Another aspect of this disclosure provides a non-volatile memory device comprising: a memory array formed on a well-doped region of a substrate, comprising a plurality of blocks, wherein each block comprises a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells connected in series to corresponding bit lines, and each block comprising one or more stages vertically stacked in a direction perpendicular to the substrate; and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to control stage selection of the plurality of stages, and to perform a stage erase operation and level adjustment as described above on the selected stage.

[0025] In some embodiments, the memory array is a three-dimensional NAND memory array, and the non-volatile memory device is a three-dimensional NAND memory device.

[0026] In some implementations, each block comprises two stages stacked vertically in a direction perpendicular to the substrate.

[0027] In some implementations, each block comprises three or more levels that are vertically stacked in a direction perpendicular to the substrate.

[0028] Another aspect of this disclosure provides a memory system including: the aforementioned memory device; and a controller coupled to the memory device and configured to control the memory device to store data.

[0029] Another aspect of this disclosure provides an electronic device including the aforementioned memory device.

[0030] Other aspects of this disclosure will be understood by those skilled in the art based on the description and accompanying drawings. Attached Figure Description

[0031] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0032] Figure 1 A block diagram of a non-volatile memory device according to some embodiments of the present disclosure is shown.

[0033] Figure 2 A cross-sectional view of a portion of the structure of a non-volatile memory device according to some embodiments of the present disclosure is shown.

[0034] Figure 3 This is a schematic diagram of an equivalent circuit of a 3D memory device according to an embodiment of the present disclosure.

[0035] Figure 4 This is a flowchart of a data erasure method for a non-volatile memory device according to some embodiments of the present disclosure.

[0036] Figure 5 A partial circuit diagram of a non-volatile memory device according to some embodiments of the present disclosure is shown.

[0037] Figure 6 This is a partial circuit diagram of a non-volatile memory device according to some other embodiments of the present disclosure.

[0038] Figure 7-10 11A-11B, 12A-12B, 13A-13B and 14A-14B are voltage waveform timing diagrams of non-volatile memory devices according to various embodiments of the present disclosure.

[0039] Figure 15 This is a schematic structural diagram of a memory system according to some embodiments of the present disclosure.

[0040] Figure 16 This is a schematic structural diagram of an electronic device according to some embodiments of the present disclosure.

[0041] The features and advantages of the invention will become more apparent from the detailed description set forth below, taken in conjunction with the accompanying drawings, in which corresponding elements are consistently indicated by similar reference numerals. In the drawings, similar reference numerals generally indicate equivalent, functionally similar, and / or structurally similar elements. The leftmost numeral in the corresponding reference numerals indicates the first appearance of an element in the drawing.

[0042] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0043] Although specific configurations and arrangements have been discussed, it should be understood that they are for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other disclosures.

[0044] It should be noted that the use of terms such as "one implementation," "implementation," "exemplary implementation," and "some implementations" in the specification indicates that the implementation may include specific features, structures, or characteristics, but not every implementation necessarily includes that specific feature, structure, or characteristic. Furthermore, such wording does not necessarily refer to the same implementation. Additionally, when describing a specific feature, structure, or characteristic in conjunction with an implementation, implementing such a feature, structure, or characteristic in conjunction with other implementations, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0045] Generally, terms can be understood at least partly from their use in context. For example, at least partly depending on the context, the term "one or more" as used herein may be used to describe a feature, structure, or characteristic of a singular meaning, or a combination of features, structures, or characteristics of a plural meaning. Similarly, at least partly depending on the context, terms such as "a," "an," or "the" may be understood to convey either singular or plural usage. Furthermore, the term "based on" may not necessarily be intended to convey an exclusive set of factors; instead, it may allow for the existence of other factors that are not explicitly stated, again at least partly depending on the context.

[0046] It should be understood that the meanings of “on,” “above,” “over,” “connected to,” or “coupled to” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only directly situated on something, but also includes the presence of an intermediate feature or layer when situated on something. Furthermore, “above,” “over,” “connected to,” or “coupled to” means not only “on,” “above,” “connected to,” or “coupled to” something, but may also imply being “on,” “above,” “connected to,” or “coupled to” something without any intermediate feature or layer in between (i.e., directly situated on something). If an element or layer is referred to as “directly on / above / over,” “directly connected to,” or “directly coupled to” another element or layer, then there is no intermediate element or layer. Additionally, the term “connected to” can refer to a physical, electrical, and / or fluid connection with or without intermediate elements.

[0047] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," "above," etc., may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to cover different orientations in the use of the apparatus or in process steps other than those shown in the figures. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted similarly accordingly.

[0048] Throughout the specification, the same reference numerals may denote the same parts. In the drawings, the thickness of layers and areas is exaggerated for clarity.

[0049] As used herein, the terms "first," "second," etc., used to describe various elements do not limit the scope of the elements. For example, these terms can be used to distinguish one element from another. Therefore, "first level" discussed below can be referred to as "second level" without departing from the teachings of one or more embodiments. Describing an element as a "first element" may not require or imply the existence of a "second element" or other elements. The terms "first," "second," etc., can also be used here to distinguish elements of different types or groups. For the sake of brevity, the terms "first," "second," etc., can respectively represent "first type (or first group)," "second type (or second group)," etc.

[0050] As used herein, the term "nominal / nominally" refers to the expected or target value set during the design phase of production or processing for a characteristic or parameter of a component or process step, and the range of values ​​above and / or below the expected value. This range may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" means that the value of a given quantity may vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, the term "approximately" may indicate that the value of a given quantity varies within, for example, 3-15% of that value (e.g., ±5%, ±10% of that value).

[0051] Figure 1 A block diagram of a non-volatile memory 100 according to some embodiments of the present disclosure is shown. For example... Figure 1As shown, the non-volatile memory 100 includes peripheral circuitry 101 and a memory array 102 coupled to the peripheral circuitry 101. In some embodiments, the peripheral circuitry 101 and the memory array 102 may be arranged on a single chip. In other embodiments, the memory array 102 may be arranged on an array chip, and the peripheral circuitry 101 may be arranged on different chips. For example, the peripheral circuitry 101 may be arranged on a complementary metal-oxide-semiconductor (CMOS) chip implemented using CMOS technology. The array chip and the CMOS chip may be electrically coupled together via a bonding process. In some embodiments, the non-volatile memory 100 may be an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0052] The non-volatile memory 100 can be configured to store data in the memory array 102 and perform operations in response to receiving one or more commands (CMDs). In some embodiments, the non-volatile memory 100 can receive one or more write commands, read commands, erase commands, etc., and can perform said one or more operations accordingly.

[0053] In some implementations, the non-volatile memory 100 can receive an erase command with an address, and then one or more memory cells can be reset to an unprogrammed state (also known as an erased state), such as the "1" state of a NAND memory cell, based on the address.

[0054] In some implementations, the memory array 102 may include one or more planes 160, and each plane 160 may include multiple blocks (e.g., Figure 1 The blocks shown are 1 through N. Each block can include multiple vertically stacked levels (e.g., level 1 through level M in block 1, as shown in the diagram). Figure 1 (As shown in the diagram). In some implementations, parallel operations can be performed at different planes 160. In some implementations, each level from level 1 to level M can be a basic unit for performing the erase operation.

[0055] In some embodiments, memory array 102 may be a flash memory array, such as a 3D NAND flash memory array. In some embodiments, peripheral circuitry 101 includes a row decoder circuit 110, a page buffer circuit 120, a data input / output (I / O) circuit 130, a voltage generator 140, and control circuitry 150 coupled to each other. The row decoder circuit 110 is capable of receiving an address, such as a row address (R-ADDR), and generating word line (WL) signals and select signals (e.g., top select gate (TSG) signals, bottom select gate (BSG) signals) based on R-ADDR, and providing the WL signals and select signals to memory array 102. During an erase operation, the row decoder circuit 110 can provide appropriate WL signals and select signals.

[0056] Page buffer circuitry 120 may be coupled to the bit lines (BL) of memory array 102 and may be configured to buffer data during read and write operations. Data I / O circuitry 130 may be coupled to page buffer circuitry 120 via one or more data lines (DL). In some examples (e.g., during write operations), data I / O circuitry 130 may be configured to receive data from external circuitry of non-volatile memory 100 and transmit the received data to memory array 102 via page buffer circuitry 120.

[0057] Voltage generator 140 can be configured to generate various voltage levels for various operations of the non-volatile memory 100. For example, during a data erase operation, voltage generator 140 can generate different voltage levels for bit line voltages, well-doped region voltages, various word line voltages, select voltages, predetermined region voltages, etc. During a data erase operation, voltage generator 140 can help provide step erase voltages to the well-doped regions of the memory array 102. During a data erase operation, voltage generator 140 can further help provide step erase auxiliary voltages to the row decoder circuit 110, enabling the row decoder circuit 110 to output a top select gate signal during the data erase operation. During a data erase operation, voltage generator 140 can further provide peak voltages for predetermined regions to the row decoder circuit 110, enabling the row decoder circuit 110 to output predetermined region signals during the data erase operation. During a data erase operation, voltage generator 140 can further help provide step erase voltages to the page buffer circuit 120, enabling the page buffer circuit 120 to drive bit lines (BLs) during the data erase operation. In some other implementations, voltage generator 140 can help provide step erase voltage to the bit line without going through page buffer circuit 120.

[0058] Control circuitry 150 can be configured to receive commands (CMDs) and addresses (ADDRs). Based on the commands and addresses, control circuitry 150 can be configured to provide control signals to row decoder circuitry 110, page buffer circuitry 120, data I / O circuitry 130, voltage generator 140, and other circuits. For example, control circuitry 150 can generate row address R-ADDR and column address C-ADDR based on address ADDR, provide row address R-ADDR to row decoder 110, and provide column address to data I / O circuitry 130. As another example, control circuitry 150 can control voltage generator 140 to generate different voltage levels based on the received CMD. Control circuitry 150 can coordinate with other circuits to provide signals with appropriate timing and voltage levels to memory array 102.

[0059] Control circuitry 150 may include a first portion 155 configured to generate control signals to control other circuitry to provide appropriate signals to memory array 102, thereby performing an erase operation using a tiered erase mechanism and a GIDL erase mechanism. That is, the first portion of control circuitry 155 may be control circuitry for combining a hybrid erase mechanism of tiered erase and GIDL erase. Control signals with appropriate timing and voltage levels for memory array 102 may use tiered erase and GIDL erase mechanisms for data erase operations on non-volatile memory. References below... Figure 4 to 1 2. Describe the waveform of this control signal in detail.

[0060] Control circuitry 150 may be provided in peripheral circuitry 101. The control logic 150 described herein and the first part 155 of the control circuitry may be implemented by a processor capable of running software modules and / or firmware modules, such as hardware modules of microcontroller units (MCUs) or finite state machines (FSMs), such as integrated circuits (ICs, e.g., application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), etc.) or combinations thereof.

[0061] Figure 2 A cross-sectional view of a portion of the structure of a non-volatile memory 200 according to some embodiments of the present disclosure is shown. For example... Figure 2 As shown in some embodiments of this disclosure, the non-volatile memory 200 may include, for example, a three-dimensional (3D) memory array chip 202 and a peripheral circuit chip 201 electrically coupled together by a bonding process.

[0062] In some embodiments, the non-volatile memory 200 may include a plurality of memory array chips 202 and a plurality of peripheral circuit chips 201. The memory array chip 202 includes a substrate 203 and a stacked structure 290 formed on the substrate 203. The peripheral circuit chip 201 may include a substrate and peripheral circuitry formed on the substrate. It should be noted that, hereinafter, the XY plane is a plane parallel to the main surface of the substrate 203, and the Z direction is perpendicular to the main surface of the substrate 203.

[0063] The substrates of substrate 203 and peripheral circuit chip 201 can be any suitable substrate, such as silicon (Si) substrates, germanium (Ge) substrates, silicon-germanium (SiGe) substrates, and / or silicon-on-insulator (SOI) substrates. In some embodiments, the substrates of substrate 203 and peripheral circuit chip 201 can each comprise the same or different semiconductor materials, such as group IV semiconductor materials, group III-V compound semiconductor materials, group II-VI oxide semiconductor materials, etc. Group IV semiconductor materials can include Si, Ge, or SiGe. Optionally, the substrates of substrate 203 and peripheral circuit chip 201 can each be a bulk wafer or an epitaxial layer.

[0064] The stacked structure 290 may include a plurality of alternately stacked gate layers 295 and a plurality of insulating layers 294. The gate layers 295 may be a laminated structure comprising a metal gate (MG) electrode encased in a gate insulating layer. The gate insulating layer may include any suitable dielectric material, such as a high-dielectric-constant (high-k) material. The insulating layers 294 may include any suitable insulating material, such as silicon nitride and / or silicon dioxide. The plurality of gate layers 295 and the plurality of insulating layers 294 may be configured to form a series of vertically stacked transistors in the Z direction, with each gate layer 295 serving as the gate electrode of a corresponding transistor.

[0065] The non-volatile memory 200 may include one or more memory cell arrays and one or more peripheral circuits (e.g., row decoder circuit 110, page buffer circuit 120, data I / O circuit 130, voltage generator 140, control circuit 150, etc.). One or more peripheral circuits may be formed on peripheral circuit chip 201, and one or more memory cell arrays may be formed on memory array chip 202. Memory array chip 202 may include a core region 01 and a stepped region 02. One or more memory cell arrays may be formed in the core region 01 of the stacked structure 290, and each may include multiple vertical memory cell strings 280. The stepped region 02 may be configured to form contact structures to connect the gates of memory cells, the gates of select gate transistors, etc., in the memory cell strings 280. The gates of memory cells in the memory cell strings 280 may be used as word lines (WL) in the memory architecture.

[0066] Each memory cell string 280 may include a channel structure 281 that passes through the stack body structure 290 and extends vertically (along the Z direction) into the substrate 203. That is, the channel structure 281 and the stack body structure 290 together form the memory cell string 280.

[0067] The channel structure 281 may include a functional layer and a semiconductor layer, both having a circular shape in the XY plane and extending into the substrate 203 in the Z direction. The functional layer may include a barrier layer (e.g., a silicon oxide layer), a charge storage layer (e.g., a silicon nitride layer), and a tunnel insulating layer (e.g., a silicon oxide layer). The semiconductor layer may include any suitable semiconductor material, such as polycrystalline silicon or single crystal. The semiconductor material may be undoped or doped with P-type or N-type impurities. In some embodiments, the barrier layer may be formed on the sidewalls of the channel vias used to form the channel structure 281. The channel vias may penetrate the stack structure 290 and extend into the substrate 203. The charge storage layer, tunnel insulating layer, semiconductor layer, and insulating fill structure may be sequentially formed on the sidewalls of the barrier layer. The insulating fill structure may include any suitable insulating material, such as silicon oxide and / or silicon nitride, and / or may include one or more air gaps.

[0068] Substrate 203 may include a well-doped region 205, which may be a highly doped semiconductor layer for forming electrical connections with semiconductor layers in channel structure 281. In some embodiments, the well-doped region 205 may be electrically connected to the bottom surface of the semiconductor layer in channel structure 281. In some other embodiments, the well-doped region 205 may be electrically connected to the sidewalls of the semiconductor layer in channel structure 281. In some other embodiments, the well-doped region 205 may be electrically connected to both the sidewalls and the bottom surface of the semiconductor layer in structure 281.

[0069] The well-doped region 205 can be formed as a source electrode conductive connection of the memory cell string 280. The well-doped region 205 may include one or more layers and may be made of one or more silicon materials, such as intrinsic polysilicon, N-type doped silicon, or P-type doped silicon. In some embodiments, the well-doped region 205 may include metal silicides to improve conductivity. The well-doped region 205 can be conductively connected to the sources of multiple memory cell strings 280 to form an array common source (ACS). In some embodiments, when the memory cell string 280 is configured to perform level erase operations, the well-doped region 205 may extend and cover the core region and step region of the block including the level corresponding to the level erase operation.

[0070] In some embodiments, the vertically stacked transistors formed by the gate layer 295 and the insulating layer 294 may include memory cells (also referred to as "memory cell transistors") and select gate transistors (e.g., one or more bottom select gates (BSGs) or top select gates (TSGs)). The semiconductor layer of the channel structure 281 described above may serve as the channel for the transistors in the memory cell string 280, and the gate layer 295 may serve as the gate for the transistors in the memory cell string 280.

[0071] Memory cells can have different threshold voltages based on the capture of charge carriers in a portion of the charge storage layer of channel structure 281. This portion of the charge storage layer can act as the floating gate of the memory cell. When a large number of holes are captured (stored) in the floating gate of the memory cell transistor, the threshold voltage of the memory cell transistor is lower than a predefined value, causing the memory cell transistor to be in an unprogrammed state (or erased state) corresponding to logic "1". When holes leak from the floating gate of the memory cell transistor, the threshold voltage of the memory cell is higher than a predefined value, causing the memory cell transistor to be in a programmed state corresponding to logic "0".

[0072] A memory cell transistor may include a control gate configured to control a channel, and includes a drain and a source on each side of the channel. In some embodiments, the upper side of the transistor channel may be used as the drain, and the lower side of the transistor channel may be used as the source. In some other embodiments, the drain and source may be swapped under certain drive configurations. In some embodiments, a TSG transistor may be connected to the upper drain of the memory cell transistor, and a BSG transistor may be connected to the lower source of the memory cell transistor.

[0073] One or more TSG transistors can be configured to couple / decouple memory cells in memory cell string 280 from bit lines. One or more BSG transistors can be configured to couple / decouple memory cells in memory cell string 280 from ACS.

[0074] Each BSG transistor can be controlled by its corresponding BSG. When the voltage applied to the BSG is greater than its threshold voltage, the BSG transistor is turned on, and the memory cell is coupled to the ACS. When the voltage applied to the BSG is less than its threshold voltage, the BSG transistor is turned off, and the memory cell is decoupled from the ACS. Similarly, each TSG transistor can be controlled by its corresponding TSG.

[0075] In some implementations, BSG transistors and TSG transistors may be referred to as select gate transistors.

[0076] In some embodiments, each channel structure 281 may have a cylindrical shape. Multiple channel structures 281 may be arranged independently of each other in the XY plane to form a memory cell array. The array of channel structures 281 may have any suitable array shape, such as a matrix array shape along the X and / or Y directions, a zigzag array shape along the X and / or Y directions, a honeycomb (e.g., hexagonal) array shape in the XY plane, etc. The memory cell array may be divided into multiple blocks by multiple gate line gap (GLS) structures 270, each GLS structure having a distance in the X direction from its adjacent channel structure 281. Each block may include multiple stages stacked along the Z direction. That is, multiple memory cell strings 280 may be formed as blocks, each block may include multiple stages stacked perpendicularly along the Z direction perpendicular to the top surface of the substrate 203. Therefore, a memory cell string 280 may include multiple memory cell substrings located at different stages.

[0077] In some implementations, one or more redundancy levels can be set among multiple levels. Each redundancy level may include at least one dummy memory cell. The dummy memory cell and the memory cell can be formed simultaneously using the same process. The dummy memory cell can be used for process and electrical buffering.

[0078] Figure 3 A schematic diagram of an equivalent circuit of a portion of a 3D memory device 300 according to an embodiment of the present disclosure is shown.

[0079] like Figure 3 As shown, in some embodiments, the 3D memory device 300 may include multiple blocks, each block may include two levels or double stacks, such as a top level 452 and a bottom level 450. The 3D memory device 300 may also include multiple memory cell strings 212, each having multiple stacked memory cells 340. Each memory cell string 212 may include multiple memory cell substrings located at different levels. Memory cell substrings located in the bottom level 450 may include memory cells 340-1 from the lower group, and memory cell substrings located in the top level 452 may include memory cells 340-2 from the upper group.

[0080] The 3D memory device 300 may further include a conductive plug 460 located between the top stage 452 and the bottom stage 450. Thus, in the two-stage 3D memory device 300, memory cells 340-2 in the top stage 452 may be electrically connected to memory cells 340-1 in the bottom stage 450 to form a memory cell string 212. The memory cell string 212 may include at least one field-effect transistor (FET, e.g., MOSFET) at both ends. At least two FETs may be controlled by BSG 332 and TSG 334, respectively. The two corresponding transistors may be referred to as BSG transistor 332-T and BSG transistor 334-T. The stacked memory cells 340 may be controlled by a plurality of control gates 333. The control gates 333 may include a lower group control gate 333-1 corresponding to the lower group memory cells 340-1, and an upper group control gate 333-2 corresponding to the upper group memory cells 340-2. The plurality of control gates 333 may be connected to word lines (WL, not shown) of the 3D memory device 300. The drain of TSG transistor 334-T can be connected to bit line 341, and the source of BSG transistor 332-T can be connected to the well-doped region. The array common source (ACS) 464 can be formed by the well-doped region and can be shared by multiple memory cell strings 212 in the block.

[0081] In a non-volatile memory device, memory cells in each row of each level can be connected to the same word line (WL), and strings of memory cells in each column can be connected to the same bit line (BL). Each WL can correspond to a page. A block can include multiple pages, and a plane can include multiple blocks. Furthermore, in a non-volatile memory device with multiple levels / layers, each level can be processed independently for efficient read, write, and / or erase operations. For example, each level in a 3D non-volatile memory device can perform an erase operation independently of other levels. Additionally, read and write operations can be performed within memory pages, where a memory page comprises multiple memory cells sharing a WL.

[0082] The above describes an exemplary structure of a 3D non-volatile memory device comprising two stages. In the following description, an exemplary data erasure method for a 3D non-volatile memory device is described in detail with reference to the accompanying drawings, according to some embodiments of the present disclosure.

[0083] Figure 4 This is a flowchart of a data erasure method 1000 for a non-volatile memory device according to some embodiments of this disclosure. For example... Figure 4 As shown, the data erasure method 1000 for non-volatile memory may include the following steps.

[0084] In step S1, a step-erase voltage can be applied to the memory cell string to perform an erase operation. The step-erase voltage can have a voltage waveform with a step-increasing shape.

[0085] In step S2, during the time period when the step erase voltage rises from the intermediate level to the peak level, the voltage of the select gate transistor of the memory cell string can be increased from the starting level to a first predetermined peak level, and the voltage of a predetermined region can be increased from the starting level to a second predetermined peak level. This generates a gate-induced drain leakage current in the memory cell string. The predetermined region may be adjacent to the select gate transistor of the memory cell string and may include at least one memory cell.

[0086] The two steps are described in detail below so that those skilled in the art can more clearly understand the specific implementation of method 1000.

[0087] Step S1 : Figure 5 This is a partial circuit diagram of a non-volatile memory device according to some embodiments of the present disclosure. Figure 6 This is a partial circuit diagram of a non-volatile memory device according to some other embodiments of the present disclosure.

[0088] In step S1, the non-volatile memory device may include multiple blocks. For example... Figure 5 As shown, the block may include a memory cell string 212, which includes a top level 452 and a bottom level 450. Either of the two levels of the memory cell string 212 to be erased may be selected as the first level to perform a level erase operation. The entire block including the memory cell string 212 may also be selected to perform a data erase operation. The level erase operation is applied to at least one level of the block instead of the entire block.

[0089] In some embodiments of this disclosure, the memory cell string 212 may include a plurality of memory cells, TSG transistors 334-T, and BSG transistors 332-T sequentially connected in the string. Figure 5 and 6 In this context, TSG can represent the electrical signal applied to TSG to control TSG transistor 334-T, and BSG can represent the electrical signal applied to BSG to control BSG transistor 332-T.

[0090] In some implementations, one or more redundant levels can be provided between multiple levels. One or more redundant levels may include at least one dummy memory cell (e.g., an IDPDMY located between top level 452 and bottom level 450). The dummy memory cell and the memory cell can be formed simultaneously using the same process. The dummy memory cell can be used for process and electrical buffering.

[0091] In some embodiments of this disclosure, the memory cell string 212 may include a top selection stage comprising at least one TSG transistor 334-T. In some embodiments, the top selection stage may include at least one TSG transistor 334-T and at least one TSG dummy memory cell 334'. At least one TSG transistor 334-T and at least one TSG dummy memory cell 334' may be formed simultaneously using the same process and are used for process and electrical buffering. Figure 5 and 6 In this context, TSG_DMY can represent the electrical signal applied to the gate of the TSG dummy memory cell 334'.

[0092] Similarly, in some embodiments of this disclosure, the memory cell string 212 may further include a bottom select stage comprising at least one BSG transistor 332-T. In some embodiments, the bottom select stage may include at least one BSG transistor 332-T and at least one BSG dummy memory cell 332'. At least one BSG transistor 332-T and at least one BSG dummy memory cell 332' may be formed simultaneously using the same process and are used for process and electrical buffering. Figure 5 and 6 In this context, BSG_DMY can represent the electrical signal applied to the gate of the BSG dummy memory cell 332'.

[0093] TSG virtual memory cell 334' and BSG virtual memory cell 332' can be referred to as selection-level virtual memory cells.

[0094] like Figure 6 As shown, the memory cell string 212 may further include a redundant layer located between the BSG transistor 332-T and the well-doped region 205 of the substrate. The redundant layer may include at least one first dummy memory cell 205'. At least one first dummy memory cell 205' and multiple memory cells may be formed simultaneously using the same process and are used for process and electrical buffering. Figure 6 In this context, DMY can represent an electrical signal applied to a predetermined region of the redundancy layer that includes the dummy memory cell 205'.

[0095] Figure 7-10 This is a voltage waveform timing diagram of a non-volatile memory device according to various embodiments of the present disclosure.

[0096] As described above, the interconnection mode of the bottom structure of the channel layer has evolved from the traditional epitaxial structure to either a lateral interconnection mode or a bottom interconnection mode. By forming a highly doped semiconductor layer (typically with the same type of doping as the channel layer) at the bottom of the channel layer as the interconnection structure, non-volatile memory devices fabricated using existing methods are unsuitable for a large number of erase operations. Therefore, gate-induced drain leakage (GIDL) is introduced to generate an auxiliary host bias to assist the erase operation at each stage, thereby enabling data erasure in non-volatile memory devices.

[0097] However, as the number of stacked layers in non-volatile memory devices continues to increase, it becomes difficult for erased carriers to reach the memory cells to be operated, thus making effective GIDL erasure difficult.

[0098] The method for erasing non-volatile memory provided in this disclosure can be implemented by applying an auxiliary voltage of a predetermined peak level to a select gate transistor and a predetermined region adjacent to the select gate transistor during a second time period of a data erase operation. Gate-induced drain leakage current can be generated in one or more memory cell strings for one or more data erase operations, thereby enabling efficient stage erase operations and / or gate-induced drain leakage erase operations.

[0099] Specifically, such as Figures 5 to 10 As shown, a step-erase voltage with a stepped-increment shape can be applied to multiple memory cell strings to perform a data erasure operation. For example, an electrical signal with a step-erase voltage can be applied to the bit line 341 corresponding to the memory cell string 212 and to the well-doped region 205, respectively.

[0100] exist Figure 7 In one example shown, BL can represent an electrical signal applied to bit line 341, and HVNW can represent an electrical signal applied to well-doped region 205. The step-erase voltage can have a voltage waveform with a stepped-up shape, including a first step and a second step. The first step spans a first time period from T0 to T2, during which the voltage rises from a starting level to an intermediate level (Vepre). The second step spans a second time period from T2 to T3, during which the voltage rises from the intermediate level (Vepre) to a peak level (Vers). In some implementations, the value of the intermediate level (Vepre) can be in the range of approximately 1 volt to approximately 4 volts (e.g., 1.5 volts, 2 volts, 2.5 volts, or 3 volts), and the value of the peak level (Vers) can be in the range of approximately 16 volts to approximately 22 volts (e.g., 18 volts, 19 volts, or 20 volts). The second time period from T2 to T3 can be in the range of approximately 0.4 milliseconds to approximately 0.9 milliseconds (e.g., 0.5 milliseconds).

[0101] WL can represent the electrical signal applied to the gates of multiple memory cells in the memory cell string 212. Figures 7 to 10 The diagram shows the voltage waveform timing when a data erase operation is performed on the entire memory block, including the memory cell string 212. When performing a data erase operation on the entire memory block, the gates of all memory cells to be erased in the memory block can be grounded or connected to a low voltage level.

[0102] In some embodiments, the data erasure operations provided in this disclosure can also be applied to level data erasure operations. When a level data erasure operation is performed, the gate of the memory cell to be erased in a level can be grounded or connected to a low voltage level. Simultaneously, the gates of memory cells in other levels that are not undergoing erasure operations can be set to a floating state. This occurs when the circuitry of other levels not undergoing erasure operations is in a floating state and does not perform any circuit interconnection functions. Those skilled in the art will understand that in this disclosure, when a component (or part, component, member, etc.) is in a floating state, such a component (or part, component, member, etc.) does not form an electrical path with other components (or parts, components, members, etc.).

[0103] Step S2: refer to Figure 5 and 7 -10. Step S2 is described in detail below. In step S2, during the time period when the step erase voltage rises from the intermediate level to the peak level, the voltage of the select gate transistor of the memory cell string can be increased from the starting level to a first predetermined peak level, and the voltage of a predetermined region can be increased from the starting level to a second predetermined peak level. This generates a gate-induced drain leakage current in the memory cell string. The predetermined region may be adjacent to the select gate transistor of the memory cell string and may include at least one memory cell.

[0104] In some implementations, step S2 may further include the following operation: During the time period in which the voltages of the select gate transistors (e.g., TSG transistor 334-T and BST transistor 332-T) are increased from a starting level to a peak level (e.g., Vtsg and Vbsg), the voltages of predetermined regions of the memory cell string (e.g., first predetermined region 101 and second predetermined region 102) may be increased from a starting level to a second peak level (e.g., Vgidl_0 or Vgidl_1).

[0105] That is, during the time period when the voltage of BSG transistor 332-T is increased from the initial level to the peak level Vbsg, the voltage of the first predetermined region 101 can be increased from the initial level to the peak level Vgidl_0. Alternatively, during the time period when the voltage of TSG transistor 334-T is increased from the initial level to the peak level Vtsg, the voltage of the second predetermined region 102 can be increased from the initial level to the peak level Vgidl_1.

[0106] Specifically, such as Figure 5 As shown, in some embodiments of this disclosure, the select gate transistor may include a top select gate transistor 334-T connected to bit line 341 and a bottom select gate transistor 332-T connected to a well-doped region 205 in the substrate. Accordingly, the predetermined regions may include at least a first predetermined region 101 and a second predetermined region 102. The first predetermined region 101 is adjacent to the BSG transistor 332-T and includes at least one memory cell. The second predetermined region 102 is adjacent to the TSG transistor 334-T and includes at least one memory cell. It should be noted that the memory cell included in each predetermined region (e.g., the first predetermined region 101 and the second predetermined region 102) may be a dummy memory cell. Figure 5 In this context, GIDL represents an electrical signal applied to the gate of a memory cell in a predetermined region.

[0107] refer to Figure 5 and 7 -10, during the time period from T2 to T3 when electrical signals BL and HVNW rise from the intermediate level Vepre to the peak level Vers, the electrical signal TSG applied to TSG transistor 334-T can rise from the initial level to the peak level Vtsg, and the electrical signal BSG applied to BSG transistor 332-T can rise from the initial level to the peak level (e.g., when BSG and GIDL have the same waveform, such as...). Figure 7 and 10 The Vgidl_0 shown, or when BSG and GIDL have different waveforms, as shown Figure 8 and 9 The Vbsg shown is used in some implementations. The starting level of the TSG transistor 334-T and the BSG transistor 332-T can be approximately 0 volts, and the peak levels Vtsg and Vbsg can be in the range of approximately 2 volts to 12 volts (e.g., 5 volts, 7 volts, 9 volts or 11 volts).

[0108] Furthermore, during the time period from T2 to T3, the electrical signal GIDL applied to the first predetermined region 101 and the second predetermined region 102 can respectively rise from an initial level to a peak level Vgidl. In some embodiments, the initial level of the first and second predetermined regions can be approximately 0 volts, and the value of the peak level Vgidl can be in the range of approximately 8 volts to 15 volts (e.g., 9 volts, 10 volts, or 14 volts).

[0109] During the second time period, by applying auxiliary voltages (e.g., Vtsg, Vbsg, Vgidl) to the select gate transistor of the memory cell string and a predetermined region adjacent to the select gate transistor, gate-induced drain leakage current can be generated to achieve high-efficiency non-volatile memory-level erase operation and gate-induced drain leakage erase operation.

[0110] In some embodiments, the voltage of the select gate transistor (e.g., TSG transistor 334-T and BSG transistor 332-T) can be increased from a starting level to a peak level (e.g., Vtsg, Vbsg). Simultaneously, the voltage of a predetermined region of the memory cell string 212 (e.g., first predetermined region 101 and second predetermined region 102) can be increased from the starting level to a peak level Vgidl. In some embodiments, the peak levels Vtsg, Vbsg, and Vgidl can have the same value. It should be noted that by simultaneously applying auxiliary voltages (e.g., Vtsg, Vbsg, Vgidl) to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor, the control circuitry of the non-volatile memory can be simplified, and the operability of the data erasure operation of the non-volatile memory can be improved.

[0111] In some other embodiments, after the voltage of the select gate transistors (e.g., TSG transistor 334-T and BSG transistor 332-T) is increased from a starting level to a peak level (e.g., Vtsg, Vbsg), the voltage of a predetermined region of the memory cell string 212 (e.g., the first predetermined region 101 and the second predetermined region 102) can then be increased from the starting level to the peak level Vgidl. It should be noted that by applying auxiliary voltages (e.g., Vtsg, Vbsg, Vgidl) to the select gate transistors of the memory cell string and the predetermined regions adjacent to the select gate transistors, respectively, the switching performance of the select gate transistors, which act as select switches for the memory cell string, can be improved, and crosstalk and leakage between adjacent memory cell strings can be avoided.

[0112] In such Figure 7In some embodiments illustrated by the dashed circle, in the top stage 452, after raising the voltage of the TSG transistor 334-T from its initial level, the voltage of the second predetermined region 102 can also be raised from its initial level. The interval between these two operations can be in the range of approximately 0.1 milliseconds to approximately 0.3 milliseconds. After the operation, the voltage of the TSG transistor 334-T can be raised to a predetermined peak level Vtsg, and the voltage of the second predetermined region 102 can be raised to a predetermined peak level Vgidl_1. In the bottom stage 450, while raising the voltage of the BSG transistor 332-T from its initial level to the predetermined peak level Vbsg, the voltage of the first predetermined region 101 can also be raised from its initial level to the predetermined peak level Vgidl_0 simultaneously. These two operations can be performed simultaneously, and the predetermined peak level Vbsg can be equal to the predetermined peak level Vgidl_0.

[0113] In such Figure 8 In some other embodiments, as shown by the dashed circle, in the top stage 452, the voltage of the second predetermined region 102 can be simultaneously increased from the starting level while the voltage of the TSG transistor 334-T is increased from the starting level. After this, the voltage of the TSG transistor 334-T can be increased to a predetermined peak level Vtsg, and the voltage of the second predetermined region 102 can also be increased to a predetermined peak level Vgidl_1. These two operations can be performed simultaneously, and the predetermined peak level Vtsg can be equal to the predetermined peak level Vgidl_1. In the bottom stage 450, after the voltage of the BSG transistor 332-T is increased from the starting level to the predetermined peak level Vbsg, the voltage of the first predetermined region 101 can then be increased from the starting level to the predetermined peak level Vgidl_0. The interval between these two operations can be in the range of approximately 0.1 milliseconds to approximately 0.3 milliseconds. After the operation, the voltage of the BSG transistor 332-T can be increased to a predetermined peak level Vbsg, and the voltage of the first predetermined region 101 can be increased to a predetermined peak level Vgidl.

[0114] In such Figure 9In some other embodiments, as shown by the dashed circle, in the top stage 452, after the voltage of the TSG transistor 334-T is raised from the start level, the voltage of the second predetermined region 102 can be raised from the start level. The interval between these two operations can be in the range of approximately 0.1 milliseconds to approximately 0.3 milliseconds. After the operation, the voltage of the TSG transistor 334-T can be raised to a predetermined peak level Vtsg, and the voltage of the second predetermined region 102 can be raised to a predetermined peak level Vgidl. In the bottom stage 450, after the voltage of the BSG transistor 332-T is raised from the start level to the predetermined peak level Vbsg, the voltage of the first predetermined region 101 can then be raised from the start level to the predetermined peak level Vgidl. The interval between these two operations can be in the range of approximately 0.1 milliseconds to approximately 0.3 milliseconds. After the operation, the voltage of the BSG transistor 332-T can be raised to the predetermined peak level Vbsg, and the voltage of the first predetermined region 101 can be raised to the predetermined peak level Vgidl.

[0115] In such Figure 10 In some other embodiments, as shown by the dashed circle, in the top stage 452, while raising the voltage of the TSG transistor 334-T from its starting level, the voltage of the second predetermined region 102 can be raised from its starting level simultaneously. Afterward, the voltage of the TSG transistor 334-T can be raised to a predetermined peak level Vtsg, and the voltage of the second predetermined region 102 can also be raised to a predetermined peak level Vgidl. These two operations can be performed simultaneously, and the predetermined peak level Vtsg can be equal to the predetermined peak level Vgidl. In the bottom stage 450, while raising the voltage of the BSG transistor 332-T from its starting level to a predetermined peak level Vbsg, the voltage of the first predetermined region 101 can also be raised from its starting level to the predetermined peak level Vgidl simultaneously. These two operations can be performed simultaneously, and the predetermined peak level Vbsg can be equal to the predetermined peak level Vgidl.

[0116] Refer again Figure 5 and 7 -10. In some embodiments of this disclosure, the memory cell string 212 may further include one or more dummy memory cells. The one or more dummy memory cells may include a bottom dummy memory cell 332' adjacent to the BSG transistor 332-T and a top dummy memory cell 334' adjacent to the TSG transistor 334-T. The dummy memory cells may be formed simultaneously with the formation of the select gate transistor and may be used for process and electrical buffering.

[0117] In some embodiments, during the time period from T2 to T3 during which the electrical signals BL and HVNW are raised from the intermediate level Vepre to the peak level Vers, electrical signals TSG_DMY and BSG_DMY can be applied to the top dummy memory cell 334' and the bottom dummy memory cell 332', respectively, so that the voltages of the top dummy memory cell 334' and the bottom dummy memory cell 332' can be raised from the initial level to the peak levels Vtsg_dmy and Vbsg_dmy, respectively. In some embodiments, the initial level values ​​of the top dummy memory cell 334' and the bottom dummy memory cell 332' can be 0 volts, and the values ​​of the peak levels Vtsg_dmy and Vbsg_dmy can be in the range of approximately 2 volts and approximately 12 volts. By applying voltage to the select-stage dummy memory cell adjacent to the select-gate transistor, the gate-induced drain leakage (GIDL) current can be increased due to inter-band tunneling, thereby achieving an efficient GIDL erase operation and improving the data erase efficiency of the non-volatile memory device.

[0118] In some embodiments of this disclosure, during the time period in which the voltages of the select gate transistors (e.g., TSG transistor 334-T and BSG transistor 332-T) are increased from a starting level to a predetermined peak level (e.g., Vtsg and Vbsg), the voltages of the select level dummy memory cells (e.g., top dummy memory cell 334' and bottom dummy memory cell 332') can be increased from a starting level to a peak level (e.g., Vtsg_dmy and Vbsg_dmy).

[0119] In such Figure 7 In one example, the TSG and TSG_DMY curves show that, during the time period from T2 to T3, the operations of applying voltage to the select-level dummy memory cell and applying voltage to the adjacent select-gate transistor can be performed simultaneously. When these two operations are performed sequentially, the control circuitry of the non-volatile memory device can be simplified, and the operability of the data erasure method for the non-volatile memory device can be improved.

[0120] In such Figure 7 In another example shown, during the time period from T2 to T3, the BSG and BSG_DMY curves demonstrate that the operation of applying a voltage to the select-stage dummy memory cell can be performed after applying a voltage to the adjacent select-gate transistor. Performing these two operations separately improves the switching performance of the select-gate transistor, which acts as the selector of the memory cell string, while simultaneously increasing the gate-induced drain leakage current.

[0121] refer to Figure 6 and 9-10. In some embodiments of this disclosure, a redundant layer including at least one first dummy memory cell 205' may be provided between the BSG transistor 332-T and the well-doped region 205 of the substrate. The first dummy memory cell and memory cell in the redundant layer may be formed simultaneously and may be used for process and electrical buffering. In the figures, DMY may represent an electrical signal applied to a predetermined region of the redundant layer including the first dummy memory cell 205'.

[0122] In some embodiments, at least one first dummy memory cell 205' may be arranged between the first predetermined region 101 and the well-doped region 205 of the substrate. This avoids the adverse effects of potential in the first predetermined region caused by process defects in the substrate, and also reduces the adverse effects of gate-induced drain leakage (GIDL) current caused by process defects in the substrate.

[0123] In some implementations, during a data erase operation, the potential of the well-doped region 205 of the substrate can be conducted by setting the first dummy memory cell 205' to a floating state. This simplifies the control circuitry for increasing the GIDL current in a non-volatile memory device and improves the operability of the data erase operation. Specifically, the first dummy memory cell 205' in a floating state can obtain a predetermined peak level of the well-doped region 205 of the substrate via voltage coupling during the data erase operation, thereby avoiding adverse effects due to substrate process defects and achieving better data erase results.

[0124] In some implementations, an electrical signal DMY can be applied directly to the first dummy memory cell 205', which serves as a gap. The electrical signal DMY can have the same step voltage waveform as the step erase voltage applied to the bit line 341 and the well doped region 205 of the substrate.

[0125] According to some embodiments of this disclosure, a first auxiliary voltage can be applied to the select gate transistor of the memory cell string, and a second auxiliary voltage can be applied to a predetermined region adjacent to the select gate transistor. Specifically, when auxiliary voltages are applied to the select gate transistor of the memory cell string and the predetermined region adjacent to the select gate transistor respectively (e.g., after applying the first auxiliary voltage to the select gate transistor of the memory cell string, the second auxiliary voltage is applied to the predetermined region adjacent to the select gate transistor), the switching performance of the select gate transistor, which acts as a selector of the memory cell string, can be improved, and crosstalk and leakage between adjacent memory cell strings can be avoided. When the operation of applying voltage to a dummy memory cell and the operation of applying voltage to an adjacent select gate transistor are performed simultaneously, the control circuit of the non-volatile memory device can be simplified, and the operability of the data erasure method of the non-volatile memory device can be improved.

[0126] Furthermore, according to some embodiments of this disclosure, a predetermined region adjacent to the BSG transistor can be close to the stage arrangement where the data erasure operation is to be performed, thereby increasing the GIDL current and enabling high-efficiency data erasure operation of the non-volatile memory device.

[0127] refer to Figure 11A-11B Voltage waveform timing diagrams of non-volatile memory devices are shown in 12A-12B, 13A-13B and 14A-14B according to various other embodiments of the present disclosure.

[0128] Figure 11A-11B The following diagram illustrates the voltage waveform timing of a non-volatile memory device during a bottom-side GIDL erase operation, according to some embodiments of the present disclosure. Figure 11A and 11B As shown, during the bottom-side GIDL erase operation, the bit line (BL) and top select gate (TSG) can be floating, and the word line (WL) can be kept low (e.g., ground).

[0129] During the first time period from T0 to T1, the high-voltage drift n-well (HVNW) can be ramped up from a low level (e.g., ground) to the intermediate level Vepre. During the second time period from T1 to T2, HVNW can remain at the intermediate level Vepre. During both the first and second time periods from T0 to T2, the dummy top select gate (TSG_DMY), dummy bottom select gate (BSG_DMY), bottom select gate (BSG), and gate-induced drain leakage (GIDL) are all kept low (e.g., ground). During the third time period from T2 to T3, TSG_DMY can be ramped up from a low level (e.g., ground) to a high level Vtsg_dmy, BSG_DMY can be ramped up from a low level (e.g., ground) to a high level Vbsg_dmy, GIDL can be ramped up from a low level (e.g., ground) to a high level Vgidl_0, and HVNW can be ramped up from the intermediate level Vepre to a high level Vers. Figure 11A In some embodiments shown, during the third time period from T2 to T3, BSG can be ramped up from a low level (e.g., ground level) to a high level Vgidl_0, and it can have the same waveform as GIDL. In such... Figure 11B In some other embodiments shown, during the third time period from T2 to T3, BSG can be ramped up from a low level (e.g., ground level) to a high level Vbsg, and it can have a different waveform than GIDL.

[0130] Figure 12A-12B The following diagram illustrates the voltage waveform timing of a non-volatile memory device during a top-side GIDL erase operation, according to some embodiments of the present disclosure. Figure 12A and 12B As shown, during the top-side GIDL erase operation, the bottom select gate (BSG) and high-voltage drift n-well (HVNW) can be in a floating state, and the word line (WL) can be kept at a low level (e.g., ground level).

[0131] During the first time period from T0 to T1, the bit line (BL) can be ramped up from low (e.g., ground) to the intermediate level Vepre. During the second time period from T1 to T2, BL can remain at the intermediate level Vepre. During both the first and second time periods from T0 to T2, the gate-induced drain leakage (GIDL), dummy top select gate (TSG_DMY), dummy bottom select gate (BSG_DMY), and bottom select gate (BSG) are all kept low (e.g., ground). During the third time period from T2 to T3, GIDL can be ramped up from low (e.g., ground) to high level Vgidl_0, TSG_DMY can be ramped up from low (e.g., ground) to high level Vtsg_dmy, and BSG_DMY can be ramped up from low (e.g., ground) to high level Vbsg_dmy. Figure 12A In some embodiments shown, during the third time period from T2 to T3, TSG can be ramped up from a low level (e.g., ground level) to a high level Vgidl_0, and it can have the same waveform as GIDL. In such... Figure 12B In some other embodiments shown, during the third time period from T2 to T3, TSG can be ramped up from a low level (e.g., ground level) to a high level Vtsg, and it can have a different waveform than GIDL.

[0132] Figures 13A-13B The following diagram illustrates the voltage waveform timing of a non-volatile memory device during a bottom-side GIDL erase operation, according to some embodiments of the present disclosure. Figure 13A and 13B As shown, during the bottom-side GIDL erase operation, the bit line (BL), top select gate (TSG), and dummy memory cell 205' (DMY) can be in a floating state, and the word line (WL) can be kept at a low level (e.g., ground level).

[0133] During the first time period from T0 to T1, the high-voltage drift n-well (HVNW) can be ramped up from a low level (e.g., ground) to the intermediate level Vepre. During the second time period from T1 to T2, HVNW can remain at the intermediate level Vepre. During both the first and second time periods from T0 to T2, the dummy top select gate (TSG_DMY), dummy bottom select gate (BSG_DMY), bottom select gate (BSG), and gate-induced drain leakage (GIDL) are all kept low (e.g., ground). During the third time period from T2 to T3, TSG_DMY can be ramped up from a low level (e.g., ground) to a high level Vtsg_dmy, BSG_DMY can be ramped up from a low level (e.g., ground) to a high level Vbsg_dmy, GIDL can be ramped up from a low level (e.g., ground) to a high level Vgidl_0, and HVNW can be ramped up from the intermediate level Vepre to a high level Vers. Figure 13A In some embodiments shown, during the third time period from T2 to T3, BSG can be ramped up from a low level (e.g., ground level) to a high level Vgidl_0, and it can have the same waveform as GIDL. In such... Figure 13B In some other embodiments shown, during the third time period from T2 to T3, BSG can be ramped up from a low level (e.g., ground level) to a high level Vbsg, and it can have a different waveform than GIDL.

[0134] Figures 14A-14B The following diagram illustrates the voltage waveform timing of a non-volatile memory device during a top-side GIDL erase operation, according to some embodiments of the present disclosure. Figure 14A and 14B As shown, during the top-side GIDL erase operation, the bottom select gate (BSG), high-voltage drift n-well (HVNW), and dummy memory cell 205' (DMY) can be in a floating state, and the word line (WL) can be kept at a low level (e.g., ground level).

[0135] During the first time period from T0 to T1, the bit line (BL) can be ramped up from low (e.g., ground) to the intermediate level Vepre. During the second time period from T1 to T2, BL can remain at the intermediate level Vepre. During both the first and second time periods from T0 to T2, the gate-induced drain leakage (GIDL), dummy top select gate (TSG_DMY), dummy bottom select gate (BSG_DMY), and bottom select gate (BSG) are all kept low (e.g., ground). During the third time period from T2 to T3, GIDL can be ramped up from low (e.g., ground) to high level Vgidl_0, TSG_DMY can be ramped up from low (e.g., ground) to high level Vtsg_dmy, and BSG_DMY can be ramped up from low (e.g., ground) to high level Vbsg_dmy. Figure 14A In some embodiments shown, during the third time period from T2 to T3, TSG can be ramped up from a low level (e.g., ground level) to a high level Vgidl_0, and it can have the same waveform as GIDL. In such... Figure 14B In some other embodiments shown, during the third time period from T2 to T3, TSG can be ramped up from a low level (e.g., ground level) to a high level Vtsg, and it can have a different waveform than GIDL.

[0136] Figure 15 This is a schematic structural diagram of a memory system 10000 according to some embodiments of this disclosure. For example... Figure 15 As shown, the memory system 10000 may include a memory device 4000 and a controller 6000. The memory device 4000 may be the same non-volatile memory device described in any of the embodiments above, and will not be repeated here. The memory system 10000 may be a two-dimensional (2D) memory system or a three-dimensional (3D) memory system. The following description uses a 3D memory system as an example.

[0137] The 3D memory system 10000 may include a 3D memory device 4000, a host 5000, and a controller 6000. The 3D memory device 4000 may be the same non-volatile memory device described in any of the embodiments above, and will not be repeated here. The controller 6000 can control the 3D memory device 4000 via channel CH. The 3D memory device 4000 can perform operations based on commands from the controller 6000 in response to requests from the host 5000. The 3D memory device 4000 can receive commands CMD and addresses ADDR from the controller 5000 via channel CH, and is able to access a specific region selected from the memory cell array in response to the address. That is, the 3D memory device 4000 can perform internal operations corresponding to the commands on the region selected based on the address.

[0138] In some implementations, the 3D memory system can take any suitable form, such as a multimedia card, a universal flash storage (UFS) device, a solid-state drive (SSD), MMC, eMMC, RS-MMC, micro MMC, SD, mini SD, micro SD, secure digital card, PCMCIA type storage device, peripheral component interconnect (PCI) type storage device, high-speed PCI (PCI-E) type storage device, compact flash memory (CF) card, smart media card, memory stick, etc.

[0139] Figure 16 This is a schematic structural diagram of an electronic device 20000 according to some embodiments of the present disclosure. As shown in FIG12, the electronic device 20000 may include a memory 4000. The memory 4000 may be the same as the memory described in any of the embodiments above, and will not be repeated here. The electronic device 20000 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle device, wearable device, power bank, or any other device with digital storage function. Therefore, the control module 8000 of the electronic device 20000 can be determined according to the specific device type of the electronic device 20000. The control module 8000 can control the 3D memory device 4000 through various channels. The 3D memory device 4000 can receive commands CMD and addresses ADDR from the control module 8000 through various channels, and access the region selected from the memory cell array based on the address, which is not limited to the present disclosure.

[0140] This disclosure provides a memory, a memory system, and an electronic device. Since the data erasure method for non-volatile memory provided in any of the embodiments described above employs the same method, the data erasure method for non-volatile memory is identical to the data erasure method for non-volatile memory. The beneficial effects will not be repeated here.

[0141] One aspect of this disclosure provides a method for erasing data in a non-volatile memory device. The memory includes a plurality of memory cell strings, each memory cell string including at least one select gate transistor and a plurality of memory cells connected in series. The method includes applying a stepped erase voltage to a memory cell string to perform an erase operation, the stepped erase voltage having a voltage waveform with a stepped-up shape. The method further includes: during a time period in which the stepped erase voltage rises from an intermediate level to a peak level, increasing the voltage of the at least one select gate transistor from a starting level to a peak level, and increasing the voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in a memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one of the plurality of memory cells.

[0142] In some embodiments, the at least one select gate transistor includes a top select gate (TSG) transistor connected to a bit line and / or a bottom select gate (BSG) transistor connected to a well-doped region in the substrate, and the predetermined region includes a first predetermined region and a second predetermined region, wherein the first predetermined region is adjacent to the BSG transistor and includes at least one of the plurality of memory cells, and the second predetermined region is adjacent to the TSG transistor and includes at least one of the plurality of memory cells.

[0143] In some embodiments, raising the voltage of the at least one select gate transistor and raising the voltage of the predetermined region includes raising the voltage of the predetermined region from the initial level of the predetermined region to the peak level of the predetermined region during a time period in which the voltage of the at least one select gate transistor is raised from the initial level of the at least one select gate transistor to the peak level of the at least one select gate transistor.

[0144] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: simultaneously increasing the voltage of the at least one select gate transistor from its initial level to its peak level and increasing the voltage of the predetermined region from its initial level to its peak level, wherein the peak level of the at least one select gate transistor is equal to the peak level of the predetermined region.

[0145] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the predetermined region from the initial level of the at least one select gate transistor after increasing the voltage of the at least one select gate transistor from the initial level of the at least one select gate transistor.

[0146] In some embodiments, the plurality of memory cells includes at least one dummy memory cell; the at least one dummy memory cell further includes at least one first dummy memory cell located between the BSG transistor and the well-doped region; and the first predetermined region is adjacent to the BSG transistor and includes the at least one dummy memory cell, and is separated from the substrate by the at least one first dummy memory cell.

[0147] In some embodiments, the method further includes setting at least one of the first dummy memory cells to a floating state during an erase operation.

[0148] In some embodiments, the method further includes applying another step erase voltage to at least one of the first dummy memory cells.

[0149] In some embodiments, the at least one dummy memory cell further includes at least one select-level dummy memory cell adjacent to the at least one select-gate transistor.

[0150] In some embodiments, the method further includes: during the time period during which the step erase voltage rises from the intermediate level to the peak level, increasing the voltage of the at least one select-level dummy memory cell from the starting level of the at least one select-level dummy memory cell to the peak level of the at least one select-level dummy memory cell.

[0151] In some embodiments, the method further includes: during a time period in which the voltage of the at least one select-gate transistor is increased from the initial level of the at least one select-gate transistor to the peak level of the at least one select-gate transistor, the voltage of the at least one select-level dummy memory cell is increased from the initial level of the at least one select-gate transistor to the peak level of the at least one select-gate transistor.

[0152] In some embodiments, the method further includes: simultaneously increasing the voltage of the at least one select gate transistor from the start level of the at least one select gate transistor to the peak level of the at least one select gate transistor and increasing the voltage of the at least one select level dummy memory cell from the start level of the at least one select level dummy memory cell to the peak level of the at least one select level dummy memory cell.

[0153] In some embodiments, the method further includes: after increasing the voltage of the at least one select gate transistor from the start level of the at least one select gate transistor, increasing the voltage of the at least one select level dummy memory cell from the start level of the at least one select level dummy memory cell.

[0154] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the first predetermined region from the initial level of the first predetermined region to the peak level of the first predetermined region during a time period in which the voltage of the BSG transistor is increased from the initial level of the BSG transistor to the peak level of the BSG transistor; and increasing the voltage of the second predetermined region from the initial level of the second predetermined region to the peak level of the second predetermined region during a time period in which the voltage of the TSG transistor is increased from the initial level of the TSG transistor to the peak level of the TSG transistor.

[0155] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the first predetermined region from the starting level of the first predetermined region after increasing the voltage of the BSG transistor from the starting level of the BSG transistor; and simultaneously increasing the voltage of the TSG transistor from the starting level of the TSG transistor to the peak level of the TSG transistor and increasing the voltage of the second predetermined region from the starting level of the second predetermined region to the peak level of the second predetermined region.

[0156] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: simultaneously increasing the voltage of the BSG transistor from the start level of the BSG transistor to the peak level of the BSG transistor and increasing the voltage of the first predetermined region from the start level of the first predetermined region to the peak level of the first predetermined region; and after increasing the voltage of the TSG transistor from the start level of the TSG transistor, increasing the voltage of the second predetermined region from the start level of the second predetermined region.

[0157] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: simultaneously increasing the voltage of the BSG transistor from the start level of the BSG transistor to the peak level of the BSG transistor and increasing the voltage of the first predetermined region from the start level of the first predetermined region to the peak level of the first predetermined region; and simultaneously increasing the voltage of the TSG transistor from the start level of the TSG transistor to the peak level of the TSG transistor and increasing the voltage of the second predetermined region from the start level of the second predetermined region to the peak level of the second predetermined region.

[0158] In some embodiments, increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region includes: increasing the voltage of the first predetermined region from the starting level of the first predetermined region after increasing the voltage of the BSG transistor from the starting level of the BSG transistor; and increasing the voltage of the second predetermined region from the starting level of the second predetermined region after increasing the voltage of the TSG transistor from the starting level of the TSG transistor.

[0159] Another aspect of this disclosure provides a non-volatile memory device comprising: a memory array formed on a well-doped region of a substrate, comprising a plurality of blocks, wherein each block comprises a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells connected in series to corresponding bit lines, and each block comprising one or more stages vertically stacked in a direction perpendicular to the substrate; and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to control stage selection of the plurality of stages and to perform stage erase operations and level adjustment as described above on the selected stages.

[0160] In some embodiments, the memory array is a three-dimensional NAND memory array, and the non-volatile memory device is a three-dimensional NAND memory device.

[0161] In some implementations, each block comprises two stages stacked vertically in a direction perpendicular to the substrate.

[0162] In some implementations, each block comprises three or more levels that are vertically stacked in a direction perpendicular to the substrate.

[0163] Another aspect of this disclosure provides a memory system including: the aforementioned memory device; and a controller coupled to the memory device and configured to control the memory device to store data.

[0164] Another aspect of this disclosure provides an electronic device including the aforementioned memory device.

[0165] The above description of specific embodiments fully demonstrates the general nature of this disclosure, enabling others to easily modify and / or adjust various disclosures of such specific embodiments using knowledge within the scope of the art without requiring excessive experimentation or departing from the general concept of this disclosure. Therefore, such modifications and adjustments are intended to fall within the meaning and scope of equivalents of the embodiments disclosed herein, based on the disclosures and guidance provided herein. It should be understood that the wording or terminology used herein is for illustrative purposes and not for limitation, and therefore the terminology or terminology in this specification should be interpreted by those skilled in the art in accordance with the disclosures and guidance provided.

[0166] The embodiments of this disclosure have been described above using functional building blocks illustrating the specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined. Alternative boundaries may be defined, provided that their specified functions and relationships are appropriately performed.

[0167] The summary and abstract may describe one or more of the invention conceived by the inventors, but not necessarily all exemplary embodiments, and are therefore not intended to limit the invention and the appended claims in any way.

[0168] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the following claims and their equivalents.

Claims

1. A method for erasing data in a non-volatile memory device, wherein, The memory device includes multiple memory cell strings, each memory cell string including at least one select gate transistor and multiple memory cells connected in series, the method comprising: An erase operation is performed by applying a stepped erase voltage to a string of memory cells, the stepped erase voltage having a voltage waveform with a progressively increasing shape; and During the time period during which the step erase voltage rises from the intermediate level of the step erase voltage to the peak level of the step erase voltage, the voltage of the at least one select gate transistor is increased from the starting level of the at least one select gate transistor to the peak level of the at least one select gate transistor, and the voltage of the predetermined region is increased from the starting level of the predetermined region to the peak level of the predetermined region, such that a gate-induced drain leakage current is generated in the one memory cell string; The predetermined region is adjacent to the at least one select gate transistor and includes at least one of the plurality of memory cells.

2. The method according to claim 1, wherein: The at least one select gate transistor includes a top select gate (TSG) transistor connected to a bit line and / or a bottom select gate (BSG) transistor connected to a well-doped region in the substrate; and The predetermined region includes a first predetermined region and a second predetermined region, wherein the first predetermined region is adjacent to the BSG transistor and includes at least one of the plurality of memory cells, and the second predetermined region is adjacent to the TSG transistor and includes at least one of the plurality of memory cells.

3. The method according to claim 1 or 2, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: During the time period in which the voltage of the at least one selected gate transistor is increased from the initial level of the at least one selected gate transistor to the peak level of the at least one selected gate transistor, the voltage of the predetermined region is increased from the initial level of the predetermined region to the peak level of the predetermined region.

4. The method according to claim 3, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: Simultaneously, the voltage of the at least one selected gate transistor is increased from the starting level of the at least one selected gate transistor to the peak level of the at least one selected gate transistor, and the voltage of the predetermined region is increased from the starting level of the predetermined region to the peak level of the predetermined region, wherein the peak level of the at least one selected gate transistor is equal to the peak level of the predetermined region.

5. The method according to claim 3, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: After increasing the voltage of the at least one selected gate transistor from the starting level of the at least one selected gate transistor, the voltage of the predetermined region is increased from the starting level of the predetermined region.

6. The method according to claim 2, wherein: The plurality of memory units includes at least one dummy memory unit; The at least one dummy memory cell further includes at least one first dummy memory cell located between the BSG transistor and the well-doped region; and The first predetermined region is adjacent to the BSG transistor and includes the at least one dummy memory cell, and is separated from the substrate by the at least one first dummy memory cell.

7. The method according to claim 6, further comprising: At least one of the first dummy memory cells is set to a floating state during the erase operation.

8. The method according to claim 6, further comprising: Another step erase voltage is applied to at least one of the first dummy memory cells.

9. The method according to claim 6, wherein: The at least one dummy memory cell further includes at least one select-level dummy memory cell adjacent to the at least one select-gate transistor; and The method further includes: During the time period during which the step erase voltage rises from the intermediate level to the peak level, the voltage of the at least one select-level dummy memory cell is increased from the initial level of the at least one select-level dummy memory cell to the peak level of the at least one select-level dummy memory cell.

10. The method of claim 9, further comprising: During the time period in which the voltage of the at least one select gate transistor is increased from the initial level of the at least one select gate transistor to the peak level of the at least one select gate transistor, the voltage of the at least one select level dummy memory cell is increased from the initial level of the at least one select level dummy memory cell to the peak level of the at least one select level dummy memory cell.

11. The method of claim 10, further comprising: Simultaneously, the voltage of the at least one select gate transistor is increased from the starting level of the at least one select gate transistor to the peak level of the at least one select gate transistor, and the voltage of the at least one select level dummy memory cell is increased from the starting level of the at least one select level dummy memory cell to the peak level of the at least one select level dummy memory cell.

12. The method of claim 10, further comprising: After increasing the voltage of the at least one select gate transistor from the starting level of the at least one select gate transistor, the voltage of the at least one select level dummy memory cell is increased from the starting level of the at least one select level dummy memory cell.

13. The method according to claim 2, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: During the time period in which the voltage of the BSG transistor is increased from its initial level to its peak level, the voltage of the first predetermined region is increased from its initial level to its peak level. During the time period in which the voltage of the TSG transistor is increased from the starting level of the TSG transistor to the peak level of the TSG transistor, the voltage of the second predetermined region is increased from the starting level of the second predetermined region to the peak level of the second predetermined region.

14. The method according to claim 13, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: After increasing the voltage of the BSG transistor from its initial level, the voltage of the first predetermined region is increased from its initial level; and Simultaneously, the voltage of the TSG transistor is increased from the starting level of the TSG transistor to the peak level of the TSG transistor, and the voltage of the second predetermined region is increased from the starting level of the second predetermined region to the peak level of the second predetermined region.

15. The method according to claim 13, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: Simultaneously, the voltage of the BSG transistor is increased from its initial level to its peak level, and the voltage of the first predetermined region is increased from its initial level to its peak level. After increasing the voltage of the TSG transistor from its initial level, the voltage of the second predetermined region is increased from its initial level.

16. The method according to claim 13, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: Simultaneously, the voltage of the BSG transistor is increased from its initial level to its peak level, and the voltage of the first predetermined region is increased from its initial level to its peak level. Simultaneously, the voltage of the TSG transistor is increased from the starting level of the TSG transistor to the peak level of the TSG transistor, and the voltage of the second predetermined region is increased from the starting level of the second predetermined region to the peak level of the second predetermined region.

17. The method according to claim 13, wherein, Increasing the voltage of the at least one select gate transistor and increasing the voltage of the predetermined region include: After increasing the voltage of the BSG transistor from its initial level, the voltage of the first predetermined region is increased from its initial level; and After increasing the voltage of the TSG transistor from its initial level, the voltage of the second predetermined region is increased from its initial level.

18. A non-volatile memory device, comprising: A memory array formed on a well-doped region of a substrate, the memory array comprising multiple blocks, wherein each block comprises multiple memory cell strings, each memory cell string comprising multiple memory cells connected in series to corresponding bit lines, and each block comprising one or more stages vertically stacked in a direction perpendicular to the substrate; and Peripheral circuitry coupled to the memory array is configured to control level selection of the plurality of levels, and to perform level erase operations and level adjustment as described in any one of claims 1-17 on the selected level.

19. The non-volatile memory device according to claim 18, wherein, The memory array is a three-dimensional NAND memory array, and the non-volatile memory device is a three-dimensional NAND memory device.

20. The non-volatile memory device according to claim 18, wherein, Each block comprises two stages stacked vertically in a direction perpendicular to the substrate.

21. The non-volatile memory device according to claim 18, wherein, Each block comprises three or more levels stacked vertically in a direction perpendicular to the substrate.

22. A memory system, comprising: The memory device according to any one of claims 18-20; as well as A controller, which is coupled to the memory device and configured to control the memory device to store data.

23. An electronic device comprising a memory device according to any one of claims 18-20.

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