Memory stick processing method and device, storage medium and electronic equipment

Abstract

Embodiments of the present application provide a memory stick processing method and device, a storage medium and an electronic device, wherein the method comprises: sequentially reading, by a baseboard management controller of a server, information stored in a first memory of a memory stick inserted in each memory slot in a group of memory slots of the server; in the case that a target memory stick is read and no specified authentication information is stored in the first memory of the target memory stick, setting, by the baseboard management controller, the target memory stick as an unusable memory stick, wherein the unusable memory stick is a memory stick that is not allowed to be identified in the process of running a basic input / output system of the server. The present application solves the problem of poor server running safety caused by the fact that a memory stick can easily cause the server to malfunction, thereby achieving the technical effect of improving the safety and stability of the server.

Description

Technical Field

[0001] This application relates to the field of storage devices, and more specifically, to a method and apparatus for processing memory modules, a storage medium, and an electronic device. Background Technology

[0002] Currently, numerous manufacturers offer memory modules. To expand memory, users can insert purchased memory modules into the memory slots on the server's motherboard. Since memory modules from different manufacturers can use the same memory specifications, the server can recognize and use the inserted memory module when it matches the memory slot's specifications.

[0003] However, there are differences between memory modules provided by different manufacturers. Even if the memory modules can be recognized and used, they can easily cause errors, crashes and other abnormalities in the server during use, thereby reducing the security and reliability of the server operation.

[0004] Therefore, it is evident that the memory module handling methods in related technologies have the problem of poor server security, as memory modules can easily cause abnormalities in the server they are used to. Summary of the Invention

[0005] This application provides a method and apparatus for processing memory modules, a storage medium, and an electronic device, to at least solve the problem in related technologies where memory module processing methods suffer from poor server security due to memory modules easily causing server malfunctions.

[0006] According to one embodiment of this application, a memory module processing method is provided, comprising: sequentially reading information stored in the first memory of a memory module inserted in each memory slot of a set of memory slots of the server through a baseboard management controller; and, if a target memory module is read and the first memory of the target memory module does not store specified authentication information, setting the target memory module as an unusable memory module through the baseboard management controller, wherein the unusable memory module is a memory module that is not allowed to be recognized during the operation of the server's basic input / output system.

[0007] In an exemplary embodiment, the step of sequentially reading information stored in the first memory of the memory module inserted in each memory slot of a set of memory slots of the server through the baseboard management controller includes: sequentially reading the information stored in the first memory of the memory module inserted in each memory slot through the internal integrated bus I2C controller of the baseboard management controller according to a preset I2C address corresponding to each memory slot.

[0008] In an exemplary embodiment, setting the target memory module as an unusable memory module by the baseboard management controller when the target memory module is read and the first memory of the target memory module does not store the specified authentication information includes: when the target memory module is read and the first memory of the target memory module does not store the specified authentication information, setting the input signal of the target improved internal integrated circuit I3C switch corresponding to the target memory module to a first level state by the general input / output controller of the baseboard management controller, so as to disconnect the channel between the memory slot where the target memory module is located and the central processing unit of the server via the target I3C switch, wherein the target memory module is the unusable memory module when the input signal of the target I3C switch is set to the first level state.

[0009] In an exemplary embodiment, the method further includes: when the target memory module is read and the designated authentication information is stored in the first memory of the target memory module, setting the target memory module as a memory module to be identified by the baseboard management controller, wherein the memory module to be identified is a memory module to be identified during the operation of the basic input / output system.

[0010] In an exemplary embodiment, the step of setting the target memory module as a memory module to be identified by the baseboard management controller when the target memory module is read and the specified authentication information is stored in the first memory of the target memory module includes: when the target memory module is read and the specified authentication information is stored in the first memory of the target memory module, setting the input signal of the target improved internal integrated circuit I3C switch corresponding to the target memory module to a second level state by the general-purpose input / output controller of the baseboard management controller, so as to conduct the channel between the memory slot where the target memory module is located and the central processing unit of the server via the target I3C switch, wherein when the input signal of the target I3C switch is set to the second level state, the target memory module is a memory module to be identified.

[0011] In an exemplary embodiment, after the target memory module is set as a memory module to be identified by the baseboard management controller, the method further includes: when all information stored in the first memory of the memory modules inserted in each memory slot has been read, triggering a power-on signal by the baseboard management controller to control the operation of the basic input / output system; when the basic input / output system runs to the memory initialization reference code, sequentially reading the serial presence detection information of the memory modules to be identified inserted in the group of memory slots; when the serial presence detection information of the target memory module is read, performing memory initialization on the target memory module; when the serial presence detection information of the target memory module is not read, setting the target memory module as a disabled memory module, wherein the disabled memory module is a memory module that is prohibited from use.

[0012] In one exemplary embodiment, the target memory module is a fifth-generation memory, the first memory is an electrically erasable programmable read-only memory, the target memory module includes a set of empty pins, five of the empty pins in the set of empty pins are set as address pins, two of the empty pins in the set of empty pins are set as serial data line pins and serial clock line pins respectively, and the specified authentication information is used to identify that the corresponding memory module is a memory module certified by the server manufacturer of the server.

[0013] According to another embodiment of this application, a memory module processing apparatus is provided, comprising: a reading unit, configured to sequentially read information stored in the first memory of a memory module inserted in each memory slot of a group of memory slots in the server via a baseboard management controller; and a setting unit, configured to set the target memory module as an unusable memory module via the baseboard management controller when a target memory module is read and the first memory of the target memory module does not store specified authentication information, wherein the unusable memory module is a memory module that is not allowed to be recognized during the operation of the server's basic input / output system.

[0014] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0015] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0016] This application allows the server's baseboard management controller to read the stored information in the first memory of each memory module in a set of memory slots at a time. This enables the acquisition of information about each memory module and the specified authentication information stored in the first memory of each memory module. If a target memory module is read but its first memory does not store the specified authentication information, the baseboard management controller sets the target memory module as an unusable memory module that cannot be recognized during the operation of the server's basic input / output system. This disables the target memory module when it is found to be unauthenticated, preventing server errors and crashes caused by unauthenticated memory. Therefore, this invention solves the problem of poor server security caused by memory modules easily causing server anomalies, achieving the technical effect of improving server security and stability. Attached Figure Description

[0017] Figure 1 This is a hardware structure block diagram of a server device according to an embodiment of the present application of a memory module processing method;

[0018] Figure 2 This is a flowchart illustrating an optional memory module processing method according to an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of an optional server system architecture according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of an optional I3C switch according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of an optional CPU and DIMM connection according to an embodiment of this application;

[0022] Figure 6 This is a schematic diagram illustrating an optional memory slot, BMC, and CPU connection relationship according to an embodiment of this application;

[0023] Figure 7 This is a schematic diagram of a memory initialization process according to an embodiment of this application;

[0024] Figure 8 This is a schematic diagram of an optional DDR5 RFU pin according to an embodiment of this application;

[0025] Figure 9 This is a schematic diagram of an optional I2C interface EEPROM memory according to an embodiment of this application;

[0026] Figure 10This is a schematic diagram of an optional I2C bus-connected device according to an embodiment of this application;

[0027] Figure 11 This is a schematic diagram of another optional DDR5 RFU pin according to an embodiment of this application;

[0028] Figure 12 This is a flowchart illustrating another optional memory module processing method according to an embodiment of this application;

[0029] Figure 13 This is a structural block diagram of an optional memory module processing device according to an embodiment of this application;

[0030] Figure 14 This is a structural block diagram of a computer system for an optional electronic device according to an embodiment of this application. Detailed Implementation

[0031] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0034] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0035] 1. BIOS (Basic Input Output System) is a set of programs embedded in a memory chip on the motherboard of a computer. It stores the most important basic input and output programs, power-on self-test programs, and system startup programs of the computer.

[0036] 2. MRC (Memory Reference Code): The memory initialization reference code contained in the BIOS.

[0037] 3. DDR5 refers to fifth-generation memory, a computer memory specification. DDR stands for DDR (Double Data Rate) SDRAM (Synchronous Dynamic Random-Access Memory). Compared to DDR4 memory, the DDR5 standard offers stronger performance and lower power consumption.

[0038] 4. RCD (Register Control Device): A control chip used for signal forwarding in memory.

[0039] 5. DIMM (Dual-Inline-Memory-Modules): A new type of memory module that provides a 64-bit data channel.

[0040] 6. RDIMM (Registered DIMM) is a type of memory module. In addition to memory chips, RDIMM also has an RCD chip. RDIMM adds a register to the memory module for data transfer. It is located between the CPU (Central Processing Unit) and the memory chips, which reduces the distance of parallel data transfer while ensuring the effectiveness of parallel data transfer.

[0041] 7. A channel is used to efficiently transfer data between a byte buffer and an entity (usually a file or socket) on the other side of the channel. With a channel, you can access the input or output of the operating system itself with minimal total overhead.

[0042] 8. IMC (integrated memory controller) is an important component of a computer system that controls memory and facilitates data exchange between memory and the CPU.

[0043] 9. EEPROM (Electrically Erasable Programmable Read Only Memory) is a type of memory chip that does not lose data after power is lost (non-volatile memory).

[0044] 10. RFU (Refersed For Used) indicates that the pin function is undefined and not used.

[0045] 11. SCK (Serial Clock) / SCL (Serial Clock Line) are used for communication data synchronization. SCK is generated by the communication host and determines the communication rate; different devices support different maximum clock frequencies.

[0046] 12. SDA (Serial Data) is used to transmit serial data between devices.

[0047] 13. I2C (Inter-Integrated Circuit) is a communication interface that includes the SCK clock and SDA data signal lines.

[0048] 14. I3C (Improved Inter Integrated Circuit): A communication interface that includes an SCK clock line and an SDA data signal line. It offers better speed and reliability and is compatible with I2C.

[0049] 15. DMI (Direct Media Interface) is a bus interface for communication between the CPU and PCH (Platform Controller Hub, integrated southbridge). This bus is used to connect the northbridge and southbridge of the motherboard.

[0050] 16. UPI (Ultra Path Interconnect) is a bus interface used for communication between CPUs and other CPUs.

[0051] The methods and embodiments provided in this application can be executed on a server device or a similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a server device according to an embodiment of the present application, illustrating a method for processing a memory module. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1The different configurations shown.

[0052] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the memory module processing method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0053] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0054] This embodiment provides a method for processing memory modules. Figure 2 This is a flowchart illustrating an optional memory module processing method according to an embodiment of this application, as shown below. Figure 2 As shown, the process includes the following steps:

[0055] Step S202: The information stored in the first memory of the memory module inserted in each memory slot of a set of memory slots in the server is read sequentially by the baseboard management controller of the server.

[0056] The memory module processing method in this embodiment can be applied to scenarios involving the processing of memory modules inserted into a server. Here, a memory module is a type of memory. Memory is an important component of a computer, also known as internal memory or main memory. It is used to temporarily store data processed by the CPU, as well as data exchanged with external storage devices such as hard drives. Memory is used to store the instructions and data of running programs. The operating system and other necessary software are loaded into memory, and during program execution, memory continuously stores the data and instructions needed by the program. Memory provides space for temporary data storage, allowing the computer to quickly read and write data during execution. Temporary storage includes variables of the running program, parameters of function calls, and return values. In terms of computation, storing data in memory can speed up the computer system's data reading and writing operations. It can be inserted into the server's memory slots, improving the system's response speed.

[0057] The BIOS (Basic Input / Output System) is a piece of software code embedded in the computer's motherboard. During computer startup, the BIOS initializes hardware devices and loads the operating system into memory. It loads the operating system and other necessary software from secondary storage into main memory, continuously storing the data and instructions needed by the programs during execution, and finally relinquishes control to the operating system. In terms of memory management, the BIOS manages the allocation and release of system memory. It detects and identifies installed memory modules and records their information in the system configuration table. The BIOS also provides basic memory management functions, such as switching to protected mode and setting memory mapping tables. Therefore, the relationship between memory and BIOS is as follows: the BIOS is responsible for starting the computer and loading the operating system into memory, while the main memory is responsible for storing the data and instructions of the operating system and other running programs. The cooperation between memory and BIOS is a crucial component for the normal operation of a server system.

[0058] As a storage device, memory requires initialization upon power-on so that the CPU can read and write data through designated interfaces. To improve the ease of memory capacity adjustment (e.g., memory expansion), the server can be equipped with a set of memory slots, each allowing one memory module to be inserted. Different memory slots can accommodate one or more types of memory modules; this embodiment does not limit this. Currently, numerous manufacturers provide memory modules. For memory expansion or other purposes, users can insert purchased memory modules into the memory slots on the server's motherboard. However, because each manufacturer tests application memory differently, memory modules tested by each manufacturer may not be compatible with the server.

[0059] Since memory modules from different manufacturers may use the same memory specifications, the server can recognize and use the inserted memory module when it matches the memory slot's specifications. However, differences exist between memory modules from different manufacturers. Even if the memory module can be recognized and used, its use can easily lead to errors, crashes, and other anomalies on the server, reducing the server's security and reliability.

[0060] Taking DDR5 as an example, since there are many manufacturers providing DDR5 memory, OEM (Original Equipment Manufacturer) server manufacturers have special testing and adaptation processes for using their own tested and certified memory (hereinafter referred to as certified memory) with their servers, thus ensuring server reliability. For DDR5 memory purchased by users themselves, OEM manufacturers do not want users to use their own DDR5 memory for compatibility and reliability reasons. This is because memory not certified and tested by server manufacturers can generally be initialized and used on a machine as long as the interface is compatible with the DDR5 specification. However, uncertified memory can easily lead to server errors and downtime during use.

[0061] To at least partially address the aforementioned technical issues, in this embodiment, for certified memory modules, specific certification information can be stored in a designated memory location. Whether the memory module is certified (i.e., whether it is certified memory, or a certified memory module) is determined by whether the specified certification information is read from the designated memory location. If the memory module is not certified, it will not be recognized during server BIOS operation, thus preventing server errors, crashes, and other anomalies caused by using uncertified memory modules, thereby improving server security and reliability. This method effectively identifies non-OEM memory and excludes it during startup.

[0062] A server may contain a set of memory slots, each of which may or may not contain a memory module. During server startup or at other times, before the BIOS runs, the server's Baseboard Management Controller (BMC) determines whether the memory modules inserted in at least some of the memory slots are certified memory modules. Optionally, the Baseboard Management Controller sequentially reads information stored in the first memory of each memory module inserted in each memory slot. The inserted memory modules can be DIMM, DDR4, DDR5, etc., or other types of memory modules; this embodiment does not limit this.

[0063] In some memory slots, no memory modules may be inserted, and the baseboard management controller will not read any information. In this scenario, the baseboard management controller can sequentially determine whether a memory module is inserted in each memory slot. If no memory module is inserted in the currently determined memory slot, the controller skips that slot. If a memory module is inserted in the currently determined memory slot, the baseboard management controller retrieves the information stored in the first memory of the memory module inserted in that slot. The first memory can be any predetermined memory, as long as the baseboard management controller can determine which memory of the memory module to read the information from. The purpose of reading the information here is to determine whether the information stored in the first memory of the memory module inserted in each memory slot contains specified authentication information. This specified authentication information can be authentication information provided by the server manufacturer, which can be used to indicate that the corresponding memory module has been certified by the server manufacturer. For example, the memory module's identification number and model, the server manufacturer's identification, etc., or other authentication information, which is not limited in this embodiment.

[0064] For example, during the memory production stage, OEM DDR5 memory certification information (referred to as certification information) can be written into the first memory of each certified memory module.

[0065] In step S204, if the target memory module is read and the first memory of the target memory module does not store the specified authentication information, the target memory module is set as an unusable memory module by the baseboard management controller.

[0066] The memory module currently read by the baseboard management controller is the target memory module, which can be a memory module inserted in any of the memory slots in a set of memory slots. If the target memory module's first memory does not store the specified authentication information (i.e., the specified authentication information is not read from the target memory module's first memory), the baseboard management controller sets the target memory module as an unusable memory module. Here, an unusable memory module can be a memory module that is not allowed to be initialized, or a memory module that is not allowed to be used after initialization. To avoid initialization errors and other problems, and to reduce redundant operations, an unusable memory module can be a memory module that is not allowed to be recognized during the operation of the basic input / output system.

[0067] There are several ways to set a target memory module as unavailable. For example, a status flag can be used to indicate that the target memory module is in an unavailable state, so that even if the target memory module is detected during the operation of the basic input / output system, it will be ignored. Alternatively, the connection between the target memory module or the memory slot into which the target memory module is inserted and the CPU can be disconnected. Other settings are also possible, but this embodiment does not limit the specific methods.

[0068] Optionally, the specified authentication information in the first memory of the target memory module is SPD (Serial Presence Detect) information. SPD is an erasable and rewritable EEPROM on the memory module, which records important information about the memory, such as the chip and module manufacturer, operating frequency, operating voltage, speed, capacity, voltage and row and column address bandwidth, etc.

[0069] In some embodiments, after reading the information stored in the first memory of each memory module inserted in the memory slot, subsequent processes, such as the BIOS startup process, can be triggered. Alternatively, the memory module processing method in this embodiment can be executed at other times, such as during BIOS operation, as long as uncertified memory can be detected and set as an unusable memory module to avoid potential subsequent anomalies.

[0070] Through the steps described above in this application embodiment, the baseboard management controller of the server sequentially reads the information stored in the first memory of the memory stick inserted in each memory slot of a group of memory slots in the server; when a target memory stick is read and the first memory of the target memory stick does not store the specified authentication information, the baseboard management controller sets the target memory stick as an unusable memory stick. The unusable memory stick is a memory stick that is not allowed to be recognized during the operation of the server's basic input / output system. This solves the problem of poor server security caused by memory sticks easily causing abnormalities in the server, and improves server security and stability.

[0071] As an optional approach, the server's baseboard management controller sequentially reads information stored in the first memory of each memory module inserted into a set of memory slots in the server, including:

[0072] S11, the I2C controller of the baseboard management controller reads the information stored in the first memory of the memory stick inserted in each memory slot in sequence according to the preset I2C address corresponding to each memory slot.

[0073] In this embodiment, the baseboard management controller can interact with the memory slots via a communication channel such as the I2C bus. The baseboard management controller may include an I2C controller (or I2C master controller), and the interaction between the baseboard management controller and the memory slots can be performed by the I2C controller. Here, the I2C bus is a shared bus system that can connect multiple I2C devices to. Devices connected to the I2C bus can act as either master or slave devices. The master device is responsible for controlling communication, sending data and generating the necessary synchronization clock pulses by initializing or terminating data transmission. Slave devices wait for commands from the master device and respond to command reception; the synchronization clock signal can only be generated by the master device. When the I2C bus is idle, both SDA and SCL are high. When a master device wants to communicate with a slave device, it first sends a start condition, then sends the slave device address and read / write control bits, and then transmits data. When data transmission ends, the master device sends a stop condition. Here, during data transmission, each byte transmitted can be 8 bits, with the most significant bit first and the least significant bit last.

[0074] For example, such as Figure 3 As shown, the server system architecture can be a CPU+PCH+BMC architecture. The BMC defines an I2C controller. Memory modules can be inserted into some or all of the DIMM slots from DIMM slot 0 to DIMM slot 31. DIMMs communicate with multiple CPUs (CPU0 and CPU1 are shown as examples). CPU0 and CPU1 communicate via a UPI interface, the CPUs communicate with the PCH via a DMI, and the PCH communicates with the BMC via an eSPI (Enhanced Serial Peripheral Interface) bus.

[0075] The address of each memory slot can be an I2C address. Taking DIMM slots as an example, the addresses defined for memory slots 0-31 are shown in Table 1.

[0076] Table 1

[0077]

[0078] When reading information stored in the first memory of a memory module inserted into a memory slot, the BMC's I2C controller can sequentially read the information stored in the first memory of each memory module inserted into the memory slot according to the preset I2C address corresponding to each memory slot. For example, it can read whether the content in the EEPROM is correct authentication information.

[0079] For example, after the server is powered on, the BMC runs. The BMC's I2C main controller reads the contents of the corresponding first memory according to the preset I2C address of the DIMM slot. Starting from DIMM slot 0, the BMC determines whether the contents of the first memory at the corresponding slot position are correct authentication information.

[0080] This embodiment improves the accuracy of data reading and enhances the compatibility of information reading by reading the information stored in the corresponding memory module according to the I2C address of the memory slot via the I2C bus.

[0081] As an optional solution, when the target memory module is read and the first memory of the target memory module does not store the specified authentication information, setting the target memory module as an unusable memory module via the baseboard management controller includes:

[0082] S21, if the target memory module is read and the first memory of the target memory module does not store the specified authentication information, the input signal of the target I3C switch corresponding to the target memory module is set to the first level state by the general input / output controller of the baseboard management controller, so as to disconnect the channel between the serial clock line and the serial data line of the target I3C switch and the central processing unit of the server.

[0083] In this embodiment, the memory slots can be connected to the server's central processing unit (CPU) via a connection component such as an I3C switch. Here, each memory slot has a corresponding I3C switch, which includes multiple combinations of SCL and SDA, one of which is connected to one SCL and SDA combination of the CPU, such as... Figure 4 The SCL and SDA combinations shown on the left, at least one of which is used to connect to the corresponding memory slot's SCL and SDA combination, as shown in the image. Figure 4 The combination of SCL and SDA shown on the right (one combination for transmitting SCK1 and SDA1, and another for transmitting SCK2 and SDA2) can control whether the channel between the memory slot and the central processing unit is open by setting the input signals to different levels, thereby adjusting the state of the memory module inserted in the memory slot. Among these, the participants... Figure 5 The CPU and DIMM can be connected via the I3C bus or other communication buses.

[0084] Here, the I3C switch (I3C interface switching chip) is a chip used to switch I3C channels according to control signals. See [link to relevant documentation]. Figure 4 The I3C controller includes SCK input, SDA input, and S input; and outputs SCK1, SCK2, SDA1, and SDA2. The signal definitions and logic are shown in Table 2.

[0085] Table 2

[0086]

[0087] If the input signal S is low (0 in Table 2), SCK and SCK1 are connected, and SDA and SDA1 are connected. If the input signal S is high (1 in Table 2), SCK and SCK2 are connected, and SDA and SDA2 are connected.

[0088] The baseboard management controller may include a General Purpose Input / Output (GPIO) controller, which can be connected to the I3C switch corresponding to each memory slot. If the first memory of the target memory module does not store the specified authentication information, the GPIO controller can set the input signal to the target I3C switch to a first level state, thereby disconnecting the channel between the memory slot containing the target memory module and the server's central processing unit via the target I3C switch. In this case, the target memory module is unusable.

[0089] For example, combining Figure 4 and Figure 6 If the authentication information is incorrect or nonexistent, the BMC pulls the S input signal of the corresponding I3C switch low via the GPIO controller, disconnecting the channel between the SCK1 / SDA1 signals and the CPU, rendering the memory module unusable. Figure 6 In this configuration, only SCK1 and SDA1 are used in the I3C switch; SCK2 and SDA2 are not used.

[0090] In this embodiment, by setting the level of the input signal of the I3C switch to disconnect the channel between the corresponding memory slot and the central processing unit, the state of the memory module inserted in the corresponding memory slot can be adjusted, thereby improving the convenience of setting the state of the memory module.

[0091] As an optional approach, the above method also includes:

[0092] S31, when the target memory module is read and the first memory of the target memory module stores the specified authentication information, the target memory module is set as the memory module to be identified by the baseboard management controller, wherein the memory module to be identified is the memory module to be identified during the operation of the basic input / output system.

[0093] If the target memory module is read and the first memory of the target memory module stores the specified authentication information, it can be determined that the memory module has been authenticated and can be applied to the subsequent memory module identification process. At this time, the baseboard management controller can set the target memory module as the memory module to be identified. Here, the memory module to be identified is the memory module to be identified during the BIOS operation. The memory module to be identified is not necessarily the memory module used during the BIOS operation, but the memory module used during the BIOS operation is the memory module to be identified (it needs to be determined that it is authenticated memory).

[0094] In this embodiment, after determining that the memory module is certified memory, it is set as the memory to be identified, so as to facilitate subsequent processing (e.g., memory initialization), which can improve the security of server operation.

[0095] As an optional solution, when the target memory module is read and the first memory of the target memory module stores the specified authentication information, the baseboard management controller sets the target memory module as the memory module to be identified, including:

[0096] S41, when the target memory module is read and the first memory of the target memory module stores the specified authentication information, the input signal of the target I3C switch corresponding to the target memory module is set to the second level state through the general input / output controller of the baseboard management controller, so as to conduct the channel between the serial clock line of the target I3C switch and the serial data line of the target I3C switch and the central processing unit of the server.

[0097] Similar to the previous embodiments, the memory slot where the target memory module is located can be connected to the central processing unit through the target I3C switch, as has been explained before, and will not be repeated here.

[0098] If the target memory module is read and the first memory of the target memory module stores the specified authentication information, that is, the target memory module is an authenticated memory, the GPIO controller can set the input signal of the target I3C switch to the second level state to open the channel between the memory slot where the target memory module is located and the central processing unit of the server through the target I3C switch. At this time, the target memory module is the memory module to be identified.

[0099] Here, the input signal of the target I3C switch may be in the first level state or the second level state at the beginning. If the set level state is consistent with the current level state, the current level state can be maintained.

[0100] For example, if the authentication information is correct, the BMC pulls the S input signal of the corresponding I3C switch high through the GPIO controller, and the channel between the SCK1 / SDA1 signal and the CPU is connected.

[0101] In this embodiment, by setting the level of the input signal of the I3C switch to conduct the channel between the corresponding memory slot and the central processing unit, the state of the memory module inserted in the corresponding memory slot can be adjusted, thereby improving the convenience of memory module state switching.

[0102] As an optional approach, after the target memory module is set as the memory module to be identified via the baseboard management controller, the above method further includes:

[0103] S51, after all the information stored in the first memory of the memory sticks inserted in each memory slot has been read, triggers a power-on signal through the board management controller to control the operation of the basic input / output system;

[0104] S52, when the basic input / output system runs to the memory initialization reference code, sequentially reads the serial presence detection information of the memory modules to be identified inserted in a set of memory slots;

[0105] S53, upon reading the serial presence detection information of the target memory module, initializes the target memory module;

[0106] S54: If no serial presence detection information for the target memory module is read, the target memory module is set as a disabled memory module, where a disabled memory module is a memory module that is prohibited from use.

[0107] If the information stored in the first memory of each memory module inserted in each memory slot has been read, subsequent processing can be executed, which may include: triggering a power-on signal by the baseboard management controller to control the operation of the basic input / output system. Here, there may be cases where no memory modules are inserted in some memory slots. In this case, these memory slots can be ignored (their connection to the central processing unit may be disconnected), or they can be used in subsequent processing (their connection to the central processing unit may be either connected or disconnected).

[0108] After the baseboard management controller triggers the power-on signal, when the BIOS runs to the memory initialization reference code (i.e., runs to the MRC stage), the BIOS can sequentially read the serial presence detection information (i.e., SPD information) of the memory modules to be identified inserted in a set of memory slots. For unusable memory modules, the BIOS cannot read their SPD information, and for memory slots without memory modules inserted, it also cannot read their SPD information.

[0109] In scenarios where the target memory module is a memory module to be identified, if the SPD information of the target memory module is read, the target memory module can be initialized. If the SPD information of the target memory module is not read, the target memory module can be set as a disabled memory module, that is, a memory module that is prohibited from use, in order to avoid its impact on the security and reliability of server operation.

[0110] For example, after all DIMM slots have been traversed, the BMC triggers a power-on signal, and the BIOS begins operation. When the BIOS reaches the MRC stage, the MRC sequentially checks whether SPD information exists in each memory slot via the SCK / SDA I3C signals on the CPU. If it exists, it continues with subsequent DIMM training and uses the trained DIMMs. If it does not exist, it skips the memory initialization of that slot, and the memory in that location is disabled.

[0111] Here, the MRC (Memory Controller Configuration) is typically provided by the CPU or BIOS manufacturer. During execution, the CPU first reads the memory parameter information from the SPD (Special Processing Unit) on the DDR5 memory via the I3C bus. Then, the MRC, according to the program code set by the CPU manufacturer, performs specific initialization actions on the memory based on the memory parameter information read from the SPD. If the SPD information cannot be read, the MRC assumes that there is a problem with the memory at that location or that the memory is not connected, and will not continue with the initialization actions.

[0112] The MRC memory initialization process is fixed and involves specific manufacturer-specific memory parameters. These parameters are obtained from the SPD (Special Purpose Device), and then set according to the fixed steps. Finally, the memory initialization is complete. The specific process is as follows: Figure 7 As shown, the MRC memory initialization process may include the following steps:

[0113] Step 1, Begin;

[0114] Step 2: Read the information stored in the SPD via the I3C bus;

[0115] Step 3: MRC performs memory initialization;

[0116] Step 4, End.

[0117] The memory initialization process of MRC can include: allocating memory space, i.e., determining the size of the memory space to be initialized and allocating sufficient memory space; zeroing memory, i.e., setting all bits in the allocated memory space to zero to ensure that there is no old data in the memory; initializing memory, i.e., initializing the memory space as needed, including setting default values, writing specific modes or data; verifying memory, i.e., verifying the initialized memory space to ensure that the data in the memory meets the expected requirements; and completing initialization, i.e., confirming that the memory initialization work is complete and releasing any temporarily allocated resources.

[0118] The memory initialization methods described above, which are not certified and tested by server manufacturers, can generally be initialized and used on the machine as long as the interface is compatible with the DDR5 specification, which can easily cause server malfunctions and other problems.

[0119] In this embodiment, during memory initialization, MRC sequentially reads the SPD information of the memory modules to be identified inserted in a set of memory slots. For unusable memory modules (uncertified memory), it is not necessary to read the SPD information. In this way, even if the memory is connected to the machine, it cannot be recognized and used during the boot process, which can effectively avoid the risks of errors and crashes caused by uncertified memory.

[0120] This embodiment improves system security and reliability by disabling memory modules inserted into memory slots that lack SPD information.

[0121] As an optional feature, each memory slot may allow the insertion of fifth-generation memory, such as DDR5 memory. Optionally, the first memory may be electrically erasable programmable read-only memory (EEPROM). DDR5 memory can be used in server systems, and the RDIMM block diagram is shown below. Figure 8 As shown, the RDIMM includes an RCD chip, multiple channels (Channel A and Channel B are shown as examples), information written to the EEPROM by the memory module manufacturer (memory SPD information), and components such as a PMIC (Power Management IC) and RFU pins.

[0122] SPD is an EEPROM memory for the I3C interface, storing parameters used for memory training; its capacity is typically several hundred bytes. The I3C interface is compatible with the I2C interface. Key signals for the I2C interface's EEPROM memory include... Figure 9As shown, SCK / SDA are the clock / data input / output channels, and A0, A1...An are pins used to define the address during that period. Multiple devices can be connected to the same I2C bus; the number of devices is related to the address, and the number of address signals An limits the number of devices that can be connected. The maximum supported number of devices is 2. N Where N is the number of address lines, as shown in the diagram. Figure 10 . Figure 9 If there are 3 address lines, then a maximum of 2 devices can be connected. 3 =8 (that is, Figure 10 The I2C interface EEPROM 1, I2C interface EEPROM 2, ..., I2C interface EEPROM n.

[0123] Optionally, the target memory module includes a set of undefined pins. Five of these undefined pins are configured as address pins, and two of these pins are configured as a serial data line pin and a serial clock line pin, respectively. Optionally, authentication information is specified to identify the corresponding memory module as certified by the server manufacturer. Here, by utilizing the undefined pin interfaces on the memory module, combined with the corresponding motherboard design, the OEM manufacturer's server only recognizes certified memory. Other uncertified memory is disabled and excluded during the boot process.

[0124] Taking DDR5 as an example, DDR5 memory has a total of 288 pins, each pin defining a different signal, as shown in Table 3 (Table 3 continued):

[0125] Table 3

[0126]

[0127] Table 3 (continued)

[0128]

[0129] Of these, seven RFU signals are defined in the DDR5 pins, but they are currently unused. Refer to Table 4, which only lists some of the DDR5 pin signal definitions:

[0130] Table 4

[0131] 2 RFU 149 RFU 150 RFU 220 RFU 231 RFU 232 RFU 144 RFU

[0132] Here, utilizing the existing interface signal definitions of DDR5, pins 149 and 150 from Table 3 are selected as two signal pins for the I3C interface, and pins 2, 220, 231, 232, and 144 are used as address signals. An EEPROM memory with an I2C interface is expanded on the DDR5 memory. The remaining five RFU pins are used as address definition pins (pins 149, 150, 2, 220, 231, 232, and 144 are all empty pins; any two can be selected as signal pins, and any five can be selected as address definition pins). Figure 11 Pins 2, 220, 231, 232, and 144 are used as address definition pins. Because five address lines are extended (i.e., 2, 220, 231, 232, and 144), this configuration can support a maximum of 32 memory modules. The memory is connected to memory slots on the Main Board (MB). For memory slots in different locations, the power / ground connections of pins 2 / 220 / 231 / 232 / 144 on the MB differ, thus defining different addresses.

[0133] In addition, such as Figure 11 As shown, Channel A and Channel B include multiple DIMM particles, and the RCD communicates with multiple channels via signals (e.g., Figure 11 The example shows signals such as "DQ[31:0]_A" and "CB[7:0]_A". SPD is an EEPROM memory with an I3C interface, which stores the parameters used for memory training. Its capacity is generally several hundred bytes.

[0134] This embodiment utilizes fifth-generation memory, electrically erasable programmable read-only memory, and empty pins to process memory modules, thereby improving compatibility with existing memory modules and enhancing the adaptability of memory module processing methods.

[0135] The processing method of the memory module in this embodiment will be explained below with reference to an optional example. This optional example provides a method for interaction between the DDR5 on the server and the motherboard interface. During the memory production stage, the EEPROM on each certified memory module is written with the OEM manufacturer's DDR5 memory certification information.

[0136] After the server is powered on, combined with Figure 12 The method for handling memory modules in this optional example includes the following steps:

[0137] In step S1202, the BMC runs, and the BMC's I2C main controller reads the contents of the corresponding EEPROM sequentially according to the preset I2C address of the DIMM slot (starting from DIMM slot 0).

[0138] Step S1204: The BMC determines the contents of the EEPROM at the corresponding slot position;

[0139] Step S1206: Determine whether the content of the EEPROM at the corresponding slot position is the correct authentication information. If yes, proceed to step S1208; otherwise, proceed to step S1210.

[0140] In step S1208, the BMC pulls up the S input signal of the corresponding slot I3C switch through the GPIO controller. That is, if the authentication information is correct, the channel between the SCK1 / SDA1 signal and the CPU is connected.

[0141] In step S1210, the BMC pulls down the S input signal of the corresponding slot I3C switch through the GPIO controller. That is, if the authentication information is incorrect or does not exist, the channel between the SCK1 / SDA1 signal and the CPU is disconnected.

[0142] Step S1212: Determine whether all DIMM slots have been traversed. If yes, proceed to step S1214; otherwise, return to step S1202.

[0143] Step S1214: The BMC triggers the server to start the BIOS, that is, the BMC triggers the power-on signal and the BIOS starts running;

[0144] In step S1216, the MRC sequentially detects each memory slot using the SCK / SDA I3C signals on the CPU;

[0145] Step S1218: Determine whether the detected memory slot has SPD information. If it does, proceed to step S1220; otherwise, proceed to step S1222.

[0146] Step S1220: MRC trains the DIMM at this location and uses it;

[0147] In step S1222, MRC skips the DIMM training at this location (i.e., skips the memory initialization of this slot) and disables the memory at this location.

[0148] Step S1224, other BIOS processes, end.

[0149] Here, DIMM training is an initialization and verification process performed in computer memory. When the computer starts up, the memory controller trains each DIMM to ensure it can function correctly. DIMM training includes setting memory timings, calibrating clock frequencies, adjusting voltages, and other parameters to ensure the module operates under correct conditions. In other words, DIMM training ensures that the memory modules can work stably and interact correctly with other system components.

[0150] This optional example demonstrates how to identify uncertified memory modules based on authentication information, thereby identifying non-OEM certified memory and disconnecting the channel between the uncertified memory and the CPU before the BIOS starts running. This can improve server reliability and avoid risks such as errors and crashes caused by uncertified memory.

[0151] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0152] This embodiment also provides a memory module processing device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0153] Figure 13 This is a structural block diagram of an optional memory module processing device according to an embodiment of this application, such as... Figure 13 As shown, the device includes:

[0154] The reading unit 1302 is used to sequentially read information stored in the first memory of the memory stick inserted in each memory slot of a set of memory slots in the server through the baseboard management controller of the server;

[0155] Setting unit 1304 is used to set the target memory module as an unusable memory module through the baseboard management controller when the target memory module is read and the first memory of the target memory module does not store the specified authentication information. The unusable memory module is a memory module that is not allowed to be recognized during the operation of the server's basic input / output system.

[0156] It should be noted that the reading unit 1302 in this embodiment can be used to perform the above step S202, and the setting unit 1304 in this embodiment can be used to perform the above step S204.

[0157] In this embodiment, the baseboard management controller of the server sequentially reads the information stored in the first memory of the memory stick inserted in each of a set of memory slots in the server; when a target memory stick is read and the first memory of the target memory stick does not store the specified authentication information, the baseboard management controller sets the target memory stick as an unusable memory stick. The unusable memory stick is a memory stick that is not allowed to be recognized during the operation of the server's basic input / output system. This solves the problem of poor server security caused by memory sticks easily causing abnormalities in the server, and improves the security and stability of the server.

[0158] In one exemplary embodiment, the reading unit includes:

[0159] The reading module is used to read the information stored in the first memory of the memory stick inserted in each memory slot sequentially according to the preset I2C address corresponding to each memory slot by the I2C controller of the baseboard management controller.

[0160] In one exemplary embodiment, the setting unit includes:

[0161] The disconnect module is used to set the input signal of the target I3C switch corresponding to the target memory module to a first level state through the general input / output controller of the baseboard management controller when the target memory module is read and the first memory of the target memory module does not store the specified authentication information, so as to disconnect the channel between the serial clock line and the serial data line of the target I3C switch and the central processing unit of the server. When the input signal of the target I3C switch is set to the first level state, the target memory module is an unusable memory module.

[0162] In one exemplary embodiment, the above-described apparatus further includes:

[0163] The identification unit is used to set the target memory module as the identification memory module through the baseboard management controller when the target memory module is read and the first memory of the target memory module stores the specified authentication information. The identification memory module is the memory module to be identified during the operation of the basic input / output system.

[0164] In one exemplary embodiment, the unit to be identified includes:

[0165] The switching module is used to set the input signal of the target I3C switch corresponding to the target memory module to a second level state through the general input / output controller of the baseboard management controller when the target memory module is read and the first memory of the target memory module stores the specified authentication information. This is to enable the channel between the serial clock line and serial data line of the target I3C switch and the central processing unit of the server. When the input signal of the target I3C switch is set to the second level state, the target memory module is the memory module to be identified.

[0166] In one exemplary embodiment, the above-described apparatus further includes:

[0167] The control unit is used to trigger a power-on signal through the baseboard management controller after the target memory module is set as the memory module to be identified by the baseboard management controller, and after all the information stored in the first memory of the memory modules inserted in each memory slot has been read. This is to control the operation of the basic input / output system.

[0168] The detection unit is used to sequentially read the serial presence detection information of the memory modules to be identified inserted in a set of memory slots when the basic input / output system runs to the memory initialization reference code;

[0169] An initialization unit is used to initialize the target memory module when the serial presence detection information of the target memory module is read.

[0170] The disable unit is used to set the target memory module as a disabled memory module when no serial presence detection information of the target memory module is read. The disabled memory module is a memory module that is prohibited from use.

[0171] In one exemplary embodiment, the target memory module is a fifth-generation memory, the first memory is an electrically erasable programmable read-only memory, the target memory module includes a set of empty pins, five of the empty pins in the set of empty pins are set as address pins, two of the empty pins in the set of empty pins are set as serial data line pins and serial clock line pins respectively, and the specified authentication information is used to identify that the corresponding memory module is a memory module certified by the server manufacturer of the server.

[0172] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0173] Embodiments of this application also provide a computer-readable storage medium storing a computer program configured to perform the steps in any of the above method embodiments when executed.

[0174] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0175] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0176] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0177] According to one aspect of this application, a computer program product is provided, comprising a computer program / instructions containing program code for performing the methods shown in the flowchart. In such an embodiment, reference is made to... Figure 14 The computer program can be downloaded and installed from a network via communication section 1409, and / or installed from removable media 1411. When the computer program is executed by central processing unit 1401, it performs various functions provided in the embodiments of this application. The sequence numbers of the embodiments in this application above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0178] refer to Figure 14 , Figure 14 This is a structural block diagram of a computer system for an optional electronic device according to an embodiment of this application.

[0179] Figure 14 A schematic block diagram of a computer system architecture for implementing embodiments of the present application is shown. Figure 14As shown, the computer system 1400 includes a central processing unit (CPU) 1401, which performs various appropriate actions and processes based on programs stored in read-only memory (ROM) 1402 or programs loaded from storage section 1408 into random access memory (RAM). The RAM 1403 also stores various programs and data required for system operation. The CPU 1401, ROM 1402, and RAM 1403 are interconnected via a bus 1404. An input / output interface 1405 (I / O interface) is also connected to the bus 1404.

[0180] The following components are connected to the input / output interface 1405: an input section 1406 including a keyboard, mouse, etc.; an output section 1407 including a cathode ray tube (CRT), liquid crystal display (LCD), and speakers, etc.; a storage section 1408 including a hard disk, etc.; and a communication section 1409 including a network interface card such as a local area network card or modem, etc. The communication section 1409 performs communication processing via a network such as the Internet. A drive 1410 is also connected to the input / output interface 1405 as needed. Removable media 1411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on the drive 1410 as needed so that computer programs read from them can be installed into the storage section 1408 as needed.

[0181] Specifically, according to embodiments of this application, the processes described in the various method flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1409, and / or installed from removable medium 1411. When the computer program is executed by central processing unit 1401, it performs various functions defined in the system of this application. It should be noted that... Figure 14 The computer system 1400 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0182] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0183] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular hardware and software combination.

[0184] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for processing memory modules, characterized in that, include: The server's baseboard management controller sequentially reads the information stored in the first memory of the memory module inserted in each of a set of memory slots in the server; If a target memory module is read and the first memory of the target memory module does not store the specified authentication information, the target memory module is set as an unusable memory module by the baseboard management controller. The unusable memory module is a memory module that is not allowed to be recognized during the operation of the server's basic input / output system. The step of setting the target memory module as an unusable memory module via the baseboard management controller when the target memory module is read and the first memory of the target memory module does not store the specified authentication information includes: If the target memory module is read and the specified authentication information is not stored in the first memory of the target memory module, the input signal of the target improved internal integrated circuit I3C switch corresponding to the target memory module is set to a first level state by the general input / output controller of the baseboard management controller, so as to disconnect the channel between the memory slot where the target memory module is located and the central processing unit of the server via the target I3C switch. When the input signal of the target I3C switch is set to the first level state, the target memory module is the unusable memory module.

2. The method according to claim 1, characterized in that, The step of sequentially reading information stored in the first memory of the memory modules inserted in each of a set of memory slots in the server via the server's baseboard management controller includes: The internal integrated bus I2C controller of the baseboard management controller reads the information stored in the first memory of the memory module inserted in each memory slot sequentially according to the preset I2C address corresponding to each memory slot.

3. The method according to claim 1, characterized in that, The method further includes: When the target memory module is read and the specified authentication information is stored in the first memory of the target memory module, the target memory module is set as a memory module to be identified by the baseboard management controller, wherein the memory module to be identified is the memory module to be identified during the operation of the basic input / output system.

4. The method according to claim 3, characterized in that, When the target memory module is read and the specified authentication information is stored in the first memory of the target memory module, setting the target memory module as a memory module to be identified through the baseboard management controller includes: When the target memory module is read and the designated authentication information is stored in the first memory of the target memory module, the input signal of the target improved internal integrated circuit I3C switch corresponding to the target memory module is set to a second level state by the general input / output controller of the baseboard management controller, so as to open the channel between the memory slot where the target memory module is located and the central processing unit of the server via the target I3C switch. When the input signal of the target I3C switch is set to the second level state, the target memory module is the memory module to be identified.

5. The method according to claim 3, characterized in that, After the target memory module is set as the memory module to be identified via the baseboard management controller, the method further includes: When all the information stored in the first memory of the memory modules inserted in each memory slot has been read, the power-on signal is triggered by the baseboard management controller to control the operation of the basic input / output system; When the basic input / output system runs to the memory initialization reference code, the serial presence detection information of the memory modules to be identified inserted in the set of memory slots is read sequentially. Upon reading the serial presence detection information of the target memory module, memory initialization is performed on the target memory module; If no serial presence detection information is read from the target memory module, the target memory module is set as a disabled memory module, wherein the disabled memory module is a memory module that is prohibited from use.

6. The method according to any one of claims 1 to 5, characterized in that, The target memory module is a fifth-generation memory, the first memory is an electrically erasable programmable read-only memory, the target memory module includes a set of empty pins, five of the empty pins in the set of empty pins are set as address pins, two of the empty pins in the set of empty pins are set as serial data line pins and serial clock line pins respectively, and the specified authentication information is used to identify that the corresponding memory module is a memory module certified by the server manufacturer of the server.

7. A processing device for a memory module, characterized in that, include: The reading unit is used to sequentially read information stored in the first memory of the memory stick inserted in each of a set of memory slots of the server through the baseboard management controller of the server; The setting unit is used to set the target memory module as an unusable memory module through the baseboard management controller when the target memory module is read and the first memory of the target memory module does not store the specified authentication information. The unusable memory module is a memory module that is not allowed to be recognized during the operation of the server's basic input / output system. The disconnect module is configured to, when the target memory module is read and the specified authentication information is not stored in the first memory of the target memory module, set the input signal of the target improved internal integrated circuit I3C switch corresponding to the target memory module to a first level state through the general input / output controller of the baseboard management controller, so as to disconnect the channel between the memory slot where the target memory module is located and the central processing unit of the server via the target I3C switch. When the input signal of the target I3C switch is set to the first level state, the target memory module is the unusable memory module.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 6.

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