A symmetric encryption and decryption method and related apparatus

Abstract

The application provides a symmetric encryption and decryption method and related device, and relates to the technical field of computer application. The symmetric encryption and decryption method can include: preprocessing to-be-processed data; wherein the to-be-processed data is to-be-encrypted data or to-be-decrypted data; obtaining residual data in the preprocessed to-be-processed data; determining N first registers corresponding to the residual data according to the data length of the residual data; N is an integer greater than or equal to 2; loading the residual data through the N first registers, and performing encryption processing or decryption processing on the data loaded by the N first registers in parallel. The technical scheme provided by the application is beneficial to improving the operation efficiency of the encryption and decryption algorithm.

Description

Technical Field

[0001] This application relates to the field of computer application technology, and in particular to a symmetric encryption / decryption method and related apparatus. Background Technology

[0002] To protect data security, encrypting data with an encryption key is an effective method. The original data can then be retrieved using the same decryption key. This type of encryption / decryption algorithm, where the encryption and decryption keys are the same, is called a symmetric encryption / decryption algorithm. However, current technologies suffer from low processing efficiency for the data to be encrypted or any remaining data to be decrypted. Summary of the Invention

[0003] Based on the defects and shortcomings of the prior art, this application proposes a symmetric encryption and decryption method and related apparatus, which can solve the problem of low processing efficiency in the encryption and decryption of data in the prior art.

[0004] According to a first aspect of the embodiments of this application, a symmetric encryption / decryption method is provided, applied to a processor, the method comprising:

[0005] Preprocessing is performed on the data to be processed; wherein the data to be processed is data to be encrypted or data to be decrypted.

[0006] Retrieve the remaining data from the preprocessed data to be processed;

[0007] Based on the length of the remaining data, determine the N corresponding first registers; N is an integer greater than or equal to 2;

[0008] The remaining data is loaded through the N first registers, and the data loaded in the N first registers is encrypted or decrypted in parallel.

[0009] According to a second aspect of the embodiments of this application, a symmetric encryption / decryption apparatus is provided, applied to a processor, the apparatus comprising:

[0010] A preprocessing module is used to preprocess the data to be processed; wherein the data to be processed is data to be encrypted or data to be decrypted.

[0011] The acquisition module is used to acquire the remaining data in the preprocessed data to be processed;

[0012] The determining module is used to determine N first registers corresponding to the remaining data based on the data length of the remaining data; N is an integer greater than or equal to 2.

[0013] The first processing module is used to load the remaining data through the N first registers, and to perform encryption or decryption processing on the data loaded in the N first registers in parallel.

[0014] According to a third aspect of the embodiments of this application, an electronic device is provided, including: a memory and a processor;

[0015] The memory is connected to the processor and is used to store programs;

[0016] The processor is used to implement the symmetric encryption / decryption method as described in the first aspect by running a program in the memory.

[0017] According to a fourth aspect of the embodiments of this application, a storage medium is provided, on which a computer program is stored, and when the computer program is run by a processor, it implements the symmetric encryption and decryption method as described in the first aspect.

[0018] In the technical solution provided in this application, different parallel processing situations can be divided according to the length of the remaining data in the preprocessed data to be encrypted or decrypted. Different register configurations are made for the remaining data so that each register can load a set of data from the remaining data. In this way, the remaining data can also be encrypted or decrypted in parallel, which improves the computational efficiency and makes reasonable use of processor resources. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0020] Figure 1 A flowchart illustrating a symmetric encryption / decryption method provided in an embodiment of this application;

[0021] Figure 2 A schematic diagram illustrating the encryption process provided in the embodiments of this application;

[0022] Figure 3 A block diagram of a symmetric encryption / decryption device provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] Exemplary methods

[0026] This application provides a symmetric encryption and decryption method that can be applied to computing devices, specifically to processors (such as CPUs) within the computing devices. This processor supports parallel encryption and decryption of data based on symmetric encryption and decryption algorithms.

[0027] like Figure 1 As shown, the method may include:

[0028] Step 101: Preprocess the data to be processed.

[0029] The data to be processed mentioned here refers to data to be encrypted or data to be decrypted.

[0030] The preprocessing mentioned here can refer to encrypting or decrypting data that meets preset conditions using a symmetric encryption / decryption algorithm. Data meeting the preset conditions can be data whose length is an integer multiple of a first preset length. This first preset length is the maximum data length that the processor can perform in one parallel encryption or decryption operation. For example, this maximum data length could be 1024 bits, and its specific value is determined by the processor's performance.

[0031] Optionally, the data that meets the preset conditions can be determined starting from the beginning of the data to be processed. For example, if the length of the data to be processed is 2432 bits and the first preset length is 1024 bits, the data that meets the preset conditions starting from the beginning is the first 2048 bits. It is understood that the data that meets the preset conditions can also be determined starting from the end of the data to be processed. In the aforementioned example, the data that meets the preset conditions is the last 2048 bits.

[0032] Optionally, the symmetric encryption and decryption algorithms described herein may include, but are not limited to, at least one of the following: Advanced Encryption Standard (AES) algorithm or SM4 algorithm, etc.

[0033] Step 102: Obtain the remaining data from the preprocessed data to be processed.

[0034] The remaining data has a length greater than the second preset length but less than the first preset length. The second preset length is the block size of the symmetric encryption / decryption algorithm, and also the minimum computational length in symmetric encryption / decryption processing. The specific value of the second preset length depends on the symmetric encryption / decryption algorithm. For example, for the AES algorithm, its block size can be 128 bits (16 bits), 192 bits (24 bits), or 256 bits (32 bits); for the SM4 algorithm, its block size can be 128 bits. Therefore, the second preset length is less than the first preset length.

[0035] Continuing with the example described above, if the data that meets the preset conditions is determined to be the first 2048 bits starting from the beginning, the remaining data is the last 384 bits; if the data that meets the preset conditions is determined to be the first 2048 bits starting from the end, the remaining data is the first 384 bits.

[0036] Step 103: Determine the N first registers corresponding to the remaining data based on the data length of the remaining data.

[0037] Where N is an integer greater than or equal to 2 and less than the ratio of the first preset length to the second preset length. For example, if the ratio of the first preset length to the second preset length is 8, then N is an integer greater than or equal to 2 and less than 8.

[0038] The purpose of this step is to determine different parallel processing scenarios based on the length of the remaining data and to configure the corresponding registers so that the remaining data can be encrypted or decrypted in parallel. The registers mentioned here can be used to load and store the data to be encrypted or decrypted. Each register can load the data of one computational unit, that is, a set of data blocks of length.

[0039] Step 104: Load the remaining data through N first registers, and encrypt or decrypt the data loaded in the N first registers in parallel.

[0040] In this step, the corresponding first register can be called according to the calculation process of the symmetric encryption and decryption algorithm to encrypt or decrypt the data in the first register.

[0041] In this embodiment, the remaining data can be divided into different parallel processing scenarios based on its length, and different register configurations can be applied. This allows the remaining data to be loaded from multiple registers, enabling parallel encryption or decryption even if the remaining data is less than the maximum data length. This improves computational efficiency and makes efficient use of processor resources. Furthermore, in this embodiment, each parallel processing scenario corresponding to the remaining data corresponds to a different combination of hardware encryption / decryption instructions. After identifying the remaining data length, the corresponding encryption / decryption instruction combination can be invoked. Thus, the remaining data can be processed in a single round of encryption or decryption. The hardware encryption / decryption instruction combination refers to a combination of instructions used for encryption and decryption. Different instructions can complete different data operation flows, and when combined and invoked in a specific order, they complete the encryption / decryption data operation flow.

[0042] In some embodiments, data meeting preset conditions from the data to be processed can be loaded first through M registers, and this portion of data can be encrypted or decrypted in parallel. After the encryption or decryption of this portion of data is completed, the remaining data is loaded using N registers from the aforementioned M registers, and the loaded data is encrypted or decrypted in parallel. Here, M is the ratio of the first preset length to the second preset length, and M is greater than N.

[0043] In some embodiments, for data whose length is less than the maximum data length for a single parallel encryption or decryption process by the processor, but greater than the block length of the symmetric encryption / decryption algorithm (i.e., the remaining data), register configurations can be performed in advance based on the different lengths of such data, i.e., a correspondence between the different lengths of the remaining data and the register configurations can be established in advance.

[0044] Assuming the maximum data length for a single parallel encryption or decryption operation by the processor is 1024 bits, and the block size of the symmetric encryption / decryption algorithm is 128 bits, the correspondence between the remaining data length and the register configuration can be as follows:

[0045] (1) When the data length is greater than 128 bits and less than or equal to 256 bits, two registers can be configured;

[0046] (2) When the data length is greater than 256 bits and less than or equal to 384 bits, three registers can be configured;

[0047] (3) When the data length is greater than 384 bits and less than or equal to 512 bits, four registers can be configured;

[0048] (4) When the data length is greater than 512 bits and less than or equal to 640 bits, 5 registers can be configured;

[0049] (5) When the data length is greater than 640 bits and less than or equal to 768 bits, 6 registers can be configured;

[0050] (6) When the data length is greater than 768 bits and less than or equal to 869 bits, 7 registers can be configured.

[0051] It should be noted that if the difference between the maximum data length and the remaining data length is less than the second preset duration (for example, in the case where the data length is greater than 869 bits and less than 1024 bits in the previous example), the remaining data length can be directly padded to the maximum data length, and then the corresponding encryption or decryption processing can be performed.

[0052] Optionally, the pre-established correspondence between data length and register configuration can include not only the number of registers corresponding to different data lengths, but also the registers used to load data, i.e., which registers are specifically used. For example, with 8 registers (v0-v7), for data lengths greater than 128 bits and less than or equal to 256 bits, in addition to configuring 2 registers, data can also be specified to be loaded from registers v0 and v1; for data lengths greater than 256 bits and less than or equal to 384 bits, in addition to configuring 3 registers, data can also be specified to be loaded from registers v0, v1, and v2, and so on for other cases. It is understandable that N registers can also be randomly selected to load the remaining data; for example, when configuring 3 registers, 3 registers can be randomly selected from registers v0-v7.

[0053] In some embodiments, step 103: loading the remaining data through N first registers, and encrypting or decrypting the data loaded in the N first registers in parallel, may include:

[0054] Step A1: Divide the remaining data into N groups according to the second preset length.

[0055] The purpose of this step is to group the remaining data based on the minimum computation length (i.e., the second preset length) to obtain N groups of data, which is the same as the number of the first registers.

[0056] Optionally, if the length of the last group of data obtained from the division is less than the minimum calculation length, the data length can be padded first. For example, if a few digits are missing, the same number of "0"s can be used to pad them; or if a few digits are missing, the same number of identical digits can be used to pad them. For example, if 8 digits are missing, 8 "8"s can be used to pad them. Of course, other feasible methods can also be used for data padding, and this application embodiment does not limit this.

[0057] Step A2: Load one set of data from the N sets of data using the N first registers.

[0058] That is, each first register loads one set of data from the N sets of data. The N sets of data mentioned here include data whose group length is obtained by padding, such as the last set of data in the previous example whose length is less than the minimum calculation length, and the new set of data obtained by padding.

[0059] Step A3: Call N first registers and encrypt or decrypt the data loaded in each first register in parallel.

[0060] Optionally, instruction-level parallelism can be used to encrypt or decrypt the data loaded in each first register. Instruction-level parallelism, as described here, refers to allowing the processor to execute multiple instructions within one clock cycle. Specifically, in the embodiments of this application, instruction-level parallelism means that multiple data encryption or decryption tasks of different block lengths can be executed within one clock cycle. For example, eight blocks of 128-bit data can be encrypted within one clock cycle.

[0061] Building upon this, parallel pipeline technology can be used to encrypt or decrypt the loaded data. Parallel pipeline technology, as described here, refers to a technique that improves processor performance by decomposing a task into a series of concurrently executable subtasks. Each subtask is called a pipeline stage, and each pipeline stage executes on an independent hardware unit (such as a register). Specifically, in the embodiments of this application, parallel pipeline technology refers to decomposing a data encryption or decryption task of a block length into multiple concurrently executable subtasks. For example, the encryption task of a 128-bit block of data can be divided into five subtasks: instruction fetch, decode, execute, memory access, and write-back.

[0062] Combining parallel pipeline technology and instruction-level parallelism can further improve processor efficiency.

[0063] In this embodiment of the application, when the length of the remaining data is greater than the second preset length and the difference between the maximum data length and the length of the remaining data is less than the second preset duration, multiple registers can load a group of data of a group length obtained by grouping the remaining data, thereby realizing parallel encryption or decryption processing of the remaining data. This improves computational efficiency and makes more reasonable use of processor resources.

[0064] In some embodiments, when the length of the remaining data is less than or equal to a second preset length, the symmetric encryption / decryption method may further include:

[0065] The remaining data is loaded through a second register; and the remaining data loaded into the second register is then encrypted or decrypted.

[0066] The second register mentioned here can be pre-set (i.e., default) or randomly selected.

[0067] When the length of the remaining data is less than or equal to the group length (i.e., the second preset length), the remaining data can be loaded using a single register, meaning all remaining data can be loaded at once by a single register. This register can be pre-set, such as pre-designating register v0 to load the remaining data. Alternatively, the register can be randomly selected, such as randomly choosing one register from registers v0-v7 to load the remaining data. It is understood that when the length of the remaining data is less than the group length, the remaining data can be padded to the second preset length before being loaded by the register. Specific padding methods can be found in the description of data padding in the preceding embodiments, and will not be repeated here.

[0068] A register can load data of one block length. Therefore, if the remaining data length is less than or equal to the second preset length, it can be loaded into a register to complete the encryption or decryption process as quickly as possible.

[0069] In some embodiments, the processor integrates a hardware encryption instruction set for encrypting the data to be processed, and / or a hardware decryption instruction set for decrypting the data to be processed. That is, the processor integrates a hardware encryption and decryption instruction set of symmetric encryption and decryption algorithms, such as the encryption and decryption instruction set of the AES algorithm, the encryption and decryption instruction set of the SM4 algorithm, etc. This can eliminate the need for a dedicated encryption and decryption chip, reduce the amount of hardware in the computing device, and reduce the space occupied in the computing device.

[0070] In addition, the processor supports multi-issue superscalar pipeline technology and, based on an integrated hardware encryption and decryption instruction set, can implement parallel pipeline technology and instruction set parallel technology to accelerate the implementation of symmetric encryption and decryption algorithms.

[0071] Finally, to better understand the technical solutions provided in the embodiments of this application, the following will be combined with... Figure 3 Let's illustrate with examples.

[0072] Taking the SM4 algorithm as an example, registers v24-v31 are 128-bit registers, each used to load a round key for the encryption algorithm. Registers v0-v7 are also 128-bit registers, each used to load data for one computation unit (i.e., one block length). The maximum data length for a single parallel encryption or decryption operation by the processor is 1024.

[0073] Assuming the data to be encrypted is 2432 bits, it is divided into two parts according to the maximum data length. The first 2048 bits are the first part of the data (i.e., the data that meets the preset conditions mentioned above), and the remaining 384 bits (i.e. 16 bytes) are the second part of the data, which is the remaining data.

[0074] The first part of the data can be divided into two data blocks according to the maximum data length, each block containing 1024 bits of data. Each data block can then be further divided into eight computation units according to the block size (i.e., 128 bits). The data for each computation unit can be loaded into eight registers (v0-v7), and then encrypted using the round keys loaded (v24-v31). After encrypting one data block, the encryption process continues for the next data block, repeating this cycle until the first part of the data is processed. Figure 2 As shown.

[0075] For the second part of the data, it can be divided into three computation units according to the group length. The data of each computation unit is loaded by three registers v0-v2, and then combined with the round keys loaded by v24-v31, the loaded data is encrypted, such as... Figure 3 As shown.

[0076] In cases where the length of the second part of the data is greater than 128 and less than or equal to 869, the parallel encryption algorithm for the second part of the data can be implemented using the aforementioned method, such as... Figure 2 As shown.

[0077] In existing technology, the second part of the data is processed by adding 640 bits after the second part of the data to reach the maximum data length, and then encrypting it.

[0078] It should be noted that for the second part of the data, if its length is less than 128 bits, it can be padded to 128 bits before being loaded and processed by register v0. If its data length is equal to 128 bits, it is directly loaded and processed by register v0, as shown below. Figure 2 As shown.

[0079] The above is a description of the symmetric encryption and decryption method provided in the embodiments of this application.

[0080] In summary, in this embodiment, the encryption and decryption processing of the remaining data is no longer done by padding to the maximum data length before parallel processing. Instead, it iterates through all possible computational lengths of the remaining data and creates an independent processing scheme for each possible length. Each processing scheme can divide the remaining data into multiple computational units, and then use hardware encryption / decryption instruction sets and parallel processing technology to accelerate the computation of multiple computational units. This achieves the goal of fully utilizing processor resources and improving computational efficiency at any data length when processing the remaining data.

[0081] Exemplary device

[0082] Accordingly, this application also provides a symmetric encryption / decryption device for use in computing devices.

[0083] like Figure 3 As shown, the device may include:

[0084] The preprocessing module 301 is used to preprocess the data to be processed.

[0085] The data to be processed is either data to be encrypted or data to be decrypted.

[0086] The acquisition module 302 is used to acquire the remaining data in the preprocessed data to be processed.

[0087] The determining module 303 is used to determine N first registers corresponding to the remaining data based on the data length of the remaining data.

[0088] Where N is an integer greater than or equal to 2.

[0089] The first processing module 304 is used to load the remaining data through the N first registers, and to perform encryption or decryption processing on the data loaded in the N first registers in parallel.

[0090] Optionally, the length of the remaining data is less than a first preset length and greater than a second preset length. The first preset length is the maximum data length for the processor to perform one parallel encryption or decryption process, and the second preset length is the block length of the encryption / decryption algorithm. The second preset length is less than the first preset length.

[0091] Optionally, the first processing module 304 may include:

[0092] A grouping unit is used to divide the remaining data group into N groups of data according to the second preset length.

[0093] The data loading unit is used to load one set of data from the N sets of data through the N first registers.

[0094] The processing unit is used to call the N first registers and perform encryption or decryption processing on the data loaded in each first register in parallel.

[0095] Optionally, if the length of the remaining data is less than or equal to a second preset length, the device may further include:

[0096] A data loading module is used to load data from the remaining data through a second register.

[0097] The second processing module is used to encrypt or decrypt the remaining data loaded in the second register.

[0098] The second register is either preset or randomly selected.

[0099] Optionally, the processor integrates a hardware encryption instruction set for encrypting the data to be processed, and / or a hardware decryption instruction set for decrypting the data to be processed.

[0100] The symmetric encryption / decryption device provided in this embodiment belongs to the same concept as the symmetric encryption / decryption method provided in the above embodiments of this application. It can execute the symmetric encryption / decryption method provided in any of the above embodiments of this application and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in this embodiment can be found in the specific processing content of the symmetric encryption / decryption method provided in the above embodiments of this application, and will not be repeated here.

[0101] Exemplary electronic devices

[0102] This application also provides an electronic device, such as... Figure 4 As shown, the electronic device includes a memory 400 and a processor 410.

[0103] The memory 400 is connected to the processor 410 and is used to store programs.

[0104] The processor 410 is used to implement the symmetric encryption and decryption method in the above embodiments by running the program stored in the memory 400.

[0105] Specifically, the aforementioned electronic device may further include: a communication interface 420, an input device 430, an output device 440, and a bus 450.

[0106] The processor 410, memory 400, communication interface 420, input device 430, and output device 440 are interconnected via a bus. Among them:

[0107] Bus 450 may include a pathway for transmitting information between various components of a computer system.

[0108] The processor 410 can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0109] Processor 410 may include a main processor, as well as a baseband chip, modem, etc.

[0110] The memory 400 stores a program that executes the technical solution of the present invention, and may also store an operating system and other key business functions. Specifically, the program may include program code, which includes computer operation instructions. More specifically, the memory 400 may include read-only memory (ROM), other types of static storage devices capable of storing static information and instructions, random access memory (RAM), other types of dynamic storage devices capable of storing information and instructions, disk storage, flash memory, etc.

[0111] Input device 430 may include a device for receiving user input data and information, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer, or gravity sensor.

[0112] Output device 440 may include devices that allow information to be output to a user, such as a display screen, printer, speaker, etc.

[0113] The communication interface 420 may include a device that uses any transceiver to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0114] The processor 410 executes the program stored in the memory 400 and calls other devices, which can be used to implement the various steps of the symmetric encryption and decryption method provided in the above embodiments of this application.

[0115] Exemplary computer program products and storage media

[0116] In addition to the methods and devices described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the symmetric encryption / decryption methods described in the embodiments of this application.

[0117] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0118] Furthermore, embodiments of this application may also be storage media storing a computer program, which is executed by a processor using the steps of the symmetric encryption / decryption method described in the embodiments of this application.

[0119] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0120] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0121] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0122] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0123] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0124] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0125] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0126] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0127] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0128] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A symmetric encryption / decryption method, characterized in that, Applied to a processor, the method includes: Preprocessing is performed on the data to be processed; wherein the data to be processed is data to be encrypted or data to be decrypted. Obtain the remaining data in the preprocessed data to be processed; wherein, the remaining data is the data in the data to be processed after removing the data whose length is an integer multiple of a first preset length, and the first preset length is the maximum data length for the processor to perform one parallel encryption or decryption process; Based on the length of the remaining data, determine the N corresponding first registers; N is an integer greater than or equal to 2; The remaining data is loaded through the N first registers, and the data loaded in the N first registers is encrypted or decrypted in parallel.

2. The symmetric encryption / decryption method according to claim 1, characterized in that, The length of the remaining data is less than a first preset length and greater than a second preset length. The first preset length is the maximum data length for which the processor performs one parallel encryption or decryption process. The second preset length is the block length of the symmetric encryption / decryption algorithm. The second preset length is less than the first preset length.

3. The symmetric encryption / decryption method according to claim 2, characterized in that, The process of loading the remaining data through the N first registers and encrypting or decrypting the data loaded in the N first registers in parallel includes: According to the second preset length, the remaining data is divided into N groups of data; One set of data from the N sets of data is loaded through the N first registers respectively; The N first registers are invoked, and the data loaded in each first register is encrypted or decrypted in parallel.

4. The symmetric encryption / decryption method according to claim 2, characterized in that, If the length of the remaining data is less than or equal to the second preset length, the method further includes: Data from the remaining data is loaded through a second register; The remaining data loaded in the second register is encrypted or decrypted; the second register is preset or randomly selected.

5. The symmetric encryption / decryption method according to any one of claims 1 to 4, characterized in that, The processor integrates a hardware encryption instruction set for encrypting the data to be processed, and / or a hardware decryption instruction set for decrypting the data to be processed.

6. A symmetrical encryption / decryption device, characterized in that, Applied to a processor, the device includes: A preprocessing module is used to preprocess the data to be processed; wherein the data to be processed is data to be encrypted or data to be decrypted. The acquisition module is used to acquire the remaining data in the preprocessed data to be processed; wherein, the remaining data is the data in the data to be processed after removing the data whose length is an integer multiple of a first preset length, and the first preset length is the maximum data length for the processor to perform one parallel encryption or decryption process; The determining module is used to determine N first registers corresponding to the remaining data based on the data length of the remaining data; N is an integer greater than or equal to 2. The first processing module is used to load the remaining data through the N first registers, and to perform encryption or decryption processing on the data loaded in the N first registers in parallel.

7. The symmetric encryption / decryption device according to claim 6, characterized in that, The length of the remaining data is less than a first preset length and greater than a second preset length. The first preset length is the maximum data length for which the processor performs one parallel encryption or decryption process. The second preset length is the block length of the symmetric encryption / decryption algorithm. The second preset length is less than the first preset length.

8. The symmetric encryption / decryption device according to claim 7, characterized in that, The first processing module includes: A grouping unit is used to divide the remaining data group into N groups of data according to the second preset length; A data loading unit is used to load one set of data from the N sets of data through the N first registers respectively; The processing unit is used to call the N first registers and perform encryption or decryption processing on the data loaded in each first register in parallel.

9. An electronic device, characterized in that, include: Memory and processor; The memory is connected to the processor and is used to store programs; The processor is used to implement the symmetric encryption / decryption method as described in any one of claims 1 to 5 by running the program in the memory.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the symmetric encryption / decryption method as described in any one of claims 1 to 5.

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