A method for encrypted self-starting of an SOC chip

Abstract

The application provides a self-starting encryption method of an SOC chip, comprising the following steps: configuring a flash program for encryption starting in the SOC chip; writing a first decryption reference number and a second decryption reference number in a boot program of an embedded device of the SOC chip; determining a first key address and a second key address by using the first decryption reference number and the second decryption reference number; determining a key value storage address in the flash program based on the first key address and the second key address; and in response to a self-starting request of the boot program, when the obtained first decryption reference number and the second decryption reference number match the key value storage address, entering a moving operation of executing the boot program to complete the self-starting encryption of the SOC chip. The method of the application uses the boot program in the SOC chip to set a global variable and cooperates with the flash storage key in the chip to perform encryption, which does not bring additional hardware peripherals and is more convenient for users to use in various scenes.

Description

Technical Field

[0001] This invention relates to the field of embedded technology, and in particular to an encrypted self-starting method for a SOC chip. Background Technology

[0002] A System on Chip (SOC) chip, also known as a system-on-a-chip, integrates components such as a microprocessor CPU, digital signal processing, interfaces, and storage onto a single chip. It is a typical product type in the field of chip design. Due to its advantages such as high performance, low cost, and short development cycle, SOC has gradually become the mainstream of current chip design.

[0003] With current technology, as long as users obtain the SOC chip components themselves, they can initially understand some of the SOC chip's functions through their experience and some experimentation. However, in actual applications, chip designers are unaware of the user's identity. Users can obtain the SOC chip itself through various means, and competitors can relatively easily obtain the SOC chip and conduct preliminary analysis of its functions. This obviously harms the interests of chip designers.

[0004] Designing a System-on-a-Chip (SoC) chip requires significant human and material resources. As chip designers, they don't want anyone who obtains SoC components, especially competitors, to have a basic understanding of the chip. Therefore, a certain level of encryption for SoC chips is essential. However, while many current SoC chips offer encryption, they primarily target encryption during transmission in fields like communication, audio, and video, rather than encrypting the chip's own startup process in these scenarios. Therefore, proposing an effective SoC chip encryption method specifically addressing these needs has a real market and application demand. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to configure the key to start the boot program so that the SOC chip can work normally and prevent non-ideal users from completing the boot process; in view of this, the present invention provides an encrypted self-boot method for SOC chips.

[0006] The technical solution adopted in this invention is an encrypted self-starting method for a SOC chip, comprising:

[0007] Step S1: Configure a flash program for encrypted startup in the SOC chip, wherein the flash program is in read-only mode and the content is burned using random numbers;

[0008] Step S2: Write a first decryption reference number and a second decryption reference number, both of which are 32 bits, into the boot program of the SOC chip embedded device;

[0009] Step S3: Determine the first key address using the convolution value of the matrix formed by the high 16-bit data matrix of the first decryption reference number and the 4-bit matrix formed by the second decryption reference number; determine the second key address using the convolution value of the matrix formed by the high 16-bit data matrix of the second decryption reference number and the 4-bit matrix formed by the first decryption reference number.

[0010] Step S4: Determine the key value storage address in the flash program based on the first key address and the second key address;

[0011] Step S5: In response to the bootloader's self-start request, repeat step S3. When the obtained first decryption reference number and second decryption reference number match the key value storage address, proceed with the bootloader's relocation operation to complete the SOC chip's encrypted self-start.

[0012] In one embodiment, step S3 specifically includes: dividing the first decryption reference number and the second decryption reference number into 8 groups of 4-bit data from high to low, and selecting the 4-bit data in the following order: the first data of the first group, the second data of the second group, the third data of the third group, and the fourth data of the fourth group.

[0013] In one embodiment, step S3 specifically includes:

[0014] Using the convolution value of the matrix formed by the high 16 bits of the first decryption reference number and the 4 bits of the second decryption reference number, a 3×3 first key matrix is ​​formed. The elements of the first key matrix are arranged in reverse order, with each element occupying 3 bits and the high bits padded with zeros to form a 32-bit first key address.

[0015] The high 16-bit data matrix of the second decryption reference number and the convolution value of the matrix formed by the 4-bit first decryption reference number are used to form a 3×3 second key matrix. The elements of the second key matrix are arranged in reverse order, with each element occupying 3 bits and the high bits padded with zeros to form a 32-bit second key address.

[0016] In one implementation, step S4 includes:

[0017] The sum of the first key address and the flash base address is determined as the first part of the key value storage address;

[0018] The sum of the second key address and the flash base address is determined as the second part of the key value storage address.

[0019] In one embodiment, step S2, the configuration process for the first decryption reference number and the second decryption reference number, includes:

[0020] Configure the lower 16 bits of the first decryption reference number to be the same as the lower 16 bits of the first part of the key value storage address;

[0021] Configure the lower 16 bits of the second decryption reference number to be the same as the lower 16 bits of the second part of the key value storage address.

[0022] In one implementation, step S5, when the obtained first decryption reference number and second decryption reference number match the key value storage address, includes:

[0023] The lower 16 bits of the first decryption reference number are the same as the lower 16 bits of the first part of the key value storage address;

[0024] The lower 16 bits of the second decryption reference number are the same as the lower 16 bits of the second part of the key value storage address.

[0025] In one embodiment, the method further includes;

[0026] The first and second decryption reference numbers are pre-configured as random values ​​in the bootloader.

[0027] In one implementation, a first decryption reference number and a second decryption reference number are written based on the SWD protocol.

[0028] Another aspect of the present invention provides an electronic device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the encrypted self-starting method for the SOC chip as described in any of the preceding claims.

[0029] Another aspect of the present invention provides a computer storage medium storing a computer program that, when executed by a processor, implements the steps of the encrypted self-starting method for the SOC chip as described in any of the preceding claims.

[0030] By adopting the above technical solution, the present invention has at least the following advantages:

[0031] This invention utilizes a method of setting global variables in the bootloader of an SOC chip in conjunction with storing the key in the on-chip flash for encryption. Firstly, it does not introduce additional hardware peripherals. Compared to some methods that require dedicated decryption equipment for startup, this method is more convenient for users to use in various scenarios. Secondly, the complexity of the encryption operation itself is addressed during the design process and the configuration of key hiding parameters and flash memory before delivery to the user. For normal users, it is only necessary to write the key hiding parameters using the SWD general protocol, which is simple and convenient for users and will not cause excessive operational difficulties for normal users during decryption and startup due to encryption-related design. Attached Figure Description

[0032] Figure 1 This is a flowchart illustrating the encrypted self-starting method for a SOC chip according to an embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the logic framework of the encrypted self-starting method for a SOC chip according to an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of an electronic device structure according to an embodiment of the present invention. Detailed Implementation

[0035] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments.

[0036] In the accompanying drawings, the thickness, size, and shape of the objects have been slightly exaggerated for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0037] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire listed feature, not individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0038] As used herein, the terms “basically,” “approximately,” and similar terms are used as terms of approximation rather than terms of degree, and are intended to describe inherent biases in measured or calculated values ​​that will be recognized by those skilled in the art.

[0039] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so specified herein.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] The first embodiment of the present invention provides an encrypted self-starting method for a SOC chip, such as... Figure 1 As shown, it includes the following steps:

[0042] Step S1: Configure a flash program for encrypted startup in the SOC chip, wherein the flash program is in read-only mode and the content is burned using random numbers;

[0043] Step S2: Write a first decryption reference number and a second decryption reference number, both of which are 32 bits, into the boot program of the SOC chip embedded device;

[0044] Step S3: Determine the first key address using the convolution value of the matrix formed by the high 16-bit data matrix of the first decryption reference number and the 4-bit matrix formed by the second decryption reference number; determine the second key address using the convolution value of the matrix formed by the high 16-bit data matrix of the second decryption reference number and the 4-bit matrix formed by the first decryption reference number.

[0045] Step S4: Determine the key value storage address in the flash program based on the first key address and the second key address;

[0046] Step S5: In response to the bootloader's self-start request, repeat step S3. When the obtained first decryption reference number and second decryption reference number match the key value storage address, proceed with the bootloader's relocation operation to complete the SOC chip's encrypted self-start.

[0047] Specifically, in step S3, the 4-bit first decryption reference number and the second decryption reference number specifically include: dividing the first decryption reference number and the second decryption reference number into 8 groups of 4-bit data from high to low, and selecting the 4-bit data in the following order: the first data of the first group, the second data of the second group, the third data of the third group, and the fourth data of the fourth group.

[0048] In this embodiment, step S3 may specifically include:

[0049] Using the convolution value of the matrix formed by the high 16 bits of the first decryption reference number and the 4 bits of the second decryption reference number, a 3×3 first key matrix is ​​formed. The elements of the first key matrix are arranged in reverse order, with each element occupying 3 bits and the high bits padded with zeros to form a 32-bit first key address.

[0050] The high 16-bit data matrix of the second decryption reference number and the convolution value of the matrix formed by the 4-bit first decryption reference number are used to form a 3×3 second key matrix. The elements of the second key matrix are arranged in reverse order, with each element occupying 3 bits and the high bits padded with zeros to form a 32-bit second key address.

[0051] In this embodiment, step S4 may further include:

[0052] The sum of the first key address and the flash base address is determined as the first part of the key value storage address;

[0053] The sum of the second key address and the flash base address is determined as the second part of the key value storage address.

[0054] In one embodiment, step S2, the configuration process for the first decryption reference number and the second decryption reference number, includes:

[0055] Configure the lower 16 bits of the first decryption reference number to be the same as the lower 16 bits of the first part of the key value storage address;

[0056] Configure the lower 16 bits of the second decryption reference number to be the same as the lower 16 bits of the second part of the key value storage address.

[0057] In this embodiment, when the obtained first decryption reference number and second decryption reference number match the key value storage address, it can specifically include:

[0058] The lower 16 bits of the first decryption reference number are the same as the lower 16 bits of the first part of the key value storage address;

[0059] The lower 16 bits of the second decryption reference number are the same as the lower 16 bits of the second part of the key value storage address.

[0060] In this embodiment, in order to improve confidentiality, the first decryption reference number and the second decryption reference number need to be pre-configured as random values ​​in the bootloader.

[0061] In this embodiment, the first decryption reference number and the second decryption reference number can be written based on the SWD protocol.

[0062] refer to Figure 2 The method provided in this embodiment will now be described in detail.

[0063] During the startup process, the SOC chip first executes the bootloader, moving the corresponding bitfile into memory. Then, it executes the program according to the bitfile, completing the movement, loading, and execution of the user program. The SWD interface protocol allows configuration of values ​​corresponding to various memory addresses, providing the foundation for encrypted startup of the SOC chip. Based on this process, this invention proposes an encrypted self-starting method. Using this method, for any chip, before delivery to the user, encryption is performed according to the following steps. Then, the chip's dedicated key is provided to the user. The user writes the key according to the SWD protocol, enabling normal startup and achieving independent encryption for each chip.

[0064] A dedicated encrypted boot flash is designed inside the SOC chip to store key hiding parameters. The content in the flash is written in before delivery to the user. The content is written using random numbers and configured in read-only mode to prevent accidental erasure by the user.

[0065] The bootloader includes two 32-bit global variables, A (first decryption reference) and B (second decryption reference). The high 16 bits of A and B store address parsing information, and the low 16 bits store the key value. The values ​​of A and B required for a correct boot are calculated based on the contents of the dedicated encryption boot flash. Because the flash storage space is large, different combinations of A and B can effectively perform independent encryption for each chip, ensuring that the key value is different for each chip during decryption, thus improving the encryption effect. The decryption references are used to perform decryption for normal users, who will obtain the address and value of A and B for each chip.

[0066] For 32-bit data A, the data is divided into groups of 4 bits each, from high to low, denoted as A11, A12, A13, A14; the second group is denoted as A21, A22, A23, A24; and so on, up to A81, A82, A83, A84, for a total of 8 groups of binary numbers, which make up data A. Similarly, data B is also composed of the same data format, denoted as B11, B12, B13, B14 up to B81, B82, B83, B84;

[0067] For data A, extract the high 16 bits to form matrix A as follows:

[0068]

[0069] For data B, extract B11, B22, B33, and B44 to form matrix B as follows:

[0070]

[0071] Convolving matrices A and B yields a new 3x3 matrix C (the first key matrix). The specific operation involves... and Find the corresponding row and column positions of the matrix, multiply them sequentially, and then add them to get C11, i.e., C11 = A11*B11 + A12*B22 + A21*B33 + A22*B44; for and Multiply and sum the corresponding row and column positions of the matrix to get C12, and so on, to obtain matrix C:

[0072]

[0073] For any element of matrix C, they are arranged in reverse order, and each element occupies 3 bits to form the key address C. Specifically, C11 corresponds to the 0th, 1st, and 2nd bits of address C, C12 corresponds to the 3rd, 4th, and 5th bits of address C, C13 corresponds to the 6th, 7th, and 8th bits of address C, and so on. C33 corresponds to the 24th, 25th, and 26th bits of address C. Since the address is 32 bits of data, the remaining high bits are padded with 0 to form the key address C (the first key address).

[0074] For data B, extract the high 16 bits and form matrix B* as follows:

[0075]

[0076] For data A, extract A11, A22, A33, and A44 to form matrix A* as follows:

[0077]

[0078] Convolving matrices A* and B* yields a new 3x3 matrix D (the second key matrix). The specific operation involves... and Find the corresponding row and column positions of the matrix, multiply them sequentially, and then add them to get D11, i.e., D11 = B11*A11 + B12*A22 + B21*A33 + B22*A44; for and Multiply and sum the corresponding row and column positions of the matrix to obtain D12, and so on, to obtain matrix D:

[0079]

[0080] For any element of matrix D, they are arranged in reverse order, and each element occupies 3 bits to form the key address D. Specifically, C11 corresponds to the 0th, 1st, and 2nd bits of address D, D12 corresponds to the 3rd, 4th, and 5th bits of address D, D13 corresponds to the 6th, 7th, and 8th bits of address D, and so on, with D33 corresponding to the 24th, 25th, and 26th bits of address D. Since the address is 32 bits of data, the remaining high bits are padded with 0s to form the key address D (the second key address).

[0081] After padding the high bits of key addresses C and D with 0s and adding the flash base address, the resulting address can be used as the address for storing the key value in the dedicated encrypted boot flash. Specifically, the key C* (the first part of the key value storage address) in the flash = flash base address + address C, and the address D* (the second part of the key value storage address) = flash base address + address D. In the design of A and B, the lower 16 bits of A and B are made the same as the lower 16 bits of C*, and the lower 16 bits of B and D* are the same. For each chip, its data A and B are independent as described in step 3, so the address where the key is written is also different for each chip. Therefore, before delivery to the user, the encrypted boot flash of each chip needs to be operated individually to write the key according to the key address. In this way, even if a non-ideal user reads the contents of the flash by means of traversal, they will not be able to obtain the key, which can effectively enhance the encryption effect.

[0082] A startup determination program is designed in the boot program. Based on the high 16 bits of A and B, the addresses of C* and D* are calculated according to the above method, and a determination is made: only when the low 16 bits of A are equal to the low 16 bits of C* and the low 16 bits of B are equal to the low 16 bits of D* can the boot program's relocation operation be entered normally.

[0083] For the initial values ​​of A and B, during the design process, the bootloader is initially configured with random values ​​that cannot complete the startup. Therefore, the above steps are necessary to write A and B into the corresponding decryption reference numbers to complete the normal startup. Non-ideal users are unaware of the above configuration of A, B, X and the dedicated encrypted flash, as well as the decryption reference numbers corresponding to each chip, and cannot achieve the purpose of cracking. Each chip delivered to normal users will be calculated and decrypted according to the above encryption method to obtain the corresponding decryption reference numbers A and B, and the value of the decryption reference number corresponding to the address of the global variables A and B will be informed to the user. Users need to write an independent key value for each chip to meet the startup configuration in step 9 and execute the bootloader normally.

[0084] In practical applications, the normal method for users to write key values ​​is as follows: using the SWD protocol, write the corresponding decryption reference values ​​provided by the chip to addresses A and B sequentially. The SWD protocol is a general-purpose serial interface debugging protocol that can complete data read and write operations to a specified memory address. Users only need to understand this protocol and follow the protocol standard to complete the writing of decryption reference values. To facilitate user operation, a demonstration case will be provided. Because the SWD protocol is a general protocol, users can read and write according to the protocol themselves, or they can use the provided demonstration case to read and write. After writing, the user performs a power-on reset on the chip. At this time, the values ​​of global variables A and B remain the written decryption reference values. After the chip is powered on and reset, the boot program is re-executed. If the values ​​of A and B are correct, the boot program will continue to execute the transfer, and then execute the user program to complete the chip's self-boot.

[0085] Compared with the prior art, this embodiment has at least the following advantages:

[0086] In this embodiment, encryption is performed by setting global variables in the bootloader of the SOC chip in conjunction with storing the key in the on-chip flash. Firstly, it does not require additional hardware peripherals. Compared with some methods that require dedicated decryption equipment to start, this method is more convenient for users to use in various scenarios.

[0087] In this embodiment, the complexity of the encryption operation itself is also addressed during the design process and the configuration of key hiding parameters and flash before delivery to the user. For normal users, it is only necessary to use the SWD general protocol to write the key hiding parameters. The operation is simple and convenient, making it easy for users to use. The encryption-related design will not cause too much operational trouble for normal users during decryption and startup.

[0088] 3) In this embodiment, the key hiding parameters and the verification key of the on-chip encrypted boot dedicated flash are used together, as well as the relevant design of the key hiding parameters and flash writing content of the present invention, to effectively block non-ideal users from the perspective of traversal attempts, brute force cracking, etc.

[0089] 4) In this embodiment, each chip has a unique key, unlike other encryption methods where a batch of chips often share the same encryption, ensuring that each chip's encryption is independent.

[0090] A second embodiment of the present invention provides an electronic device, such as... Figure 3 As shown, it can be understood as a physical device, including a processor and a memory storing processor-executable instructions. When the instructions are executed by the processor, the following operations are performed:

[0091] Step S1: Configure a flash program for encrypted startup in the SOC chip, wherein the flash program is in read-only mode and the content is burned using random numbers;

[0092] Step S2: Write a first decryption reference number and a second decryption reference number, both of which are 32 bits, into the boot program of the SOC chip embedded device;

[0093] Step S3: Determine the first key address using the convolution value of the matrix formed by the high 16-bit data matrix of the first decryption reference number and the 4-bit matrix formed by the second decryption reference number; determine the second key address using the convolution value of the matrix formed by the high 16-bit data matrix of the second decryption reference number and the 4-bit matrix formed by the first decryption reference number.

[0094] Step S4: Determine the key value storage address in the flash program based on the first key address and the second key address;

[0095] Step S5: In response to the bootloader's self-start request, repeat step S3. When the obtained first decryption reference number and second decryption reference number match the key value storage address, proceed with the bootloader's relocation operation to complete the SOC chip's encrypted self-start.

[0096] In the third embodiment of the present invention, the process of the encrypted self-booting method for the SOC chip is the same as that of the first and second embodiments. The difference lies in the engineering implementation: this embodiment can be implemented using software plus necessary general-purpose hardware platforms. While hardware implementation is also possible, the former is often a better approach. Based on this understanding, the method of the present invention can be embodied in the form of a computer software product stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including several instructions to cause a device to execute the method described in the embodiments of the present invention.

[0097] Through the description of specific embodiments, a more in-depth and specific understanding should be gained of the technical means and effects adopted by the present invention to achieve the intended purpose. However, the accompanying drawings are only provided for reference and illustration and are not intended to limit the present invention.

Claims

1. A method for encrypted self-booting of a SOC chip, characterized in that, include: Step S1: Configure a flash program for encrypted startup in the SOC chip, wherein the flash program is in read-only mode and the content is burned using random numbers; Step S2: Write a first decryption reference number and a second decryption reference number, both of which are 32 bits, into the boot program of the SOC chip embedded device; Step S3: Determine the first key address using the convolution value of the matrix formed by the high 16-bit data matrix of the first decryption reference number and the 4-bit matrix formed by the second decryption reference number; determine the second key address using the convolution value of the matrix formed by the high 16-bit data matrix of the second decryption reference number and the 4-bit matrix formed by the first decryption reference number. Step S4: Determine the key value storage address in the flash program based on the first key address and the second key address; Step S5: In response to the bootloader's self-starting request, repeat step S3. When the obtained first decryption reference number and second decryption reference number match the key value storage address, proceed to execute the bootloader's relocation operation to complete the SOC chip's encrypted self-starting. In step S3, the 4-bit first decryption reference number and the 4-bit second decryption reference number specifically include: dividing the first decryption reference number and the second decryption reference number into 8 groups of 4-bit data from high to low, and selecting the 4-bit data in the following order: the first data of the first group, the second data of the second group, the third data of the third group, and the fourth data of the fourth group. Step S3 specifically includes: Using the convolution value of the matrix formed by the high 16 bits of the first decryption reference number and the 4 bits of the second decryption reference number, a 3×3 first key matrix is ​​formed. The elements of the first key matrix are arranged in reverse order, with each element occupying 3 bits and the high bits padded with zeros to form a 32-bit first key address. The high 16-bit data matrix of the second decryption reference number and the convolution value of the matrix formed by the 4-bit first decryption reference number are used to form a 3×3 second key matrix. The elements of the second key matrix are arranged in reverse order, with each element occupying 3 bits and the high bits padded with zeros to form a 32-bit second key address.

2. The encrypted self-booting method for a SOC chip according to claim 1, characterized in that, Step S4 includes: The sum of the first key address and the flash base address is determined as the first part of the key value storage address; The sum of the second key address and the flash base address is determined as the second part of the key value storage address.

3. The encrypted self-booting method for a SOC chip according to claim 2, characterized in that, In step S2, the configuration process for the first decryption reference number and the second decryption reference number includes: Configure the lower 16 bits of the first decryption reference number to be the same as the lower 16 bits of the first part of the key value storage address; Configure the lower 16 bits of the second decryption reference number to be the same as the lower 16 bits of the second part of the key value storage address.

4. The encrypted self-booting method for a SOC chip according to claim 3, characterized in that, In step S5, when the obtained first decryption reference number and second decryption reference number match the key value storage address, the process includes: The lower 16 bits of the first decryption reference number are the same as the lower 16 bits of the first part of the key value storage address; The lower 16 bits of the second decryption reference number are the same as the lower 16 bits of the second part of the key value storage address.

5. The encrypted self-booting method for a SOC chip according to claim 4, characterized in that, The method further includes; The first and second decryption reference numbers are pre-configured as random values ​​in the bootloader.

6. The encrypted self-booting method for a SOC chip according to claim 1, characterized in that, Based on the SWD protocol, write the first decryption reference number and the second decryption reference number.

7. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, it implements the steps of the encrypted self-booting method for the SOC chip as described in any one of claims 1 to 6.

8. A computer storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the encrypted self-starting method for a SOC chip as described in any one of claims 1 to 6.

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