DUT, method, electronic device and storage medium for increasing parallel test lane rate

Abstract

The application discloses a chip for improving parallel test channel rate, a method, an electronic device and a storage medium, and relates to the fields of chip circuit structure design and test technology. The chip comprises a plurality of receiving circuits. Each receiving circuit comprises a delay module, a first buffer and a data reading control module. The delay module is used for receiving test data and adjusting the data delay of the corresponding receiving circuit, so that the test data is located in a data sampling window when reaching a sampling point. The first buffer is connected with the delay module and is used for buffering valid data. The valid data is from the test data in the sampling window. The data reading control module is used for controlling the operation of reading the valid data of the plurality of first buffers after the valid data is stored in the first buffers of the plurality of receiving circuits. The application can improve or overcome the timing offset problem between the IO pins of different test channels, thereby facilitating the improvement of the overall working frequency of the parallel test channel, and being suitable for chip test scenes.

Description

Technical Field

[0001] This invention relates to the field of chip circuit structure design and testing technology. In particular, it relates to a chip under test, a method, an electronic device, and a storage medium for improving the rate of parallel test channels. Background Technology

[0002] With advancements in integrated circuit manufacturing processes, chip integration density has continuously increased, leading to a dramatic increase in the number of chip pins. Traditional DUT (Device Under Test, referring to the chip under test) circuit structures suffer from problems such as an excessive number of parallel test pins and difficulty in increasing test frequency.

[0003] For example, traditional testing methods use a clock to input a set of test data in parallel to the chip under test. The number of pins for this set of parallel test data may be as high as hundreds or even thousands. These parallel test pins need to receive clock signals synchronously, but due to factors such as process and routing, there is a timing skew between different test pins, which restricts the overall operating frequency of the chip's parallel test channels. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip under test, method, electronic device and storage medium for improving the rate of parallel test channels, which can improve or overcome the timing offset problem between the I / O pins of different test channels, thereby facilitating the improvement of the overall operating frequency of the parallel test channels.

[0005] To achieve the above-mentioned objectives, the following technical solution is adopted: This application provides a chip, the chip comprising: Multiple receiving circuits, each receiving circuit including: The delay module is used to receive test data and adjust the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point. A first buffer, connected to the delay module, is used to buffer valid data, which comes from test data within the sampling window; and, The data read control module is used to control the operation of reading valid data from multiple first buffers after valid data has been stored in the first buffers of multiple receiving circuits.

[0006] According to a specific implementation of an embodiment of this application, each receiving circuit further includes: The data sampling module is used to sample data transmitted through the delay module at the sampling point according to the test clock; The data detection module is used to detect whether the data from the data sampling module is the test data, so as to determine whether the data delay of the delay module needs to be adjusted.

[0007] According to a specific implementation of an embodiment of this application, the data detection module is further configured to, when detecting that the data from the data sampling module is the test data, determine that the data delay of the delay module does not need to be adjusted; and, This is used to determine that the data delay of the delay module needs to be adjusted when the data from the data sampling module is not the test data.

[0008] According to a specific implementation of an embodiment of this application, the data detection module is further configured to, if it is determined that the data delay of the delay module needs to be adjusted, adjust it by moving it forward or backward based on the currently determined data delay; After each adjustment, test code sampling and data detection are repeated to obtain the data detection results after each adjustment; Compare the data detection results after each adjustment until a sampling window with the largest sampling width is found.

[0009] According to a specific implementation of an embodiment of this application, the chip further includes: a decoding module, located after the data sampling module and before the first buffer, for decoding the sampled data after sampling the data via the delay module, and sending the decoded valid data to the first buffer; The cache read control module is used to control whether to read and send cached test data based on preset conditions.

[0010] According to a specific implementation of an embodiment of this application, the decoding module is specifically used to determine the type of the decoded content after decoding the sampled data; If the content is valid data, it is sent to the first buffer. If the content is of type sync header identifier, it is discarded.

[0011] According to a specific implementation of an embodiment of this application, the cache read control module is specifically used to perform an operation of reading a valid data from the first cache of each of the multiple receiving circuits when none of the first caches of the multiple receiving circuits are empty.

[0012] According to a specific implementation of an embodiment of this application, the chip further includes: a plurality of transmitting circuits, each transmitting circuit including: The second buffer is used to receive and store the test data that needs to be sent. The encoding module is connected to the output of the second buffer and is used to encode the test data output from the second buffer and send the encoded test data.

[0013] According to a specific implementation of an embodiment of this application, the transmitting circuit further includes: a data transmitting module, used to transmit test data to the test device during data training with the test device to confirm whether the transmitting channel link is normal; The output terminals of the data transmission module and the encoding module are also equipped with a data transmission switching switch.

[0014] Secondly, embodiments of the present invention also provide a chip testing method, comprising: Receive test data sent by the test equipment and adjust the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point; Cache valid data, which comes from test data within the sampling window; and, After detecting that each receiving circuit has stored valid data, control the operation of reading the valid data buffered by each receiving circuit.

[0015] According to a specific implementation of an embodiment of this application, after receiving test data sent by a test device and adjusting the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point, the method further includes: sampling the data at the sampling point according to a test clock. The system detects whether the data from the data sampling module is the test data in order to determine whether the data delay of each corresponding receiving circuit needs to be adjusted.

[0016] According to a specific implementation of an embodiment of this application, the step of detecting whether the data from the data sampling module is the test data, so as to determine whether the data delay of each corresponding receiving circuit needs to be adjusted, includes: if the data from the data sampling module is detected to be the test data, then determining that the data delay of the delay module does not need to be adjusted; and, If the data detected from the data sampling module is not the test data, it is determined that the data delay of the delay module needs to be adjusted.

[0017] According to a specific implementation of an embodiment of this application, after determining that the data delay of the delay module needs to be adjusted, the method further includes: adjusting the data delay forward and backward based on the currently determined data delay; After each adjustment, test code sampling and data detection are repeated to obtain the data detection results after each adjustment; Compare the data detection results after each adjustment until a sampling window with the largest sampling width is found.

[0018] Thirdly, this application also provides an electronic device, comprising: One or more processors; memory; The memory stores one or more executable program codes, and the one or more processors read the executable program codes stored in the memory to run the program corresponding to the executable program codes, so as to execute any of the methods described in the second aspect.

[0019] Fourthly, this application also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement the method described in any of the second aspects. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1a This is a schematic block diagram of the circuit structure of an embodiment of the chip in this application.

[0022] Figure 1b This is a schematic block diagram of the circuit structure of another embodiment of the chip in this application.

[0023] Figure 2 This is a schematic block diagram of the circuit structure of another embodiment of the chip in this application.

[0024] Figure 3 This is a schematic diagram of the chip as a test environment architecture for a DUT (Device Under Test) according to an embodiment of this application.

[0025] Figure 4 This is a schematic diagram of the test environment architecture for a chip as the DUT in another embodiment of this application.

[0026] Figure 5 This is a schematic flowchart of an embodiment of the chip testing method of this application.

[0027] Figure 6 for Figure 5 A schematic diagram of an embodiment of step S210.

[0028] Figure 7 This is a schematic diagram of the structure of an embodiment of the electronic device of this application. Detailed Implementation

[0029] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0031] Chip testing is an indispensable part of the chip design and manufacturing process. It detects defects and ensures that the chip meets design specifications and performance requirements. Chip testing typically requires the use of Automatic Test Equipment (ATE) to perform various test modes and tests on the chip to generate test results and reports.

[0032] However, existing ATE testing solutions have some problems: large skew (timing offset) between test data I / O channels leads to poor signal quality and low test result reuse rate. For example, related technologies use a clock to drive a set of test data I / Os to send the test pattern (vector) to the chip under test. For large chips, the width of this set of I / O lines may be hundreds or even thousands, and this set of I / Os and the clock have a synchronous timing logic relationship. With so many lines, data sampling needs to simultaneously meet the setup and hold time requirements. The data sampling window of each I / O line may be different, making it difficult to find a common data sampling window. Coupled with the complexity of the process and the high frequency requirements, the physical implementation needs to ensure that the skew between parallel data I / O channels is as small as possible, which is very difficult to achieve physically, and it is difficult to increase the overall frequency.

[0033] For parallel test interfaces, the operating frequency refers to the data transmission rate of test data, specifically the number of bits of test data that can be transmitted per clock cycle. A higher operating frequency means that more test data can be transmitted per unit of time, thereby improving transmission rate and test efficiency. Therefore, if the overall frequency is difficult to increase, it means that the transmission rate of the parallel test channel is limited, and the transmission speed of test data cannot reach a high level, thus affecting test efficiency and performance.

[0034] Figure 1a This is a schematic block diagram of the circuit structure of an embodiment of the chip in this application; Figure 3 This is a schematic diagram of the test environment architecture for an embodiment of the chip used as the DUT in this application. Please refer to... Figure 1a and Figure 3 In this application embodiment, the circuit topology (i.e. circuit structure) of the chip under test is improved to provide a chip under test that can at least improve or overcome the timing offset problem between the I / O pins of different test channels.

[0035] refer to Figure 1aThe chip under test 100 includes: a plurality of receiving circuits 110, each receiving circuit 110 including: The delay module 111 is used to receive test data and adjust the data delay of the corresponding receiving circuit 110 so that the test data is within the data sampling window when it arrives at the sampling point. The data sampling window refers to the time range for sampling test data in the time domain. By adjusting the data delay of different receiving circuits through the delay module 111, the timing offset problem between the I / O pins of different test channels can be eliminated or reduced, so that the test data is within the data sampling window when it arrives at the sampling point. This can improve the accuracy and reliability of test data sampling.

[0036] A first buffer 112 is connected to the delay module 111 and is used to buffer valid data, which comes from the test data within the sampling window; and, The data reading control module 120 is used to control the operation of reading valid data from multiple first buffers after valid data has been stored in the first buffers of multiple receiving circuits.

[0037] In this embodiment, since each receiving circuit 110 has a separate delay module 111 (IODELAY) with delay control logic, which is used to adjust the time when the test data arrives at the sampling point on each receiving circuit 110, so that the test data arrives at the sampling point within the data sampling window, the validity and accuracy of the data can be guaranteed, thereby improving the accuracy and reliability of test data sampling.

[0038] Furthermore, since the I / O (input / output) pins of each receiving circuit are no longer in a parallel bus sampling relationship, the data delay can be adjusted and sampled independently on each receiving circuit. This achieves timing decoupling between the test I / O pins and ensures that the test data arrives at the sampling point within the data sampling window, improving the sampling accuracy. It also helps to increase the sampling frequency, thereby improving the overall transmission rate of test data in the parallel test channel.

[0039] See Figure 1b In one example, it includes: a receive port 101 for receiving test data; A receiving circuit 110 corresponding to each of the receiving ports 101; The corresponding data reading control module 120 of the receiving circuit 110; And, a custom test logic module 130 based on test cases. The receiving circuit 110 is provided with a delay module 111 and a first buffer 112. The input terminal of the delay module 111 is connected to the receiving port 101, the output terminal of the delay module 111 is connected to the input terminal of the first buffer 112, and the output of the first buffer 112 is connected to the test logic module 130. The delay module 111 is provided for each receiving circuit 110, at least one of which is configured to control the delay time of the test data received from the IO interface arriving at the sampling point. Specifically, the delay module 111 can be a digital delay line (DDL), an analog delay line (ADL), or other circuits capable of delay control. The delay module 111 may also include a delay setting unit, used to set the time delay of each delay module 111 according to the determined data delay, so that the time of the test data arriving at the predetermined sampling point on each receiving circuit 110 is the same or as close as possible, thereby improving the sampling accuracy.

[0040] The data reading control module 120 is used to control the timing of the first buffer 112 sending data to the test logic module 130. In this way, the data sampled by each receiving circuit 110 is first buffered in the first buffer 112. The data reading control module 120 controls the operation of reading valid data from multiple first buffers 112 according to preset conditions and the timing of sending data to the test logic module 130. This can effectively optimize the timing and process of data transmission and improve the efficiency and stability of data transmission.

[0041] Specifically, the delay module 111 is used to adjust the data delay of each receiving circuit 110 so that the data is located within the data sampling window at the rising or falling edge of the sampling clock. Preferably, the data of each receiving circuit 110 is located within the data sampling window and aligned when it arrives at the rising or falling edge of the sampling clock. This ensures the phase consistency and synchronization of the data, overcomes the impact of timing offset between different receiving channel links on the sampling accuracy, and thus improves the sampling accuracy and reliability of the data.

[0042] The receiving port can be a single-ended I / O or a differential I / O.

[0043] In this embodiment, a delay module 111 is added to the receiving circuit 110 of the chip to adjust the time when the test data arrives at the sampling point on each receiving circuit 110. Since a separate delay module 111 (IODELAY) is added to each input channel IO pin for delay control logic before data sampling, the receiving channel IO pins are no longer in a parallel bus sampling relationship. Each IO pin adjusts its delay independently for sampling, achieving timing decoupling between the test IO pins and ensuring that the test data arrives at the sampling point precisely within the sampling window. This improves sampling accuracy and also facilitates increasing the sampling frequency, thereby increasing the overall transmission rate of test data in the parallel test channels.

[0044] Furthermore, since the data delay of each receiving circuit 110 can be adjusted by the delay module 111 so that the data arrives at the sampling point within the data sampling window, accurate data sampling can be ensured in each clock cycle, solving the timing offset problem between different test channels and facilitating the operation of test IO pins at higher frequencies.

[0045] It is understood that the chip provided in this application embodiment is designed to improve the data transmission rate of the parallel test channel. Therefore, different test logic modules 130 can be customized according to the test cases, and the sampled data can be applied to different test scenarios. Since the test data transmission rate is improved, the test efficiency can be improved to a certain extent.

[0046] Please continue reading. Figure 1b In some embodiments, the receiving circuit 110 is further provided with a data sampling module 113, which is located on the link node between the output of the delay module 111 and the first buffer 112, and is used to sample the data via the delay module 111 at the sampling point according to the test clock. The data detection module 114 is located on the link node between the output end of the data sampling module 113 and the first buffer 112. It is used to detect whether the data from the data sampling module is the test data, so as to determine whether the data delay of the delay module needs to be adjusted. That is, it detects the accuracy of the data sampling, so as to determine whether the set data delay time of the delay module 111 needs to be adjusted.

[0047] The data sampling module 113 accurately samples the data transmitted through the delay module 111 according to the test clock, ensuring accurate data sampling within each test clock cycle. The data detection module 114 then detects the sampled data and compares it with preset test data to determine the accuracy of the data sampling. By adjusting the time delay setting of the delay module 111 based on the output of the data detection module 114, the data sampling window can be optimized, improving the reliability and accuracy of the test results.

[0048] See Figure 3 Specifically, the data detection module 114 can be tested and verified using a test bitstream, such as a PRBS code.

[0049] Specifically, the data sampling module 113 may include multiple flip-flops, each corresponding to a receiving circuit 110 for sampling the test data. The flip-flops may be D flip-flops or other circuits capable of data sampling. The data sampling module 113 may also include a sampling window setting module, used to adjust the sampling window of each flip-flop according to a determined data delay, so that the flip-flops sample the test data at the optimal sampling time within each clock cycle, thereby improving the sampling frequency and accuracy.

[0050] In some embodiments, the data detection module 114 is further configured to, if it is determined that the data delay of the delay module needs to be adjusted, adjust it by moving it forward or backward based on the currently determined data delay; after each adjustment, repeat the test code sampling and data detection to obtain the data detection result after each adjustment; compare the data detection result after each adjustment until a sampling window with the largest sampling width is found.

[0051] In this embodiment, by shifting the data delay value of the delay module forward and backward and comparing the PRBS detection data multiple times, a maximum common data sampling window is found. This improves the tolerance for time differences in the arrival time of test data from different receiving circuits at the sampling point, which is beneficial for improving the quality of the sampled test signal and increasing the sampling frequency. In some optional embodiments, the data delay value at the middle of the window can be selected to better meet the data setup time and hold time requirements of data sampling.

[0052] See Figure 3To aid in understanding the technical solutions of this invention, a test environment built with an ATE test device and the chip is used as an example: Before chip testing, the test device sends a test code to each receiving circuit 110 to detect and adjust the time delay on the receiving circuit 110, thereby determining the optimal sampling window. The test code can be pseudo-random binary sequence (PRBS) data, or other data that can reflect the signal transmission characteristics on the receiving circuit 110.

[0053] The test code enters the delay module 111 through the receiving port 101 (IO pin). Through the delay control of the delay module 111, the test code arrives at the predetermined sampling point on each receiving circuit 110 at the same or as close as possible, and is located within the data sampling window.

[0054] The test code is sampled by the data sampling module 113 using a clock sampling signal in each clock cycle to obtain a sampling result. The sampling result is then sent to the data detection module 114 to detect the sampled test code, determining whether the received test data is correct. This, in turn, determines whether the sampling of the received test data after passing through the delay control module is correct, thereby determining a suitable sampling window.

[0055] The delay data can be a fixed value or a dynamically changing value, adjusted according to the transmission rate of the test data or other factors.

[0056] In this embodiment, the predetermined sampling point can be a node on the receiving circuit 110, located after the delay control module. Specifically, it is a point that can reflect the state of the test data, such as a point that can display or record information such as the logic level, waveform, and frequency of the test data. For example, if the receiving circuit 110 has an amplifier or filter, the input or output terminal of that component can be selected as the predetermined sampling point. If the receiving circuit 110 has a low-pass filter, the output terminal of the filter can be selected as the predetermined sampling point to avoid interference from high-frequency noise on the sampling results.

[0057] Please continue reading. Figure 1b In some embodiments, the chip 100 further includes a decoding module 115, located after the data sampling module 113 and before the first buffer 112, for decoding the sampled data after sampling the data via the delay module, and sending the decoded valid data to the first buffer 112; The decoding can employ mainstream encoding and decoding technologies such as 8b10b or 128b130b, which are commonly used in SERDES. Taking 8b10 encoding and decoding as an example, an 8-bit data can be encoded into a 10-bit symbolic data. This 10-bit symbolic data is divided into control flag data (such as sync), and pure data symbolic data. In this embodiment of the invention, by using this type of encoding or decoding, on the one hand, it is convenient to identify the symbol boundaries of the data (e.g., confirming which bit in the bit data is bit 0); on the other hand, it prevents the data signal from having consecutive long 0s or long 1s, ensuring a balanced electrical level between 0s and 1s, improving the signal transmission quality of the physical channel link, and thus supporting operation at higher frequencies.

[0058] For the case where the encoded or decoded symbolic data includes control identifier data (including synchronization header flags) and pure data symbolic data (valid data), the decoding module 115 is specifically used to determine the type of the decoded content after decoding the sampled test data; if the type of the content is valid data, it is cached in the first buffer 112; if the type of the content is a synchronization header flag, it is discarded.

[0059] The first buffer 112 can be a FIFO memory. In this embodiment, the data decoded by each receiving circuit is written into its respective FIFO memory if the decoded data is pure data, and is discarded if the decoded data is a synchronization header flag (such as a SYNC flag).

[0060] The cache read control module 120 is used to control whether to read and send the cached test data according to preset conditions.

[0061] Specifically, the cache read control module 120 is used to perform an operation of reading a valid data from the first cache 112 of each of the multiple receiving circuits when the first cache 112 of the multiple receiving circuits is not empty.

[0062] In chip testing scenarios, in addition to receiving test data from the ATE (Automatic Test Equipment) equipment, the chip also needs to send test data to the ATE equipment. Therefore, see... Figure 2 and Figure 3 As shown, in some embodiments, the chip 100 further includes: a plurality of transmitting circuits 140, each transmitting circuit 140 including: The second buffer 141 is connected to the test logic module 130 and is used to receive and store the test data to be sent; wherein the test logic module 130 sends the test data to the second buffer 141 for storage.

[0063] The encoding module 142 is connected to the output of the second buffer 141 and is used to encode the test data retrieved from the second buffer 141 and send the encoded test data.

[0064] In this embodiment, the test data retrieved from the second buffer 141 is encoded by the encoding module 142. Efficient encoding algorithms, such as differential encoding or entropy encoding, can be used. This effectively reduces the bandwidth requirements for data transmission and improves data transmission efficiency.

[0065] Please refer to Figure 2 and Figure 3 To further ensure the normal operation of the transmitting circuit 140, in some embodiments, the transmitting circuit 140 is further provided with a data transmitting module 143, which is used to send test data to the test equipment during data training with the test equipment to confirm whether the transmitting circuit 140 is normal.

[0066] The test data can be a series of data sequences in a specific pattern, such as a PRBS (Pseudo Random Binary Sequence) stream, which can be used to test and verify the performance and reliability of the communication link.

[0067] In this embodiment, by using the data transmission module 143 to send test data to the test device, it is possible to verify whether the transmission circuit 140 is working properly. This allows for the timely detection and elimination of link problems in the transmission circuit 140, ensuring reliable data transmission.

[0068] In addition, before the formal testing begins, the effectiveness of data training can be verified by sending test data to the test equipment.

[0069] For example, suppose the chip needs to be tested for high-speed data transmission. During the data training phase, the test logic module 130 can generate PRBS31 (31-bit pseudo-random binary sequence) test data and store it in the second buffer 141. Then, the encoding module 142 encodes the PRBS-31 data retrieved from the second buffer 141. Finally, the data transmission module 143 sends the encoded PRBS-31 data to the test device.

[0070] By sending PRBS31 data, the test equipment can receive and decode the data and compare it with the expected PRBS31 sequence. If the received data matches the expected sequence, it indicates that the transmitting circuit 140 is working properly; if there is a discrepancy, there may be a problem with the transmitting circuit 140, which requires debugging and repair. This verifies and ensures the reliability of the data channel link.

[0071] Specifically, both the first and second buffers are FIFO memories, and the test data is one or more of PRBS7, PRBS9, PRBS11, and PRBS31. PRBS data is a pseudo-random binary sequence with varying lengths and complexities, which can be used to test data transmission performance under different scenarios.

[0072] Specifically, when the user test logic module 130 sends data to the ATE machine, the test logic module 130 writes the data to the second buffer 141 in each transmitting circuit. When it is determined that the second buffer 141 is not empty, a valid data is retrieved from the second buffer 141 for data encoding. When the second buffer 141 is empty, the encoding module 142 needs to insert a control symbol flag (synchronization header flag) into the encoded test data.

[0073] In some embodiments, the transmitting circuit further includes a transmitting delay circuit, which is located after the data transmitting module. The transmitting delay circuit is similar to the aforementioned delay module and can fine-tune the transmitting delay of the transmitting circuit to enable the ATE machine to obtain a wider data sampling window.

[0074] To aid in understanding the technical solutions and their effects provided by the embodiments of the present invention, the following is combined with... Figure 4 The specific test environment is described below: In a chip test case, there are multiple test channels, each with different I / O pins. Due to differences in the internal circuit layout and signal transmission paths of the chip, timing offsets may exist between different test channels built by ATE equipment. This can lead to inaccurate data acquisition for each channel during data sampling.

[0075] An example of a test environment built using the improved chip and ATE equipment of this invention is as follows: Figure 4 As shown, a chip testing method of an embodiment of the present invention will now be described using a chip provided in an embodiment of the present invention as the chip under test. The method includes the following steps: S201: Perform training operations on the data of the receiving circuit 110 and the transmitting circuit 140. In this step, the receiving circuit 110 or the transmitting circuit 140 can be trained first, or trained simultaneously.

[0076] S202: During data training on the receiving channel, the ATE continuously sends specific PRBS data. The delay time of the IODELAY module (delay module 111) is adjusted via JTAG or a user-defined method. Data is sampled after the delay, and the PRBS detection function is activated to check if correct PRBS data is received. If correct PRBS data is detected, it indicates that a correct receiving data sampling window has been found, and the receiving channel is functioning normally. If no correct PRBS data is detected, the IODELAY value is adjusted to another delay value, and the detection of correct PRBS data continues. This process is repeated until correct PRBS data is detected, at which point the receiving channel is considered to be functioning normally. When a normal data reception is detected, the IODELAY configuration data delay time can be adjusted to move around this value to find a larger data sampling window. This optimal sampling window better meets the setup and hold time requirements during sampling. During testing, the test data signal arriving at the sampling point on each receiver circuit 110 after the set data delay value is sampled according to the determined optimal sampling window. This can increase the sampling frequency, overcome or resolve the impact of timing differences on sampling accuracy, and thus improve the test data transmission rate.

[0077] For example, assume the chip has 8 I / O receive channels and 8 I / O transmit channels, each channel has a data width of 8 bits, uses 8b10b encoding and decoding, operates at a frequency of 1 GHz, and the physical channel link between the ATE equipment and the chip is an LVDS signal. In step S201, the ATE equipment and the chip simultaneously perform training operations on the receive and transmit channels to determine the optimal data sampling and transmission timing.

[0078] In step S202, the ATE machine sends PRBS7 data to the chip, which consists of 16 8-bit data sequences: 0000000, 0002011, 0020110, 0011201, 0100111, 0201100, 0110001, 0112010, 1000201, 1001110, 2010011, 2011000, 1100010, 1201001, 1120100, and 1111111. The chip sets the delay value of the IODELAY module of each IO receive channel to 0 via JTAG or a user-defined method, then samples the data, activates the PRBS detection function, and checks whether the correct PRBS data has been received. If correct PRBS data is detected, it means a correct receive data sampling window has been found, and the receive channel is functioning normally. If no data is detected, the IODELAY delay value is increased by 1, and the detection of correct PRBS data continues. This process is repeated until the receive channel is determined to be functioning normally. Assume that after multiple attempts, a correct receive data sampling window is finally found, at which point the IODELAY delay value is 10. To find a larger data sampling window, the IODELAY delay value can be shifted around 10, for example, scanning between 9 and 11. If correct PRBS data is received within this range, it means the data sampling window width is 3 delay units, which better meets the setup and hold time requirements during sampling, improving sampling frequency and accuracy.

[0079] S203: During data training on the transmission channel, the PRBS transmission module inside the transmission channel continuously sends specific PRBS data. The data transmission switch MUX switches to send data from the PRBS transmission module to the ATE machine. When the ATE machine receives the correct PRBS data, it determines that the transmission channel is functioning normally.

[0080] S204: The ATE machine first performs necessary data encoding on the data to be sent from the chip. It can use 8b10b or 128b130b encoding, which are commonly used in SERDES technology. When the chip receives the encoded data, it first sends the data to the data decoding module 115 and only writes the decoded pure data part into the FIFO module of its respective IO receiving channel.

[0081] For example, in this step, the ATE machine first encodes the data to be transmitted from the chip using 8b10b encoding. For instance, if the data to be transmitted is 00000001, 00000010, 00000011, 00000100, after encoding, it becomes 1001120100, 1001110010, 1001110001, 1001201111. When the chip receives the encoded data, it first sends the data to the data decoding module 115, and only writes the decoded pure data portion into the FIFO module of its respective IO receive channel. For instance, if the decoded data is 00000001, 00000010, 00000011, 00000100, it writes it into FIFO0, FIFO1, FIFO2, and FIFO3 respectively.

[0082] S205: When the FIFO of each IO receive channel is not empty, the receive channel FIFO control module sends a read operation to the FIFO, so that the read data of the FIFO is sent to the user test logic module 130.

[0083] In this step, when the FIFO of each IO receive channel is not empty, the receive channel FIFO control module sends a read operation to these FIFOs, so that the read data of the FIFO is sent to the user test logic module 130. For example, the read data of FIFO0 is 00000001, the read data of FIFO1 is 00000010, the read data of FIFO2 is 00000011, and the read data of FIFO3 is 00000100.

[0084] S206: When the user test logic module 130 has data to send to the ATE machine, this module writes the data to the FIFO of each data transmission channel. When the transmission channel determines that the FIFO is not empty, it retrieves a piece of data from the FIFO and performs data encoding. When the FIFO is not empty, the encoding module needs to insert a control symbol flag into the encoded data.

[0085] In this step, when the user test logic module 130 has data to send to the ATE machine, this module writes the data to the FIFOs of each data transmission channel. For example, if the data to be sent is 00000201, 00000110, 00000111, and 00001000, it is written to FIFO4, FIFO5, FIFO6, and FIFO7 respectively. When the transmission channel determines that a FIFO is not empty, it retrieves a piece of data from the FIFO and performs a data encoding operation. For example, if the data in FIFO4 is 00000201, it is encoded as 1001201201. When a FIFO is not empty, the encoding module needs to insert a control symbol flag into the encoded data, such as inserting a SYNC flag, i.e., 0011112010.

[0086] S207: The data transmission switch MUX is switched to send the output of the encoding module to the ATE machine.

[0087] In this step, the data MUX is switched to be sent to the ATE machine from the output of the encoding module. For example, the data sent is 0011112010, 1001201201, 1001201011, 1001201001, 1001100111.

[0088] S208: The ATE machine receives the encoded data, first performs data decoding, then removes unnecessary control symbols and flags, retaining only the pure data portion, and compares the pure data with the expected data. If they match, the test is successful; otherwise, the test fails.

[0089] During testing, a delay module 111 is added to each channel based on the chip provided in this embodiment of the invention. By controlling the signal reception time of the receiving circuit 110 according to the set target delay value and matching the sampling based on the determined optimal sampling window, data can be accurately sampled, thereby overcoming the impact of timing offset between different test channels on the sampling accuracy.

[0090] At least according to the above disclosure, the chip provided in the embodiments of the present invention improves the chip's circuit structure by setting a delay module 111 on the receiving circuit 110 to control the time when test data arrives at the sampling point on different receiving circuits 110, optimizing the timing of test data transmission received on different receiving circuits 110, so that the chip can receive test data at a higher rate. This can increase the bandwidth of the average single IO interface of the ATE test equipment for transmitting test data and speed up the test.

[0091] Furthermore, by improving the chip-side receiving circuit 110 and adding delay modules, appropriate delays are introduced into the receiving circuit 110 to ensure that the data transmission timing between different test I / O pins of different chips does not interfere with each other. In this way, even if there are different transmission delays or clock deviations between test I / O pins, correct data reception and transmission can be guaranteed, achieving timing and location decoupling between test I / O pins. Moreover, it allows the chip to more flexibly utilize I / O pins at various physical locations for testing, thereby improving the reusability of chip test I / O (different test requirements can share the same set of I / O pins without needing to allocate separate I / O pins for each test scenario), reducing dependence on specific locations and the number of test I / O pins used, thus reducing testing costs and improving testing efficiency.

[0092] Furthermore, by adding a delay module 111 to each receiving circuit 110, the I / O pins on all receiving circuits are no longer in a parallel bus sampling relationship. Each I / O pin can be individually delayed and sampled independently, which can achieve timing decoupling between test I / O pins, thereby supporting higher data transmission frequencies and improving the chip's testing capabilities in high-speed communication scenarios.

[0093] Furthermore, by decoupling the locations of test I / O pins, chip designers can place and route test I / O pins with greater flexibility. This simplifies the physical layout design process, increases routing flexibility, and reduces routing limitations and constraints.

[0094] Finally, by increasing the operating frequency of the receiving circuit 110, the performance of the ATE equipment can be fully utilized, and the test time can be shortened and the test efficiency improved without increasing the cost of the ATE equipment.

[0095] Please refer to Figure 5 This invention also provides a chip testing method, which can be embedded in a physical entity such as an electronic component or device in software form. When a user uses this entity in a usage scenario, the method flow of this application can be reproduced. The chip testing method includes: S210. Receive test data sent by the test equipment and adjust the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point; S220. Cache valid data, wherein the valid data comes from the test data within the sampling window; S230. After detecting that each receiving circuit has stored valid data, control the operation of reading the valid data buffered by each receiving circuit.

[0096] See Figure 6 Step S210 may specifically include: S310, receiving test data sent by the test device; S320. Based on the determined target time delay, delay control is performed on the time when the test data arrives at the predetermined sampling point on each receiving circuit 110. S330: Receive clock sampling signal, and according to the optimal sampling window corresponding to the target time delay, ensure that the test data is within the data sampling window when it arrives at the sampling point, and sample the test data arriving at the predetermined sampling point in each clock cycle.

[0097] After receiving test data sent by the test equipment and adjusting the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point, the method further includes: sampling the data at the sampling point according to the test clock; The system detects whether the data from the data sampling module is the test data in order to determine whether the data delay of each corresponding receiving circuit needs to be adjusted.

[0098] In some embodiments, detecting whether the data from the data sampling module is the test data to determine whether the data delay of each corresponding receiving circuit needs to be adjusted includes: if the data from the data sampling module is detected to be the test data, then determining that the data delay of the delay module does not need to be adjusted; and, If the data detected from the data sampling module is not the test data, it is determined that the data delay of the delay module needs to be adjusted.

[0099] In other embodiments, after determining that the data delay of the delay module needs to be adjusted, the method further includes: adjusting the data delay forward or backward based on the currently determined data delay; After each adjustment, test code sampling and data detection are repeated to obtain the data detection results after each adjustment; Compare the data detection results after each adjustment until a sampling window with the largest sampling width is found.

[0100] In some embodiments, after sampling the test data, the method further includes: decoding the sampled valid data and caching the decoded valid data; and controlling whether to read and send the cached test data according to preset conditions.

[0101] Specifically, after decoding the sampled data, the method further includes: determining the type of the decoded content; if the type of the content is valid data, then caching the valid data; if the type of the content is a synchronization header identifier, then discarding it.

[0102] The chip testing method provided in this application embodiment can be embedded in the chip provided in this embodiment. When interconnected with ATE equipment to form a test environment, the technical solution of the method of this invention embodiment can be reproduced when testing is performed. Its implementation principle and technical effect are similar to those of the device embodiment in Embodiment 1 and this embodiment, and will not be repeated here. They can be referred to each other.

[0103] Figure 7 This is a schematic block diagram of the architecture of an embodiment of the electronic device of the present invention. Based on the same technical concept as the aforementioned chip embodiment, the electronic device provided by the present invention includes: one or more processors; a memory; the memory stores one or more executable program codes, and the one or more processors read the executable program codes stored in the memory to run the program corresponding to the executable program codes, so as to execute any of the chip testing methods provided in the embodiments of the present invention.

[0104] The aforementioned electronic device may include: a housing 41, a processor 42, a memory 43, a circuit board 44, and a power supply circuit 45, wherein the circuit board 44 is disposed inside the space enclosed by the housing 41, and the processor 42 and the memory 43 are disposed on the circuit board 44; the power supply circuit 45 is used to supply power to the various circuits or devices of the aforementioned electronic device; the memory 43 is used to store executable program code; the processor 42 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 43, for executing any of the chip testing methods described in the aforementioned embodiment two.

[0105] For details on the specific execution process of the above steps by the processor 42 and the steps further executed by the processor 42 by running executable program code, please refer to the descriptions of the aforementioned chip embodiments of the present invention, which will not be repeated here.

[0106] The electronic device exists in various forms, including but not limited to: (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and are primarily designed to provide voice and data communication. These terminals include smartphones (such as iPhones), multimedia phones, feature phones, and low-end phones.

[0107] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0108] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes audio and video players (such as iPods), handheld game consoles, e-book readers, as well as smart toys and portable car navigation devices.

[0109] (4) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0110] (5) Other electronic devices with data interaction functions.

[0111] This application also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to perform any of the methods described in Embodiment 1.

[0112] In summary, the chip provided in this application improves the chip's circuit structure by setting a delay module 111 on the receiving circuit 110 to control the time when the test data on different receiving circuits 110 arrive at the sampling point, optimizing the timing of the received test data transmission on different receiving circuits 110, so that the chip can receive test data at a higher rate; and, timing decoupling and position decoupling between test IO pins are achieved.

[0113] It should be noted that while the various embodiments described herein have different focuses, they are interconnected. When understanding this application, reference can be made between the various embodiments. Furthermore, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or measurement control unit that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or measurement control unit 103. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or measurement control unit that includes said element.

[0114] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, The chip includes: Multiple receiving circuits, each receiving circuit including: The delay module is used to receive test data and adjust the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point. The data sampling module is used to sample data transmitted through the delay module at the sampling point according to the test clock; The data detection module is used to detect whether the data from the data sampling module is the test data, so as to determine whether the data delay of the delay module needs to be adjusted; A first buffer, connected to the delay module, is used to buffer valid data, which comes from test data within the sampling window; and, The data read control module is used to control the operation of reading valid data from multiple first buffers after valid data has been stored in the first buffers of multiple receiving circuits.

2. The chip according to claim 1, characterized in that, The data detection module is further configured to, when detecting that the data from the data sampling module is the test data, determine that the data delay of the delay module does not need to be adjusted; and, This is used to determine that the data delay of the delay module needs to be adjusted when the data from the data sampling module is not the test data.

3. The chip according to claim 2, characterized in that, The data detection module is also used to adjust the data delay of the delay module by moving it forward or backward based on the currently determined data delay if it is determined that the data delay of the delay module needs to be adjusted. After each adjustment, test code sampling and data detection are repeated to obtain the data detection results after each adjustment; Compare the data detection results after each adjustment until a sampling window with the largest sampling width is found.

4. The chip according to claim 1, characterized in that, The chip further includes: a decoding module, located after the data sampling module and before the first buffer, for decoding the sampled data after sampling the data via the delay module, and sending the decoded valid data to the first buffer; The cache read control module is used to control whether to read and send cached test data based on preset conditions.

5. The chip according to claim 4, characterized in that, The decoding module is specifically used to determine the type of the decoded content after decoding the sampled data; If the content is valid data, it is sent to the first buffer. If the content is of type sync header identifier, it is discarded.

6. The chip according to claim 5, characterized in that, The cache read control module is specifically used to perform an operation of reading a valid data from the first buffer of each of the multiple receiving circuits when the first buffers of the multiple receiving circuits are not empty.

7. The chip according to claim 1, characterized in that, The chip further includes: multiple transmitting circuits, each transmitting circuit comprising: The second buffer is used to receive and store the test data that needs to be sent. The encoding module is connected to the output of the second buffer and is used to encode the test data output from the second buffer and send the encoded test data.

8. The chip according to claim 7, characterized in that, The transmitting circuit further includes: a data transmitting module, used to send test data to the test equipment during data training with the test equipment to confirm whether the transmitting channel link is normal; The output terminals of the data transmission module and the encoding module are also equipped with a data transmission switching switch.

9. A chip testing method, characterized in that, include: Receive test data sent by the test equipment and adjust the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point; Cache valid data, which comes from test data within the sampling window; and, After detecting that each receiving circuit has stored valid data, control the operation of reading the valid data buffered by each receiving circuit; The method further includes, after receiving test data sent by the test equipment and adjusting the data delay of the corresponding receiving circuit so that the test data is within the data sampling window when it arrives at the sampling point, sampling the data according to the test clock at the sampling point. The system detects whether the data at the sampling points is the test data to determine whether the data delay of each corresponding receiving circuit needs to be adjusted.

10. The chip testing method according to claim 9, characterized in that, The step of detecting whether the data at the sampling point is the test data to determine whether the data delay of each corresponding receiving circuit needs to be adjusted includes: if the data at the sampling point is detected to be the test data, then determining that the data delay of the delay module does not need to be adjusted; and, If the data at the sampling point is not the test data, then the data delay of each corresponding receiving circuit needs to be adjusted.

11. The chip testing method according to claim 10, characterized in that, After determining that the data delay needs to be adjusted, the method further includes: using the currently determined data delay as a reference, making forward and backward adjustments; After each adjustment, test code sampling and data detection are repeated to obtain the data detection results after each adjustment; Compare the data detection results after each adjustment until a sampling window with the largest sampling width is found.

12. An electronic device, characterized in that, include: One or more processors; Memory; The memory stores one or more executable program codes, and the one or more processors read the executable program codes stored in the memory to run the program corresponding to the executable program codes, so as to execute the chip testing method according to any one of claims 9 to 11.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the chip testing method according to any one of claims 9 to 11.

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