Quantum fourier transform based constant modulus adder, method and related apparatus

Abstract

The application discloses a constant modulus addition operation device and method based on quantum Fourier transform and related devices, and the constant modulus addition operation device comprises a modulus addition operation module; the modulus addition operation module comprises a first constant adder, a first constant subtractor, a first CNOT gate and a controlled constant adder which are cascaded in sequence, the constant of the first constant adder is target data, the constants of the first constant subtractor and the controlled constant adder are modulus, and the modulus addition operation module is used for calculating the modulus addition operation result of inputted data to be added and the target data and the modulus.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, and in particular to a constant modular addition arithmetic unit, method and related device based on quantum Fourier transform. Background Technology

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and computes quantum information and runs quantum algorithms, it is a quantum computer. Because of its ability to process mathematical problems more efficiently than ordinary computers—for example, reducing the time complexity of cracking RSA keys from exponential to polynomial time—quantum computers have become a key technology under research.

[0003] Modular operations have wide applications in number theory and cryptography, from parity and prime number determination to the Caesar cipher, from finite fields to the implementation of block ciphers and field towers, and from elliptic curves over finite fields to elliptic curve-based public-key cryptography. Modular operations are ubiquitous in these applications. Therefore, modular operations are the most commonly used function in arithmetic units, and this is also true for quantum computing. How to implement modular addition is a technical problem that urgently needs to be solved in quantum computing. Summary of the Invention

[0004] The purpose of this invention is to provide a constant modular addition arithmetic unit, method and related device based on quantum Fourier transform, which aims to realize modular addition operations in quantum computing.

[0005] One embodiment of the present invention provides a constant modular adder based on quantum Fourier transform. The constant modular adder includes a modular adder module. The modular adder module includes a first constant adder, a first constant subtractor, a first CNOT gate, and a controlled constant adder cascaded in sequence. The constant of the first constant adder is the target data, and the constants of the first constant subtractor and the controlled constant adder are both modulo numbers. The modular adder module is used to calculate the modular adder result of the input data to be added, the target data, and the modulo numbers.

[0006] Optionally, one input terminal of the modular addition module is connected to the input terminal of the first constant adder, and the other input terminal of the modular addition module is connected to one input terminal of the first CNOT gate. The two output terminals of the controlled constant adder are connected one-to-one with the two output terminals of the modular addition module. One input terminal of the modular addition module is used to input the data to be added, and the other input terminal is used to input initial auxiliary data. One output terminal of the modular addition module is used to output the modular addition result of the data to be added, the target data, and the modulus, and the other output terminal is used to output the target auxiliary data.

[0007] Optionally, the output of the first constant adder is connected to the input of the first constant subtractor, the output of the first constant subtractor is connected to the other input of the first CNOT gate, and the two outputs of the first CNOT gate are connected one-to-one with the two inputs of the controlled constant adder.

[0008] Optionally, the output of the first constant subtractor includes a data output and a sign output, one of the inputs of the controlled constant adder includes a data input and a sign input, the data output of the first constant subtractor is connected to the data input of the controlled constant adder, the sign output of the first constant subtractor is connected to the other input of the first CNOT gate, and one of the outputs of the first CNOT gate is connected to the sign input of the controlled constant adder.

[0009] Optionally, the constant modulo addition unit further includes an auxiliary bit reset module, which is used to reset the target auxiliary data to the initial auxiliary data; the auxiliary bit reset module includes a second constant subtractor, a first NOT gate and a second CNOT gate cascaded in sequence; the constant of the second constant subtractor is the target data.

[0010] Optionally, one input terminal of the auxiliary bit reset module is connected to the input terminal of the second constant subtractor, and the other input terminal of the auxiliary bit reset module is connected to one input terminal of the second CNOT gate. The output terminal of the second constant subtractor is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the other input terminal of the second CNOT gate. The two output terminals of the second CNOT gate are connected one-to-one with the two output terminals of the auxiliary bit reset module. One output terminal of the auxiliary bit reset module is used to output intermediate data, and the other output terminal of the auxiliary bit reset module is used to output the initial auxiliary data.

[0011] Optionally, the output of the second constant subtractor includes a data output and a sign output. One of the outputs of the auxiliary bit reset module includes a data output and a sign output. The data output of the second constant subtractor is connected to the data output of the auxiliary bit reset module. The sign output of the second constant subtractor is connected to the input of the first NOT gate. One of the outputs of the second CNOT gate is connected to the sign output of the auxiliary bit reset module. The other output of the second CNOT gate is connected to the other output of the auxiliary bit reset module.

[0012] Optionally, the constant modulo addition unit further includes a modulo addition result reset module, which is used to reset the intermediate data to the modulo addition result of the data to be added, the target data, and the modulus; the modulo addition result reset module includes a second NOT gate and a second constant adder cascaded in sequence, wherein the constant of the second constant adder is the target data.

[0013] Optionally, the input terminal of the modular addition result reset module includes a sign input terminal and a data input terminal, and the input terminal of the second constant adder includes a sign input terminal and a data input terminal; the sign input terminal of the modular addition result reset module is connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate is connected to the sign input terminal of the second constant adder, the data input terminal of the modular addition result reset module is connected to the data input terminal of the second constant adder, and the output terminal of the second constant adder is connected to the output terminal of the modular addition result reset module; the output terminal of the modular addition result reset module is used to output the modular addition result of the data to be added and the target data with the modulus.

[0014] Optionally, the two input terminals of the constant modular adder are connected one-to-one with the two input terminals of the modular adder module, the two output terminals of the modular adder module are connected one-to-one with the two input terminals of the auxiliary bit reset module, one output terminal of the auxiliary bit reset module is connected to the input terminal of the modular adder result reset module, the other output terminal of the auxiliary bit reset module is connected to one output terminal of the constant modular adder, and the output terminal of the modular adder result reset module is connected to the other output terminal of the constant modular adder.

[0015] One embodiment of the present invention provides a constant modular addition method based on quantum Fourier transform, characterized in that the method includes:

[0016] Obtain the constant modulo adder described in the above embodiments and the data to be added;

[0017] The quantum state of the data to be added is input into the constant modulus adder to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus.

[0018] The result of the modular addition operation of the data to be added, the target data, and the modulus is determined based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

[0019] Another embodiment of the present invention provides a constant modular addition arithmetic device based on quantum Fourier transform, the device comprising:

[0020] The data acquisition unit is used to acquire the constant modulo adder described in the above embodiments and the data to be added;

[0021] An addition unit is used to input the quantum state of the data to be added to the constant modulo addition unit to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus;

[0022] The result determination unit is used to determine the result of the modular addition operation of the data to be added, the target data, and the modulus based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

[0023] Another embodiment of the present invention provides a storage medium storing a computer program, wherein the computer program is configured to execute the method described in any of the preceding claims when running.

[0024] Another embodiment of the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method described in any of the preceding claims.

[0025] Compared with existing technologies, the present invention provides a constant modular addition arithmetic unit based on quantum Fourier transform. The constant modular addition arithmetic unit includes a modular addition module. The modular addition module includes a first constant adder, a first constant subtractor, a first CNOT gate, and a controlled constant adder cascaded in sequence. The constant of the first constant adder is the target data, and the constants of the first constant subtractor and the controlled constant adder are both modulo numbers. The first constant adder and the first constant subtractor are used to calculate the difference between the sum of the input data to be added and the target data and the modulo number. Then, the first CNOT gate judges the calculation result. If it is greater than 0, the result is directly used as the modular addition result of the data to be added, the target data, and the modulo number. If it is less than 0, the controlled constant adder adds the result to the target data to obtain the modular addition result of the data to be added, the target data, and the modulo number. Attached Figure Description

[0026] Figure 1 A hardware structure block diagram of a computer terminal based on a constant modular adder of quantum Fourier transform provided in an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of a constant modulus adder 100 based on quantum Fourier transform provided in an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of a modular addition operation module 110 provided in an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of another constant modular adder 100 based on quantum Fourier transform provided in an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of the structure of an auxiliary bit reset module 120 provided in an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the structure of a modular addition result reset module 130 provided in an embodiment of the present invention;

[0032] Figure 7 A structural block diagram of a constant adder 200 based on quantum Fourier transform provided in an embodiment of the present invention;

[0033] Figure 8 A flowchart illustrating a constant modulo addition method based on quantum Fourier transform provided in an embodiment of the present invention;

[0034] Figure 9 This is a schematic diagram of a constant modular addition arithmetic device based on quantum Fourier transform, provided as an embodiment of the present invention. Detailed Implementation

[0035] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] The present invention first provides a constant modular adder based on quantum Fourier transform, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0037] The following detailed explanation uses a computer terminal as an example. Figure 1 This is a hardware structure block diagram of a computer terminal based on a constant modular adder using quantum Fourier transform, provided as an embodiment of the present invention. (See diagram below.) Figure 1 As shown, a computer terminal may include one or more ( Figure 1 Only one is shown in the diagram. The processor (which may include, but is not limited to, a microprocessor (MCU) or programmable logic device (FPGA)) and a memory for storing a constant-modulus adder based on quantum Fourier transform are also shown. Optionally, the computer terminal may further include a transmission device for communication functions and input / output devices. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0038] The memory can be used to store software programs and modules of application software, such as the program instructions / modules corresponding to a constant modular adder based on quantum Fourier transform in this embodiment of the invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby realizing the aforementioned constant modular adder. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0039] The transmission device is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0040] It's important to note that a true quantum computer has a hybrid structure, comprising two main parts: a classical computer responsible for performing classical computations and control, and a quantum device responsible for running quantum programs to achieve quantum computation. A quantum program is a sequence of instructions written in a quantum language such as QRunes that can run on a quantum computer, supporting operations on quantum logic gates and ultimately enabling quantum computing. Specifically, a quantum program is a sequence of instructions that operates on quantum logic gates according to a specific timing order.

[0041] In practical applications, due to limitations in the development of quantum device hardware, quantum computing simulations are often required to verify quantum algorithms, quantum applications, and so on. Quantum computing simulation is the process of simulating the execution of a quantum program corresponding to a specific problem using a virtual architecture (i.e., a quantum virtual machine) built with the resources of a regular computer. Typically, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program referred to in this embodiment of the invention is a program written in a classical language that represents qubits and their evolution, wherein qubits, quantum logic gates, etc., related to quantum computing all have corresponding classical code representations.

[0042] Quantum circuits, also known as quantum logic circuits, are a manifestation of quantum programming and are the most commonly used general-purpose quantum computing model. They represent circuits that operate on qubits under an abstract concept. They consist of qubits, circuits (timelines), and various quantum logic gates. Finally, the results are often read out through quantum measurement operations.

[0043] Unlike traditional circuits that use metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be seen as being connected by time. That is, the state of a quantum bit evolves naturally over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated on.

[0044] A quantum program corresponds to a single quantum circuit. The quantum program described in this invention refers to this single quantum circuit, where the total number of qubits in the single quantum circuit is the same as the total number of qubits in the quantum program. This can be understood as follows: a quantum program can consist of a quantum circuit, measurement operations on the qubits within the quantum circuit, registers storing the measurement results, and control flow nodes (jump instructions). A single quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution of a quantum program is the process of executing all the quantum logic gates in a specific timing order. It should be noted that the timing order refers to the chronological sequence in which individual quantum logic gates are executed.

[0045] It's important to note that in classical computing, the most basic unit is the bit, and the most fundamental control mode is the logic gate. Circuit control can be achieved through combinations of logic gates. Similarly, the way to process qubits is through quantum logic gates. Quantum logic gates enable the evolution of quantum states and are the foundation of quantum circuits. Quantum logic gates include single-qubit gates, such as Hadamard gates (H-gates), Pauli-X gates (X-gates), Pauli-Y gates (Y-gates), Pauli-Z gates (Z-gates), RX gates, RY gates, RZ gates, etc.; and multi-qubit gates, such as CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc. Quantum logic gates are generally represented using unitary matrices, which are not only matrix forms but also operations and transformations. Generally, the effect of a quantum logic gate on a quantum state is calculated by left-multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.

[0046] See Figure 2 , Figure 2 This is a schematic diagram of a constant modular adder 100 based on quantum Fourier transform, provided in an embodiment of the present invention. The constant modular adder 100 includes a modular adder module 110. The two input terminals 100p and 100q of the constant modular adder 100 are connected one-to-one with the two input terminals 110p and 110q of the modular adder module 110. The two output terminals 100m and 100n of the constant modular adder 100 are connected one-to-one with the two output terminals 110m and 110n of the modular adder module 110.

[0047] Wherein, one input terminal 110p of the modular addition module 110 is used to input the data to be added b, and the other input terminal 110q of the modular addition module 110 is used to input the initial auxiliary data 0; one output terminal 110m of the modular addition module 110 is used to output the modular addition result a+b mod N of the data to be added b, the target data a, and the modulus N; and the other output terminal 110n of the modular addition module is used to output the target auxiliary data.

[0048] The modular addition module 110 is used to calculate the modular addition result a+b mod N of the input data b to be added, the target data a, and the modulus N.

[0049] It should be noted that the modular addition module 110 described above, as well as the other modules described below, can all be composed of basic quantum logic gates. The input and output terms of each module can be qubits. Data is encoded onto the quantum states of the qubits, and each module acts on the qubits, causing the quantum states of the qubits to evolve. For example, the input of the modular addition module is the quantum state |b> corresponding to the data to be added or the quantum state |0> corresponding to the initial auxiliary data 0. Similarly, the output modular addition result a+b mod N is also the quantum state |a+b mod N>, and the target auxiliary data is also the quantum state |0> or |1>.

[0050] It should also be noted that in this embodiment, 2N>a+b>0, where a, b, and N are all positive integers.

[0051] See Figure 3 , Figure 3 This is a schematic diagram of a modular addition module 110 provided in an embodiment of the present invention, wherein the adder is represented by φ(ADD) and the subtractor is represented by φ(SUB). The modular addition module 110 includes a first constant adder 111, a first constant subtractor 112, a first CNOT gate 113, and a controlled constant adder 114, which are cascaded in sequence. The constant of the first constant adder 111 is the target data a, and the constants of the first constant subtractor 112 and the controlled constant adder 114 are both modulo N.

[0052] In this module, one input terminal 110p of the modular addition module 110 is connected to the input terminal 111p of the first constant adder 111, and the other input terminal 110q of the modular addition module 110 is connected to one input terminal 113p of the first CNOT gate 113. The two output terminals 114m and 114n of the controlled constant adder 114 are connected to the two output terminals 110m and 110n of the modular addition module 110 in a one-to-one correspondence. One input terminal 110p of the modular addition module 110 is used to input the data to be added b, and the other input terminal of the modular addition module 110 is used to input the initial auxiliary data 0. One output terminal 110m of the modular addition module 110 is used to output the modular addition result a+b mod N of the data to be added b, the target data a, and the modulus N. The other output terminal 110n of the modular addition module 110 is used to output the target auxiliary data.

[0053] Specifically, the output terminal 111m of the first constant adder 111 is connected to the input terminal 112p of the first constant subtractor 112, the output terminal 112m of the first constant subtractor 112 is connected to the other input terminal 113q of the first CNOT gate 113, and the two output terminals 113m and 113n of the first CNOT gate 113 are connected to the two input terminals 114p and 114q of the controlled constant adder 114 in a one-to-one correspondence.

[0054] The first constant subtractor 112 has an output terminal 112m, which includes a data output terminal 112m1 and a sign output terminal 112m2. One of the input terminals 114p of the controlled constant adder 114 includes a data input terminal 114p1 and a sign input terminal 114p2. The data output terminal 112m1 of the first constant subtractor 112 is connected to the data input terminal 114p1 of the controlled constant adder 114. The sign output terminal 112m2 of the first constant subtractor 112 is connected to the other input terminal 113q of the first CNOT gate 113. One of the output terminals 113m of the first CNOT gate 113 is connected to the sign input terminal 114p2 of the controlled constant adder 114.

[0055] The specific principle of this modular addition module is as follows:

[0056] Input the quantum state |b> corresponding to the data b to be added, and output the quantum state |a+b> after passing through the first constant adder 111; then pass through the first constant subtractor 112 to output the quantum state |a+bN>.

[0057] The quantum state |a+bN> and the quantum state |0> corresponding to the initial auxiliary data 0 are then input into the first CNOT gate 113. The control bit of the first CNOT gate 113 is the symbol qubit corresponding to the quantum state |a+bN>. If a+b≥N, the quantum state of the symbol qubit is |0>. The first CNOT gate 113 and the controlled constant adder 114 are not executed. The modular addition result output by the output terminal 110m is a+b-N, and the target auxiliary data output by the output terminal 110n is |0>. If a+b<N, the quantum state of the symbol qubit is |1>. The first CNOT gate 113 and the controlled constant adder 114 are executed. The modular addition result output by the output terminal 110m is a+b, and the target auxiliary data output by the output terminal 110n is |1>.

[0058] As can be seen, the embodiments of the present invention can obtain the result of modular addition and realize modular addition. However, the final quantum state of the auxiliary bit used may be |0> or |1>. If the final quantum state of the auxiliary bit is |1>, it needs to be reset before it can be used for other calculations and storage. To solve the above problem, please refer to the next embodiment.

[0059] See Figure 4 , Figure 4 This is a schematic diagram of another constant modular adder 100 based on quantum Fourier transform provided in an embodiment of the present invention. The constant modular adder 100 includes a modular adder module 110, an auxiliary bit reset module 120, and a modular adder result reset module 130, which are cascaded in sequence.

[0060] Specifically, the two input terminals 100p and 100q of the constant modular adder 100 are connected one-to-one with the two input terminals 110p and 110q of the modular adder module 110. The two output terminals 110m and 110n of the modular adder module 110 are connected one-to-one with the two input terminals 120p and 120q of the auxiliary bit reset module 120. One output terminal 120m of the auxiliary bit reset module 120 is connected to the input terminal 130p of the modular adder result reset module 130. The other output terminal 120n of the auxiliary bit reset module 120 is connected to one output terminal 100n of the constant modular adder 100. The output terminal 130m of the modular adder result reset module 130 is connected to the other output terminal 100m of the constant modular adder 100.

[0061] Wherein, one input terminal 110p of the modular addition module 110 is used to input the data to be added b, and the other input terminal of the modular addition module 110 is used to input initial auxiliary data; one output terminal 110m of the modular addition module 110 is used to output the modular addition result a+b mod N of the data to be added b, the target data a, and the modulus N; and the other output terminal 110n of the modular addition module 110 is used to output the target auxiliary data.

[0062] One of the output terminals 120m of the auxiliary bit reset module 120 is used to output intermediate data, and the other output terminal 120n of the auxiliary bit reset module 120 is used to output the initial auxiliary data.

[0063] The output terminal 130m of the modulus addition result reset module 130 is used to output the modulus addition result of the data to be added and the target data with the modulus.

[0064] The modular addition module 110 is used to calculate the modular addition result a+b mod N of the input data b to be added, the target data a, and the modulus N. The auxiliary bit reset module 120 is used to reset the target auxiliary data to the initial auxiliary data. The modular addition result reset module is used to reset the intermediate data to the modular addition result of the data to be added, the target data, and the modulus.

[0065] As can be seen, in this embodiment of the invention, the target auxiliary data is reset to the initial auxiliary data through the auxiliary bit reset module. Since the auxiliary bit reset module also changes the modulo addition result when it performs the reset, the modified intermediate data is then reset to the modulo addition result of the data to be added, the target data, and the modulus through the modulo addition result reset module. This not only realizes the modulo addition operation, but also realizes the reset of the auxiliary bits, so that the auxiliary bits can be used for other calculations and storage in the future.

[0066] See Figure 5 , Figure 5 This is a schematic diagram of an auxiliary bit reset module 120 provided in an embodiment of the present invention. The auxiliary bit reset module 120 is used to reset the target auxiliary data to the initial auxiliary data; the auxiliary bit reset module 120 includes a second constant subtractor 121, a first NOT gate 122, and a second CNOT gate 123 cascaded in sequence; the constant of the second constant subtractor 121 is the target data a.

[0067] In this configuration, one input terminal 120p of the auxiliary bit reset module 120 is connected to the input terminal 121p of the second constant subtractor 121, and the other input terminal 120q of the auxiliary bit reset module 120 is connected to one input terminal 123p of the second CNOT gate 123. The output terminal 121m of the second constant subtractor 121 is connected to the input terminal 122p of the first NOT gate 122, and the output terminal 122m of the first NOT gate 122 is connected to the other input terminal 123q of the second CNOT gate 123. The two output terminals 123m and 123n of the second CNOT gate 123 are connected to the two output terminals 120m and 120n of the auxiliary bit reset module 120 in a one-to-one correspondence. One output terminal 120m of the auxiliary bit reset module 120 is used to output intermediate data, and the other output terminal 120n of the auxiliary bit reset module 120 is used to output the initial auxiliary data.

[0068] The second constant subtractor 121 has an output terminal 121m, which includes a data output terminal 121m1 and a sign output terminal 121m2. One of the output terminals 120m of the auxiliary bit reset module 120 includes a data output terminal 120m1 and a sign output terminal 120m2. The data output terminal 121m1 of the second constant subtractor 121 is connected to the data output terminal 120m1 of the auxiliary bit reset module 120. The sign output terminal 121m2 of the second constant subtractor 121 is connected to the input terminal 122p of the first NOT gate 122. One of the output terminals 123m of the second CNOT 123 is connected to the sign output terminal 120m2 of the auxiliary bit reset module 120. The other output terminal 123n of the second CNOT 123 is connected to the other output terminal 120n of the auxiliary bit reset module 120.

[0069] The specific principle of this modular addition module is as follows:

[0070] If a + b ≥ N, then the input at input terminal 120p is |a + bN>, and the input at input terminal 120q is |0>. After passing through the second constant subtractor 121, we get b - N, where b - N < 0. Therefore, the output at output terminal 121m1 is |Nb>, and the output at output terminal 121m2 is |1>, where |1> represents a negative number. After passing through the first NOT gate 122, the output at output terminal 122m is |0>. Therefore, the inputs at the second CNOT123 input terminals 123q and 123p are both |0>, and finally, the output at 120n is |0>, which is the initial auxiliary data, thus resetting the auxiliary bits. The output at output terminal 120m1 is |Nb>, and the output at output terminal 120m2 is |0>. Therefore, the intermediate data output at output terminal 120m is |Nb>.

[0071] If a + b < N, then the input at input terminal 120p is |a + b>, and the input at input terminal 120q is |1>. After passing through the second constant subtractor 121, we get b, where b > 0. Therefore, the output at output terminal 121m1 is |b>, and the output at output terminal 121m2 is |0>, where |0> represents a negative number. After passing through the first NOT gate 122, the output at output terminal 122m is |1>. Therefore, the input at input terminal 123q of the second CNOT gate 123 is |1>, and the input at input terminal 123p is |0>. After being swapped through the second CNOT gate, the final output at 120n is |0>, which is the initial auxiliary data, thus resetting the auxiliary bits. The output at output terminal 120m1 is |b>, and the output at output terminal 120m2 is |1>. Therefore, the intermediate data output at output terminal 120m is |-b>.

[0072] See Figure 6 , Figure 6This is a schematic diagram of a modular addition result reset module 130 provided in an embodiment of the present invention. The modular addition result reset module 130 is used to reset the intermediate data to the modular addition result of the data to be added, the target data, and the modulus; the modular addition result reset module 130 includes a second NOT gate 131 and a second constant adder 132 cascaded in sequence, wherein the constant of the second constant adder 132 is the target data.

[0073] The input terminal 130p of the modular addition result reset module 130 includes a sign input terminal 130p2 and a data input terminal 130p1. The input terminal 132p of the second constant adder 132 includes a sign input terminal 132p2 and a data input terminal 132p1. The sign input terminal 130p2 of the modular addition result reset module 130 is connected to the input terminal 131p of the second NOT gate 131. The output terminal 131m of the second NOT gate 131 is connected to the sign input terminal 132p2 of the second constant adder 132. The data input terminal 130p1 of the modular addition result reset module 130 is connected to the data input terminal 132p1 of the second constant adder 132. The output terminal 132m of the second constant adder 132 is connected to the output terminal 130m of the modular addition result reset module 130. The output terminal 130m of the modular addition result reset module 130 is used to output the modular addition result of the data to be added and the target data with the modulus.

[0074] The specific principle of the modular addition result reset module 130 is as follows:

[0075] If a + b ≥ N, the input at input terminal 131p is |0>, which, after passing through the second NOT gate 131, outputs |1> at output terminal 131m. Therefore, the input at input terminal 132p1 is |Nb>, the input at input terminal 132p2 is |1>, and the input at input terminal 132p is |bN>. After passing through the second constant adder 132, output terminal 132m outputs |a + bN>, thus resetting the result of the modulo addition operation.

[0076] If a + b < N, the input at input terminal 131p is |1>. After passing through the second NOT gate 131, the output at output terminal 131m is |0>. Therefore, the input at input terminal 132p1 is |b>, the input at input terminal 132p2 is |0>, and the input at input terminal 132p is |b>. After passing through the second constant adder 132, the output at output terminal 132m is |a + b>, thus resetting the result of the modulo addition operation.

[0077] See Figure 7 , Figure 7This is a structural block diagram of a constant adder 200 based on quantum Fourier transform, provided in an embodiment of the present invention. The constant adder 200 includes a quantum Fourier transform module 210, a phase transform module 220, and an inverse quantum Fourier transform module 230 cascaded together. The phase transform parameters in the phase transform module 220 are determined based on preset target data. The constant adder 200 is used to calculate the sum of the target data and the input data to be added.

[0078] The quantum Fourier transform module 210 is used to evolve the quantum state of the data to be added into a first Fourier state, the phase transform module 220 is used to evolve the first Fourier state into a second Fourier state of the sum of the target data and the data to be added, and the inverse quantum Fourier transform module 230 is used to evolve the second Fourier state into the quantum state of the sum of the target data and the data to be added and output it.

[0079] The constant adder 200 includes n data input terminals 201, which are used to input the quantum state of the data to be added. The quantum state of the data to be added is obtained by encoding the binary data to be added into the ground state of n qubits.

[0080] The constant adder 200 also includes n data output terminals 202, which are used to output the quantum state of the sum of the target data and the data to be added.

[0081] Assume the binary representation of the data b to be added is [b n-1 b n-2 [b0] can be encoded into the ground state of n qubits to obtain the quantum state of the data b to be added:

[0082] |b>=|b n-1 b n-2 ,···,b0>

[0083] After being transformed by the quantum Fourier transform module 210, the quantum state evolves into the first Fourier state:

[0084]

[0085] make Therefore, the above formula can be expressed as

[0086]

[0087] After being processed by the phase transformation module 220, the first Fourier state evolves into the second Fourier state, which is the sum of the target data a and the data b to be added.

[0088]

[0089] After the inverse quantum Fourier transform module 230, the second Fourier state evolves into the quantum state of the sum of the target data a and the data b to be added:

[0090] |a+b>=|(a+b) n-1 ,(a+b) n-2 ,···,(a+b)0>

[0091] By decoding the quantum state |a+b>, we obtain a+b.

[0092] The phase transformation module 220 includes n RZ gates, and the rotation angle of each RZ gate is determined based on the binary representation of the target data.

[0093] The matrix expression for the RZ gate is:

[0094]

[0095] Where θ is the rotation angle.

[0096] Wherein, the binary representation of the target data a is [a n-1 a n-2 The rotation angle of the RZ gate is determined based on the following formula:

[0097]

[0098] Where, θ i Let a be the rotation angle of the i-th RZ gate. i The value can be 0 or 1.

[0099] The phase transformation module 220 further includes n input terminals 221 and output terminals 222 that correspond one-to-one with the RZ gates.

[0100] It should be noted that, in the above example, for simplicity, both the target data a and the data to be added b are encoded with n qubits. In practice, the number of qubits used for encoding can be set according to the size of a and b. Therefore, the number of qubits used to encode a and the number of qubits used to encode b can also be different.

[0101] The above Figure 1 - Figure 6 The first constant adder 111, the second constant adder 132, and the controlled constant adder 114 described herein can be based on Figure 7 The constant adder 200 shown is obtained directly, except that the input data to be added and the constant are different. The first constant subtractor 112 and the second constant subtractor 121 can be based on... Figure 7The constant adder 200 shown is obtained indirectly, for example, by negating the sign bit of the qubit to obtain the negative number of the data to be added, or for example, by... Figure 7 The constant adder 200 shown is transposed and conjugated to obtain the constant subtractor. Examples are not provided here.

[0102] Compared with existing technologies, the present invention provides a constant modular addition arithmetic unit based on quantum Fourier transform. The constant modular addition arithmetic unit includes a modular addition module. The modular addition module includes a first constant adder, a first constant subtractor, a first CNOT gate, and a controlled constant adder cascaded in sequence. The constant of the first constant adder is the target data, and the constants of the first constant subtractor and the controlled constant adder are both modulo numbers. The first constant adder and the first constant subtractor are used to calculate the difference between the sum of the input data to be added and the target data and the modulo number. Then, the first CNOT gate judges the calculation result. If it is greater than 0, the result is directly used as the modular addition result of the data to be added, the target data, and the modulo number. If it is less than 0, the controlled constant adder adds the result to the target data to obtain the modular addition result of the data to be added, the target data, and the modulo number.

[0103] See Figure 8 , Figure 8 This is a flowchart illustrating a constant modular addition method based on quantum Fourier transform, provided as an embodiment of the present invention. The method includes:

[0104] Step 801: Obtain the constant modulo adder described in the above embodiment and the data to be added;

[0105] Step 802: Input the quantum state of the data to be added into the constant modulus adder to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus;

[0106] Step 803: Determine the result of the modular addition operation of the data to be added, the target data, and the modulus based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

[0107] See Figure 9 , Figure 9 This is a schematic diagram of a constant modular addition arithmetic device based on quantum Fourier transform, provided as an embodiment of the present invention. The device includes:

[0108] Data acquisition unit 901 is used to acquire the constant modulo adder described in the above embodiment and the data to be added;

[0109] The addition unit 902 is used to input the quantum state of the data to be added to the constant modulus adder to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus;

[0110] The result determination unit 903 is used to determine the result of the modular addition operation of the data to be added, the target data, and the modulus based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

[0111] Another embodiment of the present invention provides a constant modular subtraction operator based on quantum Fourier transform, wherein the quantum circuit corresponding to the constant modular subtraction operator is transposed and conjugate with the quantum circuit corresponding to the constant modular addition operator.

[0112] Another embodiment of the present invention provides a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the method embodiments above when running.

[0113] Specifically, in this embodiment, the storage medium can be configured to store a computer program for performing the following steps:

[0114] Obtain the constant modulo adder described in the above embodiments and the data to be added;

[0115] The quantum state of the data to be added is input into the constant modulus adder to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus.

[0116] The result of the modular addition operation of the data to be added, the target data, and the modulus is determined based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

[0117] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0118] Another embodiment of the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the method embodiments described above.

[0119] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0120] Specifically, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0121] Obtain the constant modulo adder described in the above embodiments and the data to be added;

[0122] The quantum state of the data to be added is input into the constant modulus adder to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus.

[0123] The result of the modular addition operation of the data to be added, the target data, and the modulus is determined based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

[0124] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A constant-modulus adder based on quantum Fourier transform, characterized in that, The constant modular adder includes a modular adder module; the modular adder module includes a first constant adder, a first constant subtractor, a first CNOT gate, and a controlled constant adder cascaded in sequence. The constant of the first constant adder is the target data, and the constants of the first constant subtractor and the controlled constant adder are both modulo numbers. The modular adder module is used to calculate the modular adder result of the input data to be added, the target data, and the modulo numbers. One input terminal of the modular adder module is connected to the input terminal of the first constant adder, and the other input terminal of the modular adder module is connected to one input terminal of the first CNOT gate. The two output terminals of the controlled constant adder are connected one-to-one with the two output terminals of the modular adder module. One input terminal of the modular adder module is used to input the data to be added, and the other input terminal of the modular adder module is used to input the initial auxiliary number. According to the above, one output terminal of the modular addition module is used to output the modular addition result of the data to be added, the target data, and the modulus; the other output terminal of the modular addition module is used to output the target auxiliary data; the constant modular addition unit also includes an auxiliary bit reset module, which is used to reset the target auxiliary data to the initial auxiliary data; the auxiliary bit reset module includes a second constant subtractor, a first NOT gate, and a second CNOT gate cascaded in sequence; the constant of the second constant subtractor is the target data; the constant modular addition unit also includes a modular addition result reset module, which is used to reset the intermediate data to the modular addition result of the data to be added, the target data, and the modulus; the modular addition result reset module includes a second NOT gate and a second constant adder cascaded in sequence, the constant of the second constant adder is the target data.

2. The constant modulo adder according to claim 1, characterized in that, The output of the first constant adder is connected to the input of the first constant subtractor, the output of the first constant subtractor is connected to the other input of the first CNOT gate, and the two outputs of the first CNOT gate are connected one-to-one with the two inputs of the controlled constant adder.

3. The constant modulo addition arithmetic unit according to claim 2, characterized in that, The output of the first constant subtractor includes a data output and a sign output. One of the inputs of the controlled constant adder includes a data input and a sign input. The data output of the first constant subtractor is connected to the data input of the controlled constant adder. The sign output of the first constant subtractor is connected to the other input of the first CNOT gate. One of the outputs of the first CNOT gate is connected to the sign input of the controlled constant adder.

4. The constant modulo adder according to claim 3, characterized in that, One input terminal of the auxiliary bit reset module is connected to the input terminal of the second constant subtractor, and the other input terminal of the auxiliary bit reset module is connected to one input terminal of the second CNOT gate. The output terminal of the second constant subtractor is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the other input terminal of the second CNOT gate. The two output terminals of the second CNOT gate are connected one-to-one with the two output terminals of the auxiliary bit reset module. One output terminal of the auxiliary bit reset module is used to output intermediate data, and the other output terminal of the auxiliary bit reset module is used to output the initial auxiliary data.

5. The constant modulo adder according to claim 4, characterized in that, The output of the second constant subtractor includes a data output and a sign output. One of the outputs of the auxiliary bit reset module includes a data output and a sign output. The data output of the second constant subtractor is connected to the data output of the auxiliary bit reset module. The sign output of the second constant subtractor is connected to the input of the first NOT gate. One of the outputs of the second CNOT gate is connected to the sign output of the auxiliary bit reset module. The other output of the second CNOT gate is connected to the other output of the auxiliary bit reset module.

6. The constant modulo addition arithmetic unit according to claim 5, characterized in that, The input terminals of the modular addition result reset module include a sign input terminal and a data input terminal, and the input terminals of the second constant adder also include a sign input terminal and a data input terminal. The sign input terminal of the modular addition result reset module is connected to the input terminal of the second NOT gate, the output terminal of the second NOT gate is connected to the sign input terminal of the second constant adder, the data input terminal of the modular addition result reset module is connected to the data input terminal of the second constant adder, and the output terminal of the second constant adder is connected to the output terminal of the modular addition result reset module. The output terminal of the modular addition result reset module is used to output the modular addition result of the data to be added and the target data with the modulus.

7. The constant modulo adder according to claim 6, characterized in that, The two input terminals of the constant modular adder are connected one-to-one with the two input terminals of the modular adder module. The two output terminals of the modular adder module are connected one-to-one with the two input terminals of the auxiliary bit reset module. One output terminal of the auxiliary bit reset module is connected to the input terminal of the modular adder result reset module. The other output terminal of the auxiliary bit reset module is connected to one output terminal of the constant modular adder. The output terminal of the modular adder result reset module is connected to the other output terminal of the constant modular adder.

8. A constant-modulus addition method based on quantum Fourier transform, characterized in that, The method includes: Obtain the constant modulo addition arithmetic unit as described in any one of claims 1-7 and the data to be added; The quantum state of the data to be added is input into the constant modulus adder to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus. The result of the modular addition operation of the data to be added, the target data, and the modulus is determined based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

9. A constant-modulus addition arithmetic device based on quantum Fourier transform, characterized in that, The device includes: The data acquisition unit is used to acquire the constant modular adder and the data to be added as described in any one of claims 1-7; An addition unit is used to input the quantum state of the data to be added to the constant modulo addition unit to obtain the quantum state of the sum of the data to be added and the target data modulo the modulus; The result determination unit is used to determine the result of the modular addition operation of the data to be added, the target data, and the modulus based on the quantum state of the modulus obtained by modulo the sum of the data to be added and the target data.

10. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in claim 8 when it is run.

11. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method of claim 8.

Images