Goa circuit and display panel

Abstract

Embodiments of the present application provide a GOA circuit and a display panel, the GOA circuit comprising a pull-up module, a pull-up control module, a pull-down module and a pull-down maintenance module, by taking a P-type transistor with higher mobility as a first transistor of the pull-up module, fast output of the GOA circuit can be achieved, by taking an N-type transistor as a transistor in the pull-up control module, the pull-down module and the pull-down maintenance module, and by making the threshold voltage of the N-type transistor positive, negative drift of the transistor can be avoided, thus the anti-negative drift module in the existing GOA circuit can be removed, so that the size of the GOA circuit can be reduced, and the frame width of the display panel can be reduced, and the power consumption of the display panel can be reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a GOA circuit and display panel. Background Technology

[0002] As people's tastes become increasingly sophisticated, higher demands are being placed on panel specifications, such as high refresh rates, high resolutions, and long lifespans. Gate driver on array (GOA) technology has become a key development focus for panel manufacturers due to its significant advantages in cost and functionality compared to gate driver chips (Gate ICs).

[0003] To meet the pixel circuit display and compensation functions of large-size organic light-emitting diode (OLED) display panels, different types of signals (driving signals, threshold voltage compensation, mobility compensation, etc.) need to be output. The GOA circuit of large-size OLED display panels mainly uses metal-oxide-semiconductor (MOS) transistors. Because MOS transistors are inherently prone to negative drift, the GOA circuit needs to incorporate a large number of thin-film transistors (TFTs) for anti-drift design, resulting in a wider bezel and higher power consumption for the display panel. To ensure that the threshold voltage of an MOS transistor remains positive throughout its entire lifespan, it is necessary to increase not only the size of the output transistor but also the voltages of the DC high-level and DC low-level signals, further widening the bezel and increasing power consumption.

[0004] Therefore, it is necessary to provide a GOA circuit and display panel to improve this deficiency. Summary of the Invention

[0005] The embodiments of this application provide a GOA circuit and a display panel that can reduce the power consumption of the display panel while reducing the bezel width.

[0006] Embodiments of this application provide a GOA circuit, including multiple cascaded GOA units, wherein the nth-level GOA unit is used to output the nth-level scan signal, and the nth-level GOA unit includes:

[0007] The pull-up module is electrically connected to the first node and the nth level scan signal output terminal, and is also connected to the clock signal;

[0008] The pull-up control module is electrically connected to the first node and is connected to a DC low-level signal and the (n-1)th level scan signal;

[0009] The pull-down module is electrically connected to the first node, the second node, and the output terminal of the nth level scan signal, and is also connected to the (n+1)th level scan signal, the DC low-level signal, and the DC high-level signal.

[0010] The pull-down sustaining module is electrically connected to the first node and the second node, and is connected to the DC low-level signal and the DC high-level signal;

[0011] The pull-up module includes a first transistor, the gate of which is electrically connected to the first node, the source of which is connected to the clock signal, and the drain of which is electrically connected to the output terminal of the nth scan signal. The first transistor is a P-type transistor. The transistors in the pull-up control module, the pull-down module, and the pull-down sustaining module are all N-type transistors, and the threshold voltage of the N-type transistor is positive.

[0012] According to one embodiment of this application, the pull-up control module includes a second transistor, the gate of the second transistor is connected to the (n-1)th level scan signal, the source of the second transistor is connected to the DC low-level signal, and the drain of the second transistor is electrically connected to the first node.

[0013] According to one embodiment of this application, the drop-down module includes:

[0014] The third transistor has its gate electrically connected to the second node, its source connected to the DC low-level signal, and its drain electrically connected to the nth-stage scan signal output terminal.

[0015] The fourth transistor has its gate connected to the (n+1)th level scan signal, its source connected to the DC high-level signal, and its drain electrically connected to the first node.

[0016] According to one embodiment of this application, the pull-down sustaining module includes:

[0017] The fifth transistor has its gate electrically connected to the second node, its source connected to the DC high-level signal, and its drain electrically connected to the first node.

[0018] A sixth transistor, wherein the gate of the sixth transistor is electrically connected to the first node, the source of the sixth transistor is connected to the DC high-level signal, and the drain of the sixth transistor is electrically connected to the second node;

[0019] The seventh transistor has its gate connected to the (n-1)th level scan signal, its source connected to the DC low-level signal, and its drain electrically connected to the second node.

[0020] According to one embodiment of this application, the nth level GOA unit further includes a reset module, which is electrically connected to the first node and receives a reset signal and the DC high-level signal.

[0021] According to one embodiment of this application, the reset module includes an eighth transistor, the gate of the eighth transistor is connected to a reset signal, the source of the eighth transistor is connected to the DC high-level signal, and the drain of the eighth transistor is electrically connected to the first node.

[0022] According to one embodiment of this application, the nth-stage GOA unit further includes a bootstrap capacitor, which is electrically connected to the first node and the nth-stage scan signal output terminal.

[0023] According to one embodiment of this application, the P-type transistor is a polycrystalline silicon transistor or an amorphous silicon transistor, and the N-type transistor is one of a metal-oxide-semiconductor transistor, a polycrystalline silicon transistor, and an amorphous silicon transistor.

[0024] According to one embodiment of this application, the voltage of the clock signal when it is at a high level is the same as the voltage of the DC high-level signal, and the voltage of the clock signal when it is at a low level is the same as the voltage of the DC low-level signal.

[0025] Embodiments of this application also provide a display panel, the display panel including the GOA circuit as described above.

[0026] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a GOA circuit and a display panel. The GOA circuit includes a pull-up module, a pull-up control module, a pull-down module, and a pull-down sustaining module. By using a P-type transistor with high mobility as the first transistor in the pull-up module, the fast output of the GOA circuit can be achieved. By using an N-type transistor as the transistor in the pull-up control module, the pull-down module, and the pull-down sustaining module, and making the threshold voltage of the N-type transistor positive, the transistor can avoid negative drift. Therefore, the anti-negative drift module in the existing GOA circuit can be removed, thereby reducing the size of the GOA circuit, thereby reducing the bezel width of the display panel, and reducing the power consumption of the display panel. Attached Figure Description

[0027] Figure 1 A schematic diagram of the GOA circuit provided for an embodiment of this application;

[0028] Figure 2A schematic diagram of another GOA circuit provided for an embodiment of this application;

[0029] Figure 3 Timing diagram of the GOA circuit provided for embodiments of this application. Detailed Implementation

[0030] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes and not for limiting the application. In the figures, structurally similar units are represented by the same reference numerals.

[0031] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0032] The embodiments of this application provide a GOA circuit that can not only achieve fast output of the GOA circuit, but also eliminate the anti-negative drift module in the existing GOA circuit, thereby reducing the size of the GOA circuit, thereby reducing the bezel width of the display panel, and reducing the power consumption of the display panel.

[0033] Combination Figure 1 As shown, Figure 1 The diagram below shows a GOA circuit provided in an embodiment of this application. The GOA circuit includes multiple cascaded GOA units, and each GOA unit includes a pull-up module 1, a pull-up control module 2, a pull-down module 3, and a pull-down sustaining module 4.

[0034] Taking the nth level GOA unit as an example, n is greater than 1 and n is a positive integer. In the nth level GOA unit, pull-up module 1 is electrically connected to the first node Q and the nth level scan signal output terminal Gn(n). Pull-up module 1 is also connected to the clock signal CKA. Pull-up module 1 is used to output the clock signal CKA as the nth level scan signal.

[0035] Pull-up control module 2 is electrically connected to the first node Q. Pull-up control module 2 is also connected to a DC low-level signal VGL and a scanning signal Gn(n-1) of the (n-1)th stage. Pull-up control module 2 is used to control the opening time of pull-up module 1.

[0036] The pull-down module 3 is electrically connected to the first node Q, the second node QB and the output terminal Gn(n) of the nth level scan signal. The pull-down module 3 is also connected to the (n+1)th level scan signal Gn(n+1), the DC low-level signal VGL and the DC high-level signal VGH. The pull-down module 3 is used to pull the nth level scan signal down to a low potential.

[0037] The pull-down sustaining module 4 is electrically connected to the first node Q and the second node QB. The pull-down sustaining module 4 is also connected to a DC low-level signal VGL and a DC high-level signal VGH. The pull-down sustaining module 4 is used to maintain the voltage of the nth level scan signal and the first node Q at a low potential.

[0038] In the embodiments of this application, the pull-up module 1 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the first node Q, the source of the first transistor T1 is connected to the clock signal CKA, and the drain of the first transistor T1 is electrically connected to the nth scan signal output terminal Gn(n). The first transistor T1 is a P-type transistor. The transistors in the pull-up control module 2, the pull-down module 3, and the pull-down sustaining module 4 are all N-type transistors, and the threshold voltage of the N-type transistor is positive.

[0039] It should be noted that by using a P-type transistor with higher mobility as the first transistor T1 of the pull-up module 1, fast output of the GOA circuit can be achieved. By using an N-type transistor as the transistor in the pull-up control module 2, pull-down module 3, and pull-down sustaining module 4, and making the threshold voltage of the N-type transistor positive, negative drift of the transistors in the pull-up control module 2, pull-down module 3, and pull-down sustaining module 4 can be avoided. Therefore, the anti-negative drift module in the existing GOA circuit can be removed, thereby reducing the size of the GOA circuit, which in turn can reduce the bezel width of the display panel containing the GOA circuit of this application, and reduce the power consumption of the display panel.

[0040] In some embodiments, the P-type transistor is a polycrystalline silicon transistor or an amorphous silicon transistor, and the N-type transistor is one of a metal-oxide-semiconductor transistor, a polycrystalline silicon transistor, or an amorphous silicon transistor.

[0041] In one embodiment, the first transistor T1 is a polycrystalline silicon transistor, specifically a low-temperature polycrystalline silicon thin-film transistor. Low-temperature polycrystalline silicon transistors have high mobility and small size, thus not only reducing the size of the GOA circuit but also enabling fast output from the GOA circuit. The N-type transistor is a metal-oxide-semiconductor transistor, and the metal-oxide-semiconductor material can be, but is not limited to, indium gallium zinc oxide (IGZO). That is, the transistors in the pull-up control module 2, pull-down module 3, and pull-down sustaining module 4 are all metal-oxide-semiconductor transistors, and the threshold voltage of the metal-oxide-semiconductor transistor is positive throughout its entire lifespan. With this structure, negative drift of the transistor can be avoided, thus eliminating the need for the anti-negative drift module in the existing GOA circuit, thereby reducing the size of the GOA circuit, which in turn reduces the bezel width of the display panel and lowers the power consumption of the display panel.

[0042] In some other embodiments, the first transistor T1 is not limited to the low-temperature polycrystalline silicon transistor in the above embodiments, but can also be an amorphous silicon transistor or an organic transistor. The transistors in the pull-up control module 2, pull-down module 3, and pull-down sustaining module 4 are not limited to the metal-oxide-semiconductor transistors in the above embodiments, but can also be polycrystalline silicon transistors (specifically, low-temperature polycrystalline silicon transistors) or organic transistors. This also achieves the effect of reducing the bezel width of the display panel and reducing the power consumption of the display panel.

[0043] Furthermore, combined Figure 1 As shown, the pull-up control module 2 includes a second transistor T2. The gate of the second transistor T2 is connected to the (n-1)th level scan signal Gn(n-1), the source of the second transistor T2 is connected to the DC low-level signal VGL, and the drain of the second transistor T2 is electrically connected to the first node Q. The second transistor T2 is an N-type transistor, and the threshold voltage of the second transistor T2 is positive throughout its entire life cycle.

[0044] When the (n-1)th level scan signal Gn(n-1) is at a high level, the clock signal CKA is at a low level, the second transistor T2 is turned on, and the DC low-level signal VGL is output to the first node Q, which is at a low level. Since the first transistor T1 is a P-type transistor, when Q is at a low level, the first transistor T1 is turned on and outputs the voltage of the clock signal CKA to the nth level scan signal output terminal G(n), which is at a low level. When the (n-1)th level scan signal Gn(n-1) switches from a high level to a low level, the clock signal CKA switches from a low level to a high level, the second transistor T2 is turned off, the first node Q remains at a low level, the first transistor T1 remains on, and outputs the voltage of the clock signal CKA to the nth level scan signal output terminal G(n), which is at a high level.

[0045] Furthermore, combined Figure 1 As shown, the pull-down module 3 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is electrically connected to the second node QB, the source of the third transistor T3 is connected to a DC low-level signal VGL, and the drain of the third transistor T3 is electrically connected to the nth level scan signal output terminal Gn(n). The gate of the fourth transistor T4 is connected to the (n+1)th level scan signal Gn(n+1), the source of the fourth transistor T4 is connected to a DC high-level signal VGH, and the drain of the fourth transistor T4 is electrically connected to the first node Q.

[0046] The pull-down sustaining module 4 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The gate of the fifth transistor T5 is electrically connected to the second node QB, the source of the fifth transistor T5 is connected to a DC high-level signal VGH, and the drain of the fifth transistor T5 is electrically connected to the first node Q. The gate of the sixth transistor T6 is electrically connected to the first node Q, the source of the sixth transistor T6 is connected to a DC high-level signal VGH, and the drain of the sixth transistor T6 is electrically connected to the second node QB. The gate of the seventh transistor T7 is connected to the (n-1)th level scan signal Gn(n-1), the source of the seventh transistor T7 is connected to a DC low-level signal VGL, and the drain of the seventh transistor T7 is electrically connected to the second node QB.

[0047] Furthermore, the GOA circuit also includes a reset module 5, which is electrically connected to the first node Q and is connected to a reset signal VST and a DC high-level signal VGH.

[0048] In one embodiment, combined Figure 1 As shown, the reset module 5 includes an eighth transistor T8. The gate of the eighth transistor T8 is connected to the reset signal VST, the source of the eighth transistor T8 is connected to the DC high-level signal VGH, and the drain of the eighth transistor T8 is electrically connected to the first node Q. The reset signal VST is a unified reset signal, and the reset module 5 is used to perform a unified reset at the beginning or end of each frame scan cycle.

[0049] Combination Figure 3 As shown, Figure 3 The timing diagram of the GOA circuit provided for the embodiments of this application is shown below. The operation of the GOA circuit is as follows:

[0050] Combination Figure 1 As shown, in the first stage t1, the (n-1)th level scan signal Gn(n-1) is at a high potential, while the (n+1)th level scan signal Gn(n+1), the clock signal CKA, and the reset signal VST are all at a low potential. The second transistor T2 is turned on, and the DC low-level signal VGL is output to the first node Q, which is at a low potential. At this time, the first transistor T1 is turned on, the seventh transistor T7 is turned on, and the DC low-level signal VGL is output to the second node QB, which is also at a low potential. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all turned off, and the nth level scan signal output at the nth level scan signal output terminal Gn(n) is at a low potential.

[0051] In the second stage t2, the (n-1)th level scan signal Gn(n-1) switches to a low potential, the clock signal CKA switches to a high potential, the (n+1)th level scan signal Gn(n+1) is at a low potential, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned off. At this time, the potential of the first node Q is still low, the first transistor T1 remains on, and outputs the voltage of the clock signal CKA to the nth level scan signal output terminal Gn(n). The nth level scan signal output terminal Gn(n) outputs the nth level scan signal at a high potential.

[0052] In the third stage t3, the (n+1)th stage scan signal Gn(n+1) is at a high potential, while the (n-1)th stage scan signal Gn(n-1), clock signal CKA, and reset signal VST are all at low potentials. The second transistor T2 is off, the fourth transistor T4 is on, and the DC high-level signal VGH is output to the first node Q, making Q high. At this time, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are all off, while the fifth transistor T5 and the sixth transistor T6 are on. The DC high-level signal VGH is output to the second node QB, which is also high. The third transistor T3 is on, and the DC low-level signal VGL is output to the nth stage scan signal output terminal Gn(n). The nth stage scan signal output from Gn(n) is at a low potential. Under the above timing drive, the nth stage scan signal can be output as a pulsed high-voltage signal.

[0053] In one embodiment, combined Figure 1 and Figure 3 As shown, at the beginning of each frame scan cycle, the reset signal VST is at a high potential, the eighth transistor T8 is turned on, the first node Q is at a high potential, the third transistor T3 and the sixth transistor T6 are both turned on, the DC low-level signal VGL is output to the nth level scan signal output terminal Gn(n), and the nth level scan signal output terminal Gn(n) is at a low potential.

[0054] In some other embodiments, besides resetting the potentials of the first node Q and the nth level scan signal output terminal Gn(n) of each GOA unit at the beginning of each frame scan cycle, the potentials of the first node Q and the nth level scan signal output terminal Gn(n) can also be reset at the end of each frame scan cycle. That is, at the end of each frame scan cycle, the reset signal VST is high, the eighth transistor T8 is turned on, the first node Q is high, the third transistor T3 and the sixth transistor T6 are both turned on, the DC low-level signal VGL is output to the nth level scan signal output terminal Gn(n), and the nth level scan signal output by the nth level scan signal output terminal Gn(n) is low.

[0055] In one embodiment, the first transistor T1 is a low-temperature polysilicon transistor, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are of the same type, all being metal-oxide-semiconductor transistors.

[0056] In some other embodiments, the first transistor T1 may also be an amorphous silicon transistor or an organic transistor. The second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be of the same or different types, and each of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be selected from metal-oxide-semiconductor transistors, low-temperature polycrystalline silicon transistors, and amorphous silicon transistors.

[0057] In one embodiment, the voltage when the clock signal CKA is high is the same as the voltage of the DC high-level signal VGH, and the voltage when the clock signal CKA is low is the same as the voltage of the DC low-level signal VGL. This allows for the merging of the output terminals of the GOA circuit, thereby reducing the number of output terminals, simplifying the structure of the GOA circuit, and lowering its power consumption.

[0058] In one embodiment, the GOA unit further includes a bootstrap capacitor Cb, which is connected to the first node Q and the nth-level scan signal output terminal Gn(n).

[0059] like Figure 2 As shown, Figure 2 This is a schematic diagram of another GOA circuit provided in an embodiment of this application. Taking the nth-level GOA unit as an example, the nth-level GOA unit further includes a bootstrap capacitor Cb. One plate of the bootstrap capacitor Cb is electrically connected to the first node Q, and the other plate of the bootstrap capacitor Cb is electrically connected to the nth-level scan signal output terminal Gn(n). In the embodiment of this application, since the voltage of the clock signal CKA when it is high is the same as the voltage of the DC high-level signal VGH, when the clock signal CKA is high, the clock signal CKA can be directly output to the nth-level scan signal output terminal Gn(n) through the first transistor T1. There is no need for a large bootstrap capacitor to raise the potential of the first node Q a second time. Therefore, the capacitance requirement of the bootstrap capacitor Cb can be reduced, thereby reducing the size of the bootstrap capacitor Cb, and further reducing the bezel width of the display panel.

[0060] Based on the GOA circuit provided in the above embodiments of this application, the embodiments of this application also provide a display panel. The display panel includes multiple rows of pixels and a GOA circuit as provided in any of the above embodiments. Each row of pixels is connected to a corresponding first-level GOA unit in the GOA circuit and is driven by the GOA unit. The display panel provided in the embodiments of this application can achieve the same technical effect as the GOA circuit provided in the above embodiments, which will not be repeated here.

[0061] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a GOA circuit and a display panel. The GOA circuit includes a pull-up module, a pull-up control module, a pull-down module, and a pull-down sustaining module. By using a P-type transistor with high mobility as the first transistor in the pull-up module, the fast output of the GOA circuit can be achieved. By using an N-type transistor as the transistor in the pull-up control module, the pull-down module, and the pull-down sustaining module, and making the threshold voltage of the N-type transistor positive, the transistor can avoid negative drift. Therefore, the anti-negative drift module in the existing GOA circuit can be removed, thereby reducing the size of the GOA circuit, thereby reducing the bezel width of the display panel, and reducing the power consumption of the display panel.

[0062] In summary, although the present application discloses the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A GOA circuit, characterized by, It includes multiple cascaded GOA units, with the nth-level GOA unit used to output the nth-level scan signal. The nth-level GOA unit includes: The pull-up module is electrically connected to the first node and the nth level scan signal output terminal, and is also connected to the clock signal; The pull-up control module is electrically connected to the first node and is connected to a DC low-level signal and the (n-1)th level scan signal; The pull-down module is electrically connected to the first node, the second node, and the output terminal of the nth level scan signal, and is also connected to the (n+1)th level scan signal, the DC low-level signal, and the DC high-level signal. The pull-down sustaining module is electrically connected to the first node and the second node, and is connected to the DC low-level signal and the DC high-level signal; The pull-up module includes a first transistor, the gate of which is electrically connected to the first node, the source of which is connected to the clock signal, and the drain of which is electrically connected to the output terminal of the nth scan signal. The first transistor is a P-type transistor. The transistors in the pull-up control module, the pull-down module, and the pull-down sustaining module are all N-type transistors, and the threshold voltage of the N-type transistor is positive. The pull-down sustaining module includes a fifth transistor, a sixth transistor, and a seventh transistor. The gate of the fifth transistor is electrically connected to the second node, the source is connected to the DC high-level signal, and the drain is electrically connected to the first node. The gate of the sixth transistor is electrically connected to the first node, the source is connected to the DC high-level signal, and the drain is electrically connected to the second node. The gate of the seventh transistor is connected to the (n-1)th level scan signal, the source is connected to the DC low-level signal, and the drain is electrically connected to the second node.

2. The GOA circuit as described in claim 1, characterized in that, The pull-up control module includes a second transistor, the gate of which is connected to the (n-1)th level scan signal, the source of which is connected to the DC low-level signal, and the drain of which is electrically connected to the first node.

3. The GOA circuit as described in claim 1, characterized in that, The drop-down module includes: The third transistor has its gate electrically connected to the second node, its source connected to the DC low-level signal, and its drain electrically connected to the nth-stage scan signal output terminal. The fourth transistor has its gate connected to the (n+1)th level scan signal, its source connected to the DC high-level signal, and its drain electrically connected to the first node.

4. The GOA circuit as described in claim 1, characterized in that, The nth level GOA unit also includes a reset module, which is electrically connected to the first node and receives a reset signal and the DC high-level signal.

5. The GOA circuit as described in claim 4, characterized in that, The reset module includes an eighth transistor, the gate of which is connected to a reset signal, the source of which is connected to the DC high-level signal, and the drain of which is electrically connected to the first node.

6. The GOA circuit as described in claim 1, characterized in that, The nth-level GOA unit also includes a bootstrap capacitor, which is electrically connected to the first node and the nth-level scan signal output terminal.

7. The GOA circuit as described in claim 1, characterized in that, The P-type transistor is a polycrystalline silicon transistor or an amorphous silicon transistor, and the N-type transistor is one of a metal-oxide-semiconductor transistor, a polycrystalline silicon transistor, and an amorphous silicon transistor.

8. The GOA circuit as described in claim 1, characterized in that, The voltage when the clock signal is high is the same as the voltage of the DC high-level signal, and the voltage when the clock signal is low is the same as the voltage of the DC low-level signal.

9. A display panel, characterized in that, Includes the GOA circuit as described in any one of claims 1 to 8.

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