Magnetic disk device

Abstract

The present application provides a magnetic disk device with high writing performance. In the magnetic disk device according to the embodiment, a track has a plurality of first sectors and second sectors. In a case where a host computer requests writing of a second data segment to a third sector which is one of the plurality of first sectors, a controller acquires the second data segment from the host computer and stores it in a memory, acquires a first data set including all first data segments and all first attribute information from the track and stores it in the memory. The controller acquires second attribute information corresponding to the third sector, and updates the first data segment and the first attribute information in the first data set read from the third sector in the memory with the second data segment and the second attribute information. The controller writes the updated first data set to the first track while calculating second parity bits, and writes the second parity bits to the second sectors.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2022-150917 (filed on September 22, 2022). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] This embodiment relates to a disk drive. Background Technology

[0003] There exists a disk drive that has the function of protecting data written to each track on a track-by-track basis. The disk drive generates error correction codes for each track and performs track-by-track protection based on these error correction codes. Summary of the Invention

[0004] Embodiments of the present invention provide a disk device with high write performance.

[0005] According to one embodiment, a disk drive can be connected to a host. The disk drive includes a disk, read / write heads, memory, and a controller. The disk has a first track having multiple first sectors and second sectors. The read / write heads write data to and read data from the disk. When the controller stores a first data segment and first attribute information in each of the multiple first sectors, and stores a first parity bit in a second sector, it operates as follows when the host requests to write a second data segment to a third sector, which is one of the multiple first sectors. Furthermore, the first attribute information corresponds to the attribute information stored in the first sector among the multiple first sectors. The controller retrieves the second data segment from the host and stores it in the memory; it retrieves a first dataset, which includes all first data segments and all first attribute information, from the first track and stores the first dataset in the memory. The controller retrieves second attribute information, which is the attribute information corresponding to the third sector. The controller updates the third data segment and third attribute information in the first dataset using the second data segment and second attribute information in the memory. The third data segment and third attribute information are the first data segment and first attribute information read from the third sector. While writing the second dataset, which is the updated first dataset, to the first track, the controller calculates the second parity bit based on the second dataset and writes the second parity bit to the second sector. Attached Figure Description

[0006] Figure 1 This is a schematic diagram illustrating an example of the structure of a disk device according to an implementation method.

[0007] Figure 2 This is a diagram illustrating an example of the structure of a disk in an implementation method.

[0008] Figure 3 This is a schematic diagram illustrating an example of the structure of a magnetic track in an implementation method.

[0009] Figure 4 This is a schematic diagram illustrating an example of a data structure representing ATI information in an implementation.

[0010] Figure 5 This is a schematic diagram illustrating an example of sector attribute information in an implementation method.

[0011] Figure 6 This is a flowchart illustrating an example of the action involved in incrementing the ATI counter by the controller of the implementation method.

[0012] Figure 7 This is a flowchart illustrating an example of an action by which the controller of an implementation method detects the track 50 of the object to be rewritten.

[0013] Figure 8 This is a flowchart illustrating an example of a write operation in a disk device according to an implementation method.

[0014] Figure 9 This diagram illustrates the processing steps S306 to S308 in a disk device that follows a 4K Native implementation. Figure 9 (A) is a diagram showing the structure of the written data and track data in RAM27 at the point in time of S306's processing. Figure 9 (B) is a diagram showing the structure of the written data and track data in RAM27 at the time point immediately following the processing of S307. Figure 9 (C) is a graph representing the track data in RAM27 at the time point immediately following the processing of S308.

[0015] Figure 10 It is used for Figure 9 The diagram (A) illustrates the detailed structure of each data point.

[0016] Figure 11 This is a diagram used to illustrate a detailed example of the structure of the transformed written data.

[0017] Figure 12 This is a diagram illustrating a detailed example of the structure of the written data and track data in RAM at the point in time of processing S306 in a disk device that follows a 512-byte emulation implementation.

[0018] Figure 13This is a diagram illustrating a detailed example of the structure of sector data updated using transformed write data through processing S308 in a disk device that follows a 512-byte emulation implementation.

[0019] Label Explanation

[0020] 1. Disk device; 2. Host; 11. Disk; 12. Spindle motor; 13. Ramp; 15. Actuator arm; 16. VCM; 21. Motor driver IC; 22. Head; 22r read chip; 22w write chip; 23. HDC; 24. Head IC; 25. RWC; 26. Processor; 27. RAM; 28. FROM; 29. ​​Encryption / decryption module; 30. Controller; 41. Servo area; 42. Data area; 50. Track; 271. ATI information; 300. Sector attribute information; ECCb, ECCb + Error correction code; MI (Multi-purpose Control Information). Detailed Implementation

[0021] Hereinafter, the disk device according to the embodiments will be described in detail with reference to the accompanying drawings. However, this invention is not limited to these embodiments.

[0022] (Implementation Method)

[0023] Figure 1 This is a schematic diagram illustrating an example of the structure of the disk device 1 according to an embodiment.

[0024] Disk device 1 is connected to host 2. Disk device 1 can receive access commands such as write commands and read commands from host 2.

[0025] The disk drive 1 includes a disk 11 on which a magnetic layer is formed on its surface. The disk drive 1 writes data to the disk 11 and reads data from the disk 11 according to access commands.

[0026] The access command contains a logical address. Disk device 1 provides a logical address space to host 2. The logical address represents a location within that address space. Host 2 uses the logical address to specify the location to write data or the location to read data. That is, the logical address is the location information specified by host 2. Furthermore, the logical address is recorded as an LBA (Logical Block Address).

[0027] Data writing and reading are performed via the read / write head 22. In addition to the disk 11, the disk device 1 also includes a spindle motor 12, a ramp 13, an actuator arm 15, a voice coil motor (VCM) 16, a motor driver IC (Integrated Circuit) 21, a read / write head 22, a hard disk controller (HDC) 23, a head IC 24, a read / write channel (RWC) 25, a processor 26, RAM 27, and a FROM (Flash Read Only Memory) 28.

[0028] The disk 11 is rotated at a predetermined speed by a spindle motor 12 mounted coaxially. The spindle motor 12 is driven by a motor driver IC 21.

[0029] The processor 26 controls the rotation of the spindle motor 12 and the VCM 16 via the motor driver IC 21.

[0030] The read / write head 22 writes and reads information from the disk 11 using its write core 22w and read core 22r. The read / write head 22 is mounted at the front end of the actuator arm 15. The read / write head 22 moves radially across the disk 11 via the VCM 16. Furthermore, multiple copies of either or both of the write core 22w and read core 22r may be provided relative to a single read / write head 22.

[0031] When the disk 11 stops rotating, the read / write head 22 moves onto the ramp 13. The ramp 13 is configured to hold the read / write head 22 in a position where it has left the disk 11.

[0032] During a read operation, head IC24 amplifies the signal read by head 22 from disk 11 and outputs it to RWC25. Additionally, during a write operation, head IC24 amplifies the signal corresponding to the data to be written from RWC25 and outputs it to head 22.

[0033] HDC23 performs control over data transmission and reception with host 2 via the I / F bus.

[0034] The HDC23 has an encryption / decryption module 29. The HDC23 uses the encryption / decryption module 29 to encrypt data received from the host 2 using a key. The HDC23 also uses the encryption / decryption module 29 to decrypt data read from the disk 11 using a key.

[0035] The encryption / decryption module 29 manages the keys used in encryption / decryption. Generation information is associated with each key. The keys can be changed according to commands from host 2, and the generation information is updated each time a key is changed. The encryption / decryption module 29 manages the keys used in encryption / decryption by associating them with LBAs. That is, the disk device 1 is configured to use different keys at different locations in the logical address space. Alternatively, the disk device 1 can be configured to use a single key throughout the entire logical address space.

[0036] RAM27 is used as a cache for data to be written to disk 11 and data to be read from disk 11.

[0037] In addition, RAM 27 is used by the processor 26 as its working memory. RAM 27 is used as a region for loading firmware and for temporarily storing various management data.

[0038] RAM 27 is composed of volatile memory capable of high-speed operation. The type of memory constituting RAM 27 is not limited to a specific type. RAM 27 can be composed, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or a combination thereof. Furthermore, RAM 27 can also be composed of any non-volatile memory. Additionally, the memory used as a data cache and the working memory used by the processor 26 can be composed of different types of RAM.

[0039] Furthermore, RAM27 is an example of a memory used in an implementation.

[0040] RWC25 modulates the data of the write object provided from HDC23 on a sector-by-sector basis, performing error correction encoding and other processes, and provides the modulated data to the head IC24. In addition, RWC25 demodulates the signal read from disk 11 and provided from head IC24, including sector-by-sector error correction, and outputs the demodulated signal as digital data to HDC23.

[0041] The processor 26 is, for example, a CPU (Central Processing Unit). RAM 27 and FROM (Flash Read Only Memory) 28 are connected to the processor 26.

[0042] FROM28 is a non-volatile memory. Firmware (program data) and various operating parameters are stored in FROM28.

[0043] The processor 26 performs overall control of the disk device 1 according to the firmware stored in the FROM 28. For example, the processor 26 loads the firmware from the FROM 28 or the disk 11 into the RAM 27, and executes control of the motor driver IC 21, head IC 24, RWC 25, HDC 23, etc. according to the loaded firmware.

[0044] The structure including HDC23, RWC25, and processor 26 can also be regarded as a controller 30 that controls the operation of disk device 1. Controller 30 may also include other elements (such as RAM27 or FROM28).

[0045] Alternatively, the encryption / decryption module 29 does not necessarily need to be located within the HDC23. The encryption / decryption module 29 can also be located outside the HDC23 or outside the controller 30.

[0046] Alternatively, the firmware program can also be stored on disk 11. Furthermore, some or all of the functions of the processor 26 can be implemented using hardware circuitry such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit).

[0047] Furthermore, the number of disks 11 included in the disk drive 1 is not limited to one. Additionally, the disk drive 1 may have a number of actuator arms 15 and read / write heads 22 corresponding to the number of disks 11. Furthermore, when the disk drive 1 has multiple read / write heads 22, these multiple heads 22 can be moved as a single unit, or they can be configured into multiple groups capable of moving independently.

[0048] Figure 2 This is a diagram illustrating an example of the structure of the disk 11 according to an embodiment. Servo data, used for positioning the read / write head 22, is written into the magnetic layer formed on the surface of the disk 11, for example, by a servo writer or self-servo write (SSW).

[0049] exist Figure 2 The diagram shows a radially arranged servo region 41 as an example of a servo region configuration where servo data is written. In the circumferential direction, a data region 42 is defined between two servo regions 41, where data can be written. Multiple concentric tracks 50 are arranged in the radial direction of the disk 11. On each track 50, multiple sectors are arranged in the data region 42, each for writing data of a predetermined size. The predetermined size is the sector size.

[0050] The servo data includes a servo mark, gray code, burst pattern, and post code. The servo mark indicates the start of the servo data. The gray code includes an ID (track number) for identifying each track 50 on disk 11, and an ID (servo sector number) for identifying each servo sector (servo region 41) on track 50. The burst pattern is data used to detect the positional deviation from the center of the track represented by the track number contained in the gray code. The track number contained in the gray code is provided, for example, as an integer value. By demodulating the burst pattern, the offset below the decimal point, using the position represented by the track number as a reference, can be obtained. That is, by demodulating the burst pattern, the current position of the head 22 in the radial direction can be obtained. The post code is data used to correct for positional deviations from the ideal shape of the track 50, as defined by the gray code and burst pattern.

[0051] When writing data to or reading data from the disk 11, the controller 30 performs the positioning of the head 22, that is, seek control and tracking control, based on the servo data read by the head 22 from the servo area 41.

[0052] Figure 3 This is a schematic diagram illustrating an example of the structure of a track 50 in an embodiment. The servo region 41 is omitted from this diagram. Additionally, the write / read direction is illustrated in this diagram. The write / read direction is the direction in which the read / write head 22 moves relative to the track 50 as the disk 11 rotates. The read / write head 22 writes or reads data from each track 50 in the write / read direction.

[0053] Each sector on track 50 is identified by its sector number. The sector with sector number x is recorded as sector #x. Figure 3 In the example shown, track 50 has 11 sectors, from sector #0 to sector #10.

[0054] The data written to each sector contains error correction codes. The RWC25 is capable of performing sector-by-sector error correction on data read from a sector using error correction codes.

[0055] The error correction coding method used for sector-level error correction is not limited to a specific method. In one example, a low-density parity-check code can be applied as an error correction coding method for sector-level error correction.

[0056] The 11 sectors are arranged in sector number order, starting from a reference position in the circumferential direction and proceeding along the write / read direction. In this specification, the start and end points are defined based on the reference position and the write / read direction.

[0057] For example, regarding the interval from when the read / write head 22 passes the reference position to when it passes the reference position again, i.e., sector #0 to sector #10, the sector that the read / write head 22 passes through first, i.e., sector #0, is recorded as the beginning sector. Regarding sectors #0 to sector #10, the sector that the read / write head 22 passes through last, i.e., sector #10, is recorded as the end sector.

[0058] Additionally, the position where the read / write head 22 begins to pass through the sector is recorded as the beginning of the sector. The position where the read / write head 22 ends to pass through the sector is recorded as the end of the sector.

[0059] The last sector, #10, is used to store the parity bit, which serves as the error correction code. That is, writing is performed in units of track 50, for example, as follows: First, data is written to sectors #0 through #9 in the order of sector numbers. Then, the parity bit, calculated based on the data groups written to sectors #0 through #9, is written to the last sector, #10, of track 50.

[0060] The parity bit written to sector #10 protects the data groups in sectors #0 to #9 from errors. In other words, the parity bit written to sector #10 protects data on a track-by-track basis.

[0061] The method for calculating the parity bit is not limited to a specific method. In one example, the parity bit is generated by performing an XOR operation on each bit of the data #0 through #9.

[0062] In the following sections, the sector written to the end will be used (in...). Figure 3 In the example, the parity bit error correction for sector #10 is recorded as track-level error correction. Additionally, the parity bit of the sector written to the end is recorded as the track parity bit. Furthermore, the state where data written to track 50 is protected by the track parity bit is recorded as track protection function active. Conversely, the state where data written to track 50 is not protected by the track parity bit is recorded as track protection function inactive.

[0063] Additionally, sectors that store data, such as sectors #0 to #9, are recorded as data sectors. Data written to data sector #x is sometimes recorded as data #x. Data #x can also be called a data segment. Sectors that store parity bits, such as sector #10, are recorded as parity bit sectors.

[0064] For example, if data is written to all data sectors of a track 50, and the track parity bit calculated based on the data groups written to all data sectors is written to the parity bit sector of that track 50, then the data groups written to that track 50 correspond to the track parity bit. Therefore, the data groups written to that track 50 are protected by the track parity bit. That is, the track protection function is effective in that track 50.

[0065] When a random write operation is performed on track 50, which has the track protection function enabled (i.e., an overwrite of a portion of the data in a sector), the data group in track 50 does not correspond to the already written track parity bit, and thus becomes unprotected by the track parity bit. In other words, the track protection function is invalid in track 50.

[0066] When a new track parity bit is recalculated in track 50 where track protection is disabled, and this new track parity bit is overwritten into the parity bit sector, the data within track 50 is configured to be protected by the new track parity bit. In other words, the track protection function of track 50 becomes effective.

[0067] Furthermore, the state where the track protection function is active is an example of state 1. The state where the track protection function is inactive is an example of state 2.

[0068] As one of the effects of writing to a disk on adjacent tracks, Adjacent Track Interference (ATI) is known. For example, when data is written to a track 50 (referred to as track 1 50), the adjacent track 50 (track 2 50) will be affected by ATI. The ATI effect on track 2 50 accumulates corresponding to the number of writes to track 1 50. When the ATI effect on track 2 50 becomes too large, reading the data stored on track 2 50 becomes difficult.

[0069] The controller 30 performs a data rewrite before data reading becomes difficult in each track 50 due to ATI.

[0070] The controller 30 uses, for example, ATI information 271 to estimate the degree of ATI influence on each track 50.

[0071] Figure 4 This is a schematic diagram illustrating an example of the data structure of ATI information 271 in the implementation method.

[0072] ATI information 271 has a data structure that records ATI counters by track 50. When data is written to track 50, controller 30 increments the ATI counters of tracks 50 near the destination track 50. The value incremented in a single increment is determined by the designer using any method. In one example, the closer a track 50 is to the destination, the larger the increment. That is, the ATI counter represents an estimated value of the degree of ATI influence on the corresponding track 50.

[0073] The controller 30 compares the ATI counters of each track 50 with a threshold. If an ATI counter exceeds the threshold, the controller 30 rewrites the track 50 corresponding to that ATI counter. After rewriting, the controller 30 resets the ATI counters of the rewritten track 50.

[0074] Subsequently, the rewrite operation performed on track 50 when the ATI counter exceeds the threshold will be recorded as a track-by-track rewrite.

[0075] In the implementation, the controller 30 uses different values ​​as the threshold for comparison with the ATI counter when the track protection function is active and when the track protection function is inactive.

[0076] Track 50 with its track protection function disabled is more vulnerable to ATI effects compared to track 50 with its track protection function enabled. Therefore, when the track protection function is disabled, the controller 30 uses a smaller value as the threshold than when the track protection function is enabled.

[0077] For example, after writing to a track 50 (referred to as track 3 50) on a track-by-track basis, the controller 30 uses a first threshold for comparison with the ATI counter corresponding to track 3 50. Furthermore, when a portion of the data sector of track 3 50 is overwritten, the track protection function in track 3 50 becomes disabled. Therefore, the controller 30 uses a second threshold, smaller than the first threshold, for comparison with the ATI counter corresponding to track 3 50. Thus, even if the parity bit-based protection becomes disabled, it prevents the reading of data stored in track 3 50 from becoming difficult due to ATI interference.

[0078] That is, for track 50 with active track protection, controller 30 will not perform a rewrite operation even if the ATI counter exceeds the second threshold. When the ATI counter of track 50 with active track protection exceeds the first threshold, controller 30 will perform a rewrite operation.

[0079] Here, techniques compared with the implementation methods will be described. The techniques compared with the implementation methods will be described as comparative examples.

[0080] Sometimes, for tracks where the ATI counter exceeds the second threshold and the track protection function is active, random writing is required based on a write command from the host. In the comparative example and the description of the implementation relative to the comparative example, such tracks are referred to as target tracks. In the comparative example, to prevent the ATI counter from exceeding the second threshold simultaneously with the track protection function becoming inactive on the target track, the controller operates as follows: Before executing the random write operation corresponding to the write command, the controller performs a rewrite operation on the target track, resetting the ATI counter of the target track. Then, the controller performs the random write operation corresponding to the write command on the target track.

[0081] However, according to the comparative example above, random writes are performed after the rewrite operation, so the number of writes required increases and the processing time for write commands increases.

[0082] Furthermore, according to the comparative example, when the write command processing is completed, the track protection function of the target track becomes invalid. Therefore, in order to enable the track protection function of the target track, the controller needs to recalculate and overwrite the track parity bit after the write command processing.

[0083] In this implementation, when performing random writes to the target track, the controller 30, as part of the rewrite operation, reads a dataset (set) of one track value from the target track and stores it in RAM 27. This dataset of one track value is recorded as track data. The controller 30 updates the track data in RAM 27 with data requested for writing from the host 2 via a write command (hereinafter referred to as write data). In other words, the write data is merged into the track data in RAM 27. The controller 30 writes the updated track data to the target track as part of the rewrite operation. During the writing of the updated track data, the controller 30 performs a recalculation and overwrite of the track parity bit.

[0084] In other words, when the controller 30 performs random writes to the target track, it initiates a rewrite operation. During the rewrite operation, while writing track data to the disk 11, it simultaneously writes the write data. Therefore, according to the embodiment, compared to the comparative example, the number of writes to the target track can be suppressed, and thus, the time required for processing write commands can be suppressed. That is, write performance is improved.

[0085] Furthermore, according to the implementation method, when the write command processing is completed, the target track becomes active with track protection function enabled. Therefore, unlike the comparative example, the recalculation and overwriting of the track parity bit after the write command processing can be omitted.

[0086] Furthermore, the track data on disk 11 includes attribute information per sector. This attribute information is not included in the write data received from host 2. This attribute information, included in the track data on disk 11 but not in the write data, is recorded as sector attribute information. Sector attribute information 300 is written to each data sector. Sector attribute information 300 indicates the attributes of the data sector that stores this information.

[0087] Figure 5 This is a schematic diagram illustrating an example of sector attribute information in an implementation method.

[0088] Sector attribute information 300 includes generation information and multi-purpose control information.

[0089] Generation information is the generation information of the key used by the encryption / decryption module 29 to write the data to the sector during the encryption process before writing.

[0090] In this implementation, when reading data corresponding to a read command, if the generation information of the key used for decryption differs from the generation information of the key used for encryption before writing, the data is considered to have been erased. That is, the controller 30 does not respond to the data from the host 2. To enable comparison of generation information, the controller 30 writes generation information along with the data when writing data to the disk 11.

[0091] Multipurpose control information is attribute information used in various control systems. Examples of multipurpose control information include first uncorrectable information, second uncorrectable information, and generational inconsistency information.

[0092] The first and second uncorrectable messages are information associated with errors; specifically, they are messages that record the fact that the data is uncorrectable. Uncorrectable means that the errors contained in the data cannot be corrected through error correction.

[0093] The controller 30 is capable of performing various error correction operations, including sector-level and track-level error correction. If the controller 30 fails to correct the error through any error correction, it records a value indicating "uncorrectable" in the first uncorrectable information.

[0094] The second uncorrectable information is information that records a value meaning "uncorrectable" based on a request from host 2. For example, a write command may contain a flag indicating an uncorrectable write. When controller 30 receives a write command in which the uncorrectable write flag is activated, it performs data writing according to the write command and records a value meaning "uncorrectable" in the second uncorrectable information.

[0095] Generation inconsistency information is information recorded when the generation information of the key used for decryption differs from the generation information of the key used for encryption before writing. When reading data corresponding to a read command, if the generation information of the key used for decryption differs from the generation information of the key used for encryption before writing, the controller 30 records a value indicating "generation inconsistency" for the generation inconsistency information.

[0096] The controller 30 can apply the aforementioned multi-purpose control information to various control applications. In one example, when reading data in response to a read command from the host 2, if the controller 30 reads multi-purpose control information containing a value indicating "uncorrectable" in either the first or second uncorrectable information, it will not respond to the host 2 with data. Furthermore, if the controller 30 reads generation inconsistency information containing a value indicating "generation inconsistency," it will not respond to the host 2 with data.

[0097] When updating track data with write data, the controller 30 updates the track data with the transformed write data after transforming the write data into a form that includes sector attribute information 300.

[0098] Furthermore, specific examples of update methods that include transformation methods for writing data will be described later.

[0099] Next, the operation of the disk device 1 according to the embodiment will be described.

[0100] Figure 6 This is a flowchart illustrating an example of the action of the controller 30 in the implementation of the method to increment the ATI counter.

[0101] When the controller 30 writes data to a track 50 (S101), it increments the ATI counters of the tracks 50 near the destination track 50 (S102). In S102, the controller 30 can increment the ATI counters of either the tracks 50 adjacent to the destination track 50 on either side of it in the radial direction, or it can increment the ATI counters of all tracks 50 within a predetermined range in the radial direction centered on the destination track 50. The amount incremented in a single increment can be fixed or vary depending on the distance from the destination track 50.

[0102] S102 terminates the incrementing of the ATI counter. Furthermore, controller 30 executes [the following action] whenever data is written to disk 11. Figure 6 The series of actions shown.

[0103] Figure 7This is a flowchart illustrating an example of the action of the controller 30 in the implementation of the method to detect the track 50 of the object to be rewritten.

[0104] The controller 30 refers to ATI information 271 and determines whether there is a track 50 in which the track protection function is effective that has an ATI counter exceeding the first threshold (S201).

[0105] If the determination in S201 is "no", the controller 30 determines whether there is a track 50 in track 50 where the track protection function is invalid that has an ATI counter exceeding the second threshold (S202). However, as mentioned above, the second threshold is smaller than the first threshold.

[0106] If the determination process in S201 or S202 is "yes", the controller 30 determines the track 50 whose ATI counter exceeds the threshold (i.e., the track 50 where the ATI counter in the track 50 with the track protection function active exceeds the first threshold, or the track 50 where the ATI counter in the track 50 with the track protection function inactive exceeds the second threshold) as the track to be rewritten, and performs a rewrite operation on that track 50. Furthermore, in Figure 7 In the description, the track 50 that is determined to be the object of the rewrite operation is recorded as the object track. Furthermore, the case where one track 50 is determined to be the object of the rewrite operation will be explained here. When two or more tracks 50 are determined to be the object of the rewrite operation, the processing after S203 is performed on each track 50 that is determined to be the object of the rewrite operation.

[0107] The controller 30 transmits track data from the target track to the RAM 27 according to the sector attribute information 300 (S203). At this time, the controller 30 can also perform various error corrections, including track-by-track error correction, as needed.

[0108] After processing in S203, the controller 30 writes the track data in RAM 27 to the target track (S204). In S204, the controller 30 calculates the track parity bit and writes the track data, sector attribute information 300, and track parity bit together to the target track 50.

[0109] After processing in S204, the controller 30 resets the AIT counter of the target track to "0" (S205).

[0110] If the determination in S201 and S202 is "no", or after the processing in S205, the controller 30 ends the action of detecting the track 50 of the object to be rewritten.

[0111] Furthermore, in S201, it is determined whether there is a track 50 whose ATI counter exceeds the first threshold. It is also possible to determine whether there is a track 50 whose ATI counter is above the first threshold.

[0112] Additionally, in S202, it is determined whether there is a track 50 whose ATI counter exceeds the second threshold. It is also possible to determine whether there is a track 50 whose ATI counter is above the second threshold.

[0113] Figure 7 The series of actions shown can be executed at any time. For example, controller 30 can also repeatedly perform the actions of one of the examples above at a predetermined period. Alternatively, controller 30 can also... Figure 6 When the ATI counter is incremented as shown in the operation, one or more tracks whose ATI counters have been incremented are selected as the detection targets, and the operation is performed. Figure 7 The actions shown.

[0114] Figure 8 This is a flowchart illustrating an example of a write operation in disk device 1 according to an implementation method.

[0115] When the controller 30 receives write data from the host 2 (S301), it encrypts the write data through the encryption / decryption module 29 (S302). The encryption / decryption module 29 performs encryption using a key corresponding to the LBA of the write data.

[0116] The controller 30 saves the encrypted write data in RAM 27 (S303).

[0117] The controller 30 obtains the current generation information from the encryption / decryption module 29, that is, the generation information of the key used in the processing of S302 (S304).

[0118] Next, the controller 30 determines whether the track protection function of the track 50 to be written to the destination is effective and whether the ATI counter of the track 50 to be written to the destination exceeds the second threshold (S305). Figure 8 In the description, track 50, which is written to the destination, is recorded as the target track.

[0119] In addition, in S305, the controller 30 can also determine whether the track protection function of the track 50 to be written to the destination is effective and whether the ATI counter of the track 50 to be written to the destination is above the second threshold.

[0120] If the determination in S305 is "yes", the controller 30 transmits track data from the target track to the RAM 27 according to the sector attribute information 300 (S306). The controller 30 reads track data from the target track according to the sector attribute information 300 and saves the read track data in the RAM 27. At this time, the controller 30 can also perform various error corrections, including track-by-track error correction, as needed.

[0121] After the processing in S306, the controller 30 transforms the written data in RAM 27 into data in the same form as the track data, but including sector attribute information 300 (S307), which contains generation information obtained through the processing in S304. Then, the controller 30 updates the track data in RAM 27 with the transformed data (S308).

[0122] The controller 30 writes the updated track data to the target track (S309). In the processing of S309, the controller 30 calculates the track parity bit and writes the track data, sector attribute information and track parity bit together to the target track 50.

[0123] After processing in S309, controller 30 resets the AIT counter of the target track to "0" (S310).

[0124] If the determination in the S305 process is "no", the controller 30 appends data containing sector attribute information 300 to the data written to the RAM 27 and writes it to the target track (S311). The sector attribute information 300 contains the generation information obtained through the S304 process.

[0125] After processing by S301 or S311, the write operation ends.

[0126] Figure 9 It is used for Figure 8 The diagram illustrates the processing steps S307 and S308. Here, the scenario where disk device 1 follows a method known as 4K native will be described. 4K native means that both the host and the disk device process data in 4KB segments as sector sizes. That is, the host 2 can instruct data writing in 4KB units, and the controller 30 can write 4KB data segments to each data sector.

[0127] Figure 9(A) represents an example of the structure of the write data and track data in RAM 27 at the point in time of S306 processing. In the example in this figure, a set of write data of one sector (referred to herein as write data WD) and data segments read from all data sectors of the target track (referred to herein as sector data SD) (referred to herein as track data TD) are stored in RAM 27. The write data WD does not contain sector attribute information 300.

[0128] Figure 9 (B) represents an example of the structure of the write data and track data in RAM 27 at the point immediately following the processing of S307. As shown in this figure, the write data WD is transformed into write data WD' in the form of sector attribute information 300 through the processing of S307.

[0129] Figure 9 (C) represents an example of the structure of track data in RAM27 at the time point immediately following the processing in S308. In the update process, the sector data SD read from the sector of the write destination of the write data WD in track data TD is replaced by the transformed write data WD'. Here, as an example, the second sector data SD from the beginning of track data TD belongs to the sector data SD read from the sector of the write destination of the write data WD, and this sector data SD is replaced by the transformed write data WD'. The updated track data TD' is written to the target track through the processing in S309.

[0130] Figure 10 It is used for Figure 9 The diagram (A) illustrates the detailed structure of each data point.

[0131] When storing data in RAM 27, controller 30 divides the data into sub-sectors and appends error correction codes for storage in RAM 27 according to the size of each sub-sector. For example, the sub-sector size is 512 bytes.

[0132] exist Figure 10 In the example shown, the write data WD in RAM27 includes eight 512-byte sub-sector data SDs, which have a structure with an error correction code ECCb appended to the end of the sub-sector data SDs for RAM storage.

[0133] In disk 11, each data sector stores multi-purpose control information (MI), eight 512-byte sub-sector data SDs, and generation information for each sub-sector data SDs. For data read from each data sector, controller 30 appends error correction codes (ECCb) containing generation information to each sub-sector data SD. + And stored in RAM27. Thus, as... Figure 10As shown, the sector data SD constituting the track data TD includes multi-purpose control information MI in the sector attribute information 300 and eight 512-byte sub-sector data SDs. Each sub-sector data SD has an error correction code ECCb appended to the end of RAM 27 for storage, which contains generation information from the sector attribute information 300. + The structure.

[0134] Figure 11 This is a diagram illustrating a detailed example of the structure of the transformed write data WD'.

[0135] In the processing of S307, the controller 30 obtains multi-purpose control information MI from the sector data SD read from the sector of the write destination of the write data in the sector data SD contained in the track data TD, and appends the obtained multi-purpose control information MI to the beginning of the write data WD. In addition, the controller 30 transforms the error correction code ECCb of each sub-sector data SDs constituting the write data WD into an error correction code ECCb containing the generation information obtained in the processing of S304. + The result is as follows: Figure 11 As shown, transformed write data WD' is obtained, which has the same form as the sector data SD that constitutes track data TD, and contains multi-purpose control information MI and generation information.

[0136] In addition, when reading the updated track data TD' from RAM27, the error correction code ECCb is appended to the data SDs of each sub-sector. + The data is deleted, and generation information is appended to each sub-sector data SDs. Furthermore, the updated track data TD' is written to the target track as a group of sector data SDs, including multi-purpose control information MI and eight 512-byte sub-sector data SDs with appended generation information.

[0137] Thus, according to the implementation method, when data and sector attribute information 300 are stored in the data sector of a certain track 50 (referred to as the target track), and parity bits are stored in the parity bit sector, if the host 2 requests a random write to the target track, that is, a write to the data sector of the target track, the controller 30 operates as follows: The controller 30 obtains the write data from the host 2 and stores it in RAM 27 (for example, refer to...). Figure 8 (S301 to S303). Controller 30 obtains track data from the target track, that is, a dataset including data and attribute information stored in all data sectors, and saves the track data in RAM 27 (e.g., refer to...). Figure 8(S306). Furthermore, the controller 30 acquires sector attribute information 300 corresponding to the sector of the write destination of the written data, and updates the track data in RAM 27 using the acquired sector attribute information 300 and the written data (e.g., referring to...). Figure 8 S304, S307, S308 and Figures 9-11 Furthermore, while writing the updated track data to the target track, the controller 30 calculates the track parity bit and writes the track parity bit to the parity bit sector of the target track (S309).

[0138] In other words, when controller 30 initiates a rewrite operation, it simultaneously writes the requested data to the disk 11 while writing track data during the rewrite operation. This reduces the number of write operations to the target track, thus reducing the processing time for write commands. In other words, write performance is improved.

[0139] Furthermore, once the write command processing is complete, the target track becomes active with track protection enabled. Therefore, unlike the comparative example, the recalculation and overwriting of the track parity bit after the write command processing can be omitted.

[0140] Additionally, according to the implementation, sector attribute information 300 in one example is the generation information of the key used when encrypting data obtained from host 2 through encryption / decryption module 29.

[0141] Additionally, according to the implementation, the sector attribute information 300 in another example is information associated with errors in the sector where the sector attribute information 300 is stored (specifically, first uncorrectable information and second uncorrectable information).

[0142] The structure of sector attribute information 300 is not limited to the examples described above. Sector attribute information 300 may replace generation information and error-related information, or include other information on top of them.

[0143] Furthermore, according to the implementation, when the track protection function is active and a track 50 whose ATI counter has exceeded the second threshold requires a write operation, the controller 30 initiates a rewrite operation. During the rewrite operation, while writing the track data to the disk 11, it simultaneously writes the data that was requested to be written (e.g., refer to...). Figure 8 (S306 to S310). In cases other than those described above, such as when the track protection function is active and a write request is made to track 50 where the ATI counter is below the second threshold, or when a write request is made to track 50 where the track protection function is inactive, the controller 30 does not initiate the rewrite operation and writes the data to track 50 by attaching sector attribute information 300 to the data to be written.

[0144] Therefore, it is possible to prevent the track protection function from becoming invalid when the ATI counter exceeds the second threshold due to the write data to track 50 when the track protection function is active and the ATI counter exceeds the second threshold.

[0145] Furthermore, as described above, when the track protection function is active and the ATI counter exceeds the second threshold for track 50, the controller 30 initiates a rewrite operation. During the rewrite operation, track data is written to disk 11, and the requested data is written simultaneously. The controller 30 can also initiate a rewrite operation regardless of whether the track protection function of the destination track 50 is active, writing track data to disk 11 and the requested data simultaneously. Alternatively, the controller 30 can initiate a rewrite operation regardless of the ATI of the destination track 50, writing track data to disk 11 and the requested data simultaneously. The controller 30 can also initiate a write operation when any condition is met, writing track data to disk 11 and the requested data simultaneously during the rewrite operation.

[0146] The above examples illustrate the case where disk device 1 follows a native 4K standard. Figure 8 The processes S307 and S308 shown are described in detail. The disk devices to which this implementation can be applied are not limited to those conforming to 4K native standards. For example, the implementation can also be applied to disk devices conforming to a method known as 512-byte emulation.

[0147] Based on the 512-byte simulation, the host transfers data to the disk device in 512-byte units. Within the disk device, the controller collects the data transferred between the host and the controller in 512-byte units to generate a total of 4KB of data, and then transfers data between the controller and the disk in 4KB units. In other words, the host accesses the disk device using 512-byte sectors, and the controller processes data using 4KB sectors.

[0148] Figure 12 This diagram illustrates a detailed example of the structure of the write data and track data within RAM 27 at the point in time of processing S306 in a disk device 1 that follows a 512-byte simulation implementation. For ease of explanation, the data transmitted by the host 2 in 512-byte units is recorded as sub-sector data SDs.

[0149] exist Figure 12In the example shown, controller 30 receives two sub-sector data SDs from host 2. When controller 30 saves the two sub-sector data SDs received from host 2 into RAM 27, it appends an error correction code (ECCb) for RAM storage to each sub-sector data SDs. Thus, the write data WD in RAM 27 has a structure including two sub-sector data SDs, each appended with an error correction code (ECCb).

[0150] The track data TD in RAM27 has the same... Figure 10 The structure shown follows the same TD structure as the native 4K track data.

[0151] Figure 13 This is a diagram illustrating a detailed example of the structure of sector data SD' updated using the transformed write data WD' in a disk device 1 that follows a 512-byte emulation implementation, through processing S308.

[0152] In the processing of S307, the controller 30 transforms the error correction code ECCb of each sub-sector data SDs constituting the written data WD into an error correction code ECCb containing the generation information obtained through the processing of S304. + Therefore, the transformed write data WD' is generated.

[0153] In the processing of S308, controller 30 replaces the portion of sector data SD read from the sector of the write destination contained in track data TD with the transformed write data WD', which is designated as the write destination. Figure 13 In the example shown, the data in the sub-sectors at positions 5 and 6 from the beginning of the sector data SD is replaced by the transformed write data WD'. The controller 30 further appends generation-information error correction codes (ECCb) to the remaining un-replaced sub-sector data SDs in the sector data SD. + Transformed into an error-correcting code ECCb containing generational information obtained through the processing in S304. + Thus, the updated sector data SD' is completed.

[0154] Thus, in the disk device 1 that follows the 512-byte simulation, the controller 30 replaces a portion of the sector data SD contained in the track data TD with write data, and replaces the generation information of the sector data SD with the generation information obtained through the processing of S304.

[0155] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A disk drive, capable of connecting to a host computer, comprising: The disk has a first track with multiple first sectors (#1-9) and second sectors (#10); The read / write head is used to write and read data from the disk. Memory; and Controller The disk contains a plurality of second tracks, including the first track. Each of the plurality of second tracks has a plurality of fourth sectors for which data segments and attribute information are written, and a fifth sector for which parity bits are written. The controller Estimate the extent of ATI (Aspect-to-Intensity Interference) on each second track, i.e., the interference between adjacent tracks. If the ATI influence on a second track in the first state of the plurality of second tracks exceeds a first threshold, the parity bit is recalculated and the contents of the second track are rewritten, including the writing of the recalculated parity bit. The first state is the state in which the contents of the plurality of fourth sectors in the second track correspond to the parity bit in the fifth sector. When a first data segment and first attribute information (300) are stored in each of the plurality of first sectors, and a first parity bit is stored in the second sector, and the host requests the writing of a second data segment to a third sector, which is one of the plurality of first sectors, and the first track is in the first state and the degree of ATI influence on the first track exceeds a second threshold smaller than the first threshold, then... The second data segment is retrieved from the host and stored in the memory. A first dataset, comprising all first data segments and all first attribute information, is read from the first track and stored in the memory. Obtain the second attribute information, which is the attribute information corresponding to the third sector. The memory is updated with the third data segment and third attribute information in the first dataset, which are the first data segment and first attribute information read from the third sector, using the second data segment and the second attribute information. While writing the second dataset, which is the updated first dataset, to the first track, the second parity bit is calculated based on the second dataset. Write the second parity bit into the second sector. The first attribute information is the attribute information corresponding to the first sector among the plurality of first sectors that stores the first attribute information.

2. The disk drive according to claim 1, It also includes an encryption / decryption module, which uses a key to encrypt data segments obtained from the host and uses the same key to decrypt data segments sent to the host. The third attribute information includes generation information of the key used in encrypting the third data segment when the third data segment was obtained from the host. The second attribute information includes generational information of the key used in encrypting the second data segment when the second data segment was obtained from the host.

3. The disk drive according to claim 1, The attribute information includes information related to errors in the first sector among the plurality of first sectors that stores the attribute information.

4. The disk drive according to any one of claims 1 to 3, The controller If the ATI influence on a second track in a second state exceeds a second threshold, the parity bit is recalculated, and the contents of the second track are rewritten, including the recalculated parity bit. The second state is a state where the contents of the plurality of fourth sectors in the second track do not correspond to the parity bits in the fifth sector. When the first track is in the first state and the ATI influence on the first track is less than the second threshold, or when the first track is in the second state, The second data segment is obtained from the host. Obtain the second attribute information. The second data segment and the second attribute information are written together into the third sector.

5. The disk drive according to claim 4, If the second data segment is smaller than the third data segment, a portion of the third data segment is replaced with the second data segment, and the third attribute information is replaced with the second attribute information.

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