Semiconductor structure and method of forming the same

Abstract

The application discloses a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the following steps: forming a plurality of first grooves and second grooves in a substrate of a logic region and an array region respectively; forming a dielectric liner in the first grooves and the second grooves; forming a plurality of first coating blocks and second coating blocks in the first grooves and the second grooves respectively; forming a cap layer on the first coating blocks and the second coating blocks; forming a plurality of oxidation structures on the cap layer; removing part of the oxidation structures and the cap layer; and forming a semiconductor layer in the array region, the semiconductor layer being arranged between the substrate and the oxidation structures. The application can effectively prevent the isolation structure of the semiconductor structure from being broken to form defects, thereby improving the overall yield of the semiconductor structure.

Description

Technical Field

[0001] This application relates to a semiconductor structure and a method for forming the same, and more particularly to a method for forming a semiconductor structure that prevents the oxide layer from cracking and forming defects, and the semiconductor structure formed therefrom. Background Technology

[0002] In the process of manufacturing semiconductor structures, isolation structures (e.g., shallow trench isolation (STI) structures) can be formed by coating spin-on glass (SOG) onto dielectric pads. However, in subsequent processes, the isolation structure and dielectric pads may crack due to thermal stress, resulting in defects that can lead to short circuits in subsequently formed conductive structures (e.g., control gates). Summary of the Invention

[0003] This application proposes a method for forming a semiconductor structure. By forming a dielectric pad and a capping layer on the isolation structure of the semiconductor structure, the method can effectively prevent the isolation structure of the semiconductor structure from breaking and forming defects, thereby improving the overall yield of the semiconductor structure.

[0004] Some embodiments of this application include a method for forming a semiconductor structure having an array region and a logic region disposed around the array region. The method for forming the semiconductor structure includes the following steps: providing a substrate; forming a plurality of first trenches in the substrate of the logic region and a plurality of second trenches in the substrate of the array region; forming dielectric pads over the first trenches and the second trenches; forming a plurality of first coating blocks in the first trenches and a plurality of second coating blocks in the second trenches; forming a capping layer over the first coating blocks and the second coating blocks; forming a plurality of oxide structures over the capping layer; removing a portion of the oxide structures and a portion of the capping layer; and forming a semiconductor layer in the array region, the semiconductor layer being disposed over the substrate and between the oxide structures.

[0005] Some embodiments of this application include a semiconductor structure having an array region and a logic region disposed around the array region. The semiconductor structure includes a substrate, a plurality of first coating blocks, and a plurality of second coating blocks. The first coating blocks are disposed in the substrate and located within the logic region, and the second coating blocks are disposed in the substrate and located within the array region. The semiconductor structure also includes a plurality of dielectric pads and a plurality of capping layers, the dielectric pads and capping layers covering the first or second coating blocks. The semiconductor structure further includes a plurality of oxide structures and semiconductor layers, the oxide structures being disposed above the second coating blocks, and the semiconductor layers being disposed between the oxide structures. Attached Figure Description

[0006] Figure 1A , Figure 2A, Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A These are partial cross-sectional views illustrating various stages of a method for forming a logic region of a semiconductor structure, based on some embodiments of this application.

[0007] Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B These are partial cross-sectional views illustrating various stages of a method for forming an array region of a semiconductor structure according to some embodiments of this application.

[0008] Figure Labels

[0009] 100: Semiconductor Structure

[0010] 100A: Array Area

[0011] 100L: Logic Area

[0012] 10: Substrate

[0013] 10T: Top surface of the substrate

[0014] 12: First nitriding layer

[0015] 12T: Top surface of the first nitrided layer

[0016] 14: Dielectric Pad

[0017] 16: Coating layer

[0018] 16-1: First Coating Block

[0019] 16-1T: Top surface of the first coating block

[0020] 16-2: Second Coating Block

[0021] 16-2T: Top surface of the second coating block

[0022] 18: Cap layer

[0023] 20: Pre-lining

[0024] 22: First oxide layer

[0025] 22S: Oxidation structure

[0026] 22ST: Top surface of the oxide structure

[0027] 23: Tunneling Oxide Layer

[0028] 24: Semiconductor layer

[0029] 24M: Semiconductor material layer

[0030] 24T: Top surface of the semiconductor layer

[0031] 26: Barrier Layer

[0032] 26H: Hole

[0033] 28: Second oxide layer

[0034] 30: Second nitriding layer

[0035] T1: First trench

[0036] T2: Second trench

[0037] W24B: Width of the bottom of the semiconductor layer

[0038] W24T: Width of the top of the semiconductor layer

[0039] WT1: Opening width of the first groove

[0040] WT2: Opening width of the second groove Detailed Implementation

[0041] The semiconductor structure 100 in this application embodiment (e.g.) Figure 12A , Figure 12B As shown, it has an array region 100A and a logic region 100L. The logic region 100L is located around the array region 100A; therefore, the logic region 100L can also be called the peripheral region. For simplicity, Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B, Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B Some components of the semiconductor structure 100 have been omitted.

[0042] Reference Figure 1A and Figure 1B A first nitride layer 12 is formed on the substrate 10. The substrate 10 may include, for example, a semiconductor substrate, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a composite substrate formed of different materials. The substrate 10 may be doped (e.g., using p-type or n-type dopants) or undoped.

[0043] The first nitride layer 12 may comprise silicon nitride and may be formed on the substrate 10 by a deposition process. The deposition process may include, for example, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or combinations thereof, but this application is not limited thereto.

[0044] Reference Figure 2A and Figure 2B Multiple first trenches T1 are formed in the logic region 100L (in Figure 2A (Only one is shown in the diagram) and a plurality of second trenches T2 are formed in the array region 100A. In some embodiments, the opening width WT1 of the first trench T1 is greater than the opening width WT2 of the second trench T2. In addition, the number and density of the first trenches T1 per unit area may be less than the number and density of the second trenches T2 per unit area, but this application is not limited thereto.

[0045] A mask layer (not shown) can be formed on the first nitride layer 12 to serve as an etching mask for etching processes, thereby etching a first trench T1 and a second trench T2 in the substrate 10 and the first nitride layer 12. For example, the mask layer may include photoresist or a hard mask. The mask layer may be a single-layer or multi-layer structure.

[0046] The mask layer can be formed by, for example, deposition processes, photolithography processes, other suitable processes, or combinations thereof. Here, deposition processes include spin-on coating, chemical vapor deposition, atomic layer deposition, similar processes, or combinations thereof; photolithography processes can include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking (PEB), developing, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof, but this application is not limited thereto.

[0047] Next, dielectric pads 14 are formed in the plurality of first trenches T1, the plurality of second trenches T2, and over the first nitride layer 12. The dielectric pads 14 may comprise, for example, an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride) and may be formed by a deposition process, but this application is not limited thereto. Next, a thermal processing process is performed. For example, a thermal annealing process or a rapid thermal processing (RTP) may be performed to harden the dielectric pads 14.

[0048] Reference Figure 3A and Figure 3B A coating layer 16 is formed on the dielectric pad 14. The coating layer 16 may contain, for example, an insulating material (e.g., spin-on glass (SOG)), but is not limited thereto. In detail, the coating layer 16 may be formed on the top surface of the dielectric pad 14 and fill the first trench T1 and the second trench T2.

[0049] Reference Figure 4A and Figure 4B Part of the dielectric pad 14 and part of the coating layer 16 are removed to form a plurality of first coating blocks 16-1 in the first trench T1. Figure 4A (Only one is shown in the diagram), and a plurality of second coating blocks 16-2 are formed in the second trench T2. In some embodiments, the top surface 16-1T of the first coating block 16-1 is higher than the top surface 10T of the substrate 10, while the top surface 16-2T of the second coating block 16-2 is lower than the top surface 10T of the substrate 10. Here, the top surface 16-1T of the first coating block 16-1 is, for example, a flat surface, while the top surface 16-2T of the second coating block 16-2 is, for example, a recessed surface. The position of the top surface 16-2T of the second coating block 16-2 can be regarded as the position of the lowest point of the recessed surface.

[0050] Specifically, in some embodiments, a planarization process is performed to remove the dielectric pad 14 and coating layer 16 located on the top surface 12T of the first nitride layer 12, making the coating layer 16 substantially coplanar with the first nitride layer 12. Next, in some embodiments, a wet etching process is performed to remove a portion of the coating layer 16 located in the first trench T1, leaving a first coating block 16-1, and to remove a portion of the coating layer 16 located in the second trench T2, leaving a second coating block 16-2. The planarization process includes, for example, a chemical mechanical polishing (CMP) process, while the wet etching process may include a diluted hydrofluoric acid (DHF) cleaning process. Because the dielectric pad 14 and coating layer 16 have etching selectivity, the etching rate of the etching solution for the dielectric pad 14 and coating layer 16 differs. Therefore, after the wet etching process, the dielectric pad 14 can be retained on the sidewalls of the first trench T1 and the second trench T2.

[0051] Reference Figure 5A and Figure 5B A capping layer 18 is formed over the first coating block 16-1, the second coating block 16-2, and the first nitride layer 12. For example, the material and formation method of the capping layer 18 may be the same as or similar to the material and formation method of the dielectric pad 14. In other words, the capping layer 18 can be formed over the first coating block 16-1, the second coating block 16-2, and the first nitride layer 12 by a deposition process, but this application is not limited thereto. In some embodiments, the capping layer 18 above the first coating block 16-1 has a flat structure, while the capping layer 18 above the second coating block 16-2 has a recessed structure.

[0052] Next, in some embodiments, a heat treatment process is performed. For example, a thermal annealing process or a rapid heat treatment (which may be referred to as a thermal densifying process) may be performed to harden the capping layer 18. Here, the capping layer 18 (and a portion of the dielectric pad 14) may serve as an etch stop layer in subsequent processes, but this application is not limited thereto.

[0053] Reference Figure 6A and Figure 6BA pre-pad 20 is formed on the capping layer 18. Then, a first oxide layer 22 is formed on the capping layer 18 and the pre-pad 20. In other words, the pre-pad 20 is disposed between the capping layer 18 and the first oxide layer 22. In some embodiments, the bottom of the first oxide layer 22 in the logic region 100L and the array region 100A is lower than the top of the capping layer 18 and the pre-pad 20. The pre-pad 20 and the first oxide layer 22 may, for example, comprise oxides, such as silicon oxide. Furthermore, the pre-pad 20 and the first oxide layer 22 can be sequentially formed on the capping layer 18 by a deposition process.

[0054] like Figure 6A and Figure 6B As shown, in some embodiments, a portion of the first oxide layer 22 is filled into the first trench T1 and the second trench T2 to form a plurality of oxide structures 22S, and in the array region 100A, the bottom of each oxide structure 22S is located below the top surface 10T of the substrate 10. Next, in some embodiments, the first oxide layer 22 is subjected to high-density plasma treatment.

[0055] Reference Figure 7A and Figure 7B In some embodiments, a portion of the first oxide layer 22, a portion of the pre-pad 20, and a portion of the capping layer 18 located above the top surface 12T of the first nitride layer 12 are removed. For example, a planarization process (e.g., chemical mechanical polishing) is performed to remove a portion of the first oxide layer 22, a portion of the pre-pad 20, and a portion of the capping layer 18 located above the top surface 12T of the first nitride layer 12. Then, in some embodiments, the first nitride layer 12 is removed. For example, phosphoric acid can be used as the etching solution, and the first nitride layer 12 can be removed by a wet etching process, but this application is not limited thereto.

[0056] Reference Figure 8A and Figure 8B In some embodiments, a pre-cleaning process is performed to remove the remaining pre-pads 20 and oxide structures 22S on the capping layer 18 in the logic region 100L (located above the first coating block 16-1), leaving the remaining dielectric pads 14 and capping layer 18 surrounding the first coating block 16-1. In some embodiments, the remaining pre-pads 20 and oxide structures 22S on the capping layer 18 in the logic region 100L (located above the first coating block 16-1) can also be removed by a planarization process in the preceding step. During the planarization or pre-cleaning process, a dishing effect occurs due to the relatively open structure of the logic region 100L, causing the oxide structures 22S in the logic region 100L to be removed. In some embodiments, after the pre-cleaning process is completed, the top surface of the remaining capping layer 18 in the logic region 100L is a flat structure.

[0057] Compared to logic region 100L, because the pattern size of array region 100A is different from that of logic region 100L, the oxide structure 22S in array region 100A is only partially affected by the planarization or pre-cleaning process, or is not affected at all. Therefore, the oxide structure 22S in array region 100A is only partially removed or not removed at all.

[0058] In addition, a pre-cleaning process is performed to remove the dielectric pads 14 or capping layers 18 and a portion of the pre-pads 20 on both sides of the oxide structure 22S in the array region 100A (located above the substrate 10), so that the remaining oxide structure 22S and the pre-pads 20 form an approximately perpendicular profile, for example, the sidewalls of the remaining pre-pads 20 have an angle of 85 to 95 degrees with the substrate 10. After performing the pre-cleaning process, the pre-pads 20 form an upwardly tapered structure. The pre-cleaning process includes, for example, but is not limited to, a wet etching process (e.g., a diluted hydrofluoric acid cleaning (DHF) process).

[0059] Reference Figure 9A and Figure 9B A tunneling oxide layer 23 and a semiconductor material layer 24M are sequentially formed on the substrate 10. Specifically, the semiconductor material layer 24M is formed on the substrate 10, the first coating area 16-1, and the second coating area 16-2. Furthermore, in the array region 100A, the tunneling oxide layer 23 and the semiconductor material layer 24M are disposed on the substrate 10 between the oxide structure 22S and the substrate. The tunneling oxide layer 23 and the semiconductor material layer 24M can be formed by a deposition process.

[0060] For example, the semiconductor material layer 24M may include elemental semiconductors (e.g., silicon, germanium, etc.), compound semiconductors (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), etc.), alloy semiconductors (e.g., silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or indium gallium phosphide (GaInP), etc.), other suitable semiconductors, or combinations thereof, but this application is not limited thereto.

[0061] Next, as Figure 9A As shown, in some embodiments, a barrier layer 26 is formed in the logic region 100L, and the barrier layer 26 has a plurality of holes 26H corresponding to the first coating block 16-1. Figure 9A (Only one is shown in the figure). In other words, the hole 26H exposes the semiconductor material layer 24M corresponding to the portion of the first coating block 16-1.

[0062] For example, the barrier layer 26 comprises a nitride, such as silicon nitride. Furthermore, a mask layer (not shown) can be disposed on the barrier material as an etching mask for etching processes to form the barrier layer 26 having a plurality of holes 26H. The mask layer can be formed by, for example, deposition processes, photolithography processes, other suitable processes, or combinations thereof.

[0063] Reference Figure 10A and Figure 10B In some embodiments, a planarization process is performed. Specifically, a planarization process is performed to remove a portion of the semiconductor material layer 24M in the array region 100A to form a semiconductor layer 24 and expose the top surface 22ST of the oxide structure 22S. For example, the planarization process may include a chemical mechanical polishing process, but this application is not limited thereto.

[0064] In the logic region 100L, the high selectivity of the slurry for the barrier layer 26 ensures that the barrier layer 26 protects the structure of the logic region 100L from excessive removal. Therefore, only the portion of the semiconductor material layer 24M exposed by the vias 26H is removed, while the semiconductor material layer 24M located beneath the barrier layer 26 can be retained to form the semiconductor layer 24. The barrier layer 26 is only partially or almost entirely removed during the planarization process. Next, phosphoric acid can be used as an etching solution, for example, and the barrier layer 26 in the logic region 100L can be removed using a wet etching process.

[0065] like Figure 10B As shown, in some embodiments, the semiconductor layer 24 is disposed between the oxide structures 22S, and the top surface 24T of the semiconductor layer 24 and the top surface 22ST of the oxide structure 22S are substantially coplanar, but this application is not limited thereto.

[0066] Reference Figure 11A and Figure 11B A second oxide layer 28 and a second nitride layer 30 are sequentially formed on the semiconductor layer 24 and the oxide structure 22S. The material and formation method of the second oxide layer 28 may be the same as or similar to the material and formation method of the first oxide layer 22, and the material and formation method of the second nitride layer 30 may be the same as or similar to the material and formation method of the first nitride layer 12.

[0067] Reference Figure 12A In some embodiments, the second nitride layer 30, the second oxide layer 28, and the semiconductor layer 24 (or semiconductor material layer 24M) in the logic region 100L are removed to form the semiconductor structure 100. For example, the array region 100A can be masked first, and a dry etching process can be performed in the logic region 100L to sequentially remove the second nitride layer 30, the second oxide layer 28, and the semiconductor layer 24.

[0068] Simultaneously refer to Figure 12A and Figure 12B The semiconductor structure 100 includes a substrate 10 and multiple first coating blocks 16-1 ( Figure 12A (Only one is shown in the figure) and multiple second coating blocks 16-2. The first coating block 16-1 is disposed in the substrate 10 and located in the logic region 100L, while the second coating block 16-2 is disposed in the substrate 10 and located in the array region 100A.

[0069] The semiconductor structure 100 also includes a plurality of dielectric pads 14 and a plurality of capping layers 18, each dielectric pad 14 and capping layer 18 covering a corresponding first coating block 16-1 or second coating block 16-2. In some embodiments, the dielectric pads 14 are disposed on the sidewalls of the first coating block 16-1 or the second coating block 16-2, and the capping layer 18 is disposed on the top surface of the first coating block 16-1 or the second coating block 16-2. In some embodiments, the dielectric pads 14 and the capping layer 18 are hardened oxide layers.

[0070] The first coating block 16-1 can be considered as an isolation structure (e.g., a shallow trench isolation (STI) structure) of the semiconductor structure 100. Since the dielectric pad 14 and the capping layer 18 cover the first coating block 16-1 (i.e., the isolation structure), defects caused by the breakage of the isolation structure of the semiconductor structure can be effectively prevented. In some embodiments, the dielectric pad 14 and the capping layer 18 can serve as etch stop layers in the manufacturing process, thereby improving the overall yield of the semiconductor structure 100.

[0071] The semiconductor structure 100 further includes multiple oxide structures 22S and a semiconductor layer 24. The oxide structures 22S are disposed on the second coating block 16-2 (and the capping layer 18), and the semiconductor layer 24 is disposed between the oxide structures 22S. Figure 12B As shown, in some embodiments, semiconductor layer 24 has a substantially constant width.

[0072] Because of the dielectric liner 14 and the capping layer 18, during the pre-cleaning process (such as... Figure 8B When the pre-padding 20 is formed, the remaining oxide structure 22S in the array region 100A forms a substantially perpendicular profile with the array pad 20, allowing the subsequently formed semiconductor layer 24 to have substantially perpendicular sidewalls (i.e., substantially constant width), resulting in a more uniform semiconductor layer 24 compared to those formed by known techniques, and reducing the likelihood of seams. In some embodiments, the ratio of the width W24T at the top of the semiconductor layer 24 to the width W24B at the bottom of the semiconductor layer 24 is between about 0.9 and about 1.1.

[0073] As described above, in the semiconductor structure formation method according to the embodiments of this application, by forming a dielectric pad and a capping layer on the isolation structure of the semiconductor structure, it is possible to effectively prevent the isolation structure of the semiconductor structure from breaking and forming defects, thereby improving the overall yield of the semiconductor structure.

[0074] The components of several embodiments are summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of this application to achieve the same purposes and / or advantages as the embodiments described herein.

[0075] In one or more embodiments, the features, advantages, and characteristics described in this application may be combined in any suitable manner. Based on the description herein, those skilled in the art will recognize that this application may be implemented without one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, The semiconductor structure has an array region and a logic region disposed around the array region, and the method for forming the semiconductor structure includes: Provide substrate; A plurality of first trenches are formed in the substrate of the logic region and a plurality of second trenches are formed in the substrate of the array region; Dielectric pads are formed in the plurality of first trenches and the plurality of second trenches; A plurality of first coating blocks are formed in the plurality of first trenches, and a plurality of second coating blocks are formed in the plurality of second trenches; A capping layer is formed over the plurality of first coating blocks and the plurality of second coating blocks; Multiple oxide structures are formed on the capping layer; Removing a portion of the plurality of oxide structures and a portion of the capping layer; and A semiconductor layer is formed in the array region, wherein the semiconductor layer is disposed between the plurality of oxide structures.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of forming the plurality of first coating blocks and the plurality of second coating blocks include: A coating layer is formed on the dielectric pad; Perform a planarization process to remove a portion of the dielectric pad and a portion of the coating layer; and A wet etching process is performed to remove portions of the coating layer located in the plurality of first trenches, leaving the plurality of first coating blocks, and to remove portions of the coating layer located in the plurality of second trenches, leaving the plurality of second coating blocks.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, Including: After the dielectric pad is formed, a heat treatment process is performed; and After the capping layer is formed, another heat treatment process is performed.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, Including: A pre-liner is formed on the capping layer, wherein the pre-liner is disposed between the capping layer and the plurality of oxide structures.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, Including: A first oxide layer is formed on the capping layer, wherein a portion of the first oxide layer is filled into the plurality of second trenches to form the plurality of oxide structures; and The first oxide layer is subjected to high-density plasma treatment.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, A planarization process is performed to remove a portion of the first oxide layer and a portion of the capping layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, Including: A tunneling oxide layer is formed between the semiconductor layer and the substrate.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for forming the semiconductor layer include: A semiconductor material layer is formed on the substrate, the plurality of first coating blocks, and the plurality of second coating blocks; A barrier layer is formed in the logic region, wherein the barrier layer has a plurality of holes, the plurality of holes corresponding to the plurality of first coating blocks; A planarization process is performed to remove a portion of the semiconductor material layer in the array region to form the semiconductor layer and expose the top surface of the plurality of oxide structures; and Remove the semiconductor material layer in the logic region.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, Including: A second oxide layer and a nitride layer are sequentially formed on the semiconductor layer and the plurality of oxide structures.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, Including: A first nitride layer is formed on the substrate, wherein the first nitride layer is located between the substrate and the dielectric pad.

11. A semiconductor structure, characterized in that, The semiconductor structure includes an array region and a logic region disposed around the array region. Substrate; Multiple first coating blocks are disposed in the substrate and located in the logic region; Multiple second coating blocks are disposed in the substrate and located in the array region; Multiple dielectric pads and multiple capping layers cover the multiple first coating blocks or the multiple second coating blocks; Multiple oxide structures are disposed on the multiple second coating blocks; and A semiconductor layer is disposed between the plurality of oxide structures, wherein the top surface of the semiconductor layer is coplanar with the top surfaces of the plurality of oxide structures.

12. The semiconductor structure as claimed in claim 11, characterized in that, The ratio of the width of the top to the width of the bottom of the semiconductor layer is between 0.9 and 1.

1.

13. The semiconductor structure as described in claim 11, characterized in that, The materials of the plurality of dielectric pads are the same as the materials of the plurality of capping layers.

14. The semiconductor structure as claimed in claim 11, characterized in that, The plurality of dielectric pads and the plurality of capping layers are hardened oxide layers.

15. The semiconductor structure as claimed in claim 11, characterized in that, The top surface of the plurality of first coating blocks is higher than the top surface of the substrate, while the top surface of the plurality of second coating blocks is lower than the top surface of the substrate.

16. The semiconductor structure as claimed in claim 11, characterized in that, In the array region, the bottom of each of the plurality of oxide structures is located below the top surface of the substrate.

Images