A semiconductor structure, a preparation method thereof and a memory

Abstract

The embodiment of the present disclosure provides a semiconductor structure, a preparation method thereof and a memory. The method comprises the following steps: providing a wafer, and a plurality of conductive columns are formed in the wafer; inverting the wafer, and performing etching treatment on the back plane of the wafer, so that each conductive column is exposed from the back plane of the wafer; wherein the lengths of the plurality of conductive columns exposed on the back plane are different; depositing an insulating layer on the back plane of the wafer and above the conductive columns, and depositing a filling layer above the insulating layer; wherein the filling layer completely covers the back end points of the plurality of conductive columns; performing grinding treatment on the filling layer and the back end points of part of the conductive columns, until the back end points of each conductive column are exposed, and the back end points of the plurality of conductive columns are flush with the back plane of the filling layer, so that the preparation yield of the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] With the development of semiconductor technology, the feature size of integrated circuits is constantly shrinking, and the interconnect density of devices is constantly increasing. Traditional two-dimensional packaging can no longer meet the needs of the industry, while stacked packaging based on through silicon via (TSV) vertical interconnects is gradually leading the trend of packaging technology development due to its key technological advantages of short-distance interconnection and high-density integration.

[0003] In the TSV Middle process, the back side of the silicon via within the chip needs to be exposed using Backside Via Reveal (BVR) to enable multi-layer chip stacking interconnection. However, during the etching process to form the TSV, the hole depth varies among different TSVs, resulting in different backside exposure lengths for different TSVs, which adversely affects subsequent processes. Summary of the Invention

[0004] In view of the above, this disclosure provides a semiconductor structure, a method for fabricating the same, and a memory.

[0005] In a first aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, the method comprising:

[0006] A wafer is provided, and a plurality of conductive pillars are formed therein;

[0007] The wafer is inverted, and the back face of the wafer is etched so that each conductive pillar is exposed from the back face of the wafer; wherein the lengths of the conductive pillars exposed from the back face are different.

[0008] An insulating layer is deposited on the back plane of the wafer and above the conductive pillars, and a fill layer is deposited on the insulating layer; wherein the fill layer completely covers the back endpoints of the plurality of conductive pillars;

[0009] The back end points of the filling layer and some of the conductive pillars are ground until the back end point of each conductive pillar is exposed, and the back end points of the multiple conductive pillars are flush with the back plane of the filling layer.

[0010] In some embodiments, depositing an insulating layer over the back plane of the wafer and the conductive pillars includes:

[0011] An insulating material is deposited on the back plane of the wafer and above the conductive pillars using a vapor phase chemical deposition process to form the insulating layer;

[0012] The insulating material includes at least silicon nitride.

[0013] In some embodiments, the thickness of the insulating layer is less than the minimum length of the conductive post exposed on the back plane.

[0014] In some embodiments, the deposition of a fill layer over the insulating layer includes:

[0015] A filler material is coated onto the insulating layer using a spin coating process;

[0016] The wafer is baked.

[0017] The wafer is annealed to solidify the filler material and form the filler layer.

[0018] The filler material includes at least spin-coated glass (SOG).

[0019] In some embodiments, the baking process of the wafer includes:

[0020] The wafer is heated to a first temperature value using a hot plate, and a baking process of a first preset duration is performed.

[0021] The wafer is heated to a second temperature value using a hot plate, and a baking process of a first preset duration is performed.

[0022] The wafer is heated to a third temperature value using a hot plate, and a baking process of a first preset duration is performed.

[0023] In some embodiments, the first temperature value is less than the second temperature value, the second temperature value is less than the third temperature value, and the difference between the second temperature value and the first temperature value is less than the difference between the third temperature value and the second temperature value.

[0024] In some embodiments, the annealing temperature is a fourth temperature value, and the annealing time is a second preset duration; wherein the fourth temperature value is greater than the third temperature value, and the second preset duration is greater than the first preset duration.

[0025] In some embodiments, inverting the wafer includes:

[0026] Provide a substrate;

[0027] The wafer is flipped onto the carrier substrate, and the wafer and the carrier substrate are bonded together.

[0028] In some embodiments, before etching the back plane of the wafer, the maximum length of the conductive pillar is a first value, and the minimum length of the conductive pillar is a second value.

[0029] The etching process on the back plane of the wafer to expose each conductive pillar from the back plane of the wafer includes:

[0030] The back plane of the wafer is thinned; wherein the thickness of the wafer after the thinning process is a third value.

[0031] The back surface of the wafer is subjected to chemical mechanical polishing; wherein the thickness of the wafer after the chemical mechanical polishing is a fourth value;

[0032] The back surface of the wafer is subjected to silicon etching; wherein the thickness of the wafer after the silicon etching is a fifth value.

[0033] The third, fourth, and fifth values ​​decrease sequentially, with the fourth value being greater than the first value and the fifth value being less than the second value.

[0034] In some embodiments, the difference between the third value and the fourth value is greater than the difference between the fourth value and the fifth value.

[0035] In some embodiments, the thickness of the insulating layer is 0.2 to 0.3 micrometers;

[0036] Before grinding the filler layer and the back endpoints of some of the conductive pillars, the thickness of the filler layer is 7.8 to 8 micrometers; after grinding the filler layer and the back endpoints of some of the conductive pillars, the thickness of the filler layer is 0.8 to 1.2 micrometers.

[0037] In some embodiments, after the filler layer is polished until the back end of each conductive post is exposed, the method further includes:

[0038] A circuit structure is formed on the back end of each of the conductive pillars.

[0039] In a second aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0040] A wafer, wherein a plurality of conductive pillars are formed therein;

[0041] An insulating layer formed on the back plane of the wafer;

[0042] A filler layer formed on the back plane of the insulating layer;

[0043] The back plane of the filling layer exposes the back end point of each conductive post, and the back end point of each conductive post is flush with the back plane of the filling layer.

[0044] In some embodiments, the insulating layer is made of at least silicon nitride, and the filler layer is made of at least spin-coated glass (SOG).

[0045] Thirdly, embodiments of this disclosure provide a memory comprising the semiconductor structure described in the second aspect.

[0046] In this embodiment, a filler layer is used to protect the exposed portion of the conductive pillars, which not only prevents the conductive pillars from being torn during subsequent grinding, but also prevents the conductive material from being ground off from contaminating the wafer. At the same time, after the grinding process, the back plane of the filler layer exposes the back endpoints of all the conductive pillars, and the back endpoints of all the conductive pillars are at the same height, which reduces the difficulty of subsequent docking processes and improves the yield of semiconductor structure fabrication. Attached Figure Description

[0047] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0048] Figure 1 This is a schematic diagram of a wafer structure after BVR process;

[0049] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0050] Figure 3 A schematic flowchart illustrating another method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0051] Figure 4A A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment;

[0052] Figure 4B A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure is shown in Figure 2.

[0053] Figure 4C A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure is shown in Figure 3.

[0054] Figure 4D A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure is shown in Figure 4.

[0055] Figure 4E A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure is shown in Figure 5.

[0056] Figure 4F A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure is shown in Figure 6.

[0057] Figure 4G A schematic diagram seven illustrates the fabrication process of a semiconductor structure provided in this disclosure embodiment;

[0058] Figure 4H A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure is shown in Figure 8.

[0059] Figure 5 This is a schematic diagram of the molecular structure of spin-coated glass material before and after curing.

[0060] Figure 6 A schematic diagram illustrating the fabrication process of another semiconductor structure provided in this disclosure embodiment;

[0061] Figure 7 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0062] Figure 8 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.

[0063] The following is an explanation of the reference numerals in the attached figures:

[0064] 30—Wafer; 31—Conductive pillar; 32—Bump; 33—Insulating layer; 34—Filling layer; 35—Circuit structure; 40—Carrier substrate; 41—Bonding adhesive; 50—Semiconductor structure; 60—Memory. Detailed Implementation

[0065] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0066] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0067] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0068] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0070] Through-silicon vias (TSVs) can be applied to the packaging of three-dimensional dynamic random access memory (DRAM). Specifically, DRAM can use a TSV Middle process to form TSVs in the wafer, and then use a BVR process to expose the TSVs from the back plane of the wafer, so that micropads can be formed on the exposed parts, enabling subsequent multi-layer chip stacking and interconnection.

[0071] In other words, in a three-dimensional stacked structure, adjacent chips are stacked and interconnected on their front and back sides. The chips need to expose the TSV (Transient Visor) from the back plane of the wafer using a BVR (Browser-Vehicle Reflector) method. See [link / reference] Figure 1 It shows a schematic diagram of a wafer structure after BVR process. For example... Figure 1 As shown, the front side of the wafer is bonded to the carrier substrate, so that the back side of the wafer faces upward; at the same time, there are multiple conductive pillars inside the wafer (conductive pillars are the structural name of TSV), and there are other packaging bumps on the front side of the wafer to implement other types of interconnects.

[0072] However, during the etching process to form conductive pillars, due to the characteristics of the etching process, the height of the etched holes at the wafer edges is generally higher, while the height of the etched holes in the center of the wafer is lower, resulting in inconsistent depths of the conductive pillars. For the BVR process, if the etching amount on the back of the wafer is less, there may be conductive pillars exposed at the wafer edges but not in the center; if the etching amount on the back of the wafer is more, it may cause the conductive pillars at the wafer edges to be too high, making them prone to tearing during subsequent polishing and also complicating subsequent mating processes.

[0073] Based on this, the present disclosure provides a semiconductor structure in the BVR process, in which the exposed portion of the conductive pillars is protected by a filler layer. This not only prevents the conductive pillars from being torn during subsequent polishing, but also prevents the conductive material removed during polishing from contaminating the wafer. At the same time, after polishing, the back plane of the filler layer exposes the back endpoints of all the conductive pillars, and the back endpoints of all the conductive pillars are at the same height, which reduces the difficulty of subsequent docking processes and improves the yield of the semiconductor structure.

[0074] In one embodiment of this disclosure, see Figure 2 This illustration shows a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method includes:

[0075] S11: Provides a wafer, and multiple conductive pillars are formed in the wafer.

[0076] It should be noted that the semiconductor structure provided in this disclosure is applied to three-dimensional semiconductor devices, such as three-dimensional DRAM. For example, this fabrication method is specifically used to implement a BVR process with a through-hole (TSV) middle.

[0077] Here, the material of the wafer is silicon (Si), but it can also be other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or combinations thereof. This disclosure does not specifically limit the material in this regard.

[0078] The conductive pillars in the wafer are called through-silicon vias (TSVs). Before step S11, conductive pillars need to be formed in the wafer. For example, multiple etched holes are first formed in the wafer through an etching process, and then conductive material (e.g., copper, Cu) is filled into the etched holes to form conductive pillars. As mentioned above, due to the characteristics of the etching process, the depths of these etched holes are not uniform, that is, the depths of different conductive pillars are not uniform.

[0079] S12: Invert the wafer and etch the back plane of the wafer so that each conductive pillar is exposed from the back plane of the wafer; wherein the lengths of the multiple conductive pillars exposed from the back plane are different.

[0080] It should be noted that in a three-dimensional stacked architecture, different chips need to be stacked by connecting them from the front to the back. Therefore, the conductive pillars in the wafer need to be exposed from the back of the wafer to form bumps, thereby interconnecting with the conductive pillars on the front of the next wafer.

[0081] Therefore, by etching the back face of the wafer, all conductive pillars are exposed from the back face. However, since the depths of the different conductive pillars are not uniform, the exposed lengths of the conductive pillars after etching the back face of the wafer are also different. Please refer to the preceding... Figure 1 Generally, the exposed length of conductive pillars at the edge of the wafer is larger, while the exposed length of conductive pillars at the center of the wafer is smaller.

[0082] S13: An insulating layer is deposited on the back plane of the wafer and above the conductive pillars, and a fill layer is deposited on the insulating layer; wherein the fill layer completely covers the back endpoints of the multiple conductive pillars.

[0083] It should be noted that the insulating layer is used to insulate the sides of the conductive post, and the filler layer is used to protect the exposed part of the conductive post to prevent damage to the conductive post during subsequent grinding steps.

[0084] S14: Grind the back end points of the filler layer and some of the conductive pillars until the back end point of each conductive pillar is exposed, and the back end points of multiple conductive pillars are flush with the back plane of the filler layer.

[0085] It should be noted that grinding is also known as Chemical Mechanical Polishing (CMP). CMP is developed based on chemical polishing and mechanical polishing, and it overcomes the shortcomings of chemical polishing alone and mechanical polishing alone. In other words, CMP is a polishing technology that combines abrasive mechanical grinding with the chemical etching effect of polishing fluid. During CMP processing, the wafer is placed on a grinding pad, and a grinding head is used in conjunction with an etching solution to grind the wafer. CMP can achieve nanoscale global planarization of the processed surface, meeting the requirements of ultra-precision, non-destructive surface processing for integrated circuits.

[0086] In this embodiment of the disclosure, during the polishing process, a filler layer surrounds the conductive pillars. On the one hand, the filler layer can play a protective role, preventing the conductive pillars from being torn during the polishing process; on the other hand, the filler layer can also isolate the fallen conductive material and wafer material, preventing the conductive material (e.g., Cu) from contaminating the wafer (Si).

[0087] In this way, the back end point of each conductive pillar is exposed through the grinding process, which facilitates the fabrication of subsequent circuits. At the same time, the back end points of all conductive pillars are at the same height, which reduces the difficulty of subsequent connection processes and avoids stress accumulation. This reduces the difficulty of semiconductor structure fabrication and improves the yield of semiconductor structure fabrication.

[0088] Please refer to Figures 4A to 4H This illustration shows a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of the present disclosure. The following is in conjunction with 4A to... Figure 4H The aforementioned preparation steps will be explained in detail.

[0089] In some embodiments, such as Figure 3 As shown, the inverted wafer includes:

[0090] S121: Provides a substrate.

[0091] S122: The wafer is flipped onto the substrate and the wafer and the substrate are bonded together.

[0092] It should be noted that after step S122, please refer to... Figure 4A The wafer 30 is inverted and placed on the substrate 40, and the two are bonded together by bonding adhesive 41. Here, the bonding adhesive 41 can be a variety of thermoplastic adhesives, and this embodiment is not limited thereto. Specifically, in... Figures 4A to 4HSince the wafer 30 is placed upside down on the substrate 40, the upward-facing side of the wafer 30 is the "back plane of the wafer", and the upward-facing end of the conductive post 31 is the "back end point of the conductive post".

[0093] like Figure 4A As shown, the wafer 30 also includes multiple conductive pillars 31, and the length (or depth) of the conductive pillars 31 is not consistent, that is, the height of the back end point of the conductive pillars 31 is different.

[0094] In addition, multiple bumps 32 are provided on the front side of the wafer 30 to meet other types of connection requirements. The bumps 32 can be staggered from the conductive pillars 31 and then connected to the conductive pillars 32 through internal chip traces. This can increase the number of conductive pillars without increasing the number of bumps 32, thereby reducing the process complexity of forming a large number of bumps 32.

[0095] It should be noted that, please refer to Figure 4A Before etching the back face of the wafer, the maximum length of the conductive pillars is a first value, and the minimum length of the conductive pillars is a second value. In some embodiments, such as Figure 3 As shown, the etching process on the back plane of the wafer to expose each conductive pillar from the back plane of the wafer includes:

[0096] S123: Thinning process is performed on the back plane of the wafer; wherein, the thickness of the wafer after the thinning process is the third value.

[0097] It should be noted that after step S123, please refer to... Figure 4B The thickness of wafer 30 becomes a third value, which is greater than the first value, meaning that all conductive pillars 31 are located inside wafer 30. Various processes can be used to thin wafer 30, such as mechanical masking, CMP, wet etching, plasma chemical etching, etc.

[0098] S124: Perform chemical mechanical polishing (CMP) on the back surface of the wafer; wherein the wafer thickness is the fourth value after polishing.

[0099] It should be noted that after step S124, please refer to... Figure 4C The thickness of wafer 30 becomes a fourth value, which is less than the third value but still greater than the first value, meaning that all conductive pillars 31 remain inside wafer 30. In this way, CMP processing can make the surface of wafer 30 smoother and more uniform.

[0100] S125: Silicon etching is performed on the back plane of the wafer; wherein the thickness of the wafer is the fifth value after silicon etching.

[0101] It should be noted that after step S125, please refer to... Figure 4D The thickness of wafer 30 becomes the fifth value, which is less than the second value, meaning that all conductive pillars 31 are exposed from the back plane of wafer 30.

[0102] Here, the difference between the third and fourth values ​​is greater than the difference between the fourth and fifth values, meaning the wafer thickness reduced in step S123 is greater than the wafer thickness removed by grinding in step S124. This avoids impact on active devices through multiple thinning and grinding operations. For example, the third value can be 80 micrometers, the fourth value can be 65 micrometers, and the fifth value can be 57 micrometers. In some embodiments, the difference between the fifth value and the height of the conductive post 31 can be between 1 and 2 micrometers, ensuring the wafer has a good thickness and mitigating the problem of difficult soldering caused by wafer warping due to excessive thinness.

[0103] Silicon etching can be performed using a wet etching process. By selecting a solution with a suitable etching ratio, only the wafer material is etched without affecting the morphology of the conductive pillars.

[0104] In other words, the first value is greater than the second value, and the third, fourth, and fifth values ​​decrease in that order, with the fourth value being greater than the first value and the fifth value being less than the second value.

[0105] In some embodiments, such as Figure 3 As shown, the deposition of an insulating layer on the back plane of the wafer and above the conductive pillars includes:

[0106] S131: An insulating layer is formed by depositing insulating material on the back plane of the wafer and above the conductive pillars using a vapor phase chemical deposition process.

[0107] It should be noted that after step S131, please refer to... Figure 4E An insulating layer 33 is deposited on the back plane of wafer 30 and above the conductive pillars 31.

[0108] It should be noted that Chemical Vapor Deposition (CVD) refers to the process by which a gaseous substance undergoes a chemical reaction on a solid surface at a certain temperature, forming a solid deposition film on that surface. It has the advantages of high deposition purity and controllable deposition thickness. Here, the insulating material includes at least silicon nitride, but can also be silicon oxide, silicon oxynitride, or other materials with insulating properties.

[0109] It should also be noted that the thickness of the insulating layer 33 only needs to meet the insulation requirements of the conductive post 31.

[0110] In some embodiments, the thickness of the insulating layer 33 is less than the minimum length of the conductive post 31 exposed on the back plane, and the insulating layer 33 is not deposited on the side of the conductive post 31 (in actual processes, a small amount of insulating material may be deposited on the side of the conductive post 31, which will not affect subsequent steps). That is, the insulating layer 33 is not continuous, which can reduce the consumption of insulating material and reduce costs.

[0111] For example, the thickness of the insulating layer 33 can be between 0.2 and 0.3 micrometers.

[0112] In some embodiments, such as Figure 3 As shown, the deposition of a fill layer over the insulating layer includes:

[0113] S132: Apply filler material to the insulating layer using a spin coating process.

[0114] S133: Baking process for the wafer.

[0115] S134: Anneal the wafer to solidify the filler material and form a filler layer.

[0116] It should be noted that after step S134, please refer to... Figure 4F A filler material is spin-coated onto the insulating layer 33, and the filler material cures to form a filler layer 34 that completely covers the conductive pillar 32. For example, the filler layer 34 has a thickness of approximately 7.8 to 8 micrometers when initially formed.

[0117] It should be noted that the filler material includes at least spin-coated glass SOG. SOG is a liquid dielectric composed of a solvent and a dielectric, containing silicon dioxide (SiO2) or a material with a structure similar to SiO2. SOG is typically used after CVD processes to planarize the CVD-deposited layers. SOG exhibits good adhesion to silicon substrates, silicon nitride deposits, silicon oxide deposits, tetraethyl orthosilicate (TEOS), etc., and demonstrates strong trench-filling ability and good step coverage. After spin-coating the SOG material, the solvent is removed through baking and annealing, and after curing, it transforms into a low-solvent solid SiO2. Please refer to [reference needed]. Figure 5 It shows the molecular structure of SOG material before and after curing.

[0118] It should be noted that, for SOG, the following exemplary process parameters for baking are provided: the baking process for the wafer may specifically include:

[0119] The wafer is heated to a first temperature value using a hot plate and baked for a first preset time. The wafer is then heated to a second temperature value using a hot plate and baked for a first preset time. Finally, the wafer is heated to a third temperature value using a hot plate and baked for a first preset time.

[0120] Here, the purpose of baking is to remove moisture from the SOG. Baking can be performed at multiple different temperatures to improve moisture removal efficiency. Specifically, the first temperature value is lower than the second temperature value, the second temperature value is lower than the third temperature value, and the difference between the second temperature value and the first temperature value is less than the difference between the third temperature value and the second temperature value.

[0121] For example, the first temperature value is 80°C, the second temperature value is 150°C, the third temperature value is 250°C, and the first preset duration is 3 minutes.

[0122] It should also be noted that after the moisture in the SOG is removed, it needs to be cured by annealing. Compared to baking, annealing involves a higher temperature and a longer time. In other words, the annealing temperature is the fourth temperature value, and the annealing time is the second preset duration; where the fourth temperature value is higher than the third temperature value, and the second preset duration is longer than the first preset duration.

[0123] For example, the fourth temperature value is 420°C, and the second preset duration is 30 minutes.

[0124] After the filling layer 34 is formed, it is chemically mechanically polished in step 14 until the back ends of all conductive pillars 31 are exposed. Please refer to... Figure 4G At this point, the thickness of the filler layer 34 is 0.8–1.2 micrometers. Here, the material properties of SOG after curing are similar to those of SiO2, and the polishing process can be carried out using conventional etching solutions and polishing pads.

[0125] Specifically, the filler layer 34 completely surrounds the conductive pillar 31, thereby increasing the polishing area and preventing the conductive pillar from being torn during the polishing process. Figure 6 As shown, if the filling layer 34 does not surround the conductive pillar 31, the subsequent polishing process will tear the conductive pillar at the edge (higher) of the wafer, affecting the performance of the semiconductor structure.

[0126] As can be seen from the above, before the back end points of the filling layer 34 and some of the conductive pillars 31 are ground, the thickness of the filling layer 34 is about 7.8 to 8 micrometers; after the back end points of the filling layer 34 and some of the conductive pillars 31 are ground, the thickness of the filling layer is 0.8 to 1.2 micrometers.

[0127] In some embodiments, after grinding the filler layer until the back end of each conductive post is exposed, the method further includes:

[0128] S15: Form a circuit structure on the back end of each conductive post.

[0129] It should be noted that after step S15, please refer to... Figure 4H A circuit structure 35 is formed on the back end of each conductive post 31 for subsequent vertical interconnection of different stacked layers.

[0130] Thus, from Figure 4G and Figure 4H As can be seen, the method provided in this embodiment can obtain a semiconductor structure with exposed TSVs and uniform exposure height, which reduces the difficulty of subsequent docking processes and avoids stress accumulation problems. This can reduce the difficulty of semiconductor structure fabrication and improve the yield of semiconductor structure fabrication.

[0131] In some embodiments, the method further includes debonding the wafer and the carrier substrate. That is, the carrier substrate is only temporarily bonded to the wafer to allow for better processing of the back side of the wafer.

[0132] In the foregoing description, all specific material components can be replaced by material components with similar properties. The above are merely examples and do not constitute specific limitations.

[0133] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a wafer in which a plurality of conductive pillars are formed; inverting the wafer and etching the back face of the wafer to expose each conductive pillar from the back face; wherein the exposed lengths of the plurality of conductive pillars on the back face are different; depositing an insulating layer on the back face of the wafer and above the conductive pillars, and depositing a fill layer on the insulating layer; wherein the fill layer completely covers the back endpoints of the plurality of conductive pillars; and grinding the fill layer and part of the back endpoints of the conductive pillars until the back endpoints of each conductive pillar are exposed, and the back endpoints of the plurality of conductive pillars are flush with the back face of the fill layer. In this way, the exposed portions of the conductive pillars are protected by the fill layer, which not only prevents the conductive pillars from being torn during subsequent grinding but also prevents contamination of the wafer by the conductive material removed during grinding. Furthermore, this disclosure provides conductive pillars with uniform exposed heights, simplifies BVR process control, reduces the difficulty of subsequent interconnection processes, and improves the yield of semiconductor structure fabrication.

[0134] In one embodiment of this disclosure, see Figure 7 This illustrates a schematic diagram of the semiconductor structure 50 provided in an embodiment of this disclosure. For example... Figure 7 As shown, the semiconductor structure 50 includes:

[0135] A wafer 30, wherein a plurality of conductive pillars 31 are formed therein; an insulating layer 33 is formed on the back plane of the wafer 30; a filling layer 34 is formed on the back plane of the insulating layer 33; wherein the back plane of the filling layer 34 exposes the back end point of each conductive pillar 31, and the back end point of each conductive pillar 31 is flush with the back plane of the filling layer 34.

[0136] It should be noted that the semiconductor structure 50 can be applied to three-dimensional DRAM or other three-dimensional stacked devices. Specifically, the semiconductor structure 50 provided in this embodiment has conductive pillars exposed on the back side, which are also called through-silicon vias (TSVs) and can be used for vertical interconnection of different stacked layers.

[0137] In particular, Figure 7 In the middle, because wafer 30 is in an inverted state, therefore Figure 7 The upward-facing side of the wafer 30 is the "back plane of the wafer", and the upward-facing end of the conductive post 31 is the "back endpoint of the conductive post". In addition, the front side of the wafer 30 also has some bumps 32, which are relatively unrelated to the content of the embodiments of this disclosure.

[0138] As mentioned earlier, the depths of different conductive pillars are not consistent when they are initially formed. However, in this embodiment, not only is the back end point of each conductive pillar exposed, but the back end points of all conductive pillars are at the same height. This reduces the difficulty of subsequent docking processes and avoids stress accumulation issues, thereby reducing the fabrication difficulty of semiconductor structures and improving the yield of semiconductor structure fabrication.

[0139] In some embodiments, the insulating layer 33 is used to achieve side insulation of the conductive pillar, and therefore the insulating layer 33 can be formed using insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride.

[0140] It should be noted that the insulating layer 33 can be formed by depositing insulating material using a CVD process. CVD has the advantages of high deposition purity and controllable deposition thickness. Here, the insulating material includes at least silicon nitride, but can also be silicon oxide, silicon oxynitride, or other materials with insulating properties.

[0141] It should be noted that the material of the filler layer 34 includes at least spin-coated glass SOG. SOG is a liquid dielectric composed of a solvent and a dielectric, containing silicon dioxide (SiO2) or a material with a structure similar to SiO2. SOG is typically used after CVD processes to planarize the CVD-deposited layers. SOG exhibits good adhesion to silicon substrates, silicon nitride deposited layers, silicon oxide deposited layers, tetraethyl orthosilicate (TEOS), etc., and has strong trench-filling ability and good step coverage. After spin-coating the SOG material, the solvent is removed through baking and annealing, and after curing, it is converted into low-solvent solid SiO2.

[0142] Taking SOG as an example, by spin-coating SOG onto the insulating layer 33 and then baking and annealing the wafer 30, the SOG can be cured to form a filling layer 34. Specifically, after spin-coating SOG, the wafer 30 is heated to 80°C and baked for 3 minutes using a hot plate, then heated to 150°C and baked for 3 minutes, then heated to 250°C and baked for 3 minutes, and finally annealed at 420°C for 30 minutes to form the filling layer 34. At this point, the filling layer 34 will surround all the conductive pillars 31. The filling layer 34 and the conductive pillars 31 are then ground until the back surface of the filling layer 34 exposes the back endpoint of each conductive pillar 31, and the back endpoint of each conductive pillar 31 is flush with the back surface of the filling layer 34.

[0143] In this way, the filling layer 33 surrounds the conductive pillar 31. On the one hand, the filling layer 33 can play a protective role, preventing the conductive pillar 31 from being torn during the polishing process; on the other hand, the filling layer 33 can also isolate the fallen conductive material from the wafer, preventing the fallen conductive material (such as Cu) from contaminating the wafer (Si).

[0144] In some embodiments, the thickness of wafer 30 is approximately 53 to 60 micrometers. For example, the thickness of wafer 30 may be 57 micrometers, the thickness of insulating layer 33 may be approximately 0.2 to 0.3 micrometers, the thickness of filler layer 33 is 7.8 to 8 micrometers when initially formed, and the final thickness of filler layer 33 after polishing is approximately 0.8 to 1.2 micrometers.

[0145] This disclosure provides a semiconductor structure in which the conductive pillars are ground by means of a filling layer. Not only are the back ends of each conductive pillar exposed, but the back ends of all conductive pillars are at the same height. This reduces the difficulty of subsequent docking processes and avoids stress accumulation problems. It can reduce the difficulty of semiconductor structure fabrication and improve the yield of semiconductor structure fabrication.

[0146] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 8 This illustrates a schematic diagram of the structure of a memory 60 provided in an embodiment of the present disclosure. For example... Figure 8 As shown, the memory 60 includes the aforementioned semiconductor structure 50. Not only are the back ends of each conductive pillar exposed, but the back ends of all conductive pillars are at the same height, which reduces the difficulty of subsequent docking processes and avoids stress accumulation problems. This can reduce the difficulty of semiconductor structure fabrication and improve the yield of semiconductor structure fabrication.

[0147] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0148] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0149] The above descriptions are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A wafer is provided, and a plurality of conductive pillars are formed therein; The wafer is inverted, and the back face of the wafer is etched so that each conductive pillar is exposed from the back face of the wafer; wherein the lengths of the conductive pillars exposed from the back face are different. An insulating layer is deposited on the back plane of the wafer and above the conductive pillars, and a fill layer is deposited on the insulating layer; wherein the fill layer completely covers the back endpoints of the plurality of conductive pillars; The back end points of the filling layer and some of the conductive pillars are ground until the back end point of each conductive pillar is exposed, and the back end points of multiple conductive pillars are flush with the back plane of the filling layer. The deposition of a fill layer over the insulating layer includes: A filler material is coated onto the insulating layer using a spin coating process; The wafer is baked. The wafer is annealed to solidify the filler material and form the filler layer. The filler material includes at least spin-coated glass SOG; The baking process for the wafer includes: The wafer is heated to a first temperature value using a hot plate, and a baking process of a first preset duration is performed. The wafer is heated to a second temperature value using a hot plate, and a baking process of a first preset duration is performed. The wafer is heated to a third temperature value using a hot plate, and a baking process of a first preset duration is performed. The first temperature value is less than the second temperature value, the second temperature value is less than the third temperature value, and the difference between the second temperature value and the first temperature value is less than the difference between the third temperature value and the second temperature value.

2. The method according to claim 1, characterized in that, The deposition of an insulating layer on the back plane of the wafer and above the conductive pillars includes: An insulating material is deposited on the back plane of the wafer and above the conductive pillars using a vapor phase chemical deposition process to form the insulating layer; The insulating material includes at least silicon nitride.

3. The method according to claim 2, characterized in that, The thickness of the insulating layer is less than the minimum length of the conductive post exposed on the back plane.

4. The method according to claim 1, characterized in that, The annealing temperature is a fourth temperature value, and the annealing time is a second preset duration. Wherein, the fourth temperature value is greater than the third temperature value, and the second preset duration is greater than the first preset duration.

5. The method according to claim 1, characterized in that, The inverted wafer includes: Provide a substrate; The wafer is flipped onto the carrier substrate, and the wafer and the carrier substrate are bonded together.

6. The method according to claim 1, characterized in that, Before etching the back plane of the wafer, the maximum length of the conductive pillar is a first value, and the minimum length of the conductive pillar is a second value. The etching process on the back plane of the wafer to expose each conductive pillar from the back plane of the wafer includes: The back plane of the wafer is thinned; wherein the thickness of the wafer after the thinning process is a third value. The back surface of the wafer is subjected to chemical mechanical polishing; wherein the thickness of the wafer after the chemical mechanical polishing is a fourth value; The back surface of the wafer is subjected to silicon etching; wherein the thickness of the wafer after the silicon etching is a fifth value. The third, fourth, and fifth values ​​decrease sequentially, with the fourth value being greater than the first value and the fifth value being less than the second value.

7. The method according to claim 6, characterized in that, The difference between the third value and the fourth value is greater than the difference between the fourth value and the fifth value.

8. The method according to claim 7, characterized in that, The thickness of the insulating layer is 0.2~0.3 micrometers; Before grinding the filler layer and the back endpoints of some of the conductive pillars, the thickness of the filler layer is 7.8 to 8 micrometers; after grinding the filler layer and the back endpoints of some of the conductive pillars, the thickness of the filler layer is 0.8 to 1.2 micrometers.

9. The method according to claim 1, characterized in that, After grinding the filler layer until the back end of each conductive post is exposed, the method further includes: A circuit structure is formed on the back end of each of the conductive pillars.

10. A semiconductor structure, formed using the method for fabricating a semiconductor structure as described in any one of claims 1-9, characterized in that, include: A wafer, wherein a plurality of conductive pillars are formed therein; An insulating layer formed on the back plane of the wafer; A filler layer formed on the back plane of the insulating layer; The back plane of the filling layer exposes the back end point of each conductive post, and the back end point of each conductive post is flush with the back plane of the filling layer.

11. The conductor structure according to claim 10, characterized in that, The insulating layer is made of at least silicon nitride, and the filling layer is made of at least spin-coated glass (SOG).

12. A memory, characterized in that, The memory includes the semiconductor structure as described in any one of claims 10-11.

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